LTM8024

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Technical content

Rev. 0For more information www.analog.com Document Feedback TYPICAL APPLICATION FEATURES DESCRIPTION EN55022B Compliant 40V, Dual 4A or Single 8A Step- Down or 50W Inverting µModule Regulator The LTM®4655 is an ultralow noise 40V, dual 4A or single 8A DC/DC μModule® regulator designed to meet the radi- ated emissions requirements of EN55022. Its channels are fully independent, parallelable and capable of deliver- ing positive or negative output polarity. Conducted emis- sion requirements can be met by adding standard filter components. Included in the package are the switching controllers, power MOSFET s, inductors, filters and sup - port components. A 5V , 25mA LDO and clock generator enable phase interleaving of the power switching stages, for improved EMC performance. The LTM4655 can regulate positive V OUTn+ voltages between 0.5V and 26.5V from a 3.1V to 40V input. The LTM4655 can regulate negative VOUTn– voltages between –0.5V and –26.5V from a maximum input range of 3.6V to 40V, with the span from VINn to VOUTn– not to exceed 40V. A switching frequency range of 250kHz to 3MHz is supported. The LTM4655 is offered in a 16mm × 16mm × 5.01mm BGA package with SnPb or RoHS compliant terminal finish. Concurrent, ±12V Output DC/DC μModule Regulator*

APPLICATIONS

n Dual 4A/Single 8A Low EMI Switch Mode Power Supply n EN55022 Class B Compliant n T wo Fully Independent Channels, Each Configurable for Positive or Negative Output Voltage Polarity n Output Voltage Range: 0.5V ≤ |VOUTn+ – VOUTn–| ≤ 26.5V n Wide Input Voltage Range: Up to 40V n 3.1V or 3.6V Start-Up, Configuration-Dependent n ±1.67% Total DC Output Voltage Error Over Line, Load and Temperature n Analog Output Current Indicator (Positive-VOUT Only) n LDOOUT: 5V Fixed, 25mA Capable LDO n Parallelable with LTM4651/LTM4653 n Constant-Frequency Current Mode Control n Power Good Indicators and Programmable Soft-Start n Overcurrent and Overtemperature Protection n 16mm × 16mm × 5.01mm BGA Package n Automated Test and Measurement n Avionics and Industrial Control Systems n Video, Imaging and Instrumentation All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5847554, 6580258. Output Voltage Start-Up Waveforms 4.7/uni03BCF 4.7/uni03BCF VIN 13V TO 28V 124k 4.7/uni03BCF 4.7/uni03BCF 240k

4655 TA01a

22µF 12V OUT UP TO 4A 5VOUT UP TO 25mA CHANNEL 1 ANALOG OUTPUT CURRENT INDICATOR V IMON1 = 0.25/uni03A9 • IOUT1 LOAD2 47µF IOUT1 IOUT2 * FOR COMPLETE CIRCUIT , SEE FIGURE 50. FOR CHANNELS CONFIGURED TO REGULATE NEGATIVE VOUTn−: CURRENT LIMIT FREQUENCY-FOLDBACK INCEPTION IS A FUNCTION OF V INn, VOUTn-, AND fSWn. CONTINUOUS OUTPUT CURRENT CAPABILITY IS SUBJECT TO DETAILS OF APPLICATION IMPLEMENTATION. SEE NOTES 2 AND 3 AND THE APPLICATIONS INFORMATION SECTION, FOR DETAILS. 124k 240k –12VOUT UP TO 2.9A VIN1 VD1 SVIN1 fSET1 VIN2 SVIN2 VD2 fSET2 ISET1a ISET1b ISET2a ISET2b GND IMON1b IMON1a LDOOUT L TM4655 VOUT1– SVOUT1– VOUT1+ VOSNS1+ VOUT2– SVOUT2– VOUT2+ VOSNS2+ 2ms/DIV VOUT1+ 5V/DIV VOUT2– 5V/DIV PGOOD1,2 5V/DIV RUN1,2 5V/DIV

4655 TA01b

Rev. 0 For more information www.analog.com

Electrical Characteristics

Typical Performance Characteristics Pin Functions Simplified Block Diagram Test Circuit Decoupling Requirements Power Module Overview Forced Continuous Operation Output Voltage Programming, Tracking and F requency Adjustment Applications Information Power Module Protection RUN Pin Enable Loop Compensation Hot Plugging Safely I nput Disconnect/Input Short Considerations Multiphase Operation Negative Output Current Capability Varies as a Function of V INn to VOUTn– Conversion Ratios, O ptional Diodes to Guard Against Overstress, Frequency Adjustment, Negative-VOUT– Operation .34 Radiated EMI Noise Thermal Considerations and Output Current Safety Considerations T ypical Applications Package Description Package Photograph Design Resources Related Parts TABLE OF CONTENTS

Rev. 0For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS Channel 1 Terminal Voltages (All Channel 1 Terminal Voltages Relative to VOUT1– Unless Otherwise Indicated) GND, EXTVCC1, VOUT1+, VOSNS1+, INTVCC1, PGDFB1, VINREG1, COMP1a, PGOOD1, CLKIN1 (Relative to GND) Channel 2 Terminal Voltages (All Channel 2 Terminal Voltages Relative to VOUT2– Unless Otherwise Indicated) GND, EXTVCC2, VOUT2+, VOSNS2+, INTVCC2, PGDFB2, VINREG2, COMP2a, PGOOD2, CLKIN2 (Relative to GND) LDO and Clock Generator Voltages (All LDO and Clock Generator Terminal Voltages Relative to GND Unless Otherwise Indicated) CLKSET, MOD Terminal Currents Temperatures Internal Operating Temperature Range (Note 2 and Note 9) E - and I-Grade MP-Grade Storage Temperature Range Peak Package Body Temperature During Reflow .. 24 5°C (Note 1 and Note 5) M L K J H G F E D C B A BGA PACKAGE 144-LEAD (16mm × 16mm × 5.01mm) TJ(MAX) = 125°C; θ JA = 11.9°C/W; θJCtop = 10°C/W; θJCbot = 2.6°C/W; WEIGHT = 3.3 GRAMS 2 3 4 5 6 7 8 9 10 11 12 TOP VIEW VIN1 GND VD1CLKIN1 CLKOUT1 IMON1b IMON1a SVIN1 PGOOD1 COMP1b COMP1a fSET1 SVOUT1– ISET1b ISET1a EXTV CC1 RUN1 PGDFB1 VINREG1 VIN2 VD2 VOUT1+ VOUT2+ NC NC VOSNS1+ SVOUT1– VOUT1– VOUT1– SW1 VOUT1– TEMP+ TEMP– VOUT1– VOUT1– VOSNS2+SVOUT2– SW2 VOSNS1+ SVOUT1– INTVCC1 GND CLKIN2 CLKOUT2 IMON2b IMON2a SVIN2 PGOOD2 COMP2b COMP2a fSET2 SVOUT2– ISET2b ISET2a EXTV CC2 RUN2 PGDFB2 VINREG2 VOUT2–VOSNS2+ SVOUT2– INTVCC2 VOUT1– VOUT2– VOUT2– VOUT2– SVINF1 LDOIN SVINF2 CLKOUT2 GND MOD CLKSET LDOOUT NC NC VOUT2– NOTES: 1) θ VALUES ARE DETERMINED BY SIMULATION PER JESD51 CONDITIONS. 2) θ JA VALUE IS OBTAINED WITH DEMO BOARD. 3) REFER TO APPLICATION INFORMATION SECTION FOR LAB MEASUREMENT AND DERATING INFORMATION.

Rev. 0 For more information www.analog.com ORDER INFORMATION PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERA TURE RANGE (SEE NOTE 2)DEVICE FINISH CODE LTM4655EY#PBF SAC305 (RoHS) LTM4655Y e1 BGA 3 –40°C to 125°C LTM4655IY#PBF SAC305 (RoHS) LTM4655Y e1 BGA 3 –40°C to 125°C LTM4655MPY#PBF SAC305 (RoHS) LTM4655Y e1 BGA 3 –55°C to 125°C LTM4655IY SnPb (63/37) LTM4655Y e0 BGA 3 –40°C to 125°C LTM4655MPY SnPb (63/37) LTM4655Y e0 BGA 3 –55°C to 125°C Contact the factor y for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609. Recommended LGA and BGA PCB Assembly and Manufacturing Procedures LGA and BGA Package and Tray Drawings SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SVINn(DC), VINn(DC) Input DC Voltage in Positive-VOUT Configuration VOUTn– = GND l 3.1 40 V VOUTn(RANGE)+ Range of Positive Output Voltage Regulation 0.5V ≤ ISETna–SV OUTn– ≤ 26.5V, IOUTn+ = 0A (See Note 7) l 0.5 26.5 V VOUTn(24VDC)+ Output Voltage Total Variation with Line and Load at V OUTn+ = 24V 29V ≤ VINn ≤ 40V, 0A ≤ IOUTn+ ≤ 4A, CINHn = 4.7μF, CDn = 4.7μF, COUTHn = 2 × 47μF, CLKINn Driven with 1.5MHz Clock l 23.6 24 24.4 V VOUTn(0.5VDC)+ Output Voltage Total Variation with Line and Load at V OUTn+ = 0.5V Measuring VOSNSn+ to ISETna 3.1V ≤ VINn ≤ 13.2V, 0A ≤ IOUTn+ ≤ 4A, CINHn = 4.7μF, CDn = 4.7μF, COUTHn = 2 × 47μF, ISETna = 500mV, RfSETn = N/U (Note 6) l –15 0 15 mV RSVINFn Resistor Between SVINn and SVINFn 1 Ω Input Specifications VINn(UVLO) SVINn Undervoltage Lockout Threshold SVINn Rising SVINn Falling Hysteresis l l l 2.4 150 2.85 2.6 250 3.1 2.9 V V mV IINRUSH(VINn) Input Inrush Current at Start-Up CINHn = 4.7μF, CDn = 4.7μF, COUTHn = 2 × 47μF; IOUTn+ = 0A, ISETna Electrically Connected to ISETnb 300 mA IQ(SVINn) Input Supply Bias Current Shutdown, RUNn = GND RUNn = 3.3V 450 30 μA μA IS(VINn) Input Supply Current CLKINn Open Circuit, IOUTn+ = 4A 2.9 A IS(VINn, SHUTDOWN) Input Supply Current in Shutdown Shutdown, RUNn = GND 4 µA Output Specifications IOUTn+ VOUTn+ Output Continuous Current Range (Note 3) 0 4 A ∆VOUTn(LINE)+/ VOUTn+ Line Regulation Accuracy IOUTn+ = 0A, 29V ≤ VINn ≤ 40V l 0.05 0.1 % ∆VOUTn(LOAD)+/ VOUTn+ Load Regulation Accuracy VINn = 36V, 0A ≤ IOUTn+ ≤ 4A l 0.05 0.75 % VOUTn(AC)+ Output Voltage Ripple, VOUTn+ VINn = 12V, ISETna = 5V 2 mVP-P ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 5). TA = 25°C, Test Circuit 1 (positive-VOUT, noninverting step-down configuration with VOUTn– = GND), VINn = SVINn = 36V, EXTVCCn = 24V, RUNn = 3.3V, RISETn = 480k, RfSETn+ = 57.6kΩ, fSWn = 1.5MHz (CLKINn driven with 1.5MHz clock signal) and voltages referred to GND unless otherwise noted.

Rev. 0For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 5). TA = 25°C, Test Circuit 1 (positive-VOUTn+, noninverting step-down configuration with VOUTn– = GND), VINn = SVINn = 36V, EXTVCCn = 24V, RUNn = 3.3V, RISETn = 480k, RfSETn+ = 57.6kΩ, fSWn = 1.5MHz (CLKINn driven with 1.5MHz clock signal) and voltages referred to GND unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fSn VOUTn+ Ripple Frequency RfSETn = 57.6k, CLKINn Open Circuit l 1.7 1.95 2.2 MHz ∆VOUTn(START)+ Turn-On Overshoot 8 mV tSTARTn Turn-On Start-Up Time Delay Measured from VINn Toggling from 0V to 36V to PGOODn Exceeding 3V; PGOODn. Having a 100kΩ Pull-Up to 3.3V with Respect to GND, VPGFBn Resistor Divider Network as Shown in Test Circuit 1, R ISETna = 480kΩ and ISETna Electrically Connected to ISETnb and CLKIN Driven with 1.5MHz Clock l 4 9 ms ∆VOUTn(LS)+ Peak Output Voltage Deviation for Dynamic Load Step I OUTn+: 0A to 2A and 2A to 0A Load Steps in 1μs, COUTHn = 47µF × 2 400 mV tSETTLEn Settling Time for Dynamic Load Step IOUTn+: 0A to 2A and 2A to 0A Load Steps in 1μs, COUTHn = 47µF × 2 50 µs IOUTn(OCL)+ IOUTn+ Output Current Limit 5.5 A Control Section IISETna Reference Current of ISETna Pin V ISETna = 0.5V, 3.1V ≤ VINn ≤ 13.2V VISETna = 24V, 29V ≤ VINn ≤ 40V l l 49.3 50.7 µA µA IVOSNSn+ VOSNSn+ Leakage Current VVOSNSn+ = 28V 290 μA tONn(MIN) Minimum On-Time (Note 4) 60 ns VRUNn RUNn Turn-On/-Off Thresholds RUNn Input Turn-On Threshold, RUNn Rising RUNn Hysteresis l 1.08 1.2 130 1.32 V mV IRUNn RUNn Leakage Current RUNn = 3.3V l 0.1 50 nA Oscillator and Phase-Locked Loop (PLL) fOSCn Oscillator Frequency Accuracy VINn = 12V, ISETna = 5V, and: fSETn Open-Circuit RfSETn = 57.6kΩ (See fSN Specification) l 360 400 1.95 440 kHz MHz fSYNCn PLL Synchronization Capture Range VINn = 12V, ISETna = 5V, CLKINn Driven with a GND Referred Clock Toggling from 0.4V to 1.2V and Having a Clock Duty Cycle: From 10% to 90% ; fSETn Open Circuit From 40% to 60% ; RfSETn = 57.6kΩ 250 1.3 550 kHz MHz V CLKINn CLKINn Input Threshold VCLKINn Rising VCLKINn Falling 1.2 0.4 V V ICLKINn CLKINn Input Current VCLKINn = 5V VCLKINn = 0V –20 230 500 μA μA Power Good Feedback Input and Power Good Output OVPGDFBn Output Overvoltage PG00Dn Upper Threshold PGDFBn Rising l 620 645 675 mV UVPGDFBn Output Undervoltage PGOODn Lower Threshold PGDFBn Falling l 525 555 580 mV ∆VPGDFBn PGOODn Hysteresis PGDFBn Returning 8 mV RPGDFBn Resistor Between PGDFB1n and SVOUTn– 4.94 4.99 5.04 kΩ RPGOODn PGOODn Pull-Down Resistance V PGOODn = 0.1V, VPGDFBn < UVPGDFBn or VPGDFBn > OVPGDFBn 700 1500 Ω IPGOODn(LEAK) PGOODn Leakage Current VPGOODn = 3.3V, UVPGDFBn < VPGDFBn < OVPGDFBn 0.1 1 μA

Rev. 0 For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 5). TA = 25°C, Test Circuit 1 (positive-VOUTn+, noninverting step-down configuration with VOUTn– = GND), VINn = SVINn = 36V, EXTVCCn = 24V, RUNn = 3.3V, RISETn = 480k, RfSETn+ = 57.6kΩ, fSWn = 1.5MHz (CLKINn driven with 1.5MHz clock signal) and voltages referred to GND unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tPGOODn(DELAY) PGOODn Delay PGOODn Low to High (Note 4) PGOODn High to Low (Note 4) 16/fSW(Hz) 64/fSW(Hz) s s Current Monitor and Input V oltage Regulation Pins hIMONna IOUTn+/IIMONna Ratio of VOUTn+ Output Current to IIMONna Current, IOUTn+ = 4A l 36 40 44 k IOSn(IMON) IIMONna Offset Current IIMONna at IOUTn+ = 0A –5 5 μA IMONnb Resistor Resistor Between IMONnb and SVOUTn– 9.8 10 10.2 kΩ VIMONna IMONna Servo Voltage IMONna Voltage During Output Current Regulation l 1.9 2.0 2.1 V VVINREGn VINREGn Servo Voltage VINREGn Voltage During Output Current Regulation l 1.8 2.0 2.2 V IVINREGn VINREGn Leakage Current VINREGn = 2V 1 nA INTVCCn Regulator VINTVCCn Channel Internal VCC Voltage, No INTVCCn Loading (IINTVCCn = 0mA) 3.6V ≤ SVINn ≤ 40V, EXTVCCn Open Circuit 5V ≤ SVINn ≤ 40V, 3.2V ≤ EXTVCCn ≤ 26.5V 3.15 2.85 3.4 3.0 3.65 3.15 V V VEXTVCCn(TH) EXTVCCn Switchover Voltage (Note 4) 3.15 V ∆VINTVCCn(LOAD)/ VINTVCCn INTVCCn Load Regulation 0mA ≤ IINTVCCn ≤ 30mA –2 0.5 2 % SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SVINn(DC), VINn(DC) Input DC Voltage in Negative-V OUT– Configuration VINn+ |VOUTn–| ≤ 40V l 3.6 40 V VOUTn(RANGE)– Range of Negative Output Voltage Regulation 0.5V ≤ ISETna–SVOUTn– ≤ 26.5V l –26.5 –0.5 V VOUTn(–24VDC)– Output Voltage Total Variation with Line and Load at VOUTn– = –24V 3.6V ≤ VINn ≤ 16V, 0A ≤ IOUTn– ≤ 0.3A, CLKINn Driven per Note 8, CINHn = 4.7μF, CDn = 4.7μF × 2, COUTHn = 47μF × 2 l –24.4 –24 – 23.6 V VOUTn(–5VDC)– Output Voltage Total Variation with Line and Load at V OUTn– = –5V Measuring VOSNSn+ – ISETna, 12V ≤ VINn ≤ 35V, 0A ≤ IOUT– ≤ 3A, CLKINn Driven by 550kHz Clock, CINHn = 4.7μF, CDn = 4.7μF × 2, COUTHn = 47μF × 2, ISETna–SVOUTn– = 5V l –15 0 15 mV RSVINFn Resistor Between SVINn and SVINFn 1 Ω ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 5). TA = 25°C, Test Circuit 2 (negative- VOUTn–, inverting buck-boost configuration with VOUTn+ = GND), VINn = 12V and electrically connected to SVINn, RUNn–GND = 3.3V, ISETna–SVOUTn– = 24V, EXTVCCn = GND, CLKINn open circuit, RfSETn = 57.6kΩ and RISETn = 480kΩ and voltages referred to GND unless otherwise noted.

Rev. 0For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 5). TA = 25°C, Test Circuit 2 (negative- VOUTn–, inverting buck-boost configuration with VOUTn+ = GND), VINn = 12V and electrically connected to SVINn, RUNn–GND = 3.3V, ISETna–SVOUTn– = 24V, EXTVCCn = GND, CLKINn open circuit, RfSETn = 57.6kΩ and RISETn = 480kΩ and voltages referred to GND unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Specifications VINn(UVLO) SVINn Undervoltage Lockout Threshold SV INn Rising SVINn Falling Hysteresis l l l 2.1 400 3.2 2.5 700 3.6 2.8 V V mV IINRUSH(VINn) Input Inrush Current at Start-Up CINHn = 4.7μF, CDn = 4.7μF × 2, COUTHn = 47μF × 2; IOUTn– = 0A, ISETna Electrically Connected to ISETnb 1.1 A IQ(SVINn) Input Supply Bias Current Shutdown, RUNn = GND RUNn–GND = 3.3V 450 30 μA μA IS(VINn) Input Supply Current CLKINn Open Circuit, IOUTn– = 1.25A 3.0 A IS(VINn, SHUTDOWN) Input Supply Current in Shutdown Shutdown, RUNn = GND 4 µA Output Specifications IOUTn– VOUTn– Output Continuous Current Range VINn = 12V, Regulating VOUTn– = –24V at fSWn = 1MHz VINn = 12V, Regulating VOUTn– = –5V at fSWn = 550kHz (See Note 3. Capable of Up to 4A Output Current for Some Combinations of VINn, VOUTn– and fSWn) 1.25 A A VOUTn(LINE)–/VOUTn– Line Regulation Accuracy IOUTn– = 0A, 3.6V ≤ VINn ≤ 16V, ISETna–SVOUTn– = 24V, CLKINn Driven by 1.8MHz Clock l 0.05 0.25 % ∆VOUTn(LOAD)–/VOUTn– Load Regulation Accuracy VINn = 12V, 0A ≤ IOUTn– ≤ 1.25A, CLKINn Driven by 1.5MHz Clock, RfSETn = 57.6kΩ, and RISETn = 480kΩ l 0.05 0.75 % VOUTn(AC)– Output Voltage Ripple, VOUTn– VINn = 12V, ISETna–SVOUTn– = 5V 10 mV P-P fSN VOUTn– Ripple Frequency VINn = 12V, ISETna–SVOUTn– = 5V l 1.7 1.95 2.2 MHz ∆VOUTn(START)– Turn-On Overshoot 8 mV tSTARTn Turn-On Start-Up Time Delay Measured from VINn Toggling from 0V to 12V to PGOODn Exceeding 3V Above GND; PGOODn Having a 100kΩ Pull-Up to 3.3V with Respect to GND, V PGFBn Resistor Divider Network as Shown in Test Circuit 2, RISETna = 480kΩ, ISETna Electrically Connected to ISETnb, and CLKINn Driven with 1.2MHz Clock l 4 9 ms ∆VOUTn(LS)– Peak Output Voltage Deviation for Dynamic Load Step I OUTn–: 0A to 1A and 1A to 0A Load Steps in 1μs, COUTHn = 47µF × 2 400 mV tSETTLEn Settling Time for Dynamic Load Step I OUTn–: 0A to 1A and 1A to 0A Load Steps in 1μs, COUTH2 = 47µF × 2 X5R 50 µs IOUTn(OCL)– IOUTn– Output Current Limit 1.7 A Control Section IISETna Reference Current of ISETna Pin V ISETna–SVOUTn– = 0.5V, 3.6V ≤ VINn ≤ 28V 0V ≤ VISETna–SVOUTn– ≤ VINn–SVOUT– ≤ 40V l l 49.3 50.7 µA µA IVOSNSn+ VOSNSn+ Leakage Current VOSNSn+ – SVOUTn– = 28V 290 μA tONn(MIN) Minimum On-Time (Note 4 ) 60 ns VRUNn RUNn Turn-On/-Off Thresholds RUNn Input Turn-On Threshold, RUNn Rising RUNn Hysteresis (RUNn Thresholds Measured with Respect to GND) l 1.08 1.2 130 1.32 V mV IRUNn RUNn Leakage Current VINn = 12V, RUNn–GND = 3.3V l 0.1 50 nA

Rev. 0 For more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Oscillator and Phase-Locked Loop (PLL) fOSCn Oscillator Frequency Accuracy VINn = 12V, ISETna–SVOUTn– = 5V, and: fSETn Open Circuit RfSETn = 57.6kΩ (See fSN Specification) l 360 400 1.95 440 kHz MHz fSYNCn PLL Synchronization Capture Range VINn = 12V, ISETna–SVOUTn– = 5V, CLKINn Driven with a GND Referred Clock Toggling from 0.4V to 1.2V and Having a Clock Duty Cycle: From 10% to 90% ; fSETn Open Circuit From 40% to 60% ; RfSETn = 57.6kΩ 250 1.3 550 kHz MHz V CLKINn CLKINn Input Threshold VCLKINn Rising with Respect to GND VCLKINn Falling with Respect to GND 1.2 0.4 V V ICLKINn CLKINn Input Current VCLKINn = 5V with Respect to GND VCLKINn = 0V with Respect to GND –20 230 500 μA μA Power Good Feedback Input and Power Good Output OVPGDFBn Output Overvoltage PGOODn Upper Threshold PGDFB n Rising, Differential Voltage from PGDFBn to SVOUTn– l 620 645 675 mV UVPGDFBn Output Undervoltage PGOODn Lower Threshold PGDFBn Falling, Differential Voltage from PGDFBn to SV OUTn– l 525 555 580 mV ∆VPGDFBn PGOODn Hysteresis PGDFBn Returning 8 mV RPGDFBn Resistor Between PGDFBn and SVOUTn– 4.94 4.99 5.04 kΩ RPGOODn PGOODn Pull-Down Resistance V PGOODn = 0.1V with Respect to GND, VPGDFBn–SVOUTn– < UVPGDFBn or VPGDFBn–SVOUTn– > OVPGDFBn 700 1500 Ω IPGOODn(LEAK) PGOODn Leakage Current VPGOODn = 3.3V with Respect to GND, UVPGDFBn < VPGDFBn–SVOUTn– < OVPGDFBn 0.1 1 μA tPGOODn(DELAY) PGOODn Delay PGOODn Low to High (Note 4) PGOODn High to Low (Note 4) 16/fSW(Hz) 64/fSW(Hz) s s Input V oltage Regulation Pin VVINREGn VINREGn Servo Voltage VINREGn Voltage During Output Current Regulation, Measured with Respect to SVOUTn– l 1.8 2.0 2.2 V IVINREGn VINREGn Leakage Current VINREG–SVOUTn– = 2V 1 nA INTVCCn Regulator VINTVCCn Channel Internal VCC Voltage, No INTVCCn Loading (IINTVCCn = 0mA) 3.6V ≤ SVINn–SVOUTn– ≤ 40V, EXTVCCn = Open Circuit 5V ≤ SVINn–SVOUTn– ≤ 40V, 3.2V ≤ EXTVCCn– VOUTn– ≤ 26.5V (INTVCCn Measured with Respect to SVOUTn–) 3.15 2.85 3.4 3.0 3.65 3.15 V V V VEXTVCCn(TH) EXTVCCn Switchover Voltage (EXTVCCn Measured with Respect to SVOUTn–) (Note 4) 3.15 V ∆VINTVCCn(LOAD)/ VINTVCCn INTVCCn Load Regulation 0mA ≤ IINTVCCn ≤ 30mA –2 0.5 2 % ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 5). TA = 25°C, Test Circuit 2 (negative- VOUTn–, inverting buck-boost configuration with VOUTn+ = GND), VINn = 12V and electrically connected to SVINn, RUNn–GND = 3.3V, ISETna–SVOUTn– = 24V, EXTVCCn = GND, CLKINn open circuit, RfSETn = 57.6kΩ and RISETn = 480kΩ and voltages referred to GND unless otherwise noted.

Rev. 0For more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LDOIN(DC) LDO Input DC Voltage l 4.5 40 V VLDOOUT(DC) LDO Output Voltage VLDOIN = 36V, 0mA ≤ ILDOOUT ≤ 25mA VLDOIN = 4.5V, 0mA ≤ ILDOOUT ≤ 20mA l l 4.8 2.7 5.0 4.1 5.2 V V VLDOOUT(AC) Output Voltage Ripple 2 mVP-P ILDOOUT(OCL) Output Current Limit, 5V LDO LDOIN = 36V 140 mA Clock Generator ∆fOUT Clock-Generator Frequency Accuracy 2.7V ≤ LDO OUT ≤ 5.2V, 200kHz ≤ fOUT ≤ 3MHz, MOD Connected to CLKOUT2 l ±2.5 ±2.5 7.5 RCLKSET(RANGE) Frequency Setting Resistor Range R CLKSET Resistance for Which –7.5% ≤ ∆fOUT ≤ 7.5%, Over 2.7V ≤ LDOOUT ≤ 5.2V, MOD Electrically Connected to CLKOUT2 l 33.2 499 kΩ Period Variation (Frequency Spreading) LDO OUT = 5V, RCLKSET = 100kΩ, MOD Open Circuit ±10 % Duty Cycle 2.7V ≤ LDOOUT ≤ 5.2V, 200kHz ≤ fOUT ≤ 3MHz, MOD Electrically Connected to CLKOUT2 l 40 60 % θCLKOUT1/ θCLKOUT2 Phase Relationship of CLKOUT2 to CLKOUT1 2.7V ≤ LDOOUT ≤ 5.2V, 200kHz ≤ fOUT ≤ 3MHz, MOD Electrically Connected to CLKOUT2

180 Deg

VOH_CLKOUTn CLKOUTn Output Voltage, Logic High CLKOUTn V OH Measured with Respect to LDOOUT, 2.7V ≤ LDOOUT ≤ 5.2V, ICLKOUTn = –100μA –0.4 V VOL_CLKOUTn CLKOUTn Output Voltage, Logic Low CLKOUTn V OL Measured with Respect to GND, 2.7V ≤ LDOOUT ≤ 5.2V, ICLKOUTn = 100μA 0.4 V Temperature Sensor ∆VTEMP Temperature Sensor Forward Voltage, VTEMP+ to VTEMP– ITEMP+ = 100µA and ITEMP– = –100μA at TA = 25°C 0.598 V TC∆V(TEMP) ∆VTEMP Temperature Coefficient –2.0 mV/°C η Ideality Factor 1.004 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). TA = 25°C, Test Circuit 3 and voltages referred to GND unless otherwise noted. Note 1: Stresses beyond those listing under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating conditions for extended periods may affect device reliability and lifetime. Note 2: The LTM4655 is tested under pulsed load conditions such that T J ≈ TA. The LTM4655E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the full –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4655I is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. The LTM4655MP is tested and guaranteed over the full –55°C to 125°C operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: See output current derating curves for different V IN, VOUT, and TA, located in the Applications Information section. Note 4: Minimum on-time, PGOOD delay, and EXTV CCn switchover threshold are tested at wafer sort. Note 5: The two power inputs—V IN1 and VIN2—and their respective power outputs—VOUT1+ or VOUT1–, and VOUT2+ or VOUT2–, depending on operational configuration—are tested independently in production, in both positive-VOUT (noninverting step-down) and negative-VOUT– (inverting buck-boost) configurations. On occasion, a shorthand notation is used in this document that allows VINn to refer to both VIN1 and VIN2 by virtue of n being permitted to take on a value of 1 or 2. This italicized n notation and convention is extended to all such pin names. Note 6: To ensure minimum on-time criteria is met, VOUTn (0.5VDC)+ high line regulation is tested at 13.2VIN, with fSETn and CLKINn open circuit. VOUTn (–0.5VDC)– low line regulation is tested at 3.6VIN, with fSETn and CLKINn open circuit. V OUTn (–0.5VDC)– high line regulation is tested at 28VIN, and with CLKINn driven at 200kHz—so as to ensure minimum on-time criteria is met. The LTM4655 is not recommended for applications where the minimum on-time criteria (guardband to 90ns) is continuously violated. The LTM4655 can ride through events (such as V IN surge) where the on-time criteria is transiently violated. See the Applications Information section. Note 7: See the Applications Information section for dropout criteria. Note 8: V OUTn (–24VDC)– is tested at 3.6VIN and 16VIN, with CLKINn driven with a 1.8MHz clock, ISETna to SVOUTn– = 12V, and RfSET = 57.6k. It is also tested at 12VIN, with CLKINn driven with a 1.5MHz clock, RfSETn = 57.6k, and RISETn = 480k. Note 9: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 10: The INTV CCn Abs Max peak output current is specified as the sum of current drawn by circuits internal to the module biased off of INTVCCn and current drawn by external circuits biased off of INTVCCn. Specified independently, for each channel. See the Applications Information section.

Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, single channel positive-VOUTn+ operation only, unless otherwise noted. Efficiency vs Load Current at 5VIN, Forced Continuous Mode Efficiency vs Load Current at 12V IN, Forced Continuous Mode Efficiency vs Load Current at 15V IN, Forced Continuous Mode Efficiency vs Load Current at 24V IN, Forced Continuous Mode Efficiency vs Load Current at 36V IN, Forced Continuous Mode 1.2VOUT, 400kHz 1.5VOUT, 400kHz 1.8VOUT, 400kHz 2.5VOUT, 400kHz 3.3VOUT, 400kHz 1.0VOUT, 400kHz EFFICIENCY (%) LOAD CURRENT (A)

4655 G01

1.5VOUT, 400kHz 1.8VOUT, 400kHz 2.5VOUT, 400kHz 3.3VOUT, 400kHz 5.0VOUT, 400kHz 1.2VOUT, 400kHz 1.0VOUT, 400kHz65 EFFICIENCY (%) LOAD CURRENT (A)

4655 G02

1.8VOUT, 400kHz 2.5VOUT, 400kHz 3.3VOUT, 400kHz 5.0VOUT, 450kHz 12VOUT, 500kHz 1.5VOUT, 400kHz 1.2VOUT, 400kHz 1.0VOUT, 400kHz 100 EFFICIENCY (%) LOAD CURRENT (A)

4655 G03

2.5VOUT, 400kHz 3.3VOUT, 400kHz 5.0VOUT, 550kHz 12VOUT, 800kHz 15VOUT, 750kHz 1.0VOUT, 400kHz 1.2VOUT, 400kHz 1.5VOUT, 400kHz 1.8VOUT, 400kHz 100 EFFICIENCY (%) LOAD CURRENT (A)

4655 G04

5VOUT, 575kHz 12VOUT, 1.1MHz 15VOUT, 1.2MHz 24VOUT, 1.2MHz 1.5VOUT, 400kHz 1.8VOUT, 400kHz 2.5VOUT, 400kHz 100 EFFICIENCY (%) LOAD CURRENT (A)

4655 G05

3.3VOUT, 400kHz 1V Transient Response, 24VIN 40µs/DIV VOUTn+ 50mV/DIV AC-COUPLED IOUTn+ 2A/DIV

4655 G06

FIGURE 51 CIRCUIT, 24VIN, CINHn = CDn = 4.7µF, COUTn = 3 x 100µF, RfSETn = N/A, RISETn = 20k/uni03A9, CTHn = 6.8nF, RTHn = 681/uni03A9, REXTVCCn = N/A, CEXTVCCn = N/A, 2A to 4A LOAD STEP AT 2A/µs

Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, single channel positive-VOUTn+ operation only, unless otherwise noted. Start-Up, No Load Start-Up, 4A Load Start-Up, Pre-Bias Short Circuit, No Load Short Circuit, 4A Load 2ms/DIV RUNn 2V/DIV PGOODn 2V/DIV VOUTn+ 5V/DIV

4655 G07

FIGURE 51 CIRCUIT, 36VIN, CINHn = CDn = 4.7µF, COUTn = 2 x 22µF, RfSETn = 124k, RISETn = 240k/uni03A9, RPGDFBn = 95.3k/uni03A9, CTHn = 10nF, RTHn = 562/uni03A9, REXTVCCn = 49.9/uni03A9, CEXTVCCn = 1µF, NO LOAD 2ms/DIV RUNn 2V/DIV PGOODn 2V/DIV VOUTn+ 5V/DIV

4655 G08

FIGURE 51 CIRCUIT, 36VIN, CINHn = CDn = 4.7µF, COUTn = 2 x 22µF, RfSETn = 124k, RISETn = 240k/uni03A9, RPGDFBn = 95.3k/uni03A9, CTHn = 10nF, RTHn = 562/uni03A9, REXTVCCn = 49.9/uni03A9, CEXTVCCn = 1µF, 3/uni03A9 RESISTIVE LOAD 2ms/DIV RUNn 2V/DIV PGOODn 2V/DIV VOUTn+ 5V/DIV IDIODEn 1mA/DIV

4655 G09

FIGURE 51 CIRCUIT, 36VIN, CINHn = CDn = 4.7µF, COUTn = 2 x 22µF, RfSETn = 124k, RISETn = 240k/uni03A9, RPGDFBn = 95.3k/uni03A9, CTHn = 10nF, RTHn = 562/uni03A9, REXTVCCn = 49.9/uni03A9, CEXTVCCn = 1µF, VOUTn+ PRE-BIASED TO 5V THROUGH 1N4148 DIODE 10µs/DIV VOUTn+ 5V/DIV IINn 1A/DIV

4655 G10

FIGURE 51 CIRCUIT, 36VIN, CINHn = CDn = 4.7µF, COUTn = 2 x 22µF, RfSETn = 124k, RISETn = 240k/uni03A9, RPGDFBn = 95.3k/uni03A9, CTHn = 10nF, RTHn = 562/uni03A9, REXTVCCn = 49.9/uni03A9, CEXTVCCn = 1µF, NO LOAD PRIOR TO APPLICATION OF OUTPUT SHORT-CIRCUIT 10µs/DIV VOUTn+ 5V/DIV IINn 1A/DIV

4655 G11

FIGURE 51 CIRCUIT, 36VIN, CINHn = CDn = 4.7µF, COUTn = 2 x 22µF, RfSETn = 124k, RISETn = 240k/uni03A9, RPGDFBn = 95.3k/uni03A9, CTHn = 10nF, RTHn = 562/uni03A9, REXTVCCn = 49.9/uni03A9, CEXTVCCn = 1µF, 4/uni03A9 RESISTIVE LOAD PRIOR TO APPLICATION OF OUTPUT SHORT-CIRCUIT

Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, single channel negative-VOUTn– operation only, unless otherwise noted. –12V Efficiency vs Load Current –15V Efficiency vs Load Current –24V Efficiency vs Load Current Rated Operating Output Voltage –3.3V Efficiency vs Load Current –5V Efficiency vs Load Current 5VIN, 400kHz 12VIN, 400kHz 24VIN, 450kHz 36VIN, 500kHz LOAD CURRENT (A) EFFICIENCY (%)

4651 G13

LOAD CURRENT (A) EFFICIENCY (%)

4651 G14

5VIN, 400kHz 12VIN, 550kHz 24VIN, 600kHz 36VIN, 600kHz LOAD CURRENT (A) 0.5 1.5 2.5 3.5 EFFICIENCY (%) 4651G15h 5VIN, 475kHz 12VIN, 825kHz 24VIN, 1.1MHz LOAD CURRENT (A) 0.5 1.5 2.5 EFFICIENCY (%)

4655 G16

5VIN, 500kHz 12VIN, 875kHz 24VIN, 1.2MHz 5VIN, 550kHz 12VIN, 1MHz LOAD CURRENT (A) 0.5 1.5 EFFICIENCY (%)

4655 G17

INPUT VOL TAGE (V) –30 –25 –20 –15 –10 OUTPUT VOL TAGE (V)

4655 G18Output Current Capability*

V OUT – = –0.5V V OUT – = –3.3V V OUT – = –5V V OUT – = –8V V OUT – = –12V V OUT – = –15V V OUT – = –20V V OUT – = –24V INPUT VOL TAGE (V) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 CHANNEL OUTPUT CURRENT (A) OUTPUT CURRENT CAPABILITY*

4655 G12

*Current limit frequency-foldback activates at load currents higher than indicated curves. Continuous channel output current capability subject to details of application implementation. Switching frequency set per Table 1. See Notes 2 and 3.

Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, single channel negative-VOUTn– operation only, unless otherwise noted. Start-Up, Pre-Bias Short Circuit, No Load Short Circuit, 1.25A Load –24V T ransient Response, 12VIN Start-Up, No Load Start-Up, 1.25A Load –5V T ransient Response, 24VIN FIGURE 48 CIRCUIT , 24VIN, CINOUTn = CINHn = CDGNDn = CDn = 4.7/uni03BCF , COUTn = 47/uni03BCF ×2, RfSETn = 665k/uni03A9, RISETn = 100k/uni03A9, RPGDFBn = 36.5k/uni03A9, REXTVCCn = 20/uni03A9, 1.8A TO 3.8A LOAD STEP AT 2A//uni03BCs 40/uni03BCs/DIV VOUTn– 100mV/DIV AC-COUPLED IOUTn– 1A/DIV

4655 G19

FIGURE 48 CIRCUIT , 0.625A TO 1.25A LOAD STEP AT 0.625A//uni03BCs 20/uni03BCs/DIV VOUTn– 100mV/DIV AC-COUPLED IOUTn– 0.4A/DIV

4655 G20

FIGURE 48 CIRCUIT , APPLICATION OF 12VIN, START-UP INTO NO LOAD 1ms/DIV VINn 5V/DIV RUNn 2V/DIV PGOODn 5V/DIV VOUTn– 10V/DIV

4655 G21

FIGURE 48 CIRCUIT , APPLICATION OF 12VIN, START-UP INTO 19.2Ω LOAD 1ms/DIV VINn 5V/DIV IOUTn– 500mA/DIV PGOODn 5V/DIV VOUTn– 10V/DIV

4655 G22

FIGURE 48 CIRCUIT , VOUTn– PRE-BIASED TO –5V THROUGH A 1N4148 DIODE PRIOR TO RUNn TOGGLING HIGH 1ms/DIV VOUTn– 10V/DIV RUNn 2V/DIV PGOODn 2V/DIV IDIODEn 100mA/DIV

4655 G23

FIGURE 48 CIRCUIT , NO LOAD PRIOR TO APPLICATION OF V OUTn– SHORT-CIRCUIT 10/uni03BCs/DIV VOUTn– 10V/DIV IINn 10A/DIV

4655 G24

FIGURE 48 CIRCUIT , 19.2/uni03A9 LOAD PRIOR TO APPLICATION OF V OUTn– SHORT-CIRCUIT 10/uni03BCs/DIV VOUTn– 10V/DIV IINn 10A/DIV

4655 G25

Rev. 0 For more information www.analog.com PIN FUNCTIONS VIN1 (A1–A3, B3): Channel 1 Power Input Pins. Apply input voltage and input decoupling capacitance directly between VIN1 and a power ground (PGND) plane. Either connect PGND to VOUT1– in noninverting step-down appli- cations, where V OUT1+ is the regulated positive output voltage—or , connect PGND to VOUT1+ in inverting buck- boost applications, where VOUT1– is the regulated negative output voltage. VIN2 (A6–A8, B8): Channel 2 Power Input Pins. Apply input voltage and input decoupling capacitance directly between VIN2 and a power ground (PGND) plane. Either connect PGND to VOUT2– in noninverting step-down appli- cations, where V OUT2+ is the regulated positive output voltage—or , connect PGND to VOUT2+ in inverting buck- boost applications, where VOUT2– is the regulated negative output voltage. VD1 (A4, B4, C4): Drain of Channel 1’s Primary Switching MOSFET . Apply at least one 4.7μF high frequency ceramic decoupling capacitor directly from V D1 to V OUT1–. Give this capacitor higher layout priority (closer proximity to the module) than any VIN1 decoupling capacitors. VD2 (A9, B9, C9): Drain of Channel 2’s Primary Switching MOSFET . Apply at least one 4.7μF high frequency ceramic decoupling capacitor directly from V D2 to V OUT2–. Give this capacitor higher layout priority (closer proximity to the module) than any V IN2 decoupling capacitors. SVIN1 (C3): Channel 1 Input Voltage Supplies for Small Signal Circuits. SV IN1 is the input to the INTV CC1 LDO. Connect SVIN1 directly to VIN1. SVIN2 (C8): Channel 2 Input Voltage Supplies for Small Signal Circuits. SV IN2 is the input to the INTV CC2 LDO. Connect SVIN2 directly to VIN2. SVINF1 (B11): Channel 1 Filtered Voltage Supply for Small Signal Circuits. If powering the LTM4655’s 5V LDO from channel 1’s supply for small signal circuits, electrically connect SVINF1 and LDOIN with a short trace capable of carrying up to 25mA. SVINF2 (C11): Channel 2 Filtered Voltage Supply for Small Signal Circuits. If powering the LTM4655’s 5V LDO from channel 2’s supply for small signal circuits, electrically connect SVINF2 and LDOIN with a short trace capable of carrying up to 25mA. LDOIN (B12): Input to 5V LDO. Connect LDO IN to either SVINF1 or SVINF2 with a short trace capable of carrying up to 25mA, depending on which input rail is better suited for powering the 5V LDO. If LDOIN is being powered from SVINF1 or SVINF2, no bypass capacitance from LDO IN to GND is needed; otherwise, 0.1μF -to-1μF local bypass capacitance is recommended. V OUT1– (A5, B5, C5, D5, E5, F5, G4–5, H3, H5, J3–5, K4–5, L4–5, M4–5): Negative Power Output of Channel 1. Either connect V OUT1– to a PGND plane in noninverting step-down applications, where V OUT1+ is the regulated positive output voltage—or , connect VOUT1+ to PGND in inverting buck-boost applications, where V OUT1– is the regulated negative output voltage. SV OUT1– (E4, G2, H2): Signal Return of Channel 1. The SVOUT1– pins are the reference node for channel 1’s con- trol loop. A small island of SV OUT1– copper should be extended from the module and used to shield sensitive channel 1 pins and signals from noise— such as those routing to f SET1, ISET1a/b, and COMP1a/b. All SV OUT1– pins are connected to each other internal to the module. Connect Pin H2 to V OUT1– directly under the LTM4655. The remaining SVOUT1– pins can be used for redundant connectivity or routed to an ICT test point for design- for-test considerations, as desired. See the Applications Information section for the layout checklist. VOUT1+ (K1–3, L1–3, M1–3): Positive Power Output of Channel 1. Bypass V OUT1+ to V OUT1– local to the mod - ule with at least 1μF. The remainder of VOUT1+ to VOUT1– bypass caps should be located near channel 1’ s load. Either connect VOUT1+ to a PGND plane in inverting buck- boost applications, where VOUT1– is the regulated nega - tive output voltage—or , connect VOUT1– to a PGND plane noninverting step-down applications, where VOUT1+ is the regulated positive output voltage. PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y .

Rev. 0For more information www.analog.com VOSNS1+ ( G1, H1): Positive Voltage Sense Input for Channel 1. Route a signal trace from V OSNS1+ to VOUT1+ at channel 1’s point-of-load (POL). This provides the feed- back signal to channel 1’s control loop. In noisy environ- ments, shield VOSNS1+ from electrical noise by sandwich- ing the trace between PGND copper . Pins G1 and H1 are electrically connected to each other internal to the mod - ule, and thus it is only necessary to connect one VOSNS1+ pin to VOUT1+ at the POL. The remaining VOSNS1+ pin can be used for redundant connectivity or routed to an ICT test point for design-for-test considerations, as desired. VOUT2– (A10–12, B10, C10, D10–11, E10–11, F10–11, Negative Power Output of Channel 2. Either connect VOUT2– to a PGND plane in noninverting step-down appli- cations, where V OUT2+ is the regulated positive output voltage—or , connect VOUT2+ to PGND in inverting buck- boost applications, where VOUT2– is the regulated negative output voltage. SV OUT2– (E9, G7, H7): Signal Return of Channel 2. The SVOUT2– pins are the reference node for channel 2’s con- trol loop. A small island of SV OUT2– copper should be extended from the module and used to shield sensitive channel 2 pins and signals from noise— such as those routing to f SET2, ISET2a/b, and COMP2a/b. All SV OUT2– pins are connected to each other internal to the module. Connect Pin H7 to V OUT2– directly under the LTM4655. The remaining SVOUT2– pins can be used for redundant connectivity or routed to an ICT test point for design- for-test considerations, as desired. See the Applications Information section for the layout checklist. VOUT2+ (K6–8, L6–8, M6–8): Positive Power Output of Channel 2. Bypass V OUT2+ to V OUT2– local to the mod - ule with at least 1μF. The remainder of VOUT2+ to VOUT2– bypass caps should be located near channel 2’ s load. Either connect VOUT2+ to a PGND plane in inverting buck- boost applications, where VOUT2– is the regulated nega - tive output voltage—or , connect VOUT2– to a PGND plane noninverting step-down applications, where VOUT2+ is the regulated positive output voltage. VOSNS2+ ( G6, H6): Positive Voltage Sense Input for Channel 2. Route a signal trace from V OSNS2+ to VOUT2+ at channel 2’s point-of-load (POL). This provides the feed- back signal to channel 2’s control loop. In noisy environ- ments, shield VOSNS2+ from electrical noise by sandwich- ing the trace between PGND copper . Pins G6 and H6 are electrically connected to each other internal to the mod - ule, and thus it is only necessary to connect one V OSNS2+ pin to VOUT2+ at the POL. The remaining VOSNS2+ pin can be used for redundant connectivity or routed to an ICT test point for design-for-test considerations, as desired. GND (D4, D9, D12): Ground Pins. The logic thresholds for RUNn, PGOODn, and CLKINn are electrically referred to GND. GND is also the reference voltage for the 5V-fixed LDO and the CLKOUTn clock generator . Connect all GND pins to a solid ground plane, PGND. RUN1 (F4): Channel 1 Run Control Pin. A voltage above ~1.2V (with respect to GND) commands the module to regulate its output voltage. Undervoltage lockout (UVLO) can be implemented by connecting RUN1 to the midpoint node formed by a resistor divider between VIN1 and GND. RUN1 features ~130mV of hysteresis. RUN2 (F9): Channel 2 Run Control Pin. A voltage above ~1.2V (with respect to GND) commands the module to regulate its output voltage. Undervoltage lockout (UVLO) can be implemented by connecting RUN2 to the midpoint node formed by a resistor divider between VIN2 and GND. RUN2 features ~130mV of hysteresis. INTVCC1 (G3): Channel 1 Internal Regulator , 3.3V Output with Respect to VOUT1–. Channel 1 internal control circuits and MOSFET drivers derive power from INTV CC1 bias. Leave INTVCC1 open circuit. An LDO generates INTV CC1 from either SVIN1 or EXTVCC1, when RUN1 is logic high (RUN1–GND > 1.2V). The INTVCC1 LDO is turned off when RUN1 is logic low (RUN1–GND < 1.2V). (See EXTVCC1.) PIN FUNCTIONS

Rev. 0 For more information www.analog.com INTVCC2 (G8): Channel 2 Internal Regulator , 3.3V Output with Respect to VOUT2–. Channel 2 internal control circuits and MOSFET drivers derive power from INTV CC2 bias. Leave INTVCC2 open circuit. An LDO generates INTV CC2 from either SVIN2 or EXTVCC2, when RUN2 is logic high (RUN2–GND > 1.2V). The INTVCC2 LDO is turned off when RUN2 is logic low (RUN2–GND < 1.2V). (See EXTVCC2.) EXTVCC1 ( F3): External Bias, Auxiliary Input to the INTVCC1 Regulator . When EXTVCC1–VOUT1– > 3.2V and SVIN1 > 5V and RUN1– GND > 1.2V, the INTV CC1 LDO derives power from EXTVCC1 bias instead of SVIN1. This technique reduces LDO losses considerably, resulting in a corresponding reduction in module junction tempera - ture. For applications in which 4V < VOUT1+ – VOUT1– < 28V, connect EXTVCC1 to V OUT1+ through a 15Ω~110Ω resistor and locally decouple EXTV CC1 to V OUT1– with a 1μF ceramic capacitor . Otherwise, connect EXTV CC1 to VOUT1– or leave EXTVCC1 open circuit. See the Applications Information section. EXTVCC2 ( F8): External Bias, Auxiliary Input to the INTVCC2 Regulator . When EXTVCC2–VOUT2– > 3.2V and SVIN2 > 5V and RUN2– GND >1.2V, the INTV CC2 LDO derives power from EXTVCC2 bias instead of SVIN2. This technique reduces LDO losses considerably, resulting in a corresponding reduction in module junction tempera - ture. For applications in which 4V < V OUT2+ – VOUT2– < 28V, connect EXTVCC2 to V OUT2+ through a 15Ω~110Ω resistor and locally decouple EXTV CC2 to V OUT2– with a 1μF ceramic capacitor . Otherwise, connect EXTV CC2 to VOUT2– or leave EXTVCC2 open circuit. See the Applications Information section. ISET1b (F1): 1.5nF Soft-Start Capacitor for Channel 1. Connect ISET1b to ISET1a to achieve default soft-start characteristics on channel 1, if desired. See ISET1a. ISET2b (F6): 1.5nF Soft-Start Capacitor for Channel 2. Connect ISET2b to ISET2a to achieve default soft-start characteristics on channel 2, if desired. See ISET2a. ISET1a (F2): Accurate 50μA Current Source. Positive input to the error amplifier of channel 1. Connect a resis- tor R ISET1a = ((V OUT1+ – V OUT1–)/50μA) from this pin to SVOUT1– local to the module to program the desired channel 1 output voltage magnitude, VOUT1+ – VOUT1–. A capacitor can be connected from ISET1a to SV OUT1– to soft-start channel 1’s output voltage, i.e., reduce its start- up inrush current. Connect ISET1a to ISET1b in order to achieve default soft-start characteristics if desired. (See ISET1b.) In addition, the channel 1 output of the LTM4655 can track a voltage applied to this pin. (See the Applications Information section.) ISET2a (F7): Accurate 50μA Current Source. Positive input to the error amplifier of channel 1. Connect a resis- tor R ISET2a = ((V OUT2+ – V OUT2–)/50μA) from this pin to SVOUT2– local to the module to program the desired channel 2 output voltage magnitude, VOUT2+ – VOUT2–. A capacitor can be connected from ISET2a to SV OUT2– to soft-start channel 2’s output voltage, i.e., reduce its start- up inrush current. Connect ISET2a to ISET2b in order to achieve default soft-start characteristics if desired. (See ISET2b.) In addition, the channel 2 output of the LTM4655 can track a voltage applied to this pin. (See the Applications Information section.) PGOOD1 (D1): Channel 1 Power Good Indicator , Open- Drain Output Pin. PGOOD1 is high impedance when PGDFB1–SVOUT1– is within approximately ± 7.5% of 0.6V. PGOOD1 is pulled to GND when PGDFB1 is outside this range. PGOOD2 (D6): Channel 2 Power Good Indicator , Open- Drain Output Pin. PGOOD2 is high impedance when PGDFB2–SVOUT2– is within approximately ± 7.5% of 0.6V. PGOOD2 is pulled to GND when PGDFB2 is outside this range. PIN FUNCTIONS

Rev. 0For more information www.analog.com PGDFB1 ( D2): Channel 1 Power Good Feedback Programming Pin. Connect PGDFB1 to VOSNS1+ through a resistor , RPGDFB1. RPGDFB1 configures the voltage thresh- old of (VOUT1+ – VOUT1–) for which PGOOD1 toggles its state. If the PGOOD1 feature is used, set RPGDFB1 to: RPGDFB1 = VOUT1 + – VOUT1 Otherwise, leave PGDFB1 open circuit. A small filter capacitor (220pF) internal to the LTM4655 on this pin provides high frequency noise immunity for the PGOOD1 output indicator . PGDFB2 ( D7): Channel 2 Power Good Feedback Programming Pin. Connect PGDFB2 to VOSNS2+ through a resistor , RPGDFB2. RPGDFB2 configures the voltage thresh- old of (VOUT2+ – VOUT2–) for which PGOOD2 toggles its state. If the PGOOD2 feature is used, set RPGDFB2 accord- ing to Equation 2. RPGDFB2 = VOUT2 + – VOUT2 0.6V – 1

• 4.99k (2) Otherwise, leave PGDFB2 open circuit. A small filter capacitor (220pF) internal to the LTM4655 on this pin provides high frequency noise immunity for the PGOOD2 output indicator . f SET1 (E3): Channel 1 Oscillator Frequency Programming Pin. The default switching frequency of channel 1 is 400kHz. If needed, the programmed frequency can be increased by connecting a resistor between f SET1 and SVOUT1–. Keep fSET1-related trace lengths short. (See the Applications Information section.) Note the synchroniza- tion range of CLKIN1 is approximately ±40% of the oscil- lator frequency programmed by this fSET1 pin. fSET2 (E8): Channel 2 Oscillator Frequency Programming Pin. The default switching frequency of channel 2 is 400kHz. If needed, the programmed frequency can be increased by connecting a resistor between f SET2 and SVOUT2–. Keep fSET2-related trace lengths short. (See the Applications Information section.) Note the synchroniza- tion range of CLKIN2 is approximately ±40% of the oscil- lator frequency programmed by this fSET2 pin. CLKIN1 ( B1): Channel 1 Mode Select and Oscillator Synchronization Input. Referred to GND. Leave CLKIN1 open circuit for forced continuous mode operation. Alternatively, this pin can be driven so as to synchronize the switching frequency of channel 1 to a clock signal. In this condition, channel 1 operates in forced continu - ous mode and the cycle-by-cycle turn-on of its primary MOSFET is coincident with the rising edge of the clock applied to CLKIN1. Note the synchronization range of CLKIN1 is approximately ±40% of the oscillator frequency programmed by the f SET1 pin. (See the Applications Information section.) The LTM4655 contains a built-in dual 180° out-of-phase clock generator . Electrically con- nect CLKIN1 to CLKOUT1 with a short trace, if desired, to synchronize the switching frequency of channel 1 to CLKOUT1. If 0° phase interleaving is desired, connect CLKOUT1 to both CLKIN1 and CLKIN2. CLKIN2 ( B6): Channel 2 Mode Select and Oscillator Synchronization Input. Referred to GND. Leave CLKIN2 open circuit for forced continuous mode operation. Alternatively, this pin can be driven so as to synchronize the switching frequency of channel 2 to a clock signal. In this condition, channel 2 operates in forced continuous mode and the cycle-by-cycle turn-on of its primary MOSFET is coincident with the rising edge of the clock applied to CLKIN2. Note the synchronization range of CLKIN2 is approximately ±40% of the oscillator frequency programmed by the f SET2 pin. (See the Applications Information section.) The LTM4655 contains a built-in dual 180° out-of-phase clock generator. Electrically connect CLKIN2 to CLKOUT2 with a short trace, if desired, to synchronize the switching frequency of channel 2 to CLKOUT2. If 0° phase interleaving is desired, connect CLKOUT1 to both CLKIN1 and CLKIN2. PIN FUNCTIONS

Rev. 0 For more information www.analog.com COMP1a (E2): Current Control Threshold and Error Amplifier Compensation Node for Channel 1. The trip threshold of channel 1’ s current comparator increases with a respective rise in COMP1a voltage. A small filter cap (10pF) internal to the LTM4655 on this pin introduces a high frequency roll-off of the error amplifier response, yielding good noise rejection in the control loop. Often, COMP1a is electrically connected to COMP1b in one’s application, thus applying default loop compensation. Loop compensation (a series resistor capacitor) can be applied externally from COMP1a to SV OUT1–, if desired or needed, instead. (See COMP1b.) COMP2a (E7): Current Control Threshold and Error Amplifier Compensation Node for Channel 2. The trip threshold of channel 2’ s current comparator increases with a respective rise in COMP2a voltage. A small filter cap (10pF) internal to the LTM4655 on this pin introduces a high frequency roll-off of the error amplifier response, yielding good noise rejection in the control loop. Often, COMP2a is electrically connected to COMP2b in one’s application, thus applying default loop compensation. Loop compensation (a series resistor capacitor) can be applied externally from COMP2a to SV OUT2–, if desired or needed, instead. (See COMP2b.) COMP1b (E1): Channel 1 Internal Loop Compensation Network. For a majority of applications, the internal, default loop compensation of the LTM4655 is suitable to apply “as is”, and yields very satisfactory results: apply the default loop compensation to channel 1’s control loop by simply connecting COMP1a to COMP1b. When more specialized applications require a personal touch to the optimization of control loop response, this can be easily accomplished by connecting a series resistor-capacitor network from COMP1a to SVOUT1– and leaving COMP1b open circuit. COMP2b (E6): Channel 2 Internal Loop Compensation Network. For a majority of applications, the internal, default loop compensation of the LTM4655 is suitable to apply “as is”, and yields very satisfactory results: apply the default loop compensation to channel 2’s control loop by simply connecting COMP2a to COMP2b. When more specialized applications require a personal touch to the optimization of control loop response, this can be easily accomplished by connecting a series resistor-capacitor network from COMP2a to SVOUT2– and leaving COMP2b open circuit. IMON1a (C2): Channel 1 Power Inductor Current Analog Indicator Pin and Current Limit Programming Pin. In positive-VOUT step-down applications, only, the current flowing out of this pin is equal to 1/40,000 of the average channel 1 power inductor current. Optionally apply a par- allel resistor-capacitor network to this pin and terminate it to SV OUT1– in order to construct a voltage (V IMON1a– SVOUT1–) that is proportional to channel 1’s power induc- tor current. IMON1a can be connected to IMON1b if the default resis- tor capacitor termination network provided by IMON1b is desired. If this analog indicator feature is not desired— or , in negative-VOUT– buck-boost applications: connect IMON1a to SVOUT1–. If IMON1a–SVOUT1– exceeds a trip threshold of approxi- mately 2V, an IMON1 control loop servos channel 1 power inductor current accordingly and thus regulates IMON1a–SVOUT1– at 2V. In this manner , the current limit inception threshold of channel 1 can be configured. (See the Applications Information section.) IMON1b (C1): Channel 1 Power Inductor Analog Indicator Current Default Termination R-C Network. A 10k resis - tor in parallel with a 10nF capacitor and terminating to SVOUT1– connect to this pin. Connect IMON1b to IMON1a to achieve default power inductor analog indicator current characteristics: 1V (with respect to SVOUT1–) at full-scale (4A) load current in positive-V OUT, noninverting step- down applications. (See IMO N1a.) If unused, IMON1 b can be left open circuit or connected to SVOUT1–. PIN FUNCTIONS

Rev. 0For more information www.analog.com IMON2a (C7): Channel 2 Power Inductor Current Analog Indicator Pin and Current Limit Programming Pin. In positive-VOUT step-down applications, only, the current flowing out of this pin is equal to 1/40,000 of the average channel 2 power inductor current. Optionally apply a par- allel resistor-capacitor network to this pin and terminate it to SV OUT2– in order to construct a voltage (V IMON2a– SVOUT2–) that is proportional to channel 2’s power induc- tor current. IMON2a can be connected to IMON2b if the default resis- tor capacitor termination network provided by IMON2b is desired. If this analog indicator feature is not desired— or , in negative-VOUT– buck-boost applications: connect IMON2a to SVOUT2–. If IMON2a–SVOUT2– exceeds a trip threshold of approxi- mately 2V, an IMON2 control loop servos channel 2 power inductor current accordingly and thus regulates IMON2a–SVOUT2– at 2V. In this manner , the current limit inception threshold of channel 2 can be configured. (See the Applications Information section.) IMON2b (C6): Channel 2 Power Inductor Analog Indicator Current Default Termination R-C Network. A 10k resis - tor in parallel with a 10nF capacitor and terminating to SVOUT2– connect to this pin. Connect IMON2b to IMON2a to achieve default power inductor analog indicator current characteristics: 1V (with respect to SVOUT2–) at full-scale (4A) load current in positive-V OUT, noninverting step- down applications. (See IMO N2a.) If unused, IMON2 b can be left open circuit or connected to SVOUT2–. VINREG1 ( D3): Channel 1 Input Voltage Regulation Programming Pin. Optionally connect this pin to the midpoint node formed by a resistor divider between VD1 and VOUT1–. If VINREG1– SVOUT1– falls below approxi - mately 2V, a VINREG1 control loop servos the power inductor current accordingly and thus regulates VINREG1 at 2V with respect to SV OUT1–. (See the Applications Information section.) If this input voltage regulation feature is not desired on channel 1, connect VINREG1 to INTVCC1. VINREG2 ( D8): Channel 2 Input Voltage Regulation Programming Pin. Optionally connect this pin to the mid- point node formed by a resistor divider between VD2 and VOUT2–. If VINREG2–SV OUT2– falls below approximately 2V, a VINREG2 control loop servos the power inductor current accordingly and thus regulates VINREG2 at 2V with respect to SVOUT2–. (See the Applications Information section.) If this input voltage regulation feature is not desired on channel 2, connect VINREG2 to INTVCC2. TEMP+ (J6): Temperature Sensor , Positive Input. Emitter of a 2N3906-genre PNP bipolar junction transistor (BJT). Optionally interface to temperature monitoring circuitry such as L TC®2997, LTC2990, LTC2974 or LTC2975. Otherwise leave electrically open. TEMP– (J7): Temperature Sensor , Negative Input. Collector and base of a 2N3906-genre PNP bipolar junction tran - sistor (BJT). Optionally interface to temperature moni - toring circuitry such as LTC2997, LTC2990, LTC2974 or LTC2975. Otherwise leave electrically open. SW1 (H4): Switching Node of Channel 1 Switching Converter Stage. Used for test purposes. May be routed a short distance with a thin trace to a local test point to monitor switching action of the converter , if desired, but do not route near any sensitive signals; otherwise, leave electrically open circuit. SW2 (H9): Switching Node of Channel 2 Switching Converter Stage. Used for test purposes. May be routed a short distance with a thin trace to a local test point to monitor switching action of the converter , if desired, but do not route near any sensitive signals; otherwise, leave electrically open circuit. LDOOUT (G12): Output of the LTM4655’s GND Referenced 5V-Fixed LDO. No bypass capacitance is needed. Powers the clock generator internal to the LTM4655. Can deliver up to 25mA of current. PIN FUNCTIONS

Rev. 0 For more information www.analog.com CLKSET (F12): Clock Generator Frequency Setting Resistor Input. Apply a resistor , R CLKSET, between LDOOUT and CLKSET . The clock frequency of CLKOUT1 and CLKOUT2 is set by RCLKSET , according Equation 3. f(CLKOUT1, CLKOUT2) = 10MHz• 10kΩ RCLKSET(kΩ) (3) Resistor values between 32.2k and 400k are supported, corresponding to oscillator frequency settings of 3MHz to 250kHz, respectively. Minimize stray capacitance to this pin. CLKOUT1 (B2): Squarewave Output of Clock Generator for Channel 1. 180° out-of-phase from CLKOUT2. Minimize stray capacitance to this pin. Connect CLKOUT1 to CLKIN1, if desired, to synchronize channel 1 to CLKOUT1. If 0° phase interleaving is desired, connect CLKOUT1 to both CLKIN1 and CLKIN2. CLKOUT2 (B7, C12): Squarewave Output of Clock Generator for Channel 2. 180° out-of-phase from CLKOUT1. Minimize stray capacitance to these pins. Connect CLKOUT2 (pin B7, only) to CLKIN2, if desired, to synchronize channel 2 to CLKOUT2. If 0° phase inter- leaving is desired, connect CLKOUT1 to both CLKIN1 and CLKIN2. To disable spread spectrum frequency modulation (SFFM), connect CLKOUT2 (pin C12, only) to the MOD pin (pin E12) with a short trace. The CLKOUT2 pins at locations B7 and C12 are electri - cally connected together by a signal trace internal to the module. It is pinned out as described purely to facilitate routing of short traces to CLKIN2 and MOD. CLKOUT2 should be routed with minimal trace lengths. Minimize stray capacitance to these pins. MOD (E12): Modulation Setting Input. This three-state input selects among four modulation rate settings. The MOD pin should be tied to GND for the fOUT/16 modulation rate. Leaving the MOD pin open circuit selects the fOUT/32 modulation rate. The MOD pin should be electrically connected to LDO OUT for the f OUT/64 modulation rate. MOD pin (pin E12) turns the modulation off. Do not route high speed digital logic or signals with fast edges near MOD. Be advised that the f OUT/16, fOUT/32 and f OUT/64 modulation rates are not explicitly tested in factory ATE to demonstrate their stated typical modulation rates; the modulation off setting, however , is. NC (J1–2, J11–12): No Connect Pins, i.e., Pins with No Internal Connection. The NC pins predominantly serve to provide improved mounting of the module to the board. For drop-in compatibility of the LTM4651/LTM4653 into either half of a LTM4655 layout, these NC are recom - mended to be left electrically open circuit. PIN FUNCTIONS

Rev. 0For more information www.analog.com SIMPLIFIED BLOCK DIAGRAM (Only One Channel Shown Within Dotted Outlines) 4655 BD IL ÷ 40000 50µA 100/uni03A92V ERROR AMPLIFIER TO CURRENT COMPARATORS, PWM, AND FET-DRIVERS POWER CONTROL AND ANAOLG CIRCUITS COMPn BUFFER PGOOD LOGIC SVINFn 249k LDO 2.2/uni03BCF4.7nF GND 10k 10nF TERMINATE IMONa TO SVOUTn– WHEN REGULATING NEGATIVE V OUT– SVOUTn– LDOINSVINF1 OR SVINF2 IMONbn IMONan RfSETn fSETn 1/uni03BCF 10pF1.5nF 10nF VINREGn INTVCCn RISETn RISETn = VOUTn+ – VOUTn– 50µA COMPnb COMPna ISETnb ISETna EXTVCCn (REFERRED TO GND) CLKINn RUNn RUN – GND: >1.2VTYP = ON <1.07VTYP = OFF 50/uni03A9 CHANNEL n 0.1/uni03BCF 400nH BEAD 1/uni03A9 SVINFn CINHn CINLn SVINn VINn VDn SWn CDn 3.1V TO 40V (POSITIVE VOUT CONFIGURATION) 3.6V TO 40V – |VOUTn–| (NEGATIVE VOUT CONFIGURATION) PGOODn IS Hi-Z WHEN (PGDFB n–SVOUTn– ) IS WITHIN 0.6V ± 7.5% (CHANNEL n) 0.1/uni03BCF MTn MBn 4/uni03BCH 0.1/uni03BCF ILn VIN VOUTn+ VOUTn– VOSNSn+ VOUTn– SVOUTn– DOPT* OPTIONAL LOADn COUTHn GND (POSITIVE-VOUT CONFIGURATION) VOUTn– (NEGATIVE VOUT CONFIGURATION) UP TO – 0.5V DOWN TO (VINn – 40V), NOT BEYOND 26.5V BELOW GND UP TO 4A *IN NEGATIVE VOUT APPLICATIONS, APPL Y A SUITABLE SCHOTTKY DIODE (DOPT) IF IT IS IMPORTANT TO MINIMIZE THE AMPLITUDE OF REVERSE POLARITY ON VOUTn–’s START-UP WAVEFORM. SEE FIGURE 48 AND FIGURE 49. CLOCK OSCILLATOR TEMP– TEMP+ MOD CLKOUT2 CLKOUT1 CLKSET LDOOUT RCLKSET OPTIONALLY CONNECT TO CLKIN1 OPTIONALLY CONNECT TO CLKIN2 5V WITH RESPECT TO GND UP TO 25mA 4.99k 220pF RPGDFBnPGDFBn GND (NEGATIVE-VOUT CONFIGURATION) VOUTn+ (POSITIVE VOUT CONFIGURATION) UP TO 0.5V, UP TO 0.94 • VINn, UP TO 4A

Rev. 0 For more information www.analog.com TEST CIRCUIT Test Circuit 1. Positive-VOUT Configuration, Regulating VOUTn+, One Channel Shown Test Circuit 2. Negative-VOUT– Configuration, Regulating VOUTn–, One Channel Shown VINn SVINFn SVINn RUNn GND CLKINn VOUTn+ VOSNSn+ VOUTn– PGOODn EXTVCCn IMONna IMONnbISETnbISETna PGDFBn 24VOUT, UP TO 4A COUTLn 68µF COUTHn 27µF SVOUTn– RPGDFBn 196k RISETn 480k RfSETn 57.6k RTHn 499Ω CDn 4.7/uni03BCF CINHn 4.7/uni03BCF CTHn 0.1/uni03BCF VDn INTVCCn VINREGn

4655 TC01

RUN – GND: >1.2V TYP = ON <1.07V TYP = OFF PINS NOT SHOWN AND NOT TESTED IN THIS TEST CIRCUIT : LDO IN, LDOOUT, CLKOUTn, CLKSET , MOD, TEMP +, TEMP– ISETna ISETnb VINn SVINFn SVINn RUNn GND CLKINn V Dn INTVCCn VINREGn COMPna COMPnb fSETn PGOODn PGDFBn SVOUTn– VOUTn+ VOUTn– SVOUT– EXTVCCn L TM4655 VOUT– –24V UP TO 1.25A AT V IN = 12V COUTH 27µFLOAD COUTL* 68µF RPGDFB 196k RfSETn 57.6k RISETn 480k CDn 4.7/uni03BCF CINHn 4.7/uni03BCF VIN 3.6V TO 16V

4655 TC02

0.1/uni03BCF RTHn 499Ω CEXTVCCn 1/uni03BCF SWNC REXTVCCn** *Polarized output capacitors COUTL, if used, must be rated to withstand ~0.3V typical reverse polarity prior to L TM4655 start-up, stemming from a weakly forward-biased body diode. In such cases, a Schottky diode should be connected between PGND and V OUT– to limit the voltage. See the Applications Information section and Figures 49a and 49b. **Outside the ATE Test environment, REXTVCC, if used, should not be 0Ω. See the Applications Information section. RUNn RUN – GND: >1.2V TYP = ON <1.07V TYP = OFF PINS NOT SHOWN AND NOT TESTED IN THIS TEST CIRCUIT : LDO IN, LDOOUT, CLKOUTn, CLKSET , MOD, TEMP +, TEMP– IMONna IMONnb

Rev. 0For more information www.analog.com Test Circuit 3. Clock-Generator , 5V LDO and Temperature-Sensor TEST CIRCUIT APPLICATION SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Positive-VOUT Operation (Noninverting Step-Down) (Test Circuit 1) CINHn, CDn External High Frequency Input Capacitor Requirement, 27V ≤ V IN1–GND1 ≤40V, VOUT+ = 24V IOUT+ = 4A 9.4 μF COUTHn External High Frequency Output Capacitor Requirement 27V ≤ V IN1–GND1 ≤ 40V, VOUT+ = 24V IOUT+ = 4A 22 μF Negative-VOUT– Operation (Inverting Output Buck-Boost) (Test Circuit 2) C INHn, CDn External High Frequency Input Capacitor Requirement, 3.6V ≤V IN2–GND2 ≤ 16V, VOUT– = –24V IOUT– = 2A 9.4 μF COUTHn External High Frequency Output Capacitor Requirement 3.6V ≤ V IN2–GND2 ≤ 16V, VOUT– = –24V IOUT– = 2A 22 μF DECOUPLING REQUIREMENTS TA = 25°C. Refer to Test Circuit 1 and Test Circuit 2. L TM4655 0.1/uni03BCF VIN 4.5V TO 40V

4655 TC03

PINS NOT SHOWN AND NOT TESTED IN THIS TEST CIRCUIT : VINn, SVINn, SVINFn, VDn, RUNn, VOUTn+, VOSNSn+, VOUTn–, SVOUTn–, CLKINn, INTVCCn, EXTVCCn, VINREGn, COMPna, COMPnb, fSETn, ISETna, ISETnb, IMONna, IMONnb, PGDFBn, PGOODn, NC TEMP– LDOIN GND LDOOUT CLKSET CLKOUT1 CLKOUT2 MOD TEMP+ RCLKSET

Rev. 0 For more information www.analog.com OPERATION Power Module Overview The LTM4655 is a dual-channel non-isolated switch mode DC/DC power supply. Each channel is fully independent of the other . Each output can be configured for positive or negative polarity. A channel configured for positive- VOUT operation performs step-down DC/DC conversion and regulates a positive output voltage, VOUTn+. A chan- nel configured for negative-V OUT– operation performs two-switch buck-boost DC/DC conversion and regulates a negative output voltage, V OUTn– (this topology is also known as a ground-referred buck converter). An integrated LDO provides up to 25mA of output current at +5V (LDOOUT) with respect to GND. This LDO powers an internal 2-phase clock oscillator , yielding flexibility to operate the switching channels 180° out-of-phase from each other . A channel in positive-V OUT configuration (see Test Circuit 1) can deliver up to 4A output current with a few external input and output capacitors. Set by a single resis- tor , RISETn, an LTM4655 channel regulates a positive out- put voltage, VOUTn + VOUTn+ can be set to as low as 0.5V to as high as 26.5V of VINn. Channels in this positive-VOUT configuration can operate from a positive input supply rail, VINn, between 3.1V and 40V. The typical application schematic is shown in Figure 45. A channel in negative-V OUT– configuration (see Test Circuit 2) can deliver up to 4A output current with a few external input and output capacitors. The output current capability of the LTM4655 channel in this configuration is dependent on its VINn and VOUTn, as indicated in Figure 6. Set by a single resistor , R ISETn, the LTM4655 channel regulates a negative output voltage, V OUTn–. VOUTn– can be set to as low as –26.5V to as high as –0.5V. In this negative-VOUT configuration, an LTM4655 channel can operate from a positive input supply rail, V INn, between 3.6V and 40V. The LTM4655 channel’ s safe operating area is defined by: VINn + |V OUTn–| ≤ 40V. The typical application schematic is shown in Figure 48. Though an LTM4655 channel configured to regulate V OUTn– is a ground-referred buck topology, built-in level-shift cir - cuitry on the RUNn , CLKINn, and PGOODn pins result in these pins being conveniently referred to GND (not SVOUTn–). Each channel of the LTM4655 contains an independent, integrated constant-frequency current mode regulator , power MOSFETs, power inductor , EMI filter and other supporting discrete components. The nominal switching frequency range is from 400kHz to 3MHz, and the default operating frequency is 400kHz. Each channel can optionally be synchronized to its built-in clock oscillator CLKOUTn pins or to an externally applied clock, from 250kHz to 3MHz. See the Applications Information section. Each channel of the LTM4655 supports internal and external control loop compensation. Internal loop compensation is selected by connecting the COMPna and COMPnb pins. Using internal loop compensation, the LTM4655 has suf- ficient stability margins and good transient performance with a wide range of output capacitors— even ceramic- only output capacitors. For external loop compensation, see the Applications Information section. LTpowerCAD ® is available for transient load step and stability analysis. Input filter and noise cancellation circuitry reduces noise- coupling to the module’s inputs and outputs, ensuring the module’s electromagnetic interference (EMI) meets the limits of EN55022 Class B (see Figure 7 through Figure 9). Pulling the RUNn pin below 1.2V (with respect to GND) forces the corresponding LTM4655 channel into a shut - down state. A capacitor can be applied from ISETna to SVOUTn– to program the output voltage ramp rate; o r, the default LTM4655 ramp rate can be set by connect- ing ISETna to ISETnb; or , voltage tracking can be imple- mented by interfacing rail voltages to the ISETna pin. See the Applications Information section. Multiphase operation can be employed by connecting the CLKOUTn pins to their respective CLKINn pins—or , by connecting an external clock source to the LTM4655’s CLKINn pins. See the Typical Applications section. LDO losses within the module incurred primarily due to MOSFET driver power are optionally reduced by connect- ing EXTVCCn to VOUTn+ through an RC filter or by connect- ing EXTVCCn to a suitable voltage source. For channels configured for positive-VOUT operation, the IMONna pin is an analog output current indicator that sources a current proportional to its channel’s load current. (For channels configured for negative-VOUT– operation, the

Rev. 0For more information www.analog.com IMONna pin does not support such a feature and must be connected to VOUTn–.) When IMONna is electrically con- nected to IMONnb, the voltage on the IMONn a/IMONnb node is proportional to load current—with 1V correspond- ing to 4A load. If desired, IMONna can be interfaced to an external parallel RC network instead of the one provided by IMONnb. If IMONna ever exceeds 2V, a servo loop reduces the LTM4655’s output current in order to keep IMONn a at or below 2V. Through this servo mechanism, a parallel RC network can be connected to IMONna to implement an average current limit function—if desired. When the feature is not needed, connect IMONna to VOUTn–. The LTM4655 features an additional control pin called VINREGn, which has a 2V servo threshold. This pin can be used to as an extra control pin, e.g., to reduce channel input current draw during input line sag (“brownout”) conditions. Connect VINREGn to INTVCCn when this feature is not needed. TEMP+ and TEMP – pins give access to a diode-con - nected PNP transistor , making it possible to monitor the LTM4655’s internal temperature—if desired. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 11 and Table 12 and the Test Circuits for recom - mended external component values. VIN to VOUT Conversion Ratios There are restrictions on the VIN to VOUT conversion ratios that the LTM4655 can achieve. The maximum duty cycle of the LTM4655 is 96% typical. The V IN to V OUT mini- mum dropout voltage is a function of load current when operating in high duty cycle applications. As an example, VOUTn(24VDC) from the Electrical Characteristics table highlights the LTM4655’s ability to regulate 24VOUT at up to 4A from 29VIN, when running at a switching frequency, fSW, of 1.5MHz. At very low duty cycles, the LTM4655’s on-time of M T each switching cycle should be designed to exceed the LTM4655 control loop’ s specified minimum on-time of 60ns, tON(MIN), (guardband to 90ns) see Equation 4. Dn fSWn > TON(MIN)n (4) where Dn (unitless) is the duty-cycle of M Tn, given by Equation 5: Dn = VOUTn + −VOUTn VINn − −VOUTn − (5) In rare cases where the minimum on-time restriction is violated, the channel n frequency of the LTM4655 automatically and gradually folds back down to approxi- mately one-fifth of its programmed switching frequency to allow V OUT to remain in regulation. See the Frequency Adjustment section. Be reminded of Notes 2 and 3 in the Electrical Characteristics section regarding output current guidelines. Input Capacitors, Positive-VOUT Operation The LTM4655 achieves low input conducted EMI noise due to tight layout and high frequency bypassing of MOSFETs MTn and MBn within the module itself. A small filter inductor (400nH) is integrated in the input line (from VINn to VDn), providing further noise attenuation—again, local to the switching MOSFETs. The V Dn and VINn pins are available for external input capacitors—C Dn and CINHn—to form a high-frequency π filter . As shown in the Simplified Block Diagram, the ceramic capacitor CDn on the LTM4655’s V Dn pins handles the majority of the RMS current into the DC/DC converter power stage and requires careful selection, for that reason. See Figure 7 through Figure 9 for demonstration of LTM4655’s EMI performance, meeting the radiated emis- sions requirements of EN55022B. The input capacitance, CDn, is needed to filter the pulsed current drawn by MTn. To prevent excessive voltage sag on VDn, a low-effective series resistance (low-ESR, such as an X7R ceramic) input capacitor should be used, sized appropriately for the maximum C Dn RMS ripple current (Equation 6) ICDn(RMS) = IOUTn(MAX) ηn% • D n • (1–Dn) (6) where ηn% is the estimated efficiency of the chan - nel n power module. (See T ypical Performance Characteristics graphs.) OPERATION

Rev. 0 For more information www.analog.com Several capacitors may be paralleled to meet the appli - cation’s target size, height, and C Dn RMS ripple current rating. For lower input voltage applications, sufficient bulk input capacitance is needed to counteract line sag and transient effects during output load changes. The bulk capacitor can be a switcher-rated aluminum electrolytic capacitor or a Polymer capacitor . Suggested values for CDn and CINHn are found in Table 11. A final precaution regarding ceramic capacitors concerns the maximum input voltage rating of the LTM4655’s VINn, SVINn, and VDn pins. A ceramic input capacitor combined with trace or cable inductance forms a high Q (under - damped) tank circuit. If the LTM4655 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the device’ s rating. This situation is easily avoided ; see the Hot Plugging Safely section. Output Capacitors, Positive-VOUT Operation Output capacitors COUTHn and COUTLn are applied across the LTM4655’ s V OUTn+/VOUTn– power output pins. Sufficient capacitance and low ESR are called for , to meet the output voltage ripple, loop stability, and tran - sient requirements. C OUTLn can be a low ESR tantalum or polymer capacitor . COUTHn is a ceramic capacitor . The typical output capacitance is 22μF (type X5R material, or better), if ceramic-only output capacitors are used. Table 11 shows a matrix of suggested output capacitors optimized for 2A transient step-loads applied at 2A/μs. Additional output filtering may be required by the system designer , if further reduction of output ripple or dynamic transient spike is required. The L TpowerCAD design tool is available for transient and stability analysis. Stability crite- ria are considered in the Table 11 matrix, and L TpowerCAD is available for stability analysis. Multiphase operation will reduce effective output ripple as a function of the num - ber of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. L TpowerCAD can be used to calculate the output ripple reduction as the number of implemented phases increases by N times. External loop compensation can be applied from COMPna to SVOUTn–, if needed, for transient response optimization. Forced Continuous Operation Leave the CLKINn pin open circuit to command chan - nel n of the LTM4655 for forced continuous operation. In this mode, the control loop is allowed to command the inductor peak current to approximately –1A, allowing for significant negative average current. Clocking the CLKINn pin at a frequency within ±40% of the target switching fre- quency commanded by the fSETn pin synchronizes MTn’s turn-on to the rising edge of the CLKINn pin. Output Voltage Programming, T racking and Soft-Start The LTM4655 regulates its output voltage, VOUTn+ – VOUTn–, according to the differential voltage present from ISETna to SVOUTn–. In most applications, the output voltage is set by simply connecting a resistor , RISETn, from ISETna to SVOUTn–, according to Equation 7. RISETn = VOUTn + −VOUTn 50µA (7) Since the LTM4655 control loop servos its output voltage according to the voltage between ISETna and SV OUTn–: placing a capacitor , CSSn, parallel to RISETn configures the ramp-up rate of ISETna and thus the output. In the time domain, the output voltage ramp-up after the RUNn pin is toggled from low to high (t = 0s) is given by Equation 8. VOUTn(t)+ VOUTn(t)− =IISETna •RISETn • 1– e – t RISETn • CSSn (8) The soft-start time, tSS, is defined as the time it takes for channel n’s output voltage to ramp from 0V to 90% of its final value (Equation 9 or Equation 10) tSSn = –RISETn •CSSn •In (1– 0.9) (9) or tSSn = 2.3 • RISETn •CSSn (10) OPERATION

connect an external CSS capacitor parallel to RISET. according to the voltage commanded by ISETna. bipolar-output programmable power supply. ~2APK-PK. Choose fSWn according to Equation 11. where the value of LTM4655’s power inductor , Ln, is 4μH. ensure minimum on-time criteria is met (Equation 12).

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Figure 1. Relationship Between RfSETn and Target fSWn a resistor , RfSETn, between the f SETn pin and SV OUTn+. RfSETn is given (in MΩ) by Equation 13. binations of VINn, VOUTn+ and VOUTn–.

exceeded when this overtemperature protection is active. of the Electrical Characteristics table. control loop’s servo mechanism. the input supply to the RUNn pin, as shown in Figure 2.

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Figure 2. Undervoltage Lockout Resistive Divider VINn turn-off voltage, VINn(OFF) is given by Equation 15. SVOUTn– (paralleling the RTHn–CTHn series-RC network).

bypass capacitors (C Dn and C INHn) of the LTM4655. application board’s input connector , instead. VINn requirements of the module. Figure 3. Schottky Diode in Series with the Supply Figure 4. Schottky Diode from VOUTn+ to VINn

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is to prevent EXTVCCn overstress under a fault condition. VOUTn– with 1μF of X5R (or better) MLCC. of the target switching frequency set by fSETn. good current sharing as shown in Figure 45 and Figure 47. of each LTM4655 together to share the current evenly. proper start-up and shutdown behavior . common resistor on the ISETna net (see Equation 18). Figure 5. Normalized Input RMS Ripple Current vs Duty Cycle for

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INn) and output (VOUTn–) voltages. See Figure 6. For completeness, ∆InPK-PK is given by Equation 20. **Figure 6. Channel Output Current Capability*,** Table 1. See Notes 2 and 3.

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VOUTn– to remain in regulation. Figure 7. Radiated Emissions Scan of the LTM4655. Producing 24VOUT at 7A, from 36VIN. DC2898A Hardware. fSW = 1.2MHz. Figure 9. Radiated Emissions Scan of the LTM4655. Producing OUT at 4A, from 12VIN. DC2899A Hardware. fSW = 700kHz. Figure 8. Radiated Emissions Scan of the LTM4655. Producing OUT at 2A, from 12VIN , DC2899A Hardware. fSW = 1.2MHz. requires careful selection, for that reason. through Figure 9 for EMI performance.

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Rev. 0For more information www.analog.com The input capacitance, CDn, is needed to filter the pulsed current drawn by MTn. To prevent excessive voltage sag on VDn, a low-effective series resistance (low-ESR) input capacitor should be used, sized appropriately for the maximum CDn RMS ripple current (see Equation 24). ICDn(RMS) =InPK • D n • (1–Dn) (24) ICDn(RMS) is maximum for D n = 1/2. For D n = 1/2, ICDn(RMS) = 1/2 • InPK or 3A. This simplification of the worst-case condition is commonly used for design pur - poses because even significant deviations in D n do not offer much relief, in practice. Furthermore: note that ripple current ratings from capacitor manufacturers are often based on 2000 hours of life; therefore, it is advisable to significantly over-design CDn, and/or choose a capacitor rated at a higher temperature than required. Err on the side of caution and contact the capacitor manufacturer to understand the capacitor vendor’s derating methodology. Several capacitors may be paralleled to meet the appli - cation’s target size, height, and C Dn RMS ripple current rating. For lower input voltage applications, sufficient bulk input capacitance is needed for C INLn to counteract line sag and transient effects during output load changes. Suggested values for CDn and CINHn are found in Table 12. Take note that C Dn is connected from V Dn to V OUTn–, whereas C INHn and C INLn are connected from V INn to power ground; this is deliberate. A final precaution regarding ceramic capacitors concerns the maximum input voltage rating of the LTM4655’s VINn, SVINn, and VDn pins. A ceramic input capacitor combined with trace or cable inductance forms a high Q (under - damped) tank circuit. If the LTM4655 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the device’ s rating. This situation is easily avoided ; see the Hot Plugging Safely section. Output Capacitors, Negative-VOUT– Operation Output capacitors COUTHn and COUTLn are applied across the LTM4655’s VOUTn+/VOUTn– power output pins: suffi- cient capacitance and low ESR are called for , to meet the output voltage ripple, loop stability, and transient require- ments. COUTLn can be a low ESR tantalum or polymer capacitor . COUTHn is a ceramic capacitor . The typical out- put capacitance is 22μF (type X5R material, or better), if ceramic-only output capacitors are used. For highest reliability designs, polarized output capaci - tors (COUTLn) are not recommended, as there is a pos - sibility of a diode-drop of reverse voltage appearing tran- siently on VOUTn– during rapid application of input volt- age or when RUNn is toggled logic high (see Figure 49). When polarized capacitors are used on V OUTn–, contact the capacitor vendor to understand what reverse volt - age their polarized capacitor can withstand. Be advised, polarized capacitor reverse voltage rating is sometimes temperature-dependent. Output voltage ripple ( ∆VOUTn(PK-PK)–) is governed by charge lost in C OUTHn and C OUTLn while M Tn is on, in addition to the contribution of a resistive drop across the ESR of the output capacitors. This is expressed by Equation 25. ΔVOUTn(PK–PK) ≈ ILOADn •D COUTn • fSWn + ILOADn •ESRn Dn (25) T able 12 shows a matrix of suggested output capacitors optimized for transient step-loads that are 50% of the full load capability for that combination of V INn, VOUTn–, and fSW. The table optimizes total equivalent ESR and total bulk capacitance to yield the stated transient-load per - formance. Additional output filtering may be required by the system designer , if further reduction of output ripple or dynamic transient spike is required. The L TpowerCAD design tool is available for transient and stability analysis. Optional Diodes to Guard Against Overstress, Negative-V OUT– Operation Just prior to output voltage start-up, a mechanism exists whereby a diode-drop of reverse polarity can appear on V OUTn–. See the Simplified Block Diagram and observe: just prior to output voltage start-up, SV INn bias current (ISVINn) flows through the module’s control IC, to SVOUTn–; from there, the bias current (now I SVOUTn–) flows into VOUTn– and through MBn’s body diode, to SWn. This cur- rent (now ILn) continues to flow—though the 4μH power inductor—to VOUTn+ and thus ground, closing the con - trol IC bias circuit’s path. It is this current through MBn’s APPLICATIONS INFORMATION

excursion on VOUTn– is higher . (see Figure 48 circuit and Figure 49 performance). reduced by increasing output capacitance. excursions during VINn-discharge are anticipated. Table 1. Recommended Channel n Switching Frequency (fSWn) and RfSETn for Common Combinations of VINn and VOUTn–,

24 Drive CLKINn with a 200kHz

36 Not Recommended Due to

Rev. 0For more information www.analog.com Radiated EMI Noise The generation of radiated EMI noise is an inherent disadvantage of switching regulators. Fast switching turn-on and turn-off of the power MOSFETs—necessary for achieving high efficiency— create high-frequency (~30MHz+) ∆l/∆t changes within DC/DC converters. This activity tends to be the dominant source of high-frequency EMI radiation in such systems. The high level of device integration within LTM4655—including optimized gate- driver and critical front-end filter inductor— delivers low radiated EMI noise performance. Figure 7 through Figure 9 show typical examples of LTM4655 meeting the radiated emission limits established by EN55022 Class B. Thermal Considerations and Output Current Derating The thermal resistances reported in the Pin Configuration section are consistent with those parameters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board. The motivation for pro- viding these thermal coefficients is found in JESD51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the µModule regulator’s thermal performance in their appli - cation at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are, in and of themselves, not relevant to providing guidance of thermal performance; instead, the derating curves provided in this data sheet can be used in a manner that yields insight and guid - ance pertaining to one’ s application-usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section gives four thermal coeffi - cients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below APPLICATIONS INFORMATION 1. θJA, the thermal resistance from junction-to-ambient, is the natural convection junction-to-ambient air ther- mal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD51-9 defined test board, which does not reflect an actual application or viable operat- ing condition. θJCbottom, the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical µModule regulator , the bulk of the heat flows out the bottom of the pack - age, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 3. θJCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbottom, this value may be useful for comparing packages but the test condi - tions don’t generally match the user’s application. 4. θJB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resis - tance where almost all of the heat flows through the bottom of the µModule regulator and into the board, and is really the sum of the θ JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD51-9. A graphical representation of the aforementioned thermal resistances is given in Figure 10; blue resistances are contained within the µModule regulator , whereas green resistances are external to the µModule package.

airflow, a majority of the heat flow is into the board. values provided in the Pin Configuration section. Figure 10. Graphical Representation of JESD51-12 Thermal Coefficients

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an environment with temperature-controlled ambient. Table 2. Power Loss Multiplicative Factors vs Ambient

Table 11. Positive Output Voltage Response vs Component Matrix. Performance of a Channel of LTM4655 in Figure 51 Circuit, with

Table 12. Negative Output Voltage Response vs Component Matrix. Performance of Figure 48 Circuit with Values Here Indicated. *Internal loop compensation is used with Table 12 settings. COMPna connects to COMPnb in Figure 48. **To avoid violating minimum on-time criteria, drive CLKIN with a 200kHz, 50% duty cycle clock.

Figure 11. 12VIN Power Loss Figure 12. 24VIN Power Loss Curve Settings per Table 11 and Table 12. Figure 10. 12V

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Figure 13. 5V to 1VOUT Derating Figure 14. 12V to 1VOUT Figure 15. 24V to 1VOUT Figure 16. 5V to 1VOUT Derating Figure 17. 12V to 1VOUT Derating Figure 18. 24V to 1VOUT Derating Figure 19. 12V to 5VOUT

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APPLICATIONS INFORMATION—DERATING CURVESSettings per Table 11 and Table 12.

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Figure 20. 24V to 5VOUT Figure 21. 12V to 5VOUT Derating Figure 22. 24V to 5VOUT Derating Figure 23. 24V to 15VOUT Derating Figure 24. 24V to 15VOUT Derating

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Figure 25. –5VOUT Power Figure 26. –15VOUT Power Loss Figure 27. –24VOUT Power Figure 28. 5V to –5VOUT Derating

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Figure 31. 5V to –5VOUT Derating Figure 32. 12V to –5VOUT Derating Figure 33. 24V to –5VOUT Derating APPLICATIONS INFORMATION—DERATING CURVESSettings per Table 11 and Table 12.

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Figure 35. 12V to –15VOUT Figure 34. 5V to –15VOUT Figure 36. 24V to –15VOUT

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Figure 29. 12V to –5VOUT Figure 30. 24V to –5VOUT

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Figure 38. 12V to –15VOUT Derating Figure 39. 24V to –15VOUT Derating

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Figure 40. 5V to –24VOUT Derating Figure 41. 12V to –24VOUT Derating APPLICATIONS INFORMATION—DERATING CURVESSettings per Table 11 and Table 12.

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Figure 42. 5V to –24VOUT Derating Figure 43. 12V to –24VOUT Derating

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unit from catastrophic failure. much power the input voltage can deliver to this system.

• Use large PCB copper areas for high current paths, including VINn, VOUTn+ and VOUTn–. Doing so helps to minimize the PCB conduction loss and thermal stress. Place high frequency ceramic input and output (and, if used, input-to-output) capacitors next to the VINn, VDn, VOUTn+/VOUTn– pins to minimize high frequency noise. Place a dedicated power ground layer underneath the LT M4655.
• T o minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
• Do not put vias directly on pads, unless they are capped or plated over .
• For each channel, use a separate SVOUTn– copper plane for components connected to signal pins. Connect SVOUTn– to VOUTn– directly under the module.
• For parallel applications, connect the respective VOUTn+, VOUTn–, VOSNSn+, RUNn, ISETna, COMPna, PGOODn and IMONna pins, accordingly (see Figure 45). Bring out test points on the signal pins for monitoring. Figure 44 gives a good example of the recommended LTM4655 layout.

Figure 44. Recommended PCB Layout, Package Top View

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Figure 45. Single 8A, 24V Output DC/DC μModule Regulator with Optional Analog Temperature Indicator

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• PLACE 470pF DIRECTL Y ACROSS THE L TC2997'S D+/D– PINS.

ROUTE TEMP+/TEMP– DIFFERENTIALL Y TO D+/D– AND PROTECT FROM NOISE WITH GROUND SHIELDING. TERMINATE (CONNECT) THE D+/D– GROUND SHIELD AT THE L TC2997 GND PIN, ONL Y. FOR BEST VPTAT PERFORMANCE, THE VCC PIN OF THE L TC2997 MUST BE LOCALL Y BYPASSED AND QUIET . SEE L TC2997 DATA SHEET AND APRIL 2017 L T JOURNAL TECHNICAL ARTICLES.

Figure 46. Start-Up Waveforms at 36VIN, Figure 45 Circuit Figure 47. Current Sharing Performance of LTM4655 Channels in Figure 45 Circuit

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Figure 48. 1.25A, –24V Output DC/DC μModule Regulator

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Figure 49. Start-Up Waveforms at 12VIN, Figure 48 Circuit (a) Start-up Performance with D1 Not Installed.

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(b) Start-up Performance with D1 Installed.

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Figure 50. Concurrent ±12V Output DC/DC μModule Regulator

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Figure 51. Dual 4A, 12V and 5V Output DC/DC μModule Regulator

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Figure 52. A DAC-Controlled Bipolar-Output Programmable Power Supply

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Table 13. LTM4655 Component BGA Pinout

Rev. 0For more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION 144-Lead (16mm × 16mm × 5.01mm) (Reference L TC DWG # 05-08-1551 Rev Ø) PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES D E b e e b F G BGA 144 0816 REV Ø TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule DETAIL A PIN 1 A B C D E F G HK JL M SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.0000 0.630 ±0.025 Ø 144x 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 DETAIL A Øb (144 PLACES) A DETAIL B PACKAGE SIDE VIEW Z M X Y Z ddd M Z eee DETAIL B SUBSTRATE ccc Z MOLD CAP SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 4.81 0.50 4.31 0.60 0.60 0.36 3.95 NOM 5.01 0.60 4.41 0.75 0.63 16.00 16.00 1.27 13.97 13.97 0.41 4.00 MAX 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 NOTES BALL DIMENSION PAD DIMENSION DIMENSIONS TOTAL NUMBER OF BALLS: 144 // bbb Z Z NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS. DRAWING NOT TO SCALE BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES

µModule Design and Manufacturing Resources Design:

• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation T ools Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability µModule Regulator Products Sear ch 1. Sort table of products by parameters and download the result as a spread sheet. Sear ch using the Quick Power Search parametric table. Digital Power System Management Analog Devices’ family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. LTM4655 Rev. 0 For more information www.analog.com  ANALOG DEVICES, INC. 2021 www.analog.com RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTM4651 EN55022B Compliant 58VIN, 24W Inverting-Output DC/DC μModule Regulator 3.6V ≤ VIN ≤ 58V, –26.5V ≤ VOUT ≤ –0.5V, IOUT ≤ 4A, 15mm × 9mm × 5.01mm BGA LT M4653 EN55022B Compliant 58VIN, 4A Step-Down DC/DC μModule Regulator 3.1V ≤ VIN ≤ 58V, 0.5V ≤ VOUT ≤ 0.94V • VIN, 15mm × 9mm × 5.01mm BGA LT M8045 SEPIC or Inverting µModule DC/DC Converter 2.8V ≤ VIN ≤ 18V, ±2.5V ≤ VOUT ≤ ±15V. IOUT(DC) ≤ 700mA, 6.25mm × 11.25mm × 4.92mm BGA LT M8053 40V, Dual 3.5A Silent Switcher Step-Down µModule Regulator 3.4V ≤ V IN ≤ 40V, 0.97V ≤ VOUT ≤ 15V, 6.25mm × 9mm × 3.32mm BGA LT M8024 40V, 3.5A Silent Switcher Step-Down µModule Regulator 3V ≤ V IN ≤ 40V, 0.8V ≤ VOUT ≤ 8V, 9mm × 11.25mm × 3.32mm BGA LT M8049 Dual, SEPIC and/or Inverting µModule DC/DC Converter 2.6V ≤ VIN ≤ 20V, ±2.5V ≤ VOUT ≤ ±24V. IOUT(DC) ≤ 1A/Channel, 9mm × 15mm × 2.42mm BGA LT M8071 60V, 5A Silent Switcher Step-Down µModule Regulator 3.6V ≤ VIN ≤ 60V, 0.97V ≤ VOUT ≤ 15V, 6.25mm × 9mm × 3.32mm BGA LT M8073 60V, 3A Silent Switcher Step-Down µModule Regulator 3.4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 15V, 9mm × 11.25mm × 3.32mm BGA PACKAGE PHOTOGRAPH