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For more information www.linear .com/L TM4616
FEATURES
APPLICATIONS
DESCRIPTION
VIN DC/DC µModule Regulator The LT M®4616 is a complete dual 2-phase 8A per channel switch mode DC/DC power regulator system in a 15mm × 15mm surface mount LGA or BGA package. Included in the package are the switching controller, power FETs, inductor and all support components. Operating from an input voltage range of 2.7V to 5.5V, the LTM4616 supports two outputs within a voltage range of 0.6V to 5V, each set by a single external resistor. This high efficiency design delivers up to 8A continuous current (10A peak) for each output. Only bulk input and output capacitors are needed, depending on ripple requirement. The part can also be configured for a 2-phase single output at up to 16A. The low profile package enables utilization of unused space on the back side of PC boards for high density point-of- load regulation. Fault protection features include overvoltage protection, overcurrent protection and thermal shutdown. The power module is offered in space saving and thermally enhanced 15mm × 15mm × 2.82mm LGA and 15mm × 15mm × 3.42mm BGA packages. The LTM4616 is RoHS compliant with Pb-free finish. Different Combinations of Input and Output Number of Inputs Number of Outputs IOUT (MAX) 2 2 8A, 8A 2 1 16A 1 2 8A, 8A 1 1 16A Dual Output DC/DC µModule® Regulator n Complete Dual DC/DC Regulator System n Input Voltage Range: 2.7V to 5.5V n Dual 8A Outputs, or Single 16A Output with a 0.6V to 5V Range n Output Voltage T racking and Margining n ±1.75% Total DC Output Error (–55°C to 125°C) n Current Mode Control/Fast T ransient Response n Power Good T racking and Margining n Overcurrent/Thermal Shutdown Protection n Onboard Frequency Synchronization n Spread Spectrum Frequency Modulation n Multiphase Operation n Selectable Burst Mode® Operation n Output Overvoltage Protection n RoHS Compliant with Pb-Free Finish, Gold Finish LGA (e4) or SAC 305 BGA (e1) n Small Surface Mount Footprint, Low Profile (15mm × 15mm × 2.82mm) LGA and (15mm × 15mm × 3.42mm) BGA Packages n Telecom, Networking and Industrial Equipment n Storage and ATCA, PCI Express Cards n Battery Operated Equipment Efficiency vs Load CurrentTYPICAL APPLICATION L, LT, LT C, LT M, Linear Technology, the Linear logo, Burst Mode, µModule and PolyPhase are registered trademarks and L TpowerCAD is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6724174. 3.09k 100µF10µF VIN2 3.3V TO 5V VOUT2 2.5V/8A VIN1 VIN2 VOUT1 FB1 ITHM1 VOUT2 FB2 ITHM2 GND1 GND2
4616 TA01a
L TM4616 2.21k 100µF10µF VIN1 5V VOUT1 3.3V/8A LOAD CURRENT (A) EFFICIENCY (%) 2 4 6
4616 TA01b
5VIN 3.3VOUT 5VIN 2.5VOUT
For more information www.linear .com/L TM4616 PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGSABSOLUTE MAXIMUM RATINGS PGOOD1, PLLLPF1, CLKIN1, PHMODE1, MODE1, PGOOD2, PLLLPF2, CLKIN2, ITH1, ITHM1, RUN1, FB1, TRACK1, MGN1, BSEL1, ITH2, ITHM2, RUN2, FB2, TRACK2, Internal Operating Temperature Range (Note 2) (Note 1)(Note 1) LGA PACKAGE 144-LEAD (15mm × 15mm × 2.82mm) TOP VIEW VIN2 VOUT2ITH2 1 2 3 4 5 6 7 8 10 9 11 12 L K J H G F E D C B M A MODE1CLKIN1 PHMODE1 VOUT1 GND2 GND1 VIN1 SVIN1 SGND2 RUN2 SGND1 PLLLPF2 SW2 CLKOUT2 SW1 CLKIN2 PLLLPF1 BSEL2 RUN1 BSEL1 SVIN2 TRACK1 ITHM2 FB1 MODE2 ITHM1 CLKOUT1 PGOOD1 TRACK2 PHMODE2 ITH1 MGN1 PGOOD2 MGN2 FB2 TJMAX = 125°C, θJA = 10.5°C/W, θJCbottom = 2°C/W, θJCtop = 16°C/W, WEIGHT = 1.8g θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS BGA PACKAGE 144-LEAD (15mm × 15mm × 3.42mm) TOP VIEW VIN2 VOUT2ITH2 1 2 3 4 5 6 7 8 10 9 11 12 L K J H G F E D C B M A MODE1CLKIN1 PHMODE1 VOUT1 GND2 GND1 VIN1 SVIN1 SGND2 RUN2 SGND1 PLLLPF2 SW2 CLKOUT2 SW1 CLKIN2 PLLLPF1 BSEL2 RUN1 BSEL1 SVIN2 TRACK1 ITHM2 FB1 MODE2 ITHM1 CLKOUT1 PGOOD1 TRACK2 PHMODE2 ITH1 MGN1 PGOOD2 MGN2 FB2 TJMAX = 125°C, θJA = 10.5°C/W, θJCbottom = 2°C/W, θJCtop = 16°C/W, WEIGHT = 2.0g θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE (NOTE 2) LTM4616EV#PBF LTM4616EV#PBF LTM4616V 144-Lead (15mm × 15mm × 2.82mm) LGA –40°C to 125°C LTM4616IV#PBF LTM4616IV#PBF LTM4616V 144-Lead (15mm × 15mm × 2.82mm) LGA –40°C to 125°C LTM4616MPV#PBF LTM4616MPV#PBF LTM4616V 144-Lead (15mm × 15mm × 2.82mm) LGA –55°C to 125°C LTM4616EY#PBF LTM4616EY#PBF LTM4616Y 144-Lead (15mm × 15mm × 3.42mm) BGA –40°C to 125°C LTM4616IY#PBF LTM4616IY#PBF LTM4616Y 144-Lead (15mm × 15mm × 3.42mm) BGA –40°C to 125°C LTM4616MPY#PBF LTM4616MPY#PBF LTM4616Y 144-Lead (15mm × 15mm × 3.42mm) BGA –55°C to 125°C Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ ORDER INFORMATION
For more information www.linear .com/L TM4616 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). TA = 25°C, VIN = 5V unless otherwise noted. Per the typical application in Figure 18. Specified as each channel (Note 3). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN1(DC), VIN2(DC) Input DC Voltage l 2.7 5.5 V VOUT1(DC), VOUT2(DC) Output Voltage, Total Variation with Line and Load CIN = 10µF × 1, COUT = 100µF Ceramic, 100µF POSCAP, RFB = 6.65k, MODE = 0V VIN = 2.7V to 5.5V, IOUT = IOUT(DC)MIN to IOUT(DC)MAX (Note 4) l 1.472 1.464 1.49 1.49 1.508 1.516 V V Input Specifications VIN1(UVLO), VIN2(UVLO) Undervoltage Lockout Threshold SVIN Rising SVIN Falling 2.05 1.85 2.2 2.0 2.35 2.15 V V I Q(VIN1, VIN2) Input Supply Bias Current VIN = 3.3V, VOUT = 1.5V, No Switching, MODE = VIN VIN = 3.3V, VOUT = 1.5V, No Switching, MODE = 0V VIN = 3.3V, VOUT = 1.5V, Switching Continuous 400 1.15 µA mA mA V IN = 5V, VOUT = 1.5V, No Switching, MODE = VIN VIN = 5V, VOUT = 1.5V, No Switching, MODE = 0V VIN = 5V, VOUT = 1.5V, Switching Continuous 450 1.3 µA mA mA Shutdown, RUN = 0, V IN = 5V 1 µA IS(VIN1, VIN2) Input Supply Current VIN = 3.3V, VOUT = 1.5V, IOUT = 8A VIN = 5V, VOUT = 1.5V, IOUT = 8A 4.5 2.93 A A Output Specifications I OUT1(DC), IOUT2(DC) Output Continuous Current Range VOUT = 1.5V (Note 4) VIN = 3.3V, 5.5V VIN = 2.7V A A ΔV OUT1(LINE)/VOUT1 ΔVOUT2(LINE)/VOUT2 ΔVOUT1(LOAD)/VOUT1 ΔVOUT2(LOAD)/VOUT2 Load Regulation Accuracy VOUT = 1.5V (Note 4) VIN = 3.3V, 5.5V, ILOAD = 0A to 8A VIN = 2.7V, ILOAD = 0A to 5A l l 0.3 0.3 0.5 0.5 V OUT1(AC), VOUT2(AC) Output Ripple Voltage IOUT = 0A, COUT = 100µF X5R Ceramic, VIN = 5V, VOUT = 1.5V mVP-P fS1, fS2 Switching Frequency IOUT = 8A, VIN = 5V, VOUT = 1.5V 1.25 1.5 1.75 MHz fSYNC1, fSYNC2 SYNC Capture Range 0.75 2.25 MHz ΔVOUT1(START), ΔVOUT2(START) Turn-On Overshoot COUT = 100µF, VOUT = 1.5V, IOUT = 0A VIN = 3.3V VIN = 5V mV mV t START1, tSTART2 Turn-On Time COUT = 100µF, VOUT = 1.5V, VIN = 5V, IOUT = 1A Resistive Load, T rack = VIN 100 µs ΔVOUT1(LS), ΔVOUT2(LS) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load, C OUT = 100µF Ceramic x2, 470µF POSCAP, VIN = 5V, VOUT = 1.5V 20 mV tSETTLE1, tSETTLE2 Settling Time for Dynamic Load Step Load : 0% to 50% to 0% of Full Load, VIN = 5V, VOUT = 1.5V, COUT = 100µF 10 µs IOUT1(PK), IOUT2(PK) Output Current Limit COUT = 100µF VIN = 2.7V, VOUT = 1.5V VIN = 3.3V, VOUT = 1.5V VIN = 5V, VOUT = 1.5V A A A
For more information www.linear .com/L TM4616 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). TA = 25°C, VIN = 5V unless otherwise noted. Per the typical application in Figure 18. Specified as each channel (Note 3). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Control Section FB1, FB2 Voltage at FB Pin IOUT = 0A, VOUT = 1.5V, VIN = 2.7V to 5.5V l 0.590 0.587 0.596 0.596 0.602 0.606 V V SS Delay Internal Soft-Start Delay 90 µs I FB1, IFB2 0.2 µA VRUN1, VRUN2 RUN Pin On/Off Threshold RUN Rising RUN Falling 1.4 1.3 1.55 1.4 1.7 1.5 V V TRACK1, TRACK2 T racking Threshold (Rising) T racking Threshold (Falling) T racking Disable Threshold RUN = VIN RUN = 0V 0.57 0.18 V IN – 0.5 V V V R FBHI1, RFBHI2 Resistor Between VOUT and FB Pins 9.95 10 10.05 kΩ ΔVPGOOD1, ΔVPGOOD2 PGOOD Range ±10 % IPGOOD1, IPGOOD2 PGOOD Leakage Current VPGOOD = VIN = 2.7V to 5.5V, IOUT = IOUT(DC)MAX (Note 4) l 20 30 µA VPGL1, VPGL2 PGOOD Voltage Low IPGOOD = 5mA 0.2 0.4 V %Margining Output Voltage Margining Percentage MGN = V IN, BSEL = 0V MGN = VIN, BSEL = VIN MGN = VIN, BSEL = Float MGN = 0V, BSEL = 0V MGN = 0V, BSEL = VIN MGN = 0V, BSEL = Float –14 –10 –15 –11 –16 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4616 is tested under pulsed load conditions, such that TJ ≈ TA. The LTM4616E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4616I is guaranteed to meet specifications over the –40°C to 125°C internal operating temperature range. The LTM4616MP is guaranteed and tested over the –55°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: Tw o channels are tested separately and the same testing conditions are applied to each channel. Note 4: See Output Current Derating curves for different VIN, VOUT and TA.
For more information www.linear .com/L TM4616 VIN (V) VOUT (V) 1.5 2.0 2.5 3 5
4616 G06
1.0 0.5 3.0 3.5 4.0 IOUT = 6A VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V VIN (V) VOUT (V) 1.5 2.0 2.5 3 5
4616 G05
1.0 0.5 3.0 3.5 4.0 IOUT = 8A VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Load Current Burst Mode Efficiency with 5V Input VIN to VOUT Step-Down Ratio Supply Current vs VIN Load T ransient Response Load T ransient Response Efficiency vs Load Current Efficiency vs Load Current LOAD CURRENT EFFICIENCY (%) 100 2 4 6 8
4616 G01
5VIN 1.2VOUT 5VIN 1.5VOUT 5VIN 1.8VOUT 5VIN 2.5VOUT 5VIN 3.3VOUT CONTINUOUS MODE LOAD CURRENT EFFICIENCY (%) 100 2 4 6 8
4616 G02
3.3VIN 1.2VOUT 3.3VIN 1.5VOUT 3.3VIN 1.8VOUT 3.3VIN 2.5VOUT CONTINUOUS MODE LOAD CURRENT (A) EFFICIENCY (%) 100 2 4 5
4616 G03
2.7VIN 1.0VOUT 2.7VIN 1.5VOUT 2.7VIN 1.8VOUT CONTINUOUS MODE VIN to VOUT Step-Down Ratio LOAD CURRENT (A) EFFICIENCY (%)60 100 0.2 0.4 0.6 0.8
4616 G04
VOUT = 1.5V VOUT = 2.5V VOUT = 3.3V INPUT VOL TAGE (V) 2.5 SUPPL Y CURRENT (mA) 4.5 1.6 1.4 1.2 0.8 0.6 0.4 0.2
4616 G07
3.5 3 54 5.5 VO = 1.2V PULSE-SKIPPING MODE VO = 1.2V Burst Mode OPERATION ILOAD 1A/DIV VOUT 50mV/DIV 20µs/DIVVIN = 5V VOUT = 3.3V 2A/µs STEP COUT = 2 × 100µF X5R, 470µF 4V POSCAP
4616 G08
20µs/DIVVIN = 5V VOUT = 2.5V 2A/µs STEP C OUT = 2 × 100µF X5R, 470µF 4V POSCAP
4616 G09
For more information www.linear .com/L TM4616 TEMPERATURE (°C) –50 VFB (mV) 592 594 596 25 75 100
4616 G14
–25 0 50 598 600 602 125 VIN = 5.5V VIN = 3.3V VIN = 2.7V Start-Up VFB vs Temperature Load Regulation vs Current 2.5V Output Current Short-Circuit Protection (2.5V Short, No Load) VOUT 0.5V/DIV VIN 2V/DIV 50µs/DIVVIN = 5V VOUT = 1.5V COUT = 100µF NO LOAD AND 8A LOAD (DEFAUL T 100µs SOFT-START)
4616 G13
LOAD CURRENT (A) –0.6 LOAD REGULATION (%) –0.5 –0.2 –0.3 –0.1 2 4 –0.4 6 8
4616 G15
VIN = 3.3V VOUT = 1.5V Short-Circuit Protection (2.5V Short, 4A Load) OUTPUT CURRENT (A) OUTPUT VOLTAGE (V) 0.5 1.0 1.5 2.0 2.5 3.0 5 10 15 20
4616 G16
50µs/DIV
4616 G17
VIN = 5V VOUT = 2.5V 5V/DIV 5V/DIV 5A/DIV 50µs/DIV
4616 G18
VIN = 5V VOUT = 2.5V TYPICAL PERFORMANCE CHARACTERISTICSSpecified as Each Channel Load T ransient Response Load T ransient Response Load T ransient Response ILOAD 1A/DIV VOUT 50mV/DIV 20µs/DIVVIN = 5V VOUT = 1.8V 2.5A/µs STEP COUT = 2 × 100µF X5R, 470µF 4V POSCAP
4616 G10
20µs/DIVVIN = 5V VOUT = 1.5V 2.5A/µs STEP C OUT = 2 × 100µF X5R, 470µF 4V POSCAP
4616 G11
20µs/DIVVIN = 5V VOUT = 1.2V 2.5A/µs STEP C OUT = 2 × 100µF X5R, 470µF POSCAP
4616 G12
For more information www.linear .com/L TM4616 PLLLPF1 and PLLLPF2 (E6 and L6): Phase-Locked Loop Lowpass Filter for Each Channel. An internal lowpass filter is tied to this pin. In spread spectrum mode, placing a capacitor here to SGND controls the slew rate from one frequency to the next. Alternatively, floating this pin allows normal running frequency at 1.5MHz, tying this pin to SVIN forces the part to run at 1.33 times its normal frequency (2MHz), tying it to ground forces the frequency to run at 0.67 times its normal frequency (1MHz). PHMODE1 and PHMODE2 (A9 and G9): Phase Selector Input for Each Channel. This pin determines the phase relationship between the internal oscillator and CLKOUT. Tie it high for 2-phase operation, tie it low for 3-phase operation, and float or tie it to VIN/2 for 4-phase operation. MGN1 and MGN2 (A 10 and G10): Voltage Margining Pin for Each Channel. Increases or decreases the output voltage by the amount specified by the BSEL pin. To disable margining, tie the MGN pin to a voltage divider with 50k resistors from VIN to ground ( see Figure 5). For margining, connect a voltage divider from VIN to GND with the center point connected to the MGN pin for the spe- cific channel. Each resistor should be close to 50k. Margin High is within 0.3V of VIN, and Margin Low is within 0.3V of GND. See the Applications Information section and Figure 18 for margining control. The specified tri-state drivers are capable of the high and low requirements for margining. BSEL1 and BSEL2 (A6 and G6): Margining Bit Select Pin for Each Channel. Tying BSEL low selects ±5% margin value, tying it high selects 10% margin value. Floating it or tying it to VIN/2 selects 15% margin value. TRACK1 and TRACK2 (E8 and L8): Output Voltage T racking Pin for Each Channel. Voltage tracking is enabled when the TRACK voltage is below 0.57V. If tracking is not desired, then connect the TRACK pin to SVIN. If TRACK is not tied to SVIN, then the TRACK pin’s voltage needs to be below 0.18V before the chip shuts down even though RUN is VIN1, VIN2, (BANK1 and BANK2); (F1-F4, E1-E4, C1-C2, D1-D2) and (J1-J2, K1-K2, L1-L4, M1-M4): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between VIN pins and GND pins. VOUT1, VOUT2 (BANK3 and BANK6); (D9-D12, E9-E12, F9-F12) and (K9-K12, L9-L12, M9-M12): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. See Table 1. GND1 and GND2 (BANK2 and BANK5); (A1-A5, A12, B1- B5, B7-B12, C3-C12, D3-D7) and (G1-G5, G12, H1-H5, H7-H12, J3-J12, K3-K7): Power Ground Pins for Both Input and Output Returns. SV IN1 and SVIN2 (E5 and L5): Signal Input Voltage for Each Channel. This pin is internally connected to VIN through a lowpass filter. SGND1 and SGND2 (F5 and M5): Signal Ground Pin for Each Channel. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the application. See layout guidelines in Figure 17. MODE1 and MODE2 (A8 and G8): Mode Select Input for Each Channel. Tying this pin high enables Burst Mode operation. Tying this pin low enables forced continuous operation. Floating this pin or tying it to VIN/2 enables pulse-skipping operation. CLKIN1 and CLKIN2 (A7 and G7): External Synchroniza- tion Input to Phase Detector for Each Channel. This pin is internally terminated to SGND with a 50k resistor. The phase-locked loop will force the internal top power PMOS turn on to be synchronized with the rising edge of the CLKIN signal. Connect this pin to SVIN to enable spread spectrum modulation. During external synchronization, make sure the PLLLPF pin is not tied to VIN or GND. PIN FUNCTIONS
For more information www.linear .com/L TM4616 PIN FUNCTIONS already low. Do not float this pin. A resistor and capacitor can be applied to the TRACK pin to increase the soft-start time of the regulator. TRACK1 and TRACK2 can be tied together for parallel operation and tracking. See the Ap- plications Information section. FB1 and FB2 (D8 and K8): The Negative Input of the Error Amplifier for Each Channel. Internally, this pin is connected to VOUT with a 10k precision resistor. Different output voltages can be programmed with an additional resistor between FB and GND pins. In PolyPhase® operation, tying the FB pins together allows for parallel operation. See the Applications Information section for details. I TH1 and ITH2 (F8 and M8): Current Control Threshold and Error Amplifier Compensation Point for Each Channel. The current comparator threshold increases with this control voltage. Tie together in parallel operation. ITHM1 and ITHM2 (E7 and L7): Negative Input to the Internal ITH Differential Amplifier for Each Channel. Tie this pin to SGND for single phase operation on each channel. For PolyPhase operation, tie the master’s ITHM to SGND while connecting all of the ITHM pins together at the master. PGOOD1 and PGOOD2 (A11 and G11): Output Voltage Power Good Indicator for Each Channel. Open-drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point. Power good is disabled during margining. RUN1 and RUN2 (F6 and M6): Run Control Pin. A voltage above 1.7V will turn on the module. SW1 and SW2 (B6 and H6): Switching Node of Each Channel That is Used for Testing Purposes. This can be connected to an electronically open circuit copper pad on the board for improved thermal performance. CLKOUT1 and CLKOUT2 (F7 and M7): Output Clock Signal for PolyPhase Operation. The phase of CLKOUT is determined by the state of the PHMODE pin.
Figure 1. Simplified LTM4616 Block Diagram
Table 1. Decoupling Requirements. TA = 25°C, Block Diagram Configuration. 8A outputs with few external input and output capacitors. schematic is shown in Figure 18. be externally synchronized from 0.75MHz to 2.25MHz. limit and thermal shutdown in an overcurrent condition. The power good pins are disabled during margining. plications Information section. light load features will accommodate battery operation. the Typical Performance Characteristics section. gramed from ±5% to ±15% using the MGN and BSEL pins.
Figure 18. External component selection is primarily requirements for a particular application. down ratio that can be achieved for a given input voltage. 2.7V input voltage are limited to 5A. feedback resistor connects VOUT and FB pins together. Table 2. FB Resistor vs Various Output Voltages used, then this 47µF capacitor is not needed.
for those who wish to perform additional stability analysis. tently based on load demand, thus saving quiescent current. Table 3. Output Voltage Response Versus Component Matrix (Refer to Figure 18) 0A to 3A Load Step *Bulk capacitance is optional if VIN has very low input impedance.
For more information www.linear .com/L TM4616 peak current value in normal operation even though the voltage at the ITH pin indicates a lower value. The voltage at the ITH pin drops when the inductor’s average current is greater than the load requirement. As the ITH voltage drops below 0.2V, the BURST comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In Burst Mode operation, the internal circuitry is partially turned off, reducing the quiescent current to about 450µA for each output. The load current is now being supplied from the output capacitors. When the output voltage drops, causing ITH to rise above 0.25V, the internal sleep line goes low, and the LTM4616 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Each regulator can be configured for Burst Mode operation. Pulse-Skipping Mode Operation In applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the LTM4616 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Floating the MODE pin or tying it to V IN/2 enables pulse-skipping operation. This allows discontinuous conduction mode (DCM) opera- tion down to near the limit defined by the chip’s minimum on-time (about 100ns). Below this output current level, the converter will begin to skip cycles in order to main- tain output regulation. Increasing the output load current slightly, above the minimum required for discontinuous conduction mode, allows constant frequency PWM. Each regulator can be configured for pulse-skipping mode. Forced Continuous Operation In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE pin to GND. In this mode, inductor cur- rent is allowed to reverse during low output loads, the I TH APPLICATIONS INFORMATION voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4616’s output voltage is in regulation. Each regulator can be configured for forced continuous mode. Multiphase Operation For output loads that demand more than 8A of current, two outputs in LTM4616 or even multiple LTM4616s can be cascaded to run out-of-phase to provide more output current without increasing input and output voltage ripple. The CLKIN pin allows the LT C®4616 to synchronize to an external clock (between 0.75MHz and 2.25MHz) and the internal phase-locked loop allows the LTM4616 to lock onto CLKIN’s phase as well. The CLKOUT signal can be connected to the CLKIN pin of the following LTM4616 stage to line up both the frequency and the phase of the entire system. Tying the PHMODE pin to SVIN, SGND or SVIN/2 (floating) generates a phase difference (between CLKIN and CLKOUT) of 180°, 120° or 90° respectively, which corresponds to a 2-phase, 3-phase or 4-phase operation. For a 6-phase example in Figure 2, the 2nd stage that is 120° out-of-phase from the 1st stage can generate a 240° (PHMODE = 0) CLKOUT signal for the 3rd stage, which then can generate a CLKOUT signal that’s 420°, or 60° (PHMODE = SV IN) for the 4th stage. With the 60° CLKIN input, the next two stages can shift 120° (PHMODE = 0) for each to generate a 300° signal for the 6th stage. Finally, the signal with a 60° phase shift on the 6th stage (PHMODE is floating) goes back to the 1st stage. Figure 3 shows the configuration for 12-phase operation. A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used.
Figure 2. 6-Phase Operation Figure 3. 12-Phase Operation
4616 F02
4616 F03
rent sharing. This will balance the thermals on the design. design. The FB pins of the parallel module are tied together. reduction as a function of the number of interleaved phases.
where electromagnetic interference (EMI) is concerned. spectrum operation by tying the CLKIN pin to SVIN. the slew rate of the spread spectrum frequency change.
4616 F04
Figure 4. Normalized Input RMS Ripple Current vs Duty Factor for One to Six Channels (Phases)
VTRACK is the track ramp applied to the slave’s track pin. Figure 5 will be equal to RFB for coincident tracking. ramp or by RSR and CSR in Figure 5 referenced to VIN. Figure 5. Dual Outputs (3.3V and 1.5V) with T racking tracking, then RTA is equal to RFB2 with VFB = V TRACK.
4616 F05
- TIE TO VIN TO DISABLE TRACK WITH DEFAUL T 100µs SOFT START
- APPL Y A CONTROL RAMP WITH R
- APPL Y AN EXTERNAL TRACKING RAMP DIRECTL Y
4616 F06
Figure 6. Output Voltage Coincident T racking shows the output voltage for coincident tracking. voltage will reach it final value before the master output. RTB = 22.1k. Solve for RTA to equal to 4.87k. ~100µs of internal soft-start during start-up. value of 100k provides some margin. adjustments to the control loop. the output voltage is forced above the regulation point. disabled and PGOOD remains high.
the power loss for the 5V to 1.2V at 10A output is ~3.2W. Table 5. At load currents on each channel from 3A to 8A tance values for these lower currents is 15°C/W.
4616 F07
4616 F08
Figure 9. 5VIN to 3.3VOUT Figure 10. 5VIN to 1.2VOUT Figure 11. 5VIN to 3.3VOUT Figure 12. 5VIN to 1.2VOUT Figure 13. 3.3VIN to 1.2VOUT Figure 14. 3.3VIN to 2.5VOUT
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0 LFM
200 LFM
400 LFM
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Figure 15. 3.3VIN 1.2VOUT Figure 16. 3.3VIN 2.5VOUT
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Figure 17. Recommended PCB Layout siderations are still necessary.
- Use large PCB copper areas for high current paths, including VIN1, VIN2, GND1 and GND2, VOUT1 and VOUT2. It helps to minimize the PCB conduction loss and thermal stress.
- Place high frequency ceramic input and output capaci- tors next to the VIN, GND and VOUT pins to minimize high frequency noise.
- Place a dedicated power ground layer underneath the unit.
- To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
- Do not put vias directly on the pads, unless they are capped or plated over.
- Use a separated SGND ground copper area for com- ponents connected to signal pins. Connect the SGND to GND underneath the unit.
- For parallel modules, tie the ITH, FB and ITHM pins to- gether. Use an internal layer to closely connect these pins together. All of the ITHM pins connect to the SGND of the master regulator, then the master SGND connects to GND. Figure 17 gives a good example of the recommended layout. L TM4616 TOP VIEW VIN1 VOUT1 1 2 3 4 5 6 7 8 10 9 11 12 L K J H G F E D C B M A
4616 F17GND2 GND2
Figure 18. Typical 3V to 5.5VIN, to 1.8V, 1.5V Outputs
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5 PIN SC70 PACKAGE
Figure 19. LTM4616 Tw o Outputs Parallel, 1.5V at 16A Design Figure 20. LTM4616 Output Sequencing Application
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Figure 21. Four Phase in Parallel, 1.2V at 32A
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6 PIN SC70 PACKAGE
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For more information www.linear .com/L TM4616 PACKAGE DESCRIPTION Pin Assignment Table (Arranged by Pin Number) PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME A1 GND1 B1 GND1 C1 VIN1 D1 VIN1 E1 VIN1 F1 VIN1 A2 GND1 B2 GND1 C2 VIN1 D2 VIN1 E2 VIN1 F2 VIN1 A3 GND1 B3 GND1 C3 GND1 D3 GND1 E3 VIN1 F3 VIN1 A4 GND1 B4 GND1 C4 GND1 D4 GND1 E4 VIN1 F4 VIN1 A5 GND1 B5 GND1 C5 GND1 D5 GND1 E5 SVIN1 F5 SGND1 A6 BSEL1 B6 SW1 C6 GND1 D6 GND1 E6 PLLLPF1 F6 RUN1 A7 CLKIN1 B7 GND1 C7 GND1 D7 GND1 E7 ITHM1 F7 CLKOUT1 A8 MODE1 B8 GND1 C8 GND1 D8 FB1 E8 TRACK1 F8 ITH1 A9 PHMODE1 B9 GND1 C9 GND1 D9 VOUT1 E9 VOUT1 F9 VOUT1 A10 MGN1 B10 GND1 C10 GND1 D10 VOUT1 E10 VOUT1 F10 VOUT1 A11 PGOOD1 B11 GND1 C11 GND1 D11 VOUT1 E11 VOUT1 F11 VOUT1 A12 GND1 B12 GND1 C12 GND1 D12 VOUT1 E12 VOUT1 F12 VOUT1 PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME G1 GND2 H1 GND2 J1 VIN2 K1 VIN2 L1 VIN2 M1 VIN2 G2 GND2 H2 GND2 J2 VIN2 K2 VIN2 L2 VIN2 M2 VIN2 G3 GND2 H3 GND2 J3 GND2 K3 GND2 L3 VIN2 M3 VIN2 G4 GND2 H4 GND2 J4 GND2 K4 GND2 L4 VIN2 M4 VIN2 G5 GND2 H5 GND2 J5 GND2 K5 GND2 L5 SVIN2 M5 SGND2 G6 BSEL2 H6 SW2 J6 GND2 K6 GND2 L6 PLLLPF2 M6 RUN2 G7 CLKIN2 H7 GND2 J7 GND2 K7 GND2 L7 ITHM2 M7 CLKOUT2 G8 MODE2 H8 GND2 J8 GND2 K8 FB2 L8 TRACK2 M8 ITH2 G9 PHMODE2 H9 GND2 J9 GND2 K9 VOUT2 L9 VOUT2 M9 VOUT2 G10 MGN2 H10 GND2 J10 GND2 K10 VOUT2 L10 VOUT2 M10 VOUT2 G11 PGOOD2 H11 GND2 J11 GND2 K11 VOUT2 L11 VOUT2 M11 VOUT2 G12 GND2 H12 GND2 J12 GND2 K12 VOUT2 L12 VOUT2 M12 VOUT2
For more information www.linear .com/L TM4616 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW LGA 144 1111 REV B L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” 0.0000 0.0000 D E b e e b F G 144-Lead (15mm × 15mm × 2.82mm) (Reference LTC DWG # 05-08-1816 Rev B) 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 DETAIL B PACKAGE SIDE VIEW bbb Z SYMBOL A b D E e F G aaa bbb eee MIN 2.72 0.60 0.27 2.45 NOM 2.82 0.63 15.00 15.00 1.27 13.97 13.97 0.32 2.50 MAX 2.92 0.66 0.37 2.55 0.15 0.10 0.05 NOTES DIMENSIONS TOTAL NUMBER OF LGA PADS: 144 DETAIL B SUBSTRATEMOLD CAP Z A DIA 0.630 PAD 1 3x, C (0.22 x45°) DETAIL A 0.630 ±0.025 SQ. 143x S Y X eee DETAIL A F G H M L J K E A B C D 2 14 35 6 712 8 9 10 11
For more information www.linear .com/L TM4616 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW PIN 1 SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW BGA 144 1011 REV A L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” DETAIL A 0.0000 0.0000 DETAIL A Øb (144 PLACES) DETAIL B SUBSTRATE 0.27 – 0.37 2.45 – 2.55 // bbb Z D A ccc Z DETAIL B PACKAGE SIDE VIEW MOLD CAP Z M X Y Z ddd M Z eee 0.630 ±0.025 Ø 144x SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 3.22 0.50 2.72 0.60 0.60 NOM 3.42 0.60 2.82 0.75 0.63 15.0 15.0 1.27 13.97 13.97 MAX 3.62 0.70 2.92 0.90 0.66 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 144 E b e e b F G 144-Lead (15mm × 15mm × 3.42mm) (Reference LTC DWG # 05-08-1902 Rev A) 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 F G H M L J K E A B C D 2 14 35 6 712 8 9 10 11
For more information www.linear .com/L TM4616 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER C 2/11 Updated Features Updated Pin Configuration Updated Electrical Characteristics Replaced graphs G05 and G06 Updated graph G18 Updated Pin Functions Updated Simplified Block Diagram Updated Operation section Text updated in Applications Information section Updated figures 3, 5, 17, 18, 19, 20, 21, 22 Updated Package Description table Added Package Photo and updated Related Parts 2, 3, 4 10 through 20 13 through 24 D 3/12 Added BGA package option and MP temperature grade Added BGA package option, MP temperature grade, thermal resistance, and device weight Updated Note 2 Clarified Load T ransient Response conditions Updated recommended heat sinks Table Corrected MGN Pin usage Added package photo E 4/13 Added PGOOD leakage current and voltage low limits to Electrical Characteristics table Added Design Resources (Revision history begins at Rev C)
For more information www.linear .com/L TM4616 LINEAR TECHNOLOGY CORPORATION 2008 LT 0413 REV E • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L TM4616 RELATED PARTS PACKAGE PHOTO PART NUMBER DESCRIPTION COMMENTS LTM4628 Dual 8A, 26V, Step-Down µModule Regulator 0.6V ≤ VOUT ≤ 5V, 4.5V ≤ VIN ≤ 26.5V, Remote Sense Amplifier, Internal Temperature Sensing Output, 15mm × 15mm × 4.3mm LGA LTM4620A Dual 16V, 13A or Single 26A Step-Down µModule Regulator 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 5.3V, PLL input, Remote Sense Amplifier, VOUT tracking, 15mm × 15mm × 4.41mm LGA LTM8001 36V, 5A Step-Down µModule Regulator with Configurable Array of five 1A LDOs 6V ≤ VIN ≤ 36V, 0V ≤ VOUT ≤ 24V, Five Parallelable 1.1A 90µVRMS Output Noise LDOs, 15mm × 15mm × 4.92mm BGA LTM4627 20V, 15A Step-Down µModule Regulator 4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5V, PLL input, Remote Sense Amplifier, VOUT T racking, 15mm × 15mm × 4.3mm LGA and 15mm × 15mm × 4.9mm BGA LTM8045 Inverting or SEPIC µModule Converter with Up to 700mA Output Current 2.8V ≤ VIN ≤ 18V, ±2.5V ≤ VOUT ≤ ±15V, Synchronizable, No Derating or Logic Level Shift for Control Inputs When Inverting, 6.25mm × 11.25mm × 4.92mm BGA LTM8061 32V, 2A Step-Down µModule Battery Charger with Programmable Input Current Limit Suitable for CC-CV Charging Single and Dual Cell Li-Ion or Li-Poly Batteries, 4.95V ≤ V IN ≤ 32V, C/10 or Adjustable Timer Charge Termination, LTM8048 1.5W, 725VDC Galvanically Isolated µModule Converter with LDO Post Regulator 3.1V ≤ V IN ≤ 32V, 2.5V ≤ VOUT ≤ 12V, 1mVP-P Output Ripple, Internal Isolated T ransformer, 9mm × 11.25mm × 4.92mm BGA LTC2974 Quad Digital Power Supply Manager with EEPROM I2C/PMBus Interface, Configuration EEPROM, Fault Logging, Per Channel Voltage, Current and Temperature Measurements LTC3880 Dual Output PolyPhase Step-Down DC/DC Controller with Digital Power System Management I2C/PMBus Interface, Configuration EEPROM, Fault Logging, ±0.5% Output Voltage Accuracy, MOSFET Gate Drivers DESIGN RESOURCES SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:
- Selector Guides
- Demo Boards and Gerber Files
- Free Simulation Tools Manufacturing:
- Quick Start Guide
- PCB Design, Assembly and Manufacturing Guidelines
- Package and Board Level Reliability µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Search parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging.