LTM4649

LTM4649_15 LINER | Alldatasheet

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4649faFor more information www.linear .com/L TM4649 Typical applicaTion FeaTures DescripTion 10A Step-Down DC/DC µModule Regulator The LT M®4649 is a complete 10A high efficiency switching mode step-down DC/DC µModule® regulator in a 9mm × 15mm × 4.92 BGA package. Included in the package are the switching controller , power FETs, inductor , and all sup- port components. Operating over an input voltage range of 4.5V to 16V , the L TM4649 supports an output voltage range of 0.6V to 3.3V , set by a single external resistor . This high efficiency design delivers 10A continuous current. Only bulk input and output capacitors are needed. High switching frequency and a current mode architecture enables a very fast transient response to line and load changes without sacrificing stability. The device supports frequency synchronization, programmable multiphase operation, spread spectrum, output voltage tracking for supply rail sequencing. Fault protection features include overvoltage protection, overcurrent protection. The L TM4649 is offered in a small thermally enhanced 9mm × 15mm × 4.92mm BGA pack- age. The L TM4649 is available with SnPb (BGA) or RoHS compliant terminal finish. Efficiency and Power Loss at 12V and 5V Input Current Derating: 12V Input, 1.5VOUT, No Heat Sink 4.5V to 16V Input, 1.5V Output DC/DC µModule Regulator

applicaTions

n Input Voltage Range: 4.5V to 16V n Output Voltage Range: 0.6V Up to 3.3V n No Heat Sink or Current Derating Up to 85°C Ambient Temperature n ±1.5% Total DC Voltage Output Error n Multiphase Operation with Current Sharing n Remote Sense Amplifier n Built-In General Use Temperature Monitor n Selectable Pulse-Skipping Mode/Burst Mode® Operation for High Efficiency at Light Load n Soft-Start/Voltage T racking n Protection: Output Overvoltage and Over current Foldback n 9mm × 15mm × 4.92mm BGA Package n Telecom, Networking and Industrial Equipment n Point of Load Regulation L, L T , L TC, L TM, Burst Mode, µModule, PolyPhase, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066 and 6580258. Other patents pending. VIN INTVCC SW RUN MODE PHMODE TRACK/SS TEMP V OUT VOUT_LCL DIFFOUT DIFFP DIFFN VFB COMP PGOOD CLKIN FREQ L TM4649 GND0.1µF 100µF 6.3V 6.65k 22µF 16V V IN 4.5V TO 16V VOUT 1.5V 10A CLKOUT

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LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W) 0.5 1.0 1.5 2.0 2.5 3.0 2 4 6 8

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VIN = 12V VIN = 5V AMBIENT TEMPERATURE (°C) LOAD CURRENT (A) 20 40 60 80

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4649fa For more information www.linear .com/L TM4649 absoluTe MaxiMuM raTings MODE, CLKIN, TRACK/SS, DIFFP , DIFFN, 0.3V to INTVCC 0.3V to 2.7V Internal Operating Temperature Range (Note 2) 55°C to 125°C 55°C to 125°C (Note 1) pin conFiguraTion PGOOD MODE TEMP PHMODE CLKIN A B C D BGA PACKAGE 68-LEAD (9mm × 15mm × 4.92mm) E F G V OUT_LCL DIFFOUT TRACK/SS TOP VIEW DIFFN DIFFP CLKOUT GND GND VOUT GND FREQ VIN NC NC SW FB COMP INTVCC RUN TJMAX = 125°C, θJA = 14°C/W , θJCbottom = 5°C/W , θJCtop = 20°C/W WEIGHT = 1.0g orDer inForMaTion PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE (Note 2)DEVICE FINISH CODE L TM4649EY#PBF SAC305 (RoHS) L TM4649Y e1 BGA 3 –40°C to 125°C L TM4649IY#PBF SAC305 (RoHS) L TM4649Y e1 BGA 3 –40°C to 125°C L TM4649IY SnPb (63/37) L TM4649Y e0 BGA 3 –40°C to 125°C Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container . Pad or ball finish code is per IPC/JEDEC J-STD-609.

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4649faFor more information www.linear .com/L TM4649 elecTrical characTerisTics The l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V per typical application. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input DC Voltage l 4.5 16 V VOUT(RANGE) Output Voltage Range l 0.6 3.3 V VOUT(DC) Output Voltage, Total Variation with Line and Load CIN = 10µF × 1,COUT = 100µF Ceramic, 100µF POSCAP , RFB = 6.65k, MODE = GND, VIN = 4.5V to 16V , IOUT = 0A to 10A l 1.477 1.50 1.523 V Input Specifications VRUN RUN Pin On Threshold VRUN Rising 1.1 1.25 1.4 V VRUN(HYS) RUN Pin On Hysteresis 150 mV IQ(VIN) Input Supply Bias Current VIN = 12V , VOUT = 1.5V , Burst Mode Operation VIN = 12V , VOUT = 1.5V , Pulse-Skipping Mode VIN = 12V , VOUT = 1.5V , Switching Continuous Shutdown, RUN = 0, VIN = 12V mA mA mA µA I S(VIN) Input Supply Current VIN = 12V , VOUT = 1.5V , IOUT = 10A 1.5 A Output Specifications IOUT(DC) Output Continuous Current Range V IN = 12V , VOUT = 1.5V (Note 4) 0 10 A ΔVOUT(LINE) VOUT Line Regulation Accuracy VOUT = 1.5V , VIN from 4.5V to 16V IOUT = 0A l 0.010 0.04 %/V ΔVOUT(LOAD) VOUT Load Regulation Accuracy VOUT = 1.5V , IOUT = 0A to 10A, VIN = 12V (Note 4) l 0.15 0.5 % VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 100µF Ceramic, 100µF POSCAP , VIN = 12V , VOUT = 1.5V 15 mV ΔVOUT(START) Turn-On Overshoot COUT = 100µF Ceramic, 100µF POSCAP , VOUT = 1.5V , IOUT = 0A, VIN = 12V 20 mV tSTART Turn-On Time COUT = 100µF Ceramic, 100µF POSCAP , No Load, TRACK/SS = 0.01µF , VIN = 12V 5 ms ΔVOUTLS Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load, COUT = 100uF Ceramic, 100µF POSCAP , VIN = 12V , VOUT = 1.5V 60 mV tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, COUT = 100µF Ceramic, 100µF POSCAP , VIN = 12V , VOUT=1.5V 20 µs IOUTPK Output Current Limit VIN = 12V , VOUT = 1.5V (Note 4) 12 A Control Specifications V FB Voltage at VFB Pin IOUT = 0A, VOUT = 1.5V l 0.593 0.60 0.607 V IFB Current at VFB Pin (Note 6) –12 –25 nA VOVL Feedback Overvoltage Lockout l 0.64 0.66 0.68 V ITRACK/SS T rack Pin Soft-Start Pull-Up Current TRACK/SS = 0V 1.0 1.2 1.4 µA tON(MIN) Minimum On-Time (Note 3) 90 ns RFBHI Resistor Between VOUT_LCL and VFB Pins 9.90 10 10.10 kΩ DIFFP , DIFFN CM RANGE Common Mode Input Range V IN = 12V , Run > 1.4V 0 3.6 V VDIFFOUT(MAX) Maximum DIFFOUT Voltage IDIFFOUT = 300µA INTVCC-1.4 V VOS Input Offset Voltage VOSNS+ = VDIFFOUT = 1.5V , IDIFFOUT = 100µA 4 mV AV Differential Gain 1 V/V SR Slew Rate 2 V/µs

4649fa For more information www.linear .com/L TM4649 elecTrical characTerisTics The l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V per typical application. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS GBP Gain Bandwidth Product 3 MHz CMRR Common Mode Rejection (Note 6) 60 dB IDIFFOUT DIFFOUT Current Sourcing 2 mA RIN Input Resistance DIFFP , DIFFN to GND 80 kΩ VPGOOD PGOOD T rip Level VFB With Respect to Set Output VFB Ramping Negative VFB Ramping Positive –10 VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V INTVCC Linear Regulator VINTVCC Internal VCC Voltage 4.8 5 5.2 V VINTVCC Load Reg INTV CC Load Regulation ICC = 0mA to 50mA 0.9 % Oscillator and Phase-Locked Loop fSYNC SYNC Capture Range 250 800 kHz fS Nominal Switching Frequency 400 450 500 kHz RMODE Mode Input Resistance 250 kΩ VIH_CLKIN Clock Input Level High 2.0 V VIL_CLKIN Clock Input Level Low 0.8 V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Notes are automatically numbered when you apply the note style. Note 2: The L TM4649 is tested under pulsed load conditions such that T J ≈ TA. The L TM4649E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The L TM4649I is guaranteed to meet specifications over the –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: The minimum on-time condition is tested at wafer sort. Note 4: See output current derating curves for different V IN, VOUT and TA. Note 5: Guaranteed by design. Note 6: 100% tested at wafer level.

4649faFor more information www.linear .com/L TM4649 Typical perForMance characTerisTics 5VIN, 1VOUT Load T ransient 5VIN, 1.5VOUT Load T ransient12VIN, 1VOUT Load T ransient 12VIN, 1.5VOUT Load T ransient 5VIN, 2.5VOUT Load T ransient 12VIN, 2.5VOUT Load T ransient 12VIN Efficiency 5VIN Efficiency CCM, Burst Mode and Pulse- Skipping Mode Efficiency LOAD CURRENT (A) 100

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EFFICIENCY (%) VOUT = 1V , 450kHz VOUT = 1.2V , 450kHz VOUT = 1.5V , 450kHz VOUT = 2.5V , 750kHz VOUT = 3.3V , 750kHz LOAD CURRENT (A) 100

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EFFICIENCY (%) VOUT = 1V , 450kHz VOUT = 1.2V , 450kHz VOUT = 1.5V , 450kHz VOUT = 2.5V , 450kHz VOUT = 3.3V , 450kHz LOAD CURRENT (A) 0.01 EFFICIENCY (%) 0.1 1 10

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VIN = 12V VOUT = 1.5V VOUT 100mV/DIV AC IOUT 5A/DIV AC 50µs/DIV 5VIN, 1VOUT, 5A TO 10A LOAD STEP COUT = 2 • 220µF 4V CERAMIC CAPACITOR NO CFF CAPACITOR

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50µs/DIV 12VIN, 1VOUT, 5A TO 10A LOAD STEP COUT = 2 • 220µF 4V CERAMIC CAPACITOR NO CFF CAPACITOR

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50µs/DIV 5VIN, 1.5VOUT, 5A TO 10A LOAD STEP COUT = 2 • 220µF 4V CERAMIC CAPACITOR NO CFF CAPACITOR

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50µs/DIV 5VIN, 2.5VOUT, 5A TO 10A LOAD STEP COUT = 2 • 220µF 4V CERAMIC CAPACITOR NO CFF CAPACITOR

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50µs/DIV 12VIN, 2.5VOUT, 5A TO 10A LOAD STEP , 750kHz COUT = 2 • 220µF 4V CERAMIC CAPACITOR NO CFF CAPACITOR

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50µs/DIV 12VIN, 1.5VOUT, 5A TO 10A LOAD STEP COUT = 2 • 220µF 4V CERAMIC CAPACITOR NO CFF CAPACITOR

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4649fa For more information www.linear .com/L TM4649 Typical perForMance characTerisTics Soft-Start with Full Load Short-Circuit Protection with No Load Short-Circuit Protection with Full Load IN, 3.3VOUT Load T ransient 12VIN, 3.3VOUT Load T ransient Soft-Start with No Load VOUT 100mV/DIV AC IOUT 5A/DIV AC 50µs/DIV 5VIN, 3.3VOUT, 5A TO 10A LOAD STEP COUT = 2 • 220µF 4V CERAMIC CAPACITOR NO CFF CAPACITOR

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50µs/DIV 12VIN, 3.3VOUT, 5A TO 10A LOAD STEP , 750kHz COUT = 2 • 220µF 4V CERAMIC CAPACITOR NO CFF CAPACITOR

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0.5V/DIV VSW 10V/DIV IIN 1A/DIV 20ms/DIV 12VIN, 1.5VOUT IO = 0A START-UP CSS = 0.1µF

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0.5V/DIV VSW 10V/DIV IIN 1A/DIV 20ms/DIV 12VIN, 1.5VOUT IO = 10A START-UP CSS = 0.1µF

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0.5V/DIV VSW 10V/DIV IIN 1A/DIV 20µs/DIV 12VIN, 1.5VOUT SHORT CIRCUIT WITH NO LOAD COUT = 2 • 220µF 4V CERAMIC CAPACITOR

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20µs/DIV 12VIN, 1.5VOUT SHORT CIRCUIT WITH FULL LOAD C OUT = 2 • 220µF 4V CERAMIC CAPACITOR

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4649faFor more information www.linear .com/L TM4649 pin FuncTions GND (A1-A5, A7-A11, B1, B9-B11, E1, F3, F5, G1-G7): Ground Pins for Both Input and Output Returns. All ground pins need to connect with large copper areas underneath the unit. TEMP (A6): Onboard Temperature Diode for Monitoring the VBE Junction Voltage Change with Temperature. See the Applications Information section. CLKIN (B3): External Synchronization Input to Phase De- tector Pin. A clock on this pin will enable synchronization with forced continuous operation. See the Applications Information section. PHMODE (B4): This pin can be tied to GND, tied to INTVCC or left floating. This pin determines the relative phases between the internal controllers and the phasing of the CLKOUT signal. See Table 2 in the Operation section. MODE (B5): Mode Select Input. Connect this pin to IN - TV CC to enable Burst Mode operation. Connect to ground to enable forced continuous mode of operation. Floating this pin will enable pulse-skipping mode. NC (B7-B8, C3-C4): No Connection Pins. Either float these pins or connect them to GND for thermal purpose. VIN (C1, C8, C9, D1, D3-D5, D7-D9 and E8): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between V IN pins and GND pins. VOUT (C10-C11, D10-D11, E9-E11, F9-F11, G10-G11): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. SW (C5): Switching Node of the Circuit. This pin is used to check the switching frequency. Leave pin floating. A resistor-capacitor snubber can be placed from SW to PGND to eliminate high frequency switch node ringing. See the Applications Information section. PGOOD (C7): Output Voltage Power Good Indicator . Open- drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point. V OUT_LCL (G9): This pin is connected to the top of the internal top feedback resistor for the output. When the remote sense amplifier is used, connect the remote sense amplifier output DIFFOUT to V OUT_LCL to drive the 10k top feedback resistor . When the remote sense amplifier is not used, connect V OUT_LCL to VOUT directly. FREQ (E3): Frequency Set Pin. A 10µA current is sourced from this pin. A resistor from this pin to ground sets a voltage, that in turn, programs the operating frequency. Alternatively, this pin can be driven with a DC voltage that can set the operating frequency. See the Applications In- formation section. The L TM4649 has an internal resistor to program frequency to 450kHz. TRACK/SS (E5): Output V oltage T racking Pin and Soft- Start Inputs. The pin has a 1.2µA pull-up current source. A capacitor from this pin to ground will set a soft-start ramp rate. In tracking, the regulator output can be tracked to a different voltage. The different voltage is applied to a voltage divider then the slave output’s track pin. This voltage divider is equal to the slave output’s feedback divider for coincidental tracking. See the Applications Information section. FB (E7): The Negative Input of the Error Amplifier . Internally, this pin is connected to V OUT_LCL with a 10k precision resistor . Different output voltages can be programmed with an additional resistor between V FB and ground pins. In PolyPhase operation, tying the VFB pins together allows for parallel operation. See the Applications Information section for details. RUN (F1): Run Control Pin. A voltage above 1.25V will turn on the module. Each RUN pin has a 1µA pull-up cur- rent, once the RUN pin reaches 1.2V an additional 4.5µA pull-up current is added to this pin. PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y .

4649fa For more information www.linear .com/L TM4649 pin FuncTions CLKOUT (F2): Output Clock Signal for PolyPhase Opera- tion. The phase of CLKOUT is determined by the state of the PHMODE pin. INTVCC (F4): Internal 5V LDO for Driving the Control Cir- cuitry and the Power MOSFET Drivers. The 5V LDO has a 100mA current limit. COMP (F6): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Tie all COMP pins together in parallel operation. DIFFN (F7): Input to the Remote Sense Amplifier . This pin connects to the ground remote sense point. Connect to ground when not used. DIFFP (F8): Input to the Remote Sense Amplifier . This pin connects to the output remote sense point. Connect to ground when not used. DIFFOUT (G8): Output of the Remote Sense Amplifier . This pin connects to the V OUT_LCL pin for remote sense applications. Otherwise float when not used.

Figure 1. Simplified L TM4649 Block Diagram

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4649fa For more information www.linear .com/L TM4649 operaTion Power Module Description The L TM4649 is a high performance single output stand- alone nonisolated switching mode DC/DC power supply. It can provide up to 10A output current with few exter - nal input and output capacitors. This module provides precisely regulated output voltage programmable via an external resistor from 0.6VDC to 3.3VDC over a 4.5V to 16V input range. The typical application schematic is shown in Figure 17. The L TM4649 has an integrated constant-frequency cur- rent mode regulator , power MOSFETs, inductor , and other supporting discrete components. The typical switching frequency is 450kHz. For switching noise-sensitive ap - plications, it can be externally synchronized from 400kHz to 750kHz. See the Applications Information section. With current mode control and internal feedback loop compensation, the L TM4649 module has sufficient stabil- ity margins and good transient per formance with a wide range of output capacitors, especially with all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit in an overcurrent condition. An internal over voltage monitor protects the output voltage in the event of an overvoltage >10%. The top MOSFET is turned off and the bottom MOSFET is turned on until the output is cleared. Pulling the RUN pin below 1.1V forces the regulator into a shutdown state. The TRACK/SS pin is used for program- ming the output voltage ramp and voltage tracking during start-up. See the Application Information section. The LTM4649 is internally compensated to be stable over all operating conditions. T able 3 provides a guideline for input and output capacitances for several operating con- ditions. The Linear Technology µModule Power Design Tool will be provided for transient and stability analysis. The V FB pin is used to program the output voltage with a single external resistor to ground. A remote sense amplifier is provided in the L TM4649 for accurately sensing output voltages ≤3.3V at the load point. Multiphase operation can be easily employed with the synchronization inputs using an external clock source. See application examples. High efficiency at light loads can be accomplished with selectable Burst Mode operation using the MODE pin. These light load features will accommodate battery operation. Efficiency graphs are provided for light load operation in the Typical Performance Characteristics section. A diode connected PNP transistor with base and collector grounded is included in the module as a general purpose single-ended temperature monitor . The temperature monitor is intended to be used as a general temperature monitor , see Applications Information section The switching node pins are available for functional opera- tion monitoring and a resistor-capacitor snubber circuit can be careful placed on the switching node pin to ground to dampen any high frequency ringing on the transition edges. See the Applications Information section for details.

mined by the maximum load current and output voltage. for particular applications. ment section and temperature derating curves. is used, then DIFFOUT is connected to the VOUT_LCL pin. Table 1. VFB Resistor Table vs Various Output Voltages good choice with RMS ripple current ratings of ~2A each. capacitor can be used for more input bulk capacitance. planes are used, then this bulk capacitor is not needed. ed electrolytic aluminum capacitor or a Polymer capacitor .

4649fa For more information www.linear .com/L TM4649 applicaTions inForMaTion required. Table 3 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 5A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 3 matrix, and the Linear Technology µModule Power Design Tool will be provided for stability analysis. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The Linear Technology µModule Power Design Tool can calculate the output ripple reduction as the number of implemented phase’s increases by N times. Burst Mode Operation The L TM4649 is capable of Burst Mode operation in which the power MOSFETs operate intermittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. To enable Burst Mode operation, simply tie the MODE pin to INTV CC. During Burst Mode operation, the peak current of the inductor is set to approximately 30% of the maxi- mum peak current value in normal operation even though the voltage at the COMP pin indicates a lower value. The voltage at the COMP pin drops when the inductor’ s aver- age current is greater than the load requirement. As the COMP voltage drops below 0.5V , the burst comparator trips, causing the internal sleep line to go high and turn off both power MOSFET In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current. The load current is now being supplied from the output capacitors. When the output voltage drops, causing COMP to rise, the internal sleep line goes low, and the L TM4649 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Pulse-Skipping Mode Operation In applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the L TM4649 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Floating the MODE pin enables pulse-skipping operation. With pulse-skipping mode at light load, the internal current comparator may remain tripped for several cycles, thus skipping opera - tion cycles. This mode has lower ripple than Burst Mode operation and maintains a higher frequency operation than Burst Mode operation. Forced Continuous Operation In applications where fixed frequency operation is more critical than low current efficiency , and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE pin to ground. In this mode, inductor current is allowed to reverse during low output loads, the COMP voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the L TM4649’s output voltage is in regulation. Frequency Selection The L TM4649 device is internally programmed to 450kHz switching frequency to improve power conversion effi - ciency. It is recommended for all of the application of low V IN or low VOUT. For the application with high V IN (VIN> = 12V) and high V OUT (VOUT> = 1.8V), a higher 750kHz frequency is recommended to limit inductor ripple cur - rent by simply tie FREQ to INTVCC. Table 3 listed different frequency and FREQ pin recommendations for different V IN, VOUT conditions. If desired, a resistor can be connected from the FREQ pin to INTV CC to adjust the FREQ pin DC voltage to increase the switching frequency between default 450kHz and maximum 750kHz by. Figure 2 shows a graph of frequency setting verses FREQ pin DC voltage. Figure 18 shows an example of frequency programmed to 650kHz. Please be aware FREQ pin has an accurate 10µA current sourced from this pin when calculate the resistor value.

level above 2V and a low level below 0.8V at the CLKIN pin. is put in place to limit inductor ripple current. output current and reduced input and output voltage ripple. Table 2. PHASEMD and CLKOUT Signal Relationship show a schematic of the parallel design.

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90 DEGREE90 DEGREE 90 DEGREE

0 PHASE

90 PHASE

180 PHASE

270 PHASE

120 DEGREE 120 DEGREE

120 PHASE

240 PHASE

Figure 3. Examples of 3-Phase, 4-Phase Operation with PHASMD Table

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Figure 2. Operating Frequency vs FREQ Pin Voltage

the L TM4649 is capable of turning on the top MOSFET . quency. A good rule of thumb is to use an 110ns on-time. will control output regulation from the feedback divider .

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Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle

VTRACK is the track ramp applied to the slave’s track pin. in Figure 5 will be equal to the RFB for coincident tracking. Figure 6 shows the coincident tracking waveforms.

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Figure 5. Dual Outputs (1.5V and 1.2V) with T racking

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Figure 6. Output Coincident T racking Waveform = VTRACK. Therefore RTB = 10k, and RTA = 10k in Figure 5. voltage will reach it final value before the master output. pin offset to a negligible value. than 6V maximum for monitoring. pin can also be used for output voltage sequencing. ce that increases to 4.5µA during ramp-up.

4649faFor more information www.linear .com/L TM4649 applicaTions inForMaTion SW Pins The SW pin is generally for testing purposes by monitor- ing the pin. The SW pin can also be used to dampen out switch node ringing caused by LC parasitic in the switched current path. Usually a series R-C combination is used called a snubber cir cuit. The resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor If the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond wire inductance. First the SW pin can be monitored with a wide bandwidth scope with a high frequency scope probe. The ring fre - quency can be measured for its value. The impedance Z can be calculated: ZL = 2π • f • L where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to Z, then the ringing should be dampened. The snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. Calculated by: ZC = 1 2π •f •C These values are a good place to start with. Modification to these components should be made to attenuate the ringing with the least amount the power loss. Temperature Monitoring Measuring the absolute temperature of a diode is pos - sible due to the relationship between current, voltage and temperature described by the classic diode equation: ID = IS • e VD η • VT or VD = η• VT • lnID IS where ID is the diode current, VD is the diode voltage, η is the ideality factor (typically close to 1.0) and I S (satura- tion current) is a process dependent parameter . V T can be broken out to: VT = k • T q where T is the diode junction temperature in Kelvin, q is the electron charge and k is Boltzmann’s constant. V T is approximately 26mV at room temperature (298K) and scales linearly with Kelvin temperature. It is this linear temperature relationship that makes diodes suitable temperature sensors. The I S term in the equation above is the extrapolated current through a diode junction when the diode has zero volts across the terminals. The I S term varies from process to process, varies with temperature, and by definition must always be less than I D. Combining all of the constants into one term: KD = η • k q where KD = 8.62−5, and knowing ln(ID/IS) is always posi- tive because ID is always greater than I S, leaves us with the equation that: VD = T(KELVIN)• KD • lnID IS where VD appears to increase with temperature. It is com- mon knowledge that a silicon diode biased with a current source has an approximately –2mV /°C temperature rela- tionship (Figure 7), which is at odds with the equation. In fact, the I S term increases with temperature, reducing the ln(ID/IS) absolute value yielding an approximately –2mV/°C composite diode voltage slope. An external diode connected PNP transistor can be pulled up to VIN with a resistor to set the current to 100µA for using this diode connected transistor as a general tem - perature monitor by monitoring the diode voltage drop with temperature. See Figure 21 for an example.

thermal performance to one’s own application. an actual application or viable operating condition. an actual application or viable operating condition. the heat flows from the junction to the top of the part. generally match the user’s application. two layer board. This board is described in JESD 51-9.

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Figure 7. Diode Voltage VD vs Temperature

Figure 8. Graphical Representation of JESD51-12 Thermal Coefficients

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Figure 9. 5VIN, 3.3VOUT and Figure 10. 12VIN, 3.3VOUT Figure 11. No Heat Sink with 5VIN Figure 12. No Heat Sink with Figure 13. No Heat Sink with Figure 14. No Heat Sink with temperature. This approximate factor is: 1.4 for 120°C.

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rise above ambient, thus maximum junction temperature. layers and one ounce copper for the two inner layers. The PCB dimensions are 95mm × 76mm. to be provided to protect each unit from catastrophic failure. Figure 15. Thermal Image 12V to 1.5V at 10A

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Figure 16. Recommended PCB Layout

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siderations are still necessary.

• Use large PCB copper areas for high current path, including V IN, GND and VOUT. It helps to minimize the PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capaci- tors next to the V IN, GND and V OUT pins to minimize high frequency noise.
• Place a dedicated power ground layer underneath the unit.
• To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. Do not put vias directly on the pads, unless they are capped.
• Use a separated SGND ground copper area for com - ponents connected to signal pins. Connect the SGND to GND underneath the unit. Figure 16 gives a good example of the recommended layout.

Table 3. Output Voltage Response vs Component Matrix (Refer to Figure 18) 0A to 5A Load Step Typical Measured Values *Bulk capacitor is optional if VIN has very low input impedance. Table 4. 1.5V Output Table 5. 3.3V Output

Figure 17. 4.5V to 16VIN, 1.5V at 10A Design Figure 18. 4.5V to 16V VIN, 3.3VOUT at 8A Design with Increased 650kHz Frequency

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Figure 19. Three L TM4649 in Parallel, 1.5V at 30A Design

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Figure 20. Quad Outputs 4-Phase L TM4649 Regulator with T racking Function Figure 21. Single L TM4649 10A Design with Temperature Monitoring

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4649faFor more information www.linear .com/L TM4649 package DescripTion Please refer to http://www.linear .com/designtools/packaging/ for the most recent package drawings. PACKAGE TOP VIEW PIN “A1” CORNER Y X aaa Z aaa Z DETAIL A PACKAGE BOTTOM VIEW SEE NOTES PIN 1 68-Lead (15.00mm × 9.00mm × 4.92mm) (Reference LTC DWG# 05-08-1892 Rev A) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION CAN BE 96.5% Sn/3.0% Ag/0.5% Cu OR Sn Pb EUTECTIC DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE DETAIL A Øb (68 PLACES) DETAIL B SUBSTRATE A ccc Z DETAIL B PACKAGE SIDE VIEW MOLD CAP Z M X Y Z ddd M Z eee SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 4.72 0.50 4.22 0.60 0.60 0.27 3.95 NOM 4.92 0.60 4.32 0.75 0.63 15.00 9.00 1.27 12.70 7.62 0.32 4.00 MAX 5.12 0.70 4.42 0.90 0.66 0.37 4.05 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 68 D E e b F G SUGGESTED PCB LAYOUT TOP VIEW 0.000 3.810 5.080 3.810 6.350 5.080 6.350 2.540 1.270 3.810 2.540 1.270 3.810 2.540 1.270 0.3175 0.3175 0.000 // bbb Z Z 0.630 ±0.025 Ø 68x BGA 68 1212 REV A TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule G F E D C B A

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES

4649fa For more information www.linear .com/L TM4649 package DescripTion package phoTo L TM4649 BGA Pinout PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 GND B1 GND C1 V IN D1 V IN E1 GND F1 RUN G1 GND A2 GND B2 – C2 – D2 – E2 – F2 CLCKOUT G2 GND A3 GND B3 CLKIN C3 NC D3 V IN E3 FREQ F3 GND G3 GND A4 GND B4 PHMODE C4 NC D4 V IN E4 – F4 INTVCC G4 GND A5 GND B5 MODE C5 SW D5 V IN E5 TRACK/SS F5 GND G5 GND A6 TEMP B6 – C6 – D6 – E6 – F6 COMP G6 GND A7 GND B7 NC C7 PGOOD D7 V IN E7 FB F7 DIFFN G7 GND A8 GND B8 NC C8 V IN D8 V IN E8 V IN F8 DIFFP G8 DIFFOUT A9 GND B9 GND C9 V IN D9 V IN E9 V OUT F9 V OUT G9 V OUT_LCL A10 GND B10 GND C10 V OUT D10 V OUT E10 V OUT F10 V OUT G10 V OUT A11 GND B11 GND C11 V OUT D11 V OUT E11 V OUT F11 V OUT G11 V OUT PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y .

4649faFor more information www.linear .com/L TM4649 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER A 2/14 Added SnPb (lead) BGA package Figures 9 and 10 changed Y-Axis to Power Loss (W) 1, 2

Figure 22. Dual Output 1.2V , 1.8V 2-Phase L TM4649 Regulator with T racking

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• Package and Board Level Reliability µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Sear ch parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging.