LTM4630A

LTM4630A LINER | Alldatasheet

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Technical content

For more information www.linear .com/L TM4630A TYPICAL APPLICATION

DESCRIPTION

DC/DC µModule Regulator The LT M®4630A is a dual 18A or single 36A output switch- ing mode step-down DC/DC µModule ® (micromodule) regulator with wider V OUT range and higher efficiency than LTM4630. Included in the package are the switch - ing controllers, power FETs, inductors and all supporting components. Operating from an input voltage range of 4.5V to 18V, the LTM4630A supports two outputs each with an output voltage range of 0.6V to 8V, each set by a single external resistor . Its high efficiency design delivers up to 18A continuous current for each output. Only a few input and output capacitors are needed. The LTM4630A is pin compatible with the LTM4620 and LTM4620A (dual 13A, single 26A) and the LTM4630 (dual 18A, single 36A). The device supports frequency synchronization, multi phase operation, Burst Mode operation and output voltage tracking for supply rail sequencing and has an onboard temperature diode for device temperature monitoring. High switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. Fault protection features include overvoltage and overcurrent protection. The LTM4630A is offered in 16mm × 16mm × 4.41mm LGA and 16mm × 16mm × 5.01mm BGA packages.

FEATURES

APPLICATIONS

n Dual 18A or Single 36A Output n Input Voltage Range: 4.5V to 18V (after date code 1720*) n Output Voltage Range: 0.6V to 8V (after date code 1720*) n ±1.5% Maximum Total DC Output Error Over Line, Load and Temperature n Higher Light Load Efficiency and Wider VOUT Range Than LTM4630 n Differential Remote Sense Amplifier n Current Mode Control/Fast T ransient Response n Multiphase Parallel Current Sharing Up to 144A n Internal Temperature Monitor n Pin Compatible with the LTM4620A (Dual 13A, Single 26A) and LTM4630 (Dual 18A, Single 36A) n Adjustable Switching Frequency or Synchronization n Overcurrent Foldback Protection n Selectable Burst Mode® Operation, Pulse Skipping Mode Operation n Soft-Start/Voltage T racking n Output Overvoltage Protection n 16mm × 16mm × 4.41mm LGA and 16mm × 16mm × 5.01mm BGA Packages n Telecom and Networking Equipment n Storage and ATCA Cards n Industrial Equipment All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066 and 6580258. Other patents pending. *Maximum VIN = 15V and VOUT = 5.3V with date code before 1720. 36A, 1.2V Output DC/DC µModule Regulator 1.2VOUT and 3.3VOUT Efficiency vs IOUT 4630A TA01a L TM4630A VIN TEMP RUN1 RUN2 TRACK1 TRACK2 fSET 470µF 6.3V 60.4k 100µF 6.3V PHASMD V OUT1 VOUT VOUTS1 VFB1 VFB2 COMP1 COMP2 VOUT2 PGOOD2 MODE_PLLIN PINS UNUSED IN THIS APPLICATION: CLKOUT EXTV CC SW1 SW2 V OUTS2 INTVCC INTVCC PGOOD1 PGOOD 10k SGND GND DIFFP DIFFN DIFFOUT 470µF 6.3V 100µF 6.3V 75k 120k 0.1µF 22µF 25V VIN 4.5V TO 15V 4.7µF LOAD CURRENT (A) EFFICIENCY (%) 100 10 12 14 16 182 4 6 4630A TA01b 5 VIN, 3.3VOUT, 500kHz 5 VIN, 1.2VOUT, 300kHz 12 VIN, 3.3VOUT, 600kHz 12 VIN, 1.2VOUT, 300kHz

For more information www.linear .com/L TM4630A PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS PGOOD1, PGOOD2, RUN1, RUN2, MODE_PLLIN, fSET, TRACK1, TRACK2, (Note 1) LGA PACKAGE 144-LEAD (16mm × 16mm × 4.41mm) TOP VIEW TEMP CLKOUT SW1 PHASMD EXTVCC 1 2 3 4 5 6 7 8 109 11 12 L K J H G F E D C B M A SW2 PGOOD1 PGOOD2 RUN2 TRACK2 INTVCC VOUTS2 DIFFP DIFFOUT DIFFN RUN1 TRACK1 MODE_PLLIN VFB1 VOUTS1 fSET SGND COMP1 COMP2 SGND VFB2 VIN VOUT2GND GND VOUT1 SGND GND TJMAX = 125°C, ΘJA = 7°C/W , ΘJCbottom = 1.5°C/W , ΘJCtop = 3.7°C/W , ΘJB + ΘJBA ≅ 7°C/W Θ VALUES DEFINED PER JESD51-12 WEIGHT = 3.2g BGA PACKAGE 144-LEAD (16mm × 16mm × 5.01mm) TOP VIEW TEMP CLKOUT SW1 PHASMD EXTVCC 1 2 3 4 5 6 7 8 109 11 12 L K J H G F E D C B M A SW2 PGOOD1 PGOOD2 RUN2 TRACK2 INTVCC VOUTS2 DIFFP DIFFOUT DIFFN RUN1 TRACK1 MODE_PLLIN VFB1 VOUTS1 fSET SGND COMP1 COMP2 SGND VFB2 VOUT2GND GND SGND GND TJMAX = 125°C, ΘJA = 7°C/W , ΘJCbottom = 1.5°C/W , ΘJCtop = 3.7°C/W , ΘJB + ΘJBA ≅ 7°C/W Θ VALUES DEFINED PER JESD51-12 WEIGHT = 3.39g PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE (NOTE 2)DEVICE FINISH CODE LTM4630AEV#PBF Au (RoHS) LTM4630AV e4 LGA 3 –40°C to 125°C LTM4630AIV#PBF –40°C to 125°C LTM4630AEY#PBF SAC305 (RoHS) LTM4630AY e1 BGA 3 –40°C to 125°C LTM4630AIY#PBF –40°C to 125°C Internal Operating Temperature Range

• Device temperature grade is indicated by a label on the shipping container .
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Terminal Finish Part Marking: www.linear .com/leadfree
• This product is not recommended for second side reflow. For more information, go to www.linear .com/BGA-assy
• Recommended BGA PCB Assembly and Manufacturing Procedures: www.linear .com/BGA-assy
• BGA Package and T ray Drawings: www.linear .com/packaging
• This product is moisture sensitive. For more information, go to: www.linear .com/BGA-assy ORDER INFORMATIONhttp://www.linear .com/product/LTC4630A#orderinfo

For more information www.linear .com/L TM4630A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 34. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input DC Voltage l 4.5 18 V VOUT Output Voltage l 0.6 8 V VOUT1(DC), VOUT2(DC) Output Voltage, Total Variation with Line and Load CIN = 22µF × 3, COUT = 100µF × 1 Ceramic, 470µF POSCAP VIN = 12V, VOUT = 1.5V, IOUT = 0A to 18A (Note 8) l 1.477 1.5 1.523 V Input Specifications VRUN1, VRUN2 RUN Pin On/Off Threshold RUN Rising 1.1 1.25 1.40 V VRUN1HYS, VRUN2HYS RUN Pin On Hysteresis 150 mV IINRUSH(VIN) Input Inrush Current at Start-Up IOUT = 0A, CIN = 22µF ×3, CSS = 0.01µF, COUT = 100µF ×3, VOUT1 = 1.5V, VOUT2 = 1.5V, VIN = 12V 1 A IQ(VIN) Input Supply Bias Current VIN = 12V, VOUT = 1.5V, Burst Mode Operation VIN = 12V, VOUT = 1.5V, Pulse-Skipping Mode VIN = 12V, VOUT= 1.5V, Switching Continuous Shutdown, RUN = 0, VIN = 12V mA mA mA µA IS(VIN) Input Supply Current VIN = 5V, VOUT = 1.5V, IOUT = 18A VIN = 12V, VOUT = 1.5V, IOUT = 18A 6.5 2.6 A A Output Specifications IOUT1(DC), IOUT2(DC) Output Continuous Current Range VIN = 12V, VOUT = 1.5V (Note 7) 0 18 A ΔVOUT1(LINE)/VOUT1 ΔVOUT2(LINE)/VOUT2 Line Regulation Accuracy VOUT = 1.5V, VIN from 4.5V to 18V IOUT = 0A for Each Output, l 0.01 0.025 %/V ΔVOUT1/VOUT1 ΔVOUT2/VOUT2 Load Regulation Accuracy For Each Output, VOUT = 1.5V, 0A to 18A VIN = 12V (Note 7) l 0.5 0.75 % VOUT1(AC), VOUT2(AC) Output Ripple Voltage For Each Output, IOUT = 0A, COUT = 100µF ×3/ X7R/Ceramic, 470µF POSCAP , VIN = 12V, VOUT = 1.5V, Frequency = 450kHz 15 mVP-P fS (Each Channel) Output Ripple Voltage Frequency VIN = 12V, VOUT = 1.5V, fSET = 1.25V (Note 4) 500 kHz fSYNC (Each Channel) SYNC Capture Range 400 780 kHz ΔVOUTSTART (Each Channel) Turn-On Overshoot COUT = 100µF/X5R/Ceramic, 470µF POSCAP , VOUT = 1.5V, IOUT = 0A VIN = 12V 10 mV tSTART (Each Channel) Turn-On Time COUT = 100µF/X5R/Ceramic, 470µF POSCAP , No Load, TRACK/SS with 0.01µF to GND, VIN = 12V 5 ms ΔVOUT(LS) (Each Channel) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load COUT = 22µF ×3/X5R/Ceramic, 470µF POSCAP VIN = 12V, VOUT = 1.5V 30 mV tSETTLE (Each Channel) Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, VIN = 12V, COUT = 100µF, 470µF POSCAP 20 µs IOUT(PK) (Each Channel) Output Current Limit VIN = 12V, VOUT = 1.5V 30 A Control Section VFB1, VFB2 Voltage at VFB Pins IOUT = 0A, VOUT = 1.5V l 0.592 0.600 0.606 V IFB (Note 6) –5 –20 nA VOVL Feedback Overvoltage Lockout l 0.64 0.66 0.68 V

For more information www.linear .com/L TM4630A ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 34. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS TRACK1 (I), TRACK2 (I) T rack Pin Soft-Start Pull-Up Current TRACK1 (I),TRACK2 (I) Start at 0V 1 1.25 1.5 µA UVLO Undervoltage Lockout (Falling) 3.3 V UVLO Hysteresis 0.6 V tON(MIN) Minimum On-Time (Note 6) 90 ns RFBHI1, RFBHI2 Resistor Between VOUTS1, VOUTS2 and VFB1, VFB2 Pins for Each Output 60.05 60.4 60.75 kΩ VPGOOD1, VPGOOD2 Low PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V IPGOOD PGOOD Leakage Current VPGOOD = 5V ±5 µA VPGOOD PGOOD T rip Level VFB with Respect to Set Output Voltage VFB Ramping Negative VFB Ramping Positive –10 INTVCC Linear Regulator VINTVCC Internal VCC Voltage 6V < VIN < 18V 4.8 5 5.2 V VINTVCC Load Regulation INTVCC Load Regulation ICC = 0mA to 50mA 0.5 2 % VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive 4.5 4.7 V VEXTVCC(DROP) EXTVCC Dropout ICC = 20mA, VEXTVCC = 5V 50 100 mV VEXTVCC(HYST) EXTVCC Hysteresis 220 mV Oscillator and Phase-Locked Loop Frequency Nominal Nominal Frequency fSET = 1.2V 450 500 550 kHz Frequency Low Lowest Frequency fSET = 0V (Note 5) 210 250 290 kHz Frequency High Highest Frequency fSET > 2.4V, Up to INTVCC 700 780 860 kHz fSET Frequency Set Current 9 10 11 µA RMODE_PLLIN MODE_PLLIN Input Resistance 250 kΩ CLKOUT Phase (Relative to VOUT1) PHASMD = GND PHASMD = Float PHASMD = INTVCC 120 Deg Deg Deg CLK High CLK Low Clock High Output Voltage Clock Low Output Voltage 0.2 V V Differential Amplifier A V Differential Amplifier Gain 1 V/V RIN Input Resistance Measured at DIFFP Input 80 kΩ VOS Input Offset Voltage VDIFFP = VDIFFOUT = 1.5V, IDIFFOUT = 100µA 3 mV PSRR Differential Amplifier Power Supply Rejection Ratio 5V < VIN < 18V 90 dB ICL Maximum Output Current 3 mA VOUT(MAX) Maximum Output Voltage IDIFFOUT = 300µA INTVCC – 1.4 V GBW Gain Bandwidth Product 3 MHz VTEMP Diode Connected PNP I = 100µA 0.6 V TC Temperature Coefficient l –2.2 mV/C

For more information www.linear .com/L TM4630A

ELECTRICAL CHARACTERISTICS

TYPICAL PERFORMANCE CHARACTERISTICS Burst Mode and Pulse-Skip Mode Efficiency VIN=12V, VOUT = 1.2V, fS = 300kHz 1V Dual Phase Single Output Load Transient Response 1.2V Dual Phase Single Output Load Transient Response Efficiency vs Output Current, V IN = 5V Efficiency vs Output Current, V IN = 12V LOAD CURRENT (A) EFFICIENCY (%) 100 10 12 14 16 182 4 6 4630A G01 1.8VOUT, 300kHz 2.5VOUT, 400kHz 1.5VOUT, 300kHz 3.3VOUT, 500kHz 1.2VOUT, 300kHz 1.0VOUT, 300kHz 0.9VOUT, 300kHz LOAD CURRENT (A) EFFICIENCY (%) 100 10 12 14 16 182 4 6 4630A G02 1.8VOUT, 400kHz 2.5VOUT, 500kHz 1.5VOUT, 400kHz 3.3VOUT, 600kHz 1.2VOUT, 300kHz 1.0VOUT, 300kHz 5.0VOUT, 700kHz 8.0VOUT, 770kHz 0.9VOUT, 300kHz LOAD CURRENT (A) 0.01 EFFICIENCY (%) 1 100.1 4630A G04 CCM PULSE-SKIP MODE Burst Mode OPERATION 50µs/DIV VOUT(AC) 20mV/DIV LOAD STEP 10A/DIV 4630A G05 12VIN, 1VOUT, 300kHz, DUAL PHASE SINGLE OUTPUT SETUP 9A LOAD STEP UP AND STEP DOWN, 9A/µs SLEW RATE COUT = 2 • 220µF POSCAP + 4 • 100µF CERAMIC CAPS 50µs/DIV VOUT(AC) 20mV/DIV LOAD STEP 10A/DIV 4630A G06 12VIN, 1.2VOUT, 300kHz, DUAL PHASE SINGLE OUTPUT SETUP 9A LOAD STEP UP AND STEP DOWN, 9A/µs SLEW RATE C OUT = 2 • 220µF POSCAP + 4 • 100µF CERAMIC CAPS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4630A is tested under pulsed load conditions such that TJ ≈ TA. The LTM4630AE is guaranteed to meet specifications from 0°C to 125°C internal temperature. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4630AI is guaranteed over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: T wo outputs are tested separately and the same testing condition is applied to each output. Note 4: The switching frequency is programmable from 300kHz to 750kHz. Note 5: LTM4630A device is designed to operate from 300kHz to 750kHz Note 6: These parameters are tested at wafer sort. Note 7: See Table 1 for Peak Current and Thermal Design Power (TDP) current for different V IN and VOUT. See output current derating curve for different ambient temperature. Note 8: Total DC output voltage error includes all errors over temperature: Line and load regulation as well as the tolerance of the integrated top feedback resistor .

For more information www.linear .com/L TM4630A TYPICAL PERFORMANCE CHARACTERISTICS Single Phase Short Circuit Protection with 18A Single Phase Start-up with 18A Single Phase Short Circuit Protection with No load 3.3V Dual Phase Single Output Load Transient Response Single Phase Start-Up with No load 50µs/DIV VOUT(AC) 20mV/Div LOAD STEP 10A/DIV 4630A G07 12VIN, 1.5VOUT, 400kHz, DUAL PHASE SINGLE OUTPUT SETUP 9A LOAD STEP UP AND STEP DOWN, 9A/µs SLEW RATE COUT = 2 • 220µF POSCAP + 4 • 100µF CERAMIC CAPS 50µs/DIV VOUT(AC) 20mV/Div LOAD STEP 10A/DIV 4630A G08 12VIN, 1.8VOUT, 400kHz, DUAL PHASE SINGLE OUTPUT SETUP 9A LOAD STEP UP AND STEP DOWN, 9A/µs SLEW RATE C OUT = 2 • 220µF POSCAP + 4 • 100µF CERAMIC CAPS 1.5V Dual Phase Single Output Load Transient Response 1.8V Dual Phase Single Output Load Transient Response 2.5V Dual Phase Single Output Load Transient Response 50µs/DIV VOUT(AC) 20mV/Div LOAD STEP 10A/DIV 4630A G09 12VIN, 2.5VOUT, 500kHz, DUAL PHASE SINGLE OUTPUT SETUP 9A LOAD STEP UP AND STEP DOWN, 9A/µs SLEW RATE COUT = 2 • 220µF POSCAP + 4 • 100µF CERAMIC CAPS 50µs/DIV VOUT(AC) 20mV/Div LOAD STEP 10A/DIV 4630A G10 12VIN, 3.3VOUT, 600kHz, DUAL PHASE SINGLE OUTPUT SETUP 9A LOAD STEP UP AND STEP DOWN, 9A/µs SLEW RATE C OUT = 2 • 220µF POSCAP + 4 • 100µF CERAMIC CAPS 20ms/DIV VSW 10V/Div VOUT 0.5V/Div IIN 0.2A/Div 4630A G11 12VIN, 1.2VOUT, 300kHz COUT = 1 • 470µF 4V POSCAP + 1 • 100µF 6.3V CERAMIC, CSS = 0.1µF 20ms/DIV VSW 10V/Div VOUT 0.5V/Div IIN 1A/Div 4630A G12 12VIN, 1.2VOUT, 300kHz COUT = 1 • 470µF 4V POSCAP + 1 • 100µF 6.3V CERAMIC, CSS = 0.1µF 50µs/DIV VSW 10V/Div VOUT 0.5V/Div IIN 1A/Div 4630A G13 12VIN, 1.2VOUT, 300kHz COUT = 1 • 470µF 4V POSCAP + 1 • 100µF 6.3V CERAMIC 50µs/DIV VSW 10V/Div VOUT 0.5V/Div IIN 1A/Div 4630A G14 12VIN, 1.2VOUT, 300kHz COUT = 1 • 470µF 4V POSCAP + 1 • 100µF 6.3V CERAMIC

For more information www.linear .com/L TM4630A PIN FUNCTIONS VOUT1 (A1-A5, B1-B5, C1-C4): Power Output Pins. Apply output load between these pins and GND pins. Recom - mend placing output decoupling capacitance directly between these pins and GND pins. Review Table 6 for output capacitance requirement. See Table 1 for output current guideline. GND (A6-A7, B6-B7, D1-D4, D9-D12, E1-E4, E10-E12, F1-F3, F10-F12, G1, G3, G10, G12, H1-H7, H9-H12, J1, J5, J8, J12, K1, K5-K8, K12, L1, L12, M1 , M12): Power Ground Pins for Both Input and Output Returns. VOUT2 ( A8-A12, B8-B12, C9-C12) : Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling ca - pacitance directly between these pins and GND pins. Review Table 6 for output capacitance requirement. See Table 1 for output current guideline. VOUTS1, VOUTS2 (C5, C8): This pin is connected to the top of the internal top feedback resistor for each output. The pin can be directly connected to its specific output, or connected to DIFFOUT when the remote sense amplifier is used. In paralleling modules, one of the V OUTS pins is connected to the DIFFOUT pin in remote sensing or directly to VOUT with no remote sensing. It is very important to connect these pins to either the DIFFOUT or V OUT since this is the feedback path, and cannot be left open. See the Applications Information section. f SET (C6): Frequency Set Pin. A 10µA current is sourced from this pin. A resistor from this pin to ground sets a voltage that in turn programs the operating frequency. Alternatively, this pin can be driven with a DC voltage that can set the operating frequency. See the Applications Information section. SGND (C7, D6, G6-G7, F6-F7): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the ap plication. See layout guidelines in Figure 12. VFB1, V FB2 (D5, D7): The Negative Input of the Error Amplifier for each channel. Internally, this pin is con - nected to V OUTS1 or V OUTS2 with a 60.4kΩ precision resistor . Different output voltages can be programmed with an additional resistor between V FB and GND pins. In PolyPhase® operation, tying the VFB pins together allows for parallel operation. See the Applications Information section for details. TRACK1, TRACK2 (E5, D8): Output Voltage T racking Pin and Soft-Start Inputs. Each channel has a 1.3µA pull-up current source. When one channel is configured to be master of the two channels, then a capacitor from this pin to ground will set a soft-start ramp rate. The remaining channel can be set up as the slave, and have the master’s output applied through a voltage divider to the slave out put’s track pin. This voltage divider is equal to the slave output’s feedback divider for coincidental tracking. See the Applications Information section. COMP1, COMP2 (E6, E7): Current control threshold and error amplifier compensation point for each channel. The current comparator threshold increases with this control voltage. Tie the COMP pins together for parallel operation. The device is internal compensated. DIFFP (E8): Positive input of the remote sense amplifier . This pin is connected to the remote sense point of the output voltage. Diffamp can be used for ≤ 3.3V outputs. See the Applications Information section. DIFFN (E9): Negative input of the remote sense amplifier . This pin is connected to the remote sense point of the output GND. Diffamp can be used for ≤ 3.3V outputs. See the Applications Information section. (Recommended to Use Test Points to Monitor Signal Pin Connections.) PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y .

For more information www.linear .com/L TM4630A PIN FUNCTIONS MODE_PLLIN (F4): Force Continuous Mode, Burst Mode Operation, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to SGND to force both channels into force continuous mode of operation. Connect to INTV CC to enable pulse-skipping mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on the pin will force both channels into continuous mode of operation and synchronized to the external clock applied to this pin. RUN1, RUN2 (F5, F9): Run Control Pin. A voltage above 1.25V will turn on each channel in the module. A voltage below 1.25V on the RUN pin will turn off the related chan nel. Each RUN pin has a 1µA pull-up current, once the RUN pin reaches 1.2V an additional 4.5µA pull-up current is added to this pin. DIFFOUT (F8): Internal Remote Sense Amplifier Output. Connect this pin to V OUTS1 or VOUTS2 depending on which output is using remote sense. In parallel operation con - nect one of the VOUTS pin to DIFFOUT for remote sensing. Diffamp can be used for ≤ 3.3V outputs. SW1, SW2 (G2, G11): Switching node of each channel that is used for testing purposes. Also an R-C snubber network can be applied to reduce or eliminate switch node ringing, or otherwise leave floating. See the Applications Information section. PHASMD (G4): Connect this pin to SGND, INTVCC, or float- ing this pin to select the phase of CLKOUT to 60 degrees, 120 degrees, and 90 degrees respectively. CLKOUT (G5): Clock output with phase control using the PHASMD pin to enable multiphase operation between devices. See the Applications Information section. PGOOD1, PGOOD2 ( G9, G8): Output Voltage Power Good Indicator . Open drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point. INTV CC (H8): Internal 5V Regulator Output. The control circuits and internal gate drivers are powered from this voltage. Decouple this pin to PGND with a 4.7µF low ESR tantalum or ceramic. INTVCC is activated when either RUN1 or RUN2 is activated. TEMP (J6): Onboard General Purpose Temperature Diode for Monitoring the VBE Junction Voltage Change with Temperature. See the Applications Information section. EXTVCC (J7): External power input that is enabled through a switch to INTVCC whenever EXTVCC is greater than 4.7V. Do not exceed 6V on this input, and connect this pin to VIN when operating VIN on 5V. An efficiency increase will occur that is a function of the (VIN – INTVCC) multiplied by power MOSFET driver current. Typical current requirement is 30mA. V IN must be applied before EXTVCC, and EXTVCC must be removed before VIN. VIN (M2-M11, L2-L11, J2-J4, J9-J11, K2-K4, K9-K11): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between V IN pins and GND pins. (Recommended to Use Test Points to Monitor Signal Pin Connections.)

TA = 25°C. Use Figure 1 configuration. Figure 1. Simplified LTM4630A Block Diagram

Figure 34. See Table 1 for different output current and limit and foldback current limit in an overcurrent condition. voltage exits a ±10% window around the regulation point. bottom MOSFET will turn on to clamp the output voltage. is feedback voltage referred. the regulator . See the Applications Information section. sensing the output voltage at the load point. different levels. See the Applications Information section. the Applications Information section for details. the Applications Information section for details.

Figure 34. External component selection is primarily requirements for particular applications. down ratio that can be achieved for a given input voltage. where D is duty cycle and fSW is the switching frequency. tON(MIN) is specified in the electrical parameters as 90ns. The PWM controller has an internal 0.6V reference voltage. to their respective outputs for proper feedback regulation. back setting resistor can be used for the parallel design. one programming resistor as shown in Figure 2. Figure 2. 4-Phase Parallel Configurations

4 PARALLELED OUTPUTS

Table 1. FREQ Resistor , VFB Resistor , Output Current vs Various Output Voltages

For more information www.linear .com/L TM4630A APPLICATIONS INFORMATION In parallel operation, the VFB pins have an IFB current of 20nA maximum each channel. To reduce output voltage error due to this current, an additional VOUTS pin can be tied to VOUT, and an additional RFB resistor can be used to lower the total Thevenin equivalent resistance seen by this current. For example in Figure 2, the total Thevenin equivalent resistance of the V FB pin is (60.4k//RFB), which is 30.2k where RFB is equal to 60.4k for a 1.2V output. Four phases connected in parallel equates to a worse case feedback current of 4 • IFB = 80nA maximum. The voltage error is 80nA • 30.2k = 2.4mV. If VOUTS2 is connected, as shown in Figure 2, to VOUT, and another 60.4k resistor is connected from VFB2 to ground, then the voltage error is reduced to 1.2mV. If the voltage error is acceptable then no additional connections are necessary. The onboard 60.4k resistor is 0.5% accurate and the V FB resistor can be chosen by the user to be as ac- curate as needed. All COMP pins are tied together for current sharing between the phases. The TRACK/SS pins can be tied together and a single soft-start capacitor can be used to soft- start the regulator . The soft-start equation will need to have the soft-start current parameter increased by the number of paralleled channels. See Output Voltage T racking section. Input Capacitors The LTM4630A module should be connected to a low ac- impedance DC source. For each regulator input two 22µF input ceramic capacitors are used for RMS ripple current. A 47µF to 100µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this bulk capacitor is not needed. For a buck converter , the switching duty-cycle can be estimated as: D = VOUT VIN Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as: ICIN(RMS) = IOUT(MAX)

• D • 1− D( ) In the above equation, η% is the estimated efficiency of the power module. The bulk capacitor can be a switcher- rated electrolytic aluminum capacitor , Polymer capacitor . Output Capacitors The LTM4630A is designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output volt- age ripple and transient requirements. COUT can be a low ESR tantalum capacitor , the low ESR polymer capacitor or ceramic capacitor . The typical output capacitance range for each output is from 200µF to 470µF. Additional output filtering may be required by the system designer , if further reduction of output ripples or dynamic transient spikes is required. Table 6 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot for each output channel running a 4.5A load step. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 6 matrix, and the Linear Technology µModule Power Design Tool will be provided for stability analysis. Multiphase operation will reduce effective output ripple as a function of the num ber of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The Linear Technology µModule Power Design Tool can calculate the output ripple reduction as the number of implemented phases increases by N times. A small value 10Ω to 50Ω resistor can be place in series from V OUT to the VOUTS pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. The same resistor could be place in series from VOUT to DIFFP and a bode plot analyzer could inject a signal into the control loop and validate the regulator stability. Burst Mode Operation The LTM4630A is capable of Burst Mode operation on each regulator in which the power MOSFETs operate in - termittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation

For more information www.linear .com/L TM4630A APPLICATIONS INFORMATION should be applied. Burst Mode operation is enabled with the MODE_PLLIN pin floating. During this operation, the peak current of the inductor is set to approximately one third of the maximum peak current value in normal opera tion even though the voltage at the COMP pin indicates a lower value. The voltage at the COMP pin drops when the inductor’s average current is greater than the load requirement. As the COMP voltage drops below 0.5V, the BURST comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current to about 450µA for each output. The load current is now being supplied from the output capacitors. When the output voltage drops, caus ing COMP to rise above 0.5V, the internal sleep line goes low, and the LTM4630A resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Either regulator can be configured for Burst Mode operation. Pulse-Skipping Mode Operation In applications where low output ripple and high effi ciency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the LTM4630A to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE_PLLIN pin to INTV CC enables pulse-skipping operation. At light loads the internal current comparator may remain tripped for several cycles and force the top MOSFET to stay off for several cycles, thus skipping cycles. The inductor current does not reverse in this mode. This mode will maintain higher effective frequencies thus lower output ripple and lower noise than Burst Mode operation. Either regulator can be configured for pulse-skipping mode. Forced Continuous Operation In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE_PLLIN pin to GND. In this mode, inductor current is allowed to reverse during low output loads, the COMP voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4630A’s output voltage is in regulation. Either regulator can be configured for force continuous mode. Multiphase Operation For output loads that demand more than 18A of current, two outputs in LTM4630A or even multiple LTM4630As can be paralleled to run out of phase to provide more output current without increasing input and output voltage ripples. The MODE_PLLIN pin allows the LTM4630A to synchronize to an external clock (between 300kHz and 780kHz) and the internal phase-locked-loop allows the LTM4630A to lock onto incoming clock phase as well. The CLKOUT signal can be connected to the MODE_PLLIN pin of the following stage to line up both the frequency and the phase of the entire system. Tying the PHASMD pin to INTV CC, SGND, or (floating) generates a phase difference (between MODE_PLLIN and CLKOUT) of 120 degrees, 60 degrees, or 90 degrees respectively. A total of 12 phases can be cascaded to run simultaneously with respect to each other by programming the PHASMD pin of each LTM4630A chan- nel to different levels. Figure 3 shows a 2-phase design, 4-phase design and a 6-phase design example for clock phasing with the PHASMD table. A multiphase power supply significantly reduces the amount of ripple current in both the input and output ca pacitors. The RMS input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used when all of the outputs are tied together to achieve a single high output current design. The LTM4630A device is an inherently current mode controlled device, so parallel modules will have very good current sharing. This will balance the thermals on the design. Figure 35 shows an example of parallel operation and pin connection.

Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle Figure 3. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table

180 PHASE0 PHASE

90 DEGREE

270 PHASE90 PHASE

60 DEGREE 60 DEGREE

240 PHASE60 PHASE

300 PHASE120 PHASE

efficiency by lowering power MOSFET switching losses. frequency in reference to the highest output voltage. in continuous mode while being externally clock. set resistor for free run operation. and the gate charge required turning on the top MOSFET . good rule of thumb is to keep on-time longer than 110ns. Figure 5. Operating Frequency vs fSET Pin Voltage

For more information www.linear .com/L TM4630A APPLICATIONS INFORMATION 0.54V, it will operate in forced continuous mode and revert to the selected mode once TRACK > 0.54V. In order to track with another channel once in steady state operation, the LTM4630A is forced into continuous mode operation as soon as V FB is below 0.54V regardless of the setting on the MODE_PLLIN pin. Ratiometric tracking can be achieved by a few simple cal- culations and the slew rate value applied to the master’s TRACK pin. As mentioned above, the TRACK pin has a control range from 0 to 0.6V. The master’s TRACK pin slew rate is directly equal to the master’s output slew rate in Volts/Time. The equation: MR SR

• 60.4k = RTB where MR is the master’s output slew rate and SR is the slave’s output slew rate in Volts/Time. When coincident tracking is desired, then MR and SR are equal, thus R TB is equal the 60.4k. RTA is derived from equation: RTA = 0.6V VFB 60.4k + VFB RFB − VTRACK RTB where VFB is the feedback voltage reference of the regula- tor , and VTRACK is 0.6V. Since R TB is equal to the 60.4k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then R TA is equal to RFB with VFB = VTRACK. Therefore RTB = 60.4k, and RTA = 60.4k in Figure 6. In ratiometric tracking, a different slew rate maybe desired for the slave regulator . RTB can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then RTB = 76.8k. Solve for RTA to equal to 49.9k. Each of the TRACK pins will have the 1.3µA current source on when a resistive divider is used to implement tracking on that specific channel. This will impose an offset on the TRACK pin input. Smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. For example, where the 60.4k is used then a 6.04k can be used to reduce the TRACK pin offset to a negligible value. Power Good The PGOOD pins are open drain pins that can be used to monitor valid output voltage regulation. This pin monitors a 10% window around the regulation point. A resistor can be pulled up to a particular supply voltage no greater than 6V maximum for monitoring. Stability Compensation The module has already been internally compensated for all output voltages. Table 6 is provided for most ap plication requirements. The Linear Technology µModule Power Design Tool will be provided for other control loop optimization. Run Enable The RUN pins have an enable threshold of 1.4V maximum, typically 1.25V with 150mV of hysteresis. They control the turn on each of the channels and INTV CC. These pins can be pulled up to VIN for 5V operation, or a 5V Zener diode can be placed on the pins and a 10k to 100k resistor can be placed up to higher than 5V input for enabling the channels. The RUN pins can also be used for output voltage sequencing. In parallel operation the RUN pins can be tie together and controlled from a single control. See the Typical Applica tion circuits in Figure 34. INTVCC and EXTVCC The LTM4630A module has an internal 5V low dropout regulator that is derived from the input voltage. This regu- lator is used to power the control circuitry and the power MOSFET drivers. This regulator can source up to 70mA, and typically uses ~30mA for powering the device at the maximum frequency. This internal 5V supply is enabled by either RUN1 or RUN2. EXTV CC allows an external 5V supply to power the LTM4630A and reduce power dissipation from the internal low dropout 5V regulator . The power loss savings can be calculated by: (V IN – 5V) • 30mA = PLOSS

For more information www.linear .com/L TM4630A APPLICATIONS INFORMATION EXTVCC has a threshold of 4.7V for activation, and a maximum rating of 6V. When using a 5V input, connect this 5V input to EXTVCC also to maintain a 5V gate drive level. EXTVCC must sequence on after V IN, and EXTV CC must sequence off before VIN. Differential Remote Sense Amplifier An accurate differential remote sense amplifier is provided to sense low output voltages accurately at the remote load points. This is especially true for high current loads. The amplifier can be used on one of the two channels, or on a single parallel output. It is very important that the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to either V OUTS1 or V OUTS2. In parallel operation, the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to one of the V OUTS pins. Review the parallel schematics in Figure 32 and review Figure 2. The diffamp can only be used for output voltage ≤ 3.3V. SW Pins The SW pins are generally for testing purposes by moni toring these pins. These pins can also be used to dampen out switch node ringing caused by LC parasitic in the switched current paths. Usually a series R-C combina - tion is used called a snubber circuit. The resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor . If the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond wire inductance. First the SW pin can be monitored with a wide bandwidth scope with a high frequency scope probe. The ring fre quency can be measured for its value. The impedance Z can be calculated: ZL = 2πfL, where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to Z, then the ringing should be dampened. The snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. Calculated by: ZC = 1/(2πfC). These values are a good place to start with. Modification to these components should be made to attenuate the ringing with the least amount of power loss. Temperature Monitoring A diode connected PNP transistor is used for the TEMP monitor function by monitoring its voltage over tempera ture. The temperature dependence of this diode voltage can be understood in the equation: VD =nVT ln ID IS where VT is the thermal voltage (kT/q), and n, the ideality factor , is 1 for the diode connected PNP transistor being used in the LTM4630A. I S is expressed by the typical empirical equation: IS =I0 exp –VG0 VT where I0 is a process and geometry dependent current, (I0 is typically around 20k orders of magnitude larger than IS at room temperature) and VG0 is the band gap voltage of 1.2V extrapolated to absolute zero or –273°C. If we take the IS equation and substitute into the VD equa- tion, then we get: VD = VG0 – kT q ⎠⎟ ln I0 ID ⎠⎟, VT = kT q The expression shows that the diode voltage decreases (linearly if I0 were constant) with increasing temperature and constant diode current. Figure 8 shows a plot of V D vs Temperature over the operating temperature range of the LTM4630A. If we take this equation and differentiate it with respect to temperature T , then: dVD dT = – VG0 – VD T This dVD/dT term is the temperature coefficient equal to about –2mV/K or –2mV/°C. The equation is simplified for the first order derivation.

Kelvin temp and subtracting 273 from it. temperature will provide a general temperature monitor . rent to 100µA. See Figure 35 for an example. thermal performance to one’s own application.

1. θJA, the thermal resistance from junction to ambi -

dissipation flowing through the bottom of the package. Figure 8. Diode Voltage VD vs Temperature T(K)

don’t generally match the user’s application.

1. θJB, the thermal resistance from junction to the

board is described in JESD51-9. resistances are external to the µModule. Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients

For more information www.linear .com/L TM4630A operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. An outcome of this process and due-diligence yields a set of derating curves provided in other sections of this data sheet. After these laboratory test have been performed and correlated to the µModule model, then the θ JB and θBA are summed together to cor- relate quite well with the µModule model with no airflow or heat sinking in a properly define chamber . This θ JB + θBA value is shown in the Pin Configuration section and should accurately equal the θ JA value because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink. Each system has its own thermal characteristics, therefore thermal analysis must be performed by the user in a particular system. The LTM4630A module has been designed to effectively remove heat from both the top and bottom of the pack age. The bottom substrate material has very low thermal resistance to the printed circuit board. An external heat sink can be applied to the top of the device for excellent heat sinking with airflow. Figures 10 and 11 show temperature plots of the LTM4630A with no heat sink and 200LFM airflow. These plots equate to a paralleled 12V to 1.0V at 36A design operating at 86.5% efficiency, and 12V to 3.3V at 36A design operating at 93.7% efficiency. APPLICATIONS INFORMATION Safety Considerations The LTM4630A modules do not provide isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. The device does support over current protection. A temperature diode is provided for monitoring internal temperature, and can be used to detect the need for thermal shutdown that can be done by controlling the RUN pin. Power Derating The 1.0V, 1.8V, 3.3V, 5V and 8V power loss curves in Figures 13 to 17 can be used in coordination with the load current derating curves in Figures 18 to 33 for calculating an approximate Θ JA thermal resistance for the LTM4630A with various heat sinking and airflow conditions. The power loss curves are taken at room temperature, and are increased with a 1.35 to 1.4 multiplicative factor at 125°C. These factors come from the fact that the power loss of the regulator increases about 45% from 25°C to 150°C, thus a 50% spread over 125°C delta equates to ~0.35%/°C loss increase. A 125°C maximum junction minus 25°C room temperature equates to a 100°C increase. This 100°C increase multiplied by 0.35%/°C equals a 35% power loss increase at the 125°C junction, thus the 1.35 multiplier . The derating curves are plotted with CH1 and CH2 in parallel single output operation starting at 36A of load with low ambient temperature. The output voltages are 1.0V, 1.8V, 3.3V, 5V and 8V. These are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled tem perature chamber along with thermal modeling analysis.

Figure 12. Recommended PCB Layout

Table 2. 1.0V Output Table 3. 1.8V Output Table 4. 3.3V Output Table 5. 5V Output

Table 7. Dual Channel Single Output Voltage Response vs Component Matrix (Refer to Figure 32, 0A to 9A, ±25% Load Step Typical *Bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads. Table 6. 8V Output

Figure 34. Typical 4.5VIN to 18VIN, 300kHz, 1.0V and 1.2V at 18A Outputs

Figure 35. LTM4630A 2-Phase, 600kHz, 3.3V at 28A Design with Temperature Monitoring

Figure 36. LTM4630A 3.3V and 2.5V Output with T racking Function

Figure 37. LTM4630A 4-Phase, 1.2V at 70A Output Design

For more information www.linear .com/L TM4630A LTM4630A Component LGA and BGA Pinout PACKAGE DESCRIPTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 VOUT1 B1 VOUT1 C1 VOUT1 D1 GND E1 GND F1 GND A2 VOUT1 B2 VOUT1 C2 VOUT1 D2 GND E2 GND F2 GND A3 VOUT1 B3 VOUT1 C3 VOUT1 D3 GND E3 GND F3 GND A4 VOUT1 B4 VOUT1 C4 VOUT1 D4 GND E4 GND F4 MODE_PLLIN A5 VOUT1 B5 VOUT1 C5 VOUT1S D5 VFB1 E5 TRACK1 F5 RUN1 A6 GND B6 GND C6 fSET D6 SGND E6 COMP1 F6 SGND A7 GND B7 GND C7 SGND D7 VFB2 E7 COMP2 F7 SGND A8 VOUT2 B8 VOUT2 C8 VOUT2S D8 TRACK2 E8 DIFFP F8 DIFFOUT A9 VOUT2 B9 VOUT2 C9 VOUT2 D9 GND E9 DIFFN F9 RUN2 A10 VOUT2 B10 VOUT2 C10 VOUT2 D10 GND E10 GND F10 GND A11 VOUT2 B11 VOUT2 C11 VOUT2 D11 GND E11 GND F11 GND A12 VOUT2 B12 VOUT2 C12 VOUT2 D12 GND E12 GND F12 GND PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 GND J1 GND K1 GND L1 GND M1 GND G2 SW1 H2 GND J2 VIN K2 VIN L2 VIN M2 VIN G3 GND H3 GND J3 VIN K3 VIN L3 VIN M3 VIN G4 PHASEMD H4 GND J4 VIN K4 VIN L4 VIN M4 VIN G5 CLKOUT H5 GND J5 GND K5 GND L5 VIN M5 VIN G6 SGND H6 GND J6 TEMP K6 GND L6 VIN M6 VIN G7 SGND H7 GND J7 EXTVCC K7 GND L7 VIN M7 VIN G8 PGOOD2 H8 INTVCC J8 GND K8 GND L8 VIN M8 VIN G9 PGOOD1 H9 GND J9 VIN K9 VIN L9 VIN M9 VIN G10 GND H10 GND J10 VIN K10 VIN L10 VIN M10 VIN G11 SW2 H11 GND J11 VIN K11 VIN L11 VIN M11 VIN G12 GND H12 GND J12 GND K12 GND L12 GND M12 GND PACKAGE PHOTO LGA BGA

For more information www.linear .com/L TM4630A 144-Lead (16mm × 16mm × 4.41mm) (Reference L TC DWG # 05-08-1901 Rev B) DETAIL B DETAIL B SUBSTRATEMOLD CAP // bbb Z Z A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 144 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW PAD “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES D E b e e b F G LGA 144 0213 REV B TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” SYMBOL A b D E e F G aaa bbb eee MIN 4.31 0.60 0.36 3.95 NOM 4.41 0.63 16.0 16.0 1.27 13.97 13.97 0.41 4.00 MAX 4.51 0.66 0.46 4.05 0.15 0.10 0.05 NOTES DIMENSIONS TOTAL NUMBER OF LGA PADS: 144 DETAIL A DIA 0.630 PAD 1 L K J H G F E D C BM A SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.0000 0.630 ±0.025 SQ. 143x 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 DETAIL A 0.630 ±0.025 SQ. 143x S YXZØ eee 3x, C (0.22 x45°) SEE NOTES

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y L TMXXXXXX µModule PACKAGE DESCRIPTION Please refer to http://www.linear .com/product/LTM4630A#packaging for the most recent package drawings.

For more information www.linear .com/L TM4630A PACKAGE DESCRIPTION Please refer to http://www.linear .com/product/LTC4630A#packaging for the most recent package drawings. 144-Lead (16mm × 16mm × 5.01mm) (Reference L TC DWG # 05-08-1969 Rev Ø) PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES D E b e e b F G BGA 144 0114 REV Ø TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule DETAIL A PIN 1 ABCDEFGHK JLM SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.0000 0.630 ±0.025 Ø 144x 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 DETAIL A Øb (144 PLACES) A DETAIL B PACKAGE SIDE VIEW Z M X YZddd M Zeee DETAIL B SUBSTRATE ccc Z MOLD CAP SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 4.81 0.50 4.31 0.60 0.60 0.36 3.95 NOM 5.01 0.60 4.41 0.75 0.63 16.00 16.00 1.27 13.97 13.97 0.41 4.00 MAX 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 144 // bbb Z Z NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS. DRAWING NOT TO SCALE BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES

For more information www.linear .com/L TM4630A

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 12/16 Added BGA package 2, 34 B 01/18 Changed VIN(MAX) from 15V to 18V. Added date code information. Changed VIN Absolute Maximum Rating from 16V to 20V. Changed VOUT(MAX) from 5.3V to 8V. Updated Efficiency vs Output Current graph. Updated Table 1. Updated thermal images. Updated text to match updated efficiency and thermal data. Added Fibure 17. Added Figure 32 and Figure 33. Updated Power Loss curves. Updated Derating curves. 1, 3 1, 3 21, 23 27, 28, 29 Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

For more information www.linear .com/L TM4630A LT 0118 REV B • PRINTED IN USA  ANALOG DEVICES, INC. 2015 www.linear .com/L TM4630A RELATED PARTS DESIGN RESOURCES SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:

• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools Manufacturing:
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• Package and Board Level Reliability µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Search parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. PART NUMBER DESCRIPTION COMMENTS LTM4620A Lower Current of the LTM4630A, Dual 13A or Single 26A Pin Compatible with LTM4630A, 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 5.3V, 15mm × 15mm × 4.41mm (BGA) and, 15mm × 15mm × 5.01mm (BGA) LTM4620 Lower VOUT of the LTM4620, Dual 13A or Single 26A, VOUT ≤ 2.5V Pin Compatible with LTM4630A, 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 2.5V, 15mm × 15mm × 4.41mm(BGA), 15mm × 15mm × 5.01mm (BGA) LTM4630 Lower VOUT of the LTM4630A, VOUT ≤ 1.8V Pin Compatible with LTM4630A; 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 4.41mm (LGA), 16mm × 16mm × 5.01mm (BGA) LTM4630-1 External Compensation of the LTM4630 with ±0.8% (-1A) and ±1.5% DC V OUT Accuracy 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 4.41mm (LGA), 16mm × 16mm × 5.01mm (BGA) LTM4650 Higher Current of the LTM4630, Dual 25A or Single 50A Pin Compatible with LTM4630A; 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 5.01mm (BGA) LTM4650-1 External Compensation of the LTM4650 with ±0.8% (-1A) and ±1.5% DC V OUT Accuracy 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 4.41mm (LGA), 16mm × 16mm × 5.01mm (BGA) LTM4631 Ultrathin, Lower Current of the LTM4630, Dual 10A or Single 20A, 1.91mm Package Height Pin Compatible with LTM4630A, 4.5V ≤ V IN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 1.91mm (LGA) LTM4636 Single 40A µModule Regulator with Excellent Thermal Performance 4.7V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 3.3V, 16mm × 16mm × 7.07mm BGA Package LTM4647 Single 30A µModule Regulator in Small Package 4.7V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 1.8V, 9mm × 15mm × 5.01mm BGA Package LTM4677 LTM4630 with PSM Function 4.5V ≤ VIN ≤ 16V, 0.5V ≤ VOUT ≤ 1.8V, 16mm × 16mm × 5.01mm (BGA) LTM4643 Ultrathin, Quad 3A µModule Regulator 4V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 3.3V, 9mm × 15mm × 1.82mm (LGA) LTM4644 Quad 4A µModule Regulator 4V ≤ VIN ≤ 14V, 0.6V ≤ VOUT ≤ 5.5V, 9mm × 15mm × 5.01mm (BGA) LTM4639 Lower VIN (2.375V ≤ VIN ≤ 7V), 20A 0.6V ≤ VOUT ≤ 5.5V, 15mm × 15mm × 4.92mm (BGA)