LTM4620A LINER | Alldatasheet
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For more information www.linear.com/4620A Typical applicaTion
DescripTion
DC/DC µModule Regulator The LT M®4620A is a complete dual 13A, or single 26A output switching mode DC/DC power supply with wider VOUT range and higher efficiency than the LTM4620. Included in the package are the switching controller, power FETs, inductors and all supporting components. Operating from an input voltage range of 4.5V to 16V, the LTM4620A supports two outputs each with an output voltage range of 0.6V to 5.3V, set by a single external resistor. Its high efficiency design delivers up to 13A continuous current for each output. Only a few input and output capacitors are needed. The device supports frequency synchronization, multiphase operation, Burst Mode ® operation and output voltage tracking for supply rail sequencing and has an onboard temperature diode for device temperature monitoring. High switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. Fault protection features include overvoltage and over- current protection. The power module is offered in a proprietary space saving and thermally enhanced 15mm × 15mm × 4.41mm LGA package. The LTM4620A is RoHS compliant. 26A, 5V Output DC/DC µModule® Regulator
FeaTures
applicaTions
n Dual 13A or Single 26A Output n Wide Input Voltage Range: 4.5V to 16V n Output Voltage Range: 0.6V to 5.3V n ±1.5% Maximum Total DC Output Error n Multiphase Current Sharing with Multiple LTM4620As Up to 100A n Higher Efficiency and Wider VOUT Range Than LTM4620 n Differential Remote Sense Amplifier n Current Mode Control/Fast T ransient Response n Adjustable Switching Frequency n Overcurrent Foldback Protection n Frequency Synchronization n Internal Temperature Sensing Diode Output n Output Overvoltage Protection n Pin Compatible with the LTM4628 (Dual 8A) and LTM4620 (Dual 13A) n 15mm × 15mm × 4.41mm LGA Package n Telecom and Networking Equipment n Industrial Equipment 5V Efficiency vs IOUT TOTAL OUTPUT CURRENT (A) EFFICIENCY (%) 100 3 5 8 10 4620A TA01b 12 14 19 21 16 23 8V TO 5V EFF (650kHz) 12V TO 5V EFF (750kHz) 4620A TA01a L TM4620A VIN TEMP RUN1 RUN2 TRACK1 TRACK2 f SET 8.25k 100µF 6.3V 100µF 6.3V PHASMD V OUT1 VOUTS1 SW1 VFB1 VFB2 COMP1 COMP2 VOUTS2 VOUT2 VOUT 26ASW2 PGOOD2 PGOOD MODE_PLLIN CLKOUT INTV CC EXTVCC PGOOD1 PGOOD SGND GND DIFFP DIFFN DIFFOUT 10k* 5.1V* 120k 0.1µF 22µF 25V 4.7µF INTVCC 220pF INTVCC VOUT * PULL-UP RESISTOR AND ZENER ARE OPTIONAL V IN 7V TO 16V INTVCC L, LT, LT C, LT M, Linear Technology, the Linear logo, µModule, Burst Mode and PolyPhase are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
For more information www.linear.com/4620A pin conFiguraTionabsoluTe MaxiMuM raTings PGOOD1, PGOOD2, RUN1, RUN2, MODE_PLLIN, fSET, TRACK1, TRACK2, 3V to INTVCC to INTVCC Internal Operating Temperature Range 0°C to 125°C 5°C to 125°C Peak Package Body Temperature 5°C (Note 1) LGA PACKAGE 144-LEAD (15mm × 15mm × 4.41mm) TOP VIEW TEMP CLKOUT SW1 PHASMD EXTVCC 1 2 3 4 5 6 7 8 10 9 11 12 L K J H G F E D C B M A SW2 PGOOD1 PGOOD2 RUN2 TRACK2 INTVCC VOUTS2 DIFFP DIFFOUT DIFFN RUN1 TRACK1 MODE_PLLIN VFB1 VOUTS1 fSET SGND COMP1 COMP2 SGND VFB2 VIN VOUT2GND GND VOUT1 SGND GND TJMAX = 125°C, ΘJA = 7°C/W, ΘJCbottom = 1.5°C/W, ΘJCtop = 3.7°C/W, ΘJB + ΘJBA ≅ 7°C/W, weight = 3.037g Θ VALUES DEFINED PER JESD 51-12 LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTM4620AEV#PBF LTM4620AEV#PBF LTM4620AV 144-Lead (15mm × 15mm × 4.41mm) LGA –40°C to 125°C LTM4620AIV#PBF LTM4620AIV#PBF LTM4620AV 144-Lead (15mm × 15mm × 4.41mm) LGA –40°C to 125°C Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ orDer inForMaTion SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input DC Voltage l 4.5 16 V VOUT Output Voltage (Note 8) l 0.6 5.3 V VOUT1(DC), VOUT2(DC) Output Voltage, Total Variation with Line and Load C IN = 22µF × 3, COUT = 100µF × 1 Ceramic, 220µF POSCAP l 1.477 1.5 1.523 V Input Specifications VRUN1, VRUN2 RUN Pin On/Off Threshold RUN Rising 1.1 1.25 1.40 V VRUN1HYS, VRUN2HYS RUN Pin On Hysteresis 150 mV IINRUSH(VIN) Input Inrush Current at Start-Up I OUT = 0A, CIN = 22µF ×3, CSS = 0.01µF, COUT = 100µF ×3, VOUT1 = 1.5V, VOUT2 = 1.5V, VIN = 12V 1 A elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 26.
For more information www.linear.com/4620A elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 26. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IQ(VIN) Input Supply Bias Current V IN = 12V, VOUT = 1.5V, Burst Mode Operation VIN = 12V, VOUT = 1.5V, Pulse-Skipping Mode VIN = 12V, VOUT= 1.5V, Switching Continuous Shutdown, RUN = 0, VIN = 12V mA mA mA µA I S(VIN) Input Supply Current VIN = 5V, VOUT = 1.5V, IOUT = 13A VIN = 12V, VOUT = 1.5V, IOUT = 13A 4.6 1.853 A A Output Specifications I OUT1(DC), IOUT2(DC) Output Continuous Current Range V IN = 12V, VOUT = 1.5V (Notes 7, 8) 0 13 A ΔVOUT1(LINE)/VOUT1 ΔVOUT2(LINE)/VOUT2 Line Regulation Accuracy VOUT = 1.5V, VIN from 4.75V to 16V IOUT = 0A for Each Output, l 0.01 0.025 %/V ΔVOUT1/VOUT1 ΔVOUT2/VOUT2 Load Regulation Accuracy For Each Output, V OUT = 1.5V, 0A to 13A VIN = 12V (Note 7) l 0.35 0.5 % VOUT1(AC), VOUT2(AC) Output Ripple Voltage For Each Output, IOUT = 0A, COUT = 100µF ×3/ X7R/Ceramic, 470µF POSCAP, VIN = 12V, VOUT = 1.5V, Frequency = 400kHz 15 mVP-P fS (Each Channel) Output Ripple Voltage Frequency V IN = 12V, VOUT = 1.5V, fSET = 1.25V (Note 4) 500 kHz fSYNC (Each Channel) SYNC Capture Range 400 780 kHz ΔVOUTSTART (Each Channel) Turn-On Overshoot COUT = 100µF/X5R/Ceramic, 470µF POSCAP, VOUT = 1.5V, IOUT = 0A VIN = 12V mV mV t START (Each Channel) Turn-On Time COUT = 100µF/X5R/Ceramic, 470µF POSCAP, No Load, TRACK/SS with 0.01µF to GND, V IN = 12V ms ms ΔVOUT(LS) (Each Channel) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load COUT = 22µF ×3/X5R/Ceramic, 470µF POSCAP VIN = 12V, VOUT = 1.5V 30 mV tSETTLE (Each Channel) Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, V IN = 12V, COUT = 100µF, 470µF POSCAP 20 µs IOUT(PK) (Each Channel) Output Current Limit VIN = 12V, VOUT = 1.5V 20 A Control Section VFB1, VFB2 Voltage at VFB Pins IOUT = 0A, VOUT = 1.5V l 0.592 0.600 0.606 V IFB (Note 6) –5 –20 nA VOVL Feedback Overvoltage Lockout l 0.64 0.66 0.68 V TRACK1 (I), TRACK2 (I) T rack Pin Soft-Start Pull-Up Current TRACK1 (I),TRACK2 (I) Start at 0V 1 1.25 1.5 µA UVLO Undervoltage Lockout VIN Falling VIN Rising 3.3 3.9 V V UVLO Hysteresis 0.6 V t ON(MIN) Minimum On-Time (Note 6) 90 ns RFBHI1, RFBHI2 Resistor Between VOUTS1, VOUTS2 and VFB1, VFB2 Pins for Each Output 59.90 60.4 60.75 kΩ VPGOOD1, VPGOOD2 Low PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V IPGOOD PGOOD Leakage Current VPGOOD = 5V ±5 µA VPGOOD PGOOD T rip Level VFB with Respect to Set Output Voltage VFB Ramping Negative VFB Ramping Positive –10
For more information www.linear.com/4620A elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range. Specified as each individual output channel. TA = 25°C (Note 2), VIN = 12V and VRUN1, VRUN2 at 5V unless otherwise noted. Per the typical application in Figure 26. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS INTVCC Linear Regulator VINTVCC Internal VCC Voltage 6V < VIN < 16V 4.8 5 5.2 V VINTVCC Load Regulation INTVCC Load Regulation ICC = 0mA to 50mA 0.5 2 % VEXTVCC EXTVCC Switchover Voltage EXTV CC Ramping Positive 4.5 4.7 V VEXTVCC(DROP) EXTVCC Dropout ICC = 20mA, VEXTVCC = 5V 50 100 mV VEXTVCC(HYST) EXTVCC Hysteresis 200 mV Oscillator and Phase-Locked Loop Frequency Nominal Nominal Frequency fSET = 1.2V 450 500 550 kHz Frequency Low Lowest Frequency fSET = 0V (Note 5) 210 250 290 kHz Frequency High Highest Frequency fSET > 2.4V , Up to INTVCC 700 780 860 kHz fSET Frequency Set Current 9 10 11 µA RMODE_PLLIN MODE_PLLIN Input Resistance 250 kΩ CLKOUT Phase (Relative to VOUT1) PHASMD = GND PHASMD = Float PHASMD = INTV CC 120 Deg Deg Deg CLK High CLK Low Clock High Output Voltage Clock Low Output Voltage 0.2 V V Differential Amplifier A V Differential Amplifier Gain 1 V RIN Input Resistance Measured at DIFFP Input 80 kΩ VOS Input Offset Voltage VDIFFP = VDIFFOUT = 1.5V, IDIFFOUT = 100µA 3 mV PSRR Differential Amplifier Power Supply Rejection Ratio 5V < V IN < 16V 90 dB ICL Maximum Output Current 2 mA VOUT(MAX) Maximum Output Voltage IDIFFOUT = 300µA INTVCC – 1.4 V GBW Gain Bandwidth Product 3 MHz VTEMP Diode Connected PNP I = 100µA 0.6 V TC Temperature Coefficient l 2.2 mV/C Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4620A is tested under pulsed load conditions such that TJ ≈ TA. The LTM4620AE is guaranteed to meet specifications from 0°C to 125°C internal temperature. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4620AI is guaranteed over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: Tw o outputs are tested separately and the same testing condition is applied to each output. Note 4: The switching frequency is programmable from 400kHz to 750kHz. Note 5: The LTM4620A is designed to operate from 400kHz to 750kHz Note 6: These parameters are tested at wafer sort. Note 7: See output current derating curves for different V IN, VOUT and TA. Note 8: Output current limitations. For 10V ≤ VIN ≤ 16V, the 5V output current needs to be limited to 12A/channel, switching frequency = 750kHz. Derating cur ves apply. For 7V ≤ VIN ≤ 9V, the 5V output current needs to be limited to 13A/channel, switching frequency = 750kHz. Derating curves apply. All other input and output combinations are 13A/channel with recommended switching frequency included in the efficiency graphs. Derating curves apply.
For more information www.linear.com/4620A Typical perForMance characTerisTics 12V to 1V Load Step Response 12V to 1.8V Load Step Response 12V to 1.2V Load Step Response 12V to 2.5V Load Step Response 12V to 1.5V Load Step Response 12V to 3.3V Load Step Response Efficiency vs Output Current, VIN = 8V Efficiency vs Output Current, V IN = 12V Efficiency vs Output Current, V IN = 5V OUTPUT CURRENT (A) EFFICIENCY (%) 100 4620A G01 10.8 12.2 5V TO 1V (400kHz) 5V TO 1.2V (400kHz) 5V TO 1.5V (400kHz) 5V TO 1.8V (500kHz) 5V TO 2.5V (500kHz) 5V TO 3.3V (500kHz) 20mV/DIV 50µs/DIV CFF = 150pF COUT = 2 × 470µF 9m/uni03A9 EACH POSCAP 1 × 100µF CERAMIC 4620A G04 5A/DIV 6A/µs STEP 20mV/DIV 50µs/DIV CFF = 150pF COUT = 2 × 470µF 9m/uni03A9 EACH POSCAP 1 × 100µF CERAMIC 4620A G05 5A/DIV 6A/µs STEP 50mV/DIV 50µs/DIV CFF = 47pF COUT = 220µF 9m/uni03A9 POSCAP 100µF CERAMIC 4620A G06 5A/DIV 6A/µs STEP 50mV/DIV 50µs/DIV CFF = 33pF COUT = 220µF 9m/uni03A9 POSCAP 100µF CERAMIC 4620A G07 5A/DIV 6A/µs STEP 50mV/DIV 50µs/DIV CFF = 100pF COUT = 220µF 9m/uni03A9 POSCAP 100µF CERAMIC 4620A G08 5A/DIV 6A/µs STEP 100mV/DIV 50µs/DIV CFF = 33pF COUT = 100µF 15m/uni03A9 POSCAP 100µF CERAMIC 4620A G09 5A/DIV 6A/µs STEP OUTPUT CURRENT (A) EFFICIENCY (%) 100 4620A G02 10.8 12.2 8V TO 1V (400kHz) 8V TO 1.2V (400kHz) 8V TO 1.5V (500kHz) 8V TO 1.8V (600kHz) 8V TO 2.5V (650kHz) 8V TO 3.3V (700kHz) 8V TO 5V (750kHz) TIE 5V OUT TO EXTVCC OUTPUT CURRENT (A) EFFICIENCY (%) 100 4620A G03 10.8 12.2 12V TO 1V (400kHz) 12V TO 1.2V (400kHz) 12V TO 1.5V (500kHz) 12V TO 1.8V (600kHz) 12V TO 2.5V (650kHz) 12V TO 3.3V (700kHz) 12V TO 5V (750kHz) TIE 5V OUT TO EXTVCC
For more information www.linear.com/4620A Typical perForMance characTerisTics 12V to 5V Load Step Response Single Phase Start-Up, 13A Load Output Current Sharing 12V to 1.5V, 0A Load Short-Circuit Testing 12V to 1.5V, 13A No Load Short-Circuit Testing 12V to 1.5V Start-Up, No Load 500mV/DIV 10ms/DIV 12VIN, 1.5VOUT AT NO LOAD COUT = 2 × 470µF , 4V SANYO POSCAP , 1 × 100µF , 6.3V CERAMIC SOFT-START CAPACITOR = 0.01µF USE RUN PIN TO CONTROL START-UP 4620A G12 500mV/DIV 10ms/DIV 12VIN, 1.5VOUT AT 13A LOAD COUT = 2 × 470µF , 4V SANYO POSCAP , 1 × 100µF , 6.3V CERAMIC SOFT-START CAPACITOR = 0.01µF USE RUN PIN TO CONTROL START-UP 4620A G13 500mV/DIV 1A/DIV 25ms/DIV 12VIN, 1.5VOUT AT 0A LOAD COUT = 2 × 470µF , 4V SANYO POSCAP , 1 × 100µF , 6.3V X5R CERAMIC SOFT-START CAPACITOR = 0.01µF USE RUN PIN TO CONTROL START-UP 4620A G14 500mV/DIV 10A/DIV 25ms/DIV 12VIN, 1.5VOUT AT 13A LOAD COUT = 2 × 470µF , 4V SANYO POSCAP , 1 × 100µF , 6.3V X5R CERAMIC SOFT-START CAPACITOR = 0.01µF USE RUN PIN TO CONTROL START-UP 4620A G15 100mV/DIV 50µs/DIV CFF = 47pF COUT = 100µF CERAMIC X7R 4620A G10 5A/DIV 6A/µs STEP TOTAL OUTPUT CURRENT (A) EACH CHANNEL CURRENT (A) 4620A G11 19 224 8 162 6 11
1 IOUT1
For more information www.linear.com/4620A pin FuncTions VOUT1 (A1-A5, B1-B5, C1-C4): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. Review Table 5. See Note 8 in the Electrical Characteristics section for output current guideline. GND (A6-A7, B6-B7, D1-D4, D9-D12, E1-E4, E10-E12, F1-F3, F10-F12, G1, G3, G10, G12, H1-H7, H9-H12, J1, J5, J8, J12, K1, K5-K8, K12, L1, L12, M1 , M12): Power Ground Pins for Both Input and Output Returns. V OUT2 (A8-A12, B8-B12, C9-C12): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance di- rectly between these pins and GND pins. Review Table 5. See Note 8 in the Electrical Characteristics section for output current guideline. V OUTS1, VOUTS2 (C5, C8): This pin is connected to the top of the internal top feedback resistor for each output. The pin can be directly connected to its specific output, or connected to DIFFOUT when the remote sense amplifier is used. In paralleling modules, one of the V OUTS pins is connected to the DIFFOUT pin in remote sensing or directly to VOUT with no remote sensing. It is very important to connect these pins to either the DIFFOUT or V OUT since this is the feedback path, and cannot be left open. See the Applications Information section. fSET (C6): Frequency Set Pin. A 10µA current is sourced from this pin. A resistor from this pin to ground sets a voltage that in turn programs the operating frequency. Alternatively, this pin can be driven with a DC voltage that can set the operating frequency. See the Applications Information section. SGND (C7, D6, G6-G7, F6-F7): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the ap- plication. See layout guidelines in Figure 25. V FB1, V FB2 (D5, D7): The Negative Input of the Error Amplifier for Each Channel. Internally, this pin is con- nected to V OUTS1 or V OUTS2 with a 60.4kΩ precision resistor. Different output voltages can be programmed with an additional resistor between VFB and GND pins. In PolyPhase® operation, tying the VFB pins together allows for parallel operation. See the Applications Information section for details. TRACK1, TRACK2 (E5, D8): Output Voltage T racking Pin and Soft-Start Inputs. Each channel has a 1.3µA pull-up current source. When one channel is configured to be master of the two channels, then a capacitor from this pin to ground will set a soft-start ramp rate. The remaining channel can be set up as the slave, and have the master’s output applied through a voltage divider to the slave out- put’s track pin. This voltage divider is equal to the slave output’s feedback divider for coincidental tracking. See the Applications Information section. COMP1, COMP2 (E6, E7): Current control threshold and error amplifier compensation point for each channel. The current comparator threshold increases with this control voltage. Tie the COMP pins together for parallel operation. The device is internal compensated. DIFFP (E8): Positive input of the remote sense amplifier. This pin is connected to the remote sense point of the output voltage. Diffamp can be used for ≤3.3V outputs. See the Applications Information section. DIFFN (E9): Negative input of the remote sense amplifier. This pin is connected to the remote sense point of the output GND. Diffamp can be used for ≤3.3V outputs. See the Applications Information section. MODE_PLLIN (F4): Force Continuous Mode, Burst Mode Operation, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to SGND to force both channels into force continuous mode of operation. Connect to INTV CC to enable pulse-skipping mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock on the pin will force both channels into continuous mode of operation and synchronized to the external clock applied to this pin. (Recommended to Use Test Points to Monitor Signal Pin Connections.) PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y.
For more information www.linear.com/4620A pin FuncTions RUN1, RUN2 (F5, F9): Run Control Pin. A voltage above 1.25V will turn on each channel in the module. A voltage below 1.25V on the RUN pin will turn off the related chan- nel. Each RUN pin has a 1µA pull-up current, once the RUN pin reaches 1.2V an additional 4.5µA pull-up current is added to this pin. DIFFOUT (F8): Internal Remote Sense Amplifier Output. Connect this pin to VOUTS1 or VOUTS2 depending on which output is using remote sense. In parallel operation con- nect one of the VOUTS pin to DIFFOUT for remote sensing. Diffamp can be used for ≤3.3V outputs. SW1, SW2 (G2, G11): Switching node of each channel that is used for testing purposes. Also an R-C snubber network can be applied to reduce or eliminate switch node ringing, or otherwise leave floating. See the Applications Information section. PHASMD (G4): Connect this pin to SGND, INTV CC, or float- ing this pin to select the phase of CLKOUT to 60 degrees, 120 degrees, and 90 degrees respectively. CLKOUT (G5): Clock output with phase control using the PHASMD pin to enable multiphase operation between devices. See the Applications Information section. PGOOD1, PGOOD2 (G 9, G8): Output Voltage Power Good Indicator. Open drain logic output that is pulled to ground when the output voltage is not within ±7.5% of the regulation point. INTVCC (H8): Internal 5V Regulator Output. The control circuits and internal gate drivers are powered from this voltage. Decouple this pin to PGND with a 4.7µF low ESR tantalum or ceramic. INTVCC is activated when either RUN1 or RUN2 is activated. TEMP (J6): Onboard Temperature Diode for Monitoring the VBE Junction Voltage Change with Temperature. See the Applications Information section. EXTV CC (J7): External power input that is enabled through a switch to INTVCC whenever EXTVCC is greater than 4.7V. Do not exceed 6V on this input, and connect this pin to VIN when operating VIN on 5V. An efficiency increase will occur that is a function of the (V IN – INTVCC) multiplied by power MOSFET driver current. Typical current require- ment is 30mA. VIN must be applied before EXTV CC, and EXTVCC must be removed before VIN. A 5V output can be tied to this pin to increase efficiency. See Applications Information section. V IN (M2-M11, L2-L11, J2-J4, J9-J11, K2-K4, K9-K11): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between VIN pins and GND pins. (Recommended to Use Test Points to Monitor Signal Pin Connections.)
TA = 25°C. Use Figure 1 configuration. Figure 1. Simplified LTM4620A Block Diagram
Figure 26. See Note 8 in the Electrical Characteristics section for output current guideline. can be externally synchronized from 400kHz to 780kHz. SET pin. See the Applications Information section. limit and foldback current limit in an overcurrent condition. voltage exits a ±10% window around the regulation point. bottom MOSFET will turn on to clamp the output voltage. is feedback voltage referred. the regulator. See the Applications Information section. Tool will be provided for transient and stability analysis. allel operation sensing the output voltage at the load point. different levels. See the Applications Information section. Information section for details. edges. See the Applications Information section for details.
For more information www.linear.com/4620A applicaTions inForMaTion Input Capacitors The LTM4620A module should be connected to a low ac- impedance DC source. For the regulator input four 22µF input ceramic capacitors are used for RMS ripple current. A 47µF to 100µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this bulk capacitor is not needed. For a buck converter, the switching duty-cycle can be estimated as: D = VOUT VIN Without considering the inductor current ripple, for each output, the RMS current of the input capacitor can be estimated as: ICIN(RMS) = IOUT(MAX) η% • D • 1− D( ) In the above equation, η% is the estimated efficiency of the power module. The bulk capacitor can be a switcher- rated electrolytic aluminum capacitor, Polymer capacitor. Output Capacitors The LTM4620A is designed for low output voltage ripple noise and good transient response. The bulk output capacitors defined as C OUT are chosen with low enough effective series resistance (ESR) to meet the output volt- age ripple and transient requirements. COUT can be a low ESR tantalum capacitor, the low ESR polymer capacitor or ceramic capacitor. The typical output capacitance range for each output is from 200µF to 470µF. Additional output filtering may be required by the system designer, if further reduction of output ripples or dynamic transient spikes is required. Table 5 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 7A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to optimize the transient performance. Stability criteria are considered in the Table 5 matrix, and the Linear Technology µModule Power Design Tool will be provided for stability analysis. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. The Linear Technology µModule Power Design Tool can calculate the output ripple reduc- tion as the number of implemented phases increases by N times. A small value 10Ω to 50Ω resistor can be place in series from V OUT to the VOUTS pin to allow for a bode plot analyzer to inject a signal into the control loop and validate the regulator stability. The same resistor could be place in series from V OUT to DIFFP and a bode plot analyzer could inject a signal into the control loop and validate the regulator stability.
For more information www.linear.com/4620A applicaTions inForMaTion Burst Mode Operation The LTM4620A is capable of Burst Mode operation on each regulator in which the power MOSFETs operate in- termittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. Burst Mode operation is enabled with the MODE/PLLIN pin floating. During this operation, the peak current of the inductor is set to approximately one third of the maximum peak current value in normal opera- tion even though the voltage at the COMP pin indicates a lower value. The voltage at the COMP pin drops when the inductor’s average current is greater than the load requirement. As the COMP voltage drops below 0.5V, the BURST comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current to about 450µA for each output. The load current is now being supplied from the output capacitors. When the output voltage drops, caus- ing COMP to rise above 0.5V, the internal sleep line goes low, and the LTM4620A resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Either regulator can be configured for Burst Mode operation. Pulse-Skipping Mode Operation In applications where low output ripple and high effi- ciency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the LTM4620A to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE/PLLIN pin to INTV CC enables pulse-skipping operation. At light loads the internal current comparator may remain tripped for several cycles and force the top MOSFET to stay off for several cycles, thus skipping cycles. The inductor current does not reverse in this mode. This mode will maintain higher effective frequencies thus lower output ripple and lower noise than Burst Mode operation. Either regulator can be configured for pulse-skipping mode. Forced Continuous Operation In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE/PLLIN pin to GND. In this mode, induc- tor current is allowed to reverse during low output loads, the COMP voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continu- ous mode is disabled and inductor current is prevented from reversing until the LTM4620A’s output voltage is in regulation. Either regulator can be configured for force continuous mode. Multiphase Operation For output loads that demand more than 13A of current, two outputs in LTM4620A or even multiple LTM4620As can be paralleled to run out of phase to provide more output current without increasing input and output volt- age ripples. The MODE/PLLIN pin allows the LTM4620A to synchronize to an external clock (between 400kHz and 780kHz) and the internal phase-locked-loop allows the LTM4620A to lock onto an incoming clock phase as well. The CLKOUT signal can be connected to the MODE/PLLIN pin of the following stage to line up both the frequency and the phase of the entire system. Tying the PHMODE pin to INTV CC, SGND, or (floating) generates a phase difference (between MODE/PLLIN and CLKOUT) of 120 degrees, 60 degrees, or 90 degrees respectively. A total of 12 phases can be cascaded to run simultaneously with respect to each other by programming the PHMODE pin of each LTM4620A channel to different levels. Figure 3 shows a 2-phase design, 4-phase design and a 6-phase design example for clock phasing with the PHASMD table. A multiphase power supply significantly reduces the amount of ripple current in both the input and output ca- pacitors. The RMS input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater
than the number of phases used times the output voltage). to achieve a single high output current design. Figure 3. Examples of 2-Phase, 4-Phase, and 6-Phase Operation with PHASMD Table
180 PHASE0 PHASE
90 DEGREE
270 PHASE90 PHASE
60 DEGREE 60 DEGREE
240 PHASE60 PHASE
300 PHASE120 PHASE
Figure 4. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle efficiency by lowering power MOSFET switching losses. reference to the highest output voltage.
For more information www.linear.com/4620A applicaTions inForMaTion The TRACK pin can be controlled by a capacitor placed on the regulator TRACK pin to ground. A 1.3µA current source will charge the TRACK pin up to the reference voltage and then proceed up to INTVCC. After the 0.6V ramp, the TRACK pin will no longer be in control, and the internal voltage reference will control output regulation from the feedback divider. Foldback current limit is disabled during this sequence of turn-on during tracking or soft-starting. The TRACK pins are pulled low when the RUN pin is below 1.2V. The total soft-start time can be calculated as: tSOFT-START = CSS 1.3µA ⎠⎟ • 0.6 Regardless of the mode selected by the MODE/PLLIN pin, the regulator channels will always start in pulse-skipping mode up to TRACK = 0.5V. Between TRACK = 0.5V and 0.54V, it will operate in forced continuous mode and revert to the selected mode once TRACK > 0.54V. In order to track with another channel once in steady state operation, the LTM4620A is forced into continuous mode operation as soon as V FB is below 0.54V regardless of the setting on the MODE/PLLIN pin. Ratiometric tracking can be achieved by a few simple cal- culations and the slew rate value applied to the master’s TRACK pin. As mentioned above, the TRACK pin has a control range from 0 to 0.6V. The master’s TRACK pin slew rate is directly equal to the master’s output slew rate in Volts/Time. The equation: MR SR • 60.4k = RTB where MR is the master’s output slew rate and SR is the slave’s output slew rate in Volts/Time. When coincident tracking is desired, then MR and SR are equal, thus R TB is equal the 60.4k. RTA is derived from equation: RTA = 0.6V VFB 60.4k + VFB RFB − VTRACK RTB where VFB is the feedback voltage reference of the regula- tor, and VTRACK is 0.6V. Since R TB is equal to the 60.4k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then RTA is equal to RFB with VFB = VTRACK. Therefore RTB = 60.4k, and RTA = 60.4k in Figure 6. In ratiometric tracking, a different slew rate maybe desired for the slave regulator. R TB can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach it final value before the master output. For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then RTB = 76.8k. Solve for RTA to equal to 49.9k. Each of the TRACK pins will have the 1.3µA current source on when a resistive divider is used to implement tracking on that specific channel. This will impose an offset on the TRACK pin input. Smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. For example, where the 60.4k is used then a 6.04k can be used to reduce the TRACK pin offset to a negligible value. Power Good The PGOOD pins are open drain pins that can be used to monitor valid output voltage regulation. This pin monitors a ±10% window around the regulation point. A resistor can be pulled up to a particular supply voltage no greater than 6V maximum for monitoring. Stability Compensation The module has already been internally compensated for all output voltages. Table 5 is provided for most ap- plication requirements. The Linear Technology µModule Power Design Tool will be provided for other control loop optimization. Run Enable The RUN pins have an enable threshold of 1.4V maximum, typically 1.25V with 150mV of hysteresis. They control the turn on each of the channels and INTVCC. These pins can be pulled up to VIN for 5V operation, or a 5V Zener diode can be placed on the pins and a 10k to 100k resistor can be placed up to higher than 5V input for enabling the channels. The RUN pins can also be used for output voltage sequencing. In parallel operation the RUN pins can be tie together and
For more information www.linear.com/4620A applicaTions inForMaTion controlled from a single control. See the Typical Applica- tion circuits in Figure 26. INTVCC and EXTVCC The LTM4620A module has an internal 5V low dropout regulator that is derived from the input voltage. This regu- lator is used to power the control circuitry and the power MOSFET drivers. This regulator can source up to 70mA, and typically uses ~30mA for powering the device at the maximum frequency. This internal 5V supply is enabled by either RUN1 or RUN2. EXTVCC allows an external 5 V supply to power the LTM4620A and reduce power dissipation from the internal low dropout 5V regulator. The power loss savings can be calculated by: VIN – 5V) • 30mA = PLOSS EXTVCC has a threshold of 4.7V for activation, and a maxi- mum rating of 6V. When using a 5V input, connect this 5V input to EXTVCC also to maintain a 5V gate drive level. EXTVCC must sequence on after V IN, and EXTV CC must sequence off before V IN. When designing a 5V output, connect this 5V output to EXTVCC. Use an external 5V bias on EXTVCC to improve efficiency. Differential Remote Sense Amplifier An accurate differential remote sense amplifier is provided to sense low output voltages accurately at the remote load points. This is especially true for high current loads. The amplifier can be used on one of the two channels, or on a single parallel output. It is very important that the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to either V OUTS1 or V OUTS2. In parallel operation, the DIFFP and DIFFN are connected properly at the output, and DIFFOUT is connected to one of the VOUTS pins. Review the parallel schematics in Figure 29 and review Figure 2. The diffamp can only be used for output voltage ≤3.3V. SW Pins The SW pins are generally for testing purposes by moni- toring these pins. These pins can also be used to dampen out switch node ringing caused by LC parasitic in the switched current paths. Usually a series R-C combina- tion is used called a snubber circuit. The resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor. If the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond wire inductance. First the SW pin can be monitored with a wide bandwidth scope with a high frequency scope probe. The ring fre- quency can be measured for its value. The impedance Z can be calculated: Z(L) = 2πfL, where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to Z, then the ringing should be dampened. The snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. Calculated by: Z(C) = 1/(2πfC). These values are a good place to start with. Modification to these components should be made to attenuate the ringing with the least amount of power loss. Temperature Monitoring Measuring the absolute temperature of a diode is pos- sible due to the relationship between current, voltage and temperature described by the classic diode equation: ID =IS • e VD η • VT or VD = η• VT • lnID IS where ID is the diode current, V D is the diode voltage, η is the ideality factor (typically close to 1.0) and IS (satura- tion current) is a process dependent parameter. V T can be broken out to: VT = k • T q
composite diode voltage slope. Figure 8. Diode Voltage VD vs Temperature remove the IS dependency from the following equation. a zero intercept at 0 Kelvin.
Package Thermal Information”). formance to one’s own application.
- θJA, the thermal resistance from junction to ambient, is
air” although natural convection causes the air to move. an actual application or viable operating condition. dissipation flowing through the bottom of the package. the heat flows from the junction to the top of the part. generally match the user’s application. Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients
For more information www.linear.com/4620A 4. θJB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule and into the board, and is really the sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder joints and through a por- tion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD 51-9. A graphical representation of the aforementioned ther- mal resistances is given in Figure 9; blue resistances are contained within the µModule regulator, whereas green resistances are external to the µModule. As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD 51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a µModule. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclu- sively through the top or exclusively through bottom of the µModule—as the standard defines for θJCtop and θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. Within a SIP (system-in-package) module, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also, not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the µModule and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JSED51-9 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the µModule with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. An outcome of this process and due-diligence yields a set of derating curves provided in other sections of this data sheet. After these laboratory test have been performed and correlated to the µModule model, then the θJB and θBA are summed together to cor- relate quite well with the µModule model with no airflow or heat sinking in a properly define chamber. This θJB + θBA value is shown in the Pin Configuration section and should accurately equal the θJA value because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink. Each system has its own thermal characteristics, therefore thermal analysis must be performed by the user in a particular system. applicaTions inForMaTion
For more information www.linear.com/4620A Power Derating The 1V, 2.5V and 5V power loss curves in Figures 12 to 14 can be used in coordination with the load current derating curves in Figures 15 to 24 for calculating an approximate ΘJA thermal resistance for the LTM4620A with various heat sinking and airflow conditions. The power loss curves are taken at room temperature, and are increased with a 1.35 to 1.4 multiplicative factor at 125°C. These factors come from the fact that the power loss of the regulator increases about 45% from 25°C to 150°C, thus a 45% spread over 125°C delta equates to ~0.35%/°C loss increase. A 125°C maximum junction minus 25°C room temperature equates to a 100°C increase. This 100°C increase multiplied by 0.35%/°C equals a 35% power loss increase at the 125°C junction, thus the 1.35 multiplier. The derating curves are plotted with CH1 and CH2 in parallel single output operation starting at 26A of load with low ambient temperature. The output voltages are 1V, 2.5V and 5V. These are chosen to include the lower and higher output voltage ranges for correlating the ther- mal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at ~120°C maximum while lowering output current or power while increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased. The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example in Figure 15, the load current is derated to ~19A at ~80°C with no air or heat sink and the power loss for the 12V to 1.0V at 19A output is a ~5.1W loss. The 5.1W loss is calculated with the ~3.75W room temperature loss from the 12V to 1.0V power loss curve at 19A, and the 1.35 multiplying factor at 125°C ambient. If the 80°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 40°C divided 5.1W equals a 7.8°C/W ΘJA thermal resistance. Table 2 specifies a 6.5 to 7°C/W value which is pretty close. The airflow graphs are more accurate due to the fact that the ambient temperature environment is controlled better with airflow. As an example in Figure 16, the load current is derated to ~22A at ~90°C with 200LFM of airflow and the power loss for the 12V to 1.0V at 22A output is a ~5.94W loss. The 5.94W loss is calculated with the ~4.4W room tem- perature loss from the 12V to 1.0V power loss curve at 22A, and the 1.35 multiplying factor at 125°C ambient. If the 90°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 30°C divided 5.94W equals a 5.1°C/W Θ JA thermal resistance. Table 2 specifies a 5.5°C/W value which is pretty close. Tables 2-4 provide equivalent thermal resistances for 1.0V, 2.5V and 5V outputs with and without airflow and heat sinking. The derived thermal resistances in Tables 2-4 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves and adjusted with the above ambient temperature multiplicative factors. The printed circuit board is a 1.6mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. The PCB dimensions are 101mm × 114mm. The BGA heat sinks are listed below Table 4. applicaTions inForMaTion
Table 5. Output Voltage Response vs Component Matrix (Refer to Figure 23) 0A to 7A Load Step Typical Measured Values **Bulk capacitance is optional if VIN has very low input impedance.
Figure 26. Typical 5VIN to 16VIN, 1.5V and 1.2V Outputs
Figure 27. LTM4620A 2-Phase, 5V at 20A Design with Temperature Monitoring
Figure 28. LTM4620A 3.3V and 2.5V Output T racking
Figure 29. 4-Phase, 3.3V at 50A, 750kHz
For more information www.linear.com/4620A LTM4620A Component LGA Pinout package DescripTion PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 V OUT1 B1 V OUT1 C1 V OUT1 D1 GND E1 GND F1 GND A2 V OUT1 B2 V OUT1 C2 V OUT1 D2 GND E2 GND F2 GND A3 V OUT1 B3 V OUT1 C3 V OUT1 D3 GND E3 GND F3 GND A4 V OUT1 B4 V OUT1 C4 V OUT1 D4 GND E4 GND F4 MODE_PLLIN A5 V OUT1 B5 V OUT1 C5 V OUT1S D5 V FB1 E5 TRACK1 F5 RUN1 A6 GND B6 GND C6 f SET D6 SGND E6 COMP1 F6 SGND A7 GND B7 GND C7 SGND D7 V FB2 E7 COMP2 F7 SGND A8 V OUT2 B8 V OUT2 C8 V OUT2S D8 TRACK2 E8 DIFFP F8 DIFFOUT A9 V OUT2 B9 V OUT2 C9 V OUT2 D9 GND E9 DIFFN F9 RUN2 A10 V OUT2 B10 V OUT2 C10 V OUT2 D10 GND E10 GND F10 GND A11 V OUT2 B11 V OUT2 C11 V OUT2 D11 GND E11 GND F11 GND A12 V OUT2 B12 V OUT2 C12 V OUT2 D12 GND E12 GND F12 GND PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 GND J1 GND K1 GND L1 GND M1 GND G2 SW1 H2 GND J2 V IN K2 V IN L2 V IN M2 V IN G3 GND H3 GND J3 V IN K3 V IN L3 V IN M3 V IN G4 PHASEMD H4 GND J4 V IN K4 V IN L4 V IN M4 V IN G5 CLKOUT H5 GND J5 GND K5 GND L5 V IN M5 V IN G6 SGND H6 GND J6 TEMP K6 GND L6 V IN M6 V IN G7 SGND H7 GND J7 EXTV CC K7 GND L7 V IN M7 V IN G8 PGOOD2 H8 INTV CC J8 GND K8 GND L8 V IN M8 V IN G9 PGOOD1 H9 GND J9 V IN K9 V IN L9 V IN M9 V IN G10 GND H10 GND J10 V IN K10 V IN L10 V IN M10 V IN G11 SW2 H11 GND J11 V IN K11 V IN L11 V IN M11 V IN G12 GND H12 GND J12 GND K12 GND L12 GND M12 GND PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y.
For more information www.linear.com/4620A Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package DescripTion 144-Lead (15mm × 15mm × 4.41mm) (Reference L TC DWG # 05-08-1844 Rev B) Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. PACKAGE TOP VIEW PAD 1 CORNER DETAIL A PACKAGE BOTTOM VIEW3 PADS SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 L TMXXXXXX µModule DIA 0.630 PAD 1 3x, C (0.22 x45°) DETAIL A 0.630 ±0.025 SQ. 143x S Y X eee L K J H G F E D C B M A 1 2 3 4 5 6 7 810 911 12 144-Lead (15mm × 15mm × 4.41mm) (Reference L TC DWG # 05-08-1844 Rev B) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 144 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE LGA 144 0312 REV B TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” SYMBOL A b D E e F G aaa bbb eee MIN 4.31 0.60 0.36 3.95 NOM 4.41 0.63 15.00 15.00 1.27 13.97 13.97 0.41 4.00 MAX 4.51 0.66 0.46 4.05 0.15 0.10 0.05 NOTES DIMENSIONS TOTAL NUMBER OF LGA PADS: 144 X Y aaa Z aaa Z E D DETAIL B bbb ZDETAIL B SUBSTRATEMOLD CAP Z A be G e F b
For more information www.linear.com/4620A Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com LINEAR TECHNOLOGY CORPORA TION 2013 LT 0113 • PRINTED IN USA relaTeD parTs package phoTo PART NUMBER DESCRIPTION COMMENTS LTM4628 Dual 8A, Single 16A µModule Regulator Pin Compatible with LTM4620A; 4.5V ≤ V IN ≤ 26.5V, 0.6V ≤ VOUT ≤ 5.5V, 15mm × 15mm × 4.32mm LTM4627 15A µModule Regulator 4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 15mm × 15mm × 4.32mm LTM4611 Ultralow V IN, 15A µModule Regulator 1.5V ≤ V IN ≤ 5.5V, 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 4.32mm LTM4620 Dual 13A or Single 26A Lower Output Voltage Range, 0.6V to 2.5V, Pin Compatible Design resources SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:
- Selector Guides
- Demo Boards and Gerber Files
- Free Simulation T ools Manufacturing:
- Quick Start Guide
- PCB Design, Assembly and Manufacturing Guidelines
- Package and Board Level Reliability µModule Regulator Products Sear ch 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Sear ch parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging.