LTM4616 LINER | Alldatasheet
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FEATURES
APPLICATIONS
DESCRIPTION
VIN DC/DC µModule The L TM®4616 is a complete dual 2-phase 8A per channel switch mode DC/DC power regulator system in a 15mm × 15mm surface mount LGA package. Included in the package are the switching controller, power FETs, inductor and all support components. Operating from an input voltage range of 2.7V to 5.5V, the L TM4616 supports two outputs within a voltage range of 0.6V to 5V, each set by a single external resistor. This high effi ciency design delivers up to 8A continuous current (10A peak) for each output. Only bulk input and output capacitors are needed, depending on ripple requirement. The part can also be confi gured for a 2-phase single output at up to 16A. The low profi le package (2.82mm) enables utilization of unused space on the back side of PC boards for high density point-of-load regulation. Fault protection features include overvoltage protection, overcurrent protection and thermal shutdown. The power module is offered in a space saving and thermally enhanced 15mm × 15mm × 2.82mm LGA package. The L TM4616 is Pb-free and RoHS compliant. Different Combinations of Input and Output Number of Inputs Number of Outputs I OUT (MAX) 2 2 8A, 8A 2 1 16A 1 2 8A, 8A 1 1 16A Dual Output DC/DC μModule™ Regulator ■ Complete Dual DC/DC Regulator System ■ Input Voltage Range: 2.7V to 5.5V ■ Dual 8A Outputs, or Single 16A Output with a 0.6V to 5V Range ■ Output Voltage T racking and Margining ■ ±1.75% Total DC Output Error (–40°C to 125°C) ■ Current Mode Control/Fast T ransient Response ■ Power-Good T racking and Margining ■ Overcurrent/Thermal Shutdown Protection ■ Onboard Frequency Synchronization ■ Spread Spectrum Frequency Modulation ■ Multiphase Operation ■ Selectable Burst Mode ® Operation ■ Output Overvoltage Protection ■ Gold-Pad Finish Allows Soldering with Pb and Pb- Free Solder Paste ■ Small Surface Mount Footprint, Low Profi le (15mm × 15mm × 2.82mm) LGA Package ■ Telecom, Networking and Industrial Equipment ■ Storage and ATCA, PCI Express Cards ■ Battery Operated Equipment Effi ciency vs Load Current TYPICAL APPLICATION L, L T , L TC, L TM and Burst Mode are registered trademarks of Linear Technology Corporation. μModule is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6724174. 3.09k 100μF10μF VIN2 3.3V TO 5V VOUT2 2.5V/8A VIN1 VIN2 VOUT1 FB1 ITHM1 VOUT2 FB2 ITHM2 GND1 GND2
4616 TA01a
L TM4616 2.21k 100μF10μF VIN1 5V VOUT1 3.3V/8A LOAD CURRENT (A) EFFICIENCY (%) 246
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5VIN 3.3VOUT 5VIN 2.5VOUT
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS PGOOD1, PLLLPF1, CLKIN1, PHMODE1, MODE1, PGOOD2, PLLLPF2, CLKIN2, IN ITH1, ITHM1, RUN1, FB1, TRACK1, MGN1, BSEL1, ITH2, ITHM2, RUN2, FB2, TRACK2, Internal Operating Temperature Range (Note 1) LGA PACKAGE 144-LEAD (15mm × 15mm × 2.8mm) TOP VIEW VIN2 VOUT2 12345678 1 0 91 1 1 2 L K J H G F E D C B M A SW1, I/O & CONTROL VOUT1 GND2 GND1 VIN1 SGND2 & CONTROL SGND1 & CONTROL SW2, I/O & CONTROL TJMAX = 125°C, θJP = 2°C/W , θJC = 16°C/W SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN1(DC), VIN2(DC) Input DC Voltage ● 2.7 5.5 V VOUT1(DC), VOUT2(DC) Output Voltage, Total Variation with Line and Load CIN = 10μF × 1, COUT = 100μF Ceramic, 100μF POSCAP , RFB = 6.65k VIN = 2.7V to 5.5V , IOUT = IOUT(DC)MIN to IOUT(DC)MAX (Note 4) ● 1.472 1.464 1.49 1.49 1.508 1.516 V V Input Specifi cations V IN1(UVLO), VIN2(UVLO) Undervoltage Lockout Threshold SV IN Rising SVIN Falling 2.05 1.85 2.2 2.0 2.35 2.15 V V The ● denotes the specifi cations which apply over the –40°C to 125°C internal operating temperature range. TA = 25°C, VIN = 5V unless otherwise noted. Per the typical application in Figure 18. Specifi ed as each channel (Note 3). LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION INTERNAL TEMPERATURE RANGE L TM4616EV#PBF L TM4616EV#PBF L TM4616V 144-Lead (15mm × 15mm × 2.82mm) LGA –40°C to 125°C L TM4616IV#PBF L TM4616IV#PBF L TM4616V 144-Lead (15mm × 15mm × 2.82mm) LGA –40°C to 125°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear .com/packaging/ ORDER INFORMATION
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the –40°C to 125°C internal operating temperature range. TA = 25°C, VIN = 5V unless otherwise noted. Per the typical application in Figure 18. Specifi ed as each channel (Note 3). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IQ(VIN1, VIN2) Input Supply Bias Current V IN = 3.3V, VOUT = 1.5V, No Switching, Mode = VIN VIN = 3.3V, VOUT = 1.5V, No Switching, Mode = 0V VIN = 3.3V, VOUT = 1.5V, Switching Continuous 400 1.15 μA mA mA V IN = 5V, VOUT = 1.5V, No Switching, Mode = VIN VIN = 5V, VOUT = 1.5V, No Switching, Mode = 0V VIN = 5V, VOUT = 1.5V, Switching Continuous 450 1.3 μA mA mA Shutdown, RUN = 0, V IN = 5V 1 μA IS(VIN1, VIN2) Input Supply Current V IN = 3.3V, VOUT = 1.5V, IOUT = 8A VIN = 5V, VOUT = 1.5V, IOUT = 8A 4.5 2.93 A A Output Specifi cations IOUT1(DC), IOUT2(DC) Output Continuous Current Range (Note 4) VOUT = 1.5V V IN = 3.3V, 5.5V V IN = 2.7V A A ΔVOUT1(LINE)/VOUT1 ΔVOUT2(LINE)/VOUT2 ΔVOUT1(LOAD)/VOUT1 ΔVOUT2(LOAD)/VOUT2 Load Regulation Accuracy V OUT = 1.5V (Note 4) V IN = 3.3V, 5.5V, ILOAD = 0A to 8A V IN = 2.7V, ILOAD = 0A to 5A 0.3 0.3 0.5 0.5 VOUT1(AC), VOUT2(AC) Output Ripple Voltage I OUT = 0A, COUT = 100μF X5R Ceramic, VIN = 5V, VOUT = 1.5V 10 mV P-P fS1, fS2 Switching Frequency I OUT = 8A, VIN = 5V, VOUT = 1.5V 1.25 1.5 1.75 MHz fSYNC1, fSYNC2 SYNC Capture Range 0.75 2.25 MHz ΔVOUT1(START), ΔVOUT2(START) Turn-On Overshoot C OUT = 100μF, VOUT = 1.5V, IOUT = 0A V IN = 3.3V V IN = 5V mV mV tSTART1, tSTART2 Turn-On Time C OUT = 100μF, VOUT = 1.5V, VIN = 5V, IOUT = 1A Resistive Load, T rack = VIN 100 μs ΔVOUT1(LS), ΔVOUT2(LS) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load, COUT = 100μF Ceramic x2, 470μF POSCAP, VIN = 5V, VOUT = 1.5V 20 mV tSETTLE1, tSETTLE2 Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, VIN = 5V, VOUT = 1.5V, COUT = 100μF 10 μs IOUT1(PK), IOUT2(PK) Output Current Limit C OUT = 100μF V IN = 2.7V, VOUT = 1.5V V IN = 3.3V, VOUT = 1.5V V IN = 5V, VOUT = 1.5V A A A Control Section FB1, FB2 Voltage at FB Pin I OUT = 0A, VOUT = 1.5V, VIN = 2.7V to 5.5V 0.590 0.587 0.596 0.596 0.602 0.606 V V SS Delay Internal Soft-Start Delay 90 μs IFB 0.2 μA VRUN1, VRUN2 RUN Pin On/Off Threshold RUN Rising RUN Falling 1.4 1.3 1.55 1.4 1.7 1.5 V V TRACK1, TRACK2 T racking Threshold (Rising) T racking Threshold (Falling) T racking Disable Threshold RUN = V IN RUN = 0V 0.57 0.18 VIN – 0.5 V V V
Effi ciency vs Load Current ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the –40°C to 125°C internal operating temperature range. TA = 25°C, VIN = 5V unless otherwise noted. Per the typical application in Figure 18. Specifi ed as each channel (Note 3). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS RFBHI1, RFBHI2 Resistor Between VOUT and FB Pins 9.95 10 10.05 kΩ ΔVPGOOD1, ΔVPGOOD2 PGOOD Range ±10 % %Margining Output Voltage Margining Percentage MGN = VIN, BSEL = 0V MGN = VIN, BSEL = VIN MGN = VIN, BSEL = Float MGN = 0V, BSEL = 0V MGN = 0V, BSEL = V IN MGN = 0V, BSEL = Float –14 –10 –15 –11 –16 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TM4616E is guaranteed to meet performance specifi cations over the 0°C to 125°C internal operating temperature range. Specifi cations over the full –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The L TM4616I is guaranteed to meet specifi cations over the full internal operating temperature range. Note that the maximum ambient temperature is determined by specifi c operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: T wo channels are tested separately and the same testing conditions are applied to each channel. Note 4: See Output Current Derating curves for different V IN, VOUT and TA. Effi ciency vs Load Current Effi ciency vs Load Current LOAD CURRENT EFFICIENCY (%) 100 24 68
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5VIN 1.2VOUT 5VIN 1.5VOUT 5VIN 1.8VOUT 5VIN 2.5VOUT 5VIN 3.3VOUT CONTINUOUS MODE LOAD CURRENT EFFICIENCY (%) 100 2468
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3.3VIN 1.2VOUT 3.3VIN 1.5VOUT 3.3VIN 1.8VOUT 3.3VIN 2.5VOUT CONTINUOUS MODE LOAD CURRENT (A) EFFICIENCY (%) 100 2 4 5
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2.7VIN 1.0VOUT 2.7VIN 1.5VOUT 2.7VIN 1.8VOUT CONTINUOUS MODE TYPICAL PERFORMANCE CHARACTERISTICSSpecifi ed as Each Channel
VIN (V) VOUT (V) 1.5 2.0 2.5 3 5
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1.0 0.5 12 4 3.0 3.5 4.0 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V IOUT = 5A VIN (V) VOUT (V) 1.5 2.0 2.5 3 5
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1.0 0.5 12 4 3.0 3.5 4.0 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V IOUT = 8A TYPICAL PERFORMANCE CHARACTERISTICS Burst Mode Effi ciency with 5V Input VIN to VOUT Step-Down Ratio Supply Current vs VIN Load T ransient Response Load T ransient Response VIN to VOUT Step-Down Ratio LOAD CURRENT (A) EFFICIENCY (%)60 100 0.2 0.4 0.6 0.8
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VOUT = 1.5V VOUT = 2.5V VOUT = 3.3V INPUT VOL TAGE (V) 2.5 SUPPL Y CURRENT (mA) 4.5 1.6 1.4 1.2 0.8 0.6 0.4 0.2
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3.53 54 5.5 VO = 1.2V PULSE-SKIPPING MODE VO = 1.2V BURST MODE ILOAD 1A/DIV VOUT 50mV/DIV 20μs/DIVVIN = 5V VOUT = 3.3V 2A/μs STEP C OUT = 2 × 100μF X5R, 470μF 4V POSCAP
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Specifi ed as Each Channel ILOAD 1A/DIV VOUT 50mV/DIV 20μs/DIVVIN = 5V VOUT = 2.5V 2A/μs STEP C OUT = 2 × 100μF X5R, 470μF 4V POSCAP
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Load T ransient Response Load T ransient Response Load T ransient Response ILOAD 1A/DIV VOUT 50mV/DIV 20μs/DIVVIN = 5V VOUT = 1.8V 2.5A/μs STEP C OUT = 2 × 100μF X5R, 470μF 4V POSCAP
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20μs/DIVVIN = 5V VOUT = 1.5V 2.5A/μs STEP C OUT = 2 × 100μF X5R, 470μF 4V POSCAP
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20μs/DIVVIN = 5V VOUT = 1.2V 2.5A/μs STEP C OUT = 2 × 100μF X5R, 470μF POSCAP
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GND1 and GND2 (BANK2 and BANK5); (A1-A5, A12, B1- B5, B7-B12, C3-C12, D3-D7) and (G1-G5, G12, H1-H5, H7-H12, J3-J12, K3-K7): Power Ground Pins for Both Input and Output Returns. SV IN1 and SVIN2 (E5 and L5): Signal Input Voltage for Each Channel. This pin is internally connected to V IN through a lowpass fi lter. SGND1 and SGND2 (F5 and M5): Signal Ground Pin for Each Channel. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND in the application. See layout guidelines in Figure 17. TEMPERATURE (°C) –50 VFB (mV) 592 594 596 25 75 100
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–25 0 50 598 600 602 125 VIN = 5.5V VIN = 3.3V VIN = 2.7V Start-Up V FB vs Temperature Load Regulation vs Current 2.5V Output Current Short-Circuit Protection (2.5V Short, No Load) VOUT 0.5V/DIV VIN 2V/DIV 50μs/DIVVIN = 5V VOUT = 1.5V COUT = 100μF NO LOAD AND 8A LOAD (DEFAUL T 100μs SOFT-START)
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LOAD CURRENT (A) –0.6 LOAD REGULATION (%) –0.5 –0.2 –0.3 –0.1 –0.4
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VIN = 3.3V VOUT = 1.5V Short-Circuit Protection (2.5V Short, 4A Load) OUTPUT CURRENT (A) OUTPUT VOLTAGE (V) 0.5 1.0 1.5 2.0 2.5 3.0 51 01 5 2 0
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50μs/DIV
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VIN = 5V VOUT = 2.5V 5V/DIV 5V/DIV 5A/DIV 5A/DIV 50μs/DIV
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VIN = 5V VOUT = 2.5V VIN1, VIN2, (BANK1 and BANK2); (F1-F4, E1-E4, C1-C2, D1-D2) and (J1-J2, K1-K2, L1-L4, M1-M4): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between V IN pins and GND pins. VOUT1, VOUT2 (BANK3 and BANK6); (D9-D12, E9-E12, F9-F12) and (K9-K12, L9-L12, M9-M12): Power Output Pins. Apply output load between these pins and GND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins. See Table 1. TYPICAL PERFORMANCE CHARACTERISTICSSpecifi ed as Each Channel PIN FUNCTIONS
PolyPhase is a registered trademark of Linear Technology Corporation. MODE1 and MODE2 (A8 and G8): Mode Select Input for Each Channel. Tying this pin high enables Burst Mode operation. Tying this pin low enables forced continuous operation. Floating this pin or tying it to V IN/2 enables pulse-skipping operation. CLKIN1 and CLKIN2 (A7 and G7): External Synchronization Input to Phase Detector for Each Channel. This pin is internally terminated to SGND with a 50k resistor. The phase-locked loop will force the internal top power PMOS turn on to be synchronized with the rising edge of the CLKIN signal. Connect this pin to SV IN to enable spread spectrum modulation. During external synchronization, make sure the PLLLPF pin is not tied to V IN or GND. PLLLPF1 and PLLLPF2 (E6 and L6): Phase-Locked Loop Lowpass Filter for Each Channel. An internal lowpass fi lter is tied to this pin. In spread spectrum mode, placing a capacitor here to SGND controls the slew rate from one frequency to the next. Alternatively, fl oating this pin allows normal running frequency at 1.5MHz, tying this pin to SV IN forces the part to run at 1.33 times its normal frequency (2MHz), tying it to ground forces the frequency to run at 0.67 times its normal frequency (1MHz). PHMODE1 and PHMODE2 (A9 and G9): Phase Selector Input for Each Channel. This pin determines the phase relationship between the internal oscillator and CLKOUT. Tie it high for 2-phase operation, tie it low for 3-phase operation, and fl oat or tie it to V IN/2 for 4-phase operation. MGN1 and MGN2 (A10 and G10): Voltage Margining Pin for Each Channel. Tie this pin to VOUT to disable margining. For margining, connect a voltage divider from VIN to GND with the center point connected to the MGN pin for the specifi c channel. Each resistor should be close to 50k. Margin High is within 0.3V of V IN, and Margin Low is within 0.3V of GND. See the Applications section and Figure 18 for margining control. The specifi ed tri-state drivers are capable of the high and low requirements for margining. BSEL1 and BSEL2 (A6 and G6): Margining Bit Select Pin for Each Channel. Tying BSEL low selects ±5% margin value, tying it high selects 10% margin value. Floating it or tying it to V IN/2 selects 15% margin value. TRACK1 and TRACK2 (E8 and L8): Output Voltage T racking Pin for Each Channel. Voltage tracking is enabled when the TRACK voltage is below 0.57V. If tracking is not desired, then connect the TRACK pin to SV IN. If TRACK is not tied to SVIN, then the TRACK pin’s voltage needs to be below 0.18V before the chip shuts down even though RUN is already low. Do not fl oat this pin. A resistor and capacitor can be applied to the TRACK pin to increase the soft-start time of the regulator. TRACK1 and TRACK2 can be tied together for parallel operation and tracking. See the Applications section. FB1 and FB2 (D8 and K8): The Negative Input of the Error Amplifi er for Each Channel. Internally, this pin is connected to V OUT with a 10k precision resistor. Different output voltages can be programmed with an additional resistor between FB and GND pins. In PolyPhase ® operation, tying the FB pins together allows for parallel operation. See Applications section for details. I TH1 and ITH2 (F8 and M8): Current Control Threshold and Error Amplifi er Compensation Point for Each Channel. The current comparator threshold increases with this control voltage. Tie together in parallel operation. I THM1 and ITHM2 (E7 and L7): Negative Input to the Internal ITH Differential Amplifi er for Each Channel. Tie this pin to SGND for single phase operation on each channel. For PolyPhase operation, tie the master’s I THM to SGND while connecting all of the ITHM pins together at the master. PGOOD1 and PGOOD2 (A11 and G11): Output Voltage Power Good Indicator for Each Channel. Open-drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point. Power good is disabled during margining. RUN1 and RUN2 (F6 and M6): Run Control Pin. A voltage above 1.5V will turn on the module. SW1 and SW2 (B6 and H6): Switching Node of Each Channel That is Used for Testing Purposes. This can be connected to copper on the board for improved thermal performance. CLKOUT1 and CLKOUT2 (F7 and M7): Output Clock Signal for PolyPhase Operation. The phase of CLKOUT is determined by the state of the PHMODE pin.
Figure 1. Simplifi ed L TM4616 Block Diagram
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Table 1. Decoupling Requirements. TA = 25°C, Block Diagram Confi guration. 8A outputs with few external input and output capacitors. schematic is shown in Figure 18. be externally synchronized from 0.75MHz to 2.25MHz. limit and thermal shutdown in an overcurrent condition. voltage exits a ±10% window around the regulation point. The power good pins are disabled during margining. external resistor to ground. other by programming the PHMODE pin to different levels. multiple devices or frequency synchronization. light load features will accommodate battery operation. the Typical Performance Characteristics section.
Figure 18. External component selection is primarily requirements for a particular application. down ratio that can be achieved for a given input voltage. of its load current. For 5V input, all outputs can deliver 8A. Table 2. FB Resistor vs Various Output Voltages ceramic capacitors are included inside the module. used, then this 47μF capacitor is not needed. meet the output voltage ripple and transient requirements. Power Design Tool will be provided for stability analysis.
Table 3. Output Voltage Response Versus Component Matrix (Refer to Figure 18) 0A to 3A Load Step IN has very low input impedance.
the maximum peak current value in normal operation even though the voltage at the I TH pin indicates a lower value. The voltage at the ITH pin drops when the inductor’s average current is greater than the load requirement. As the I TH voltage drops below 0.2V, the BURST comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In Burst Mode operation, the internal circuitry is partially turned off, reducing the quiescent current to about 450μA for each output. The load current is now being supplied from the output capacitors. When the output voltage drops, causing I TH to rise above 0.25V, the internal sleep line goes low, and the L TM4616 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Each regulator can be confi gured for Burst Mode operation. Pulse-Skipping Mode Operation In applications where low output ripple and high effi ciency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the L TM4616 to skip cycles at low output loads, thus increasing effi ciency by reducing switching loss. Floating the MODE pin or tying it to V IN/2 enables pulse-skipping operation. This allows discontinuous conduction mode (DCM) operation down to near the limit defi ned by the chip’s minimum on-time (about 100ns). Below this output current level, the converter will begin to skip cycles in order to maintain output regulation. Increasing the output load current slightly, above the minimum required for discontinuous conduction mode, allows constant frequency PWM. Each regulator can be confi gured for Pulse-Skipping mode. Forced Continuous Operation In applications where fi xed frequency operation is more critical than low current effi ciency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE pin to GND. In this mode, inductor current is allowed to reverse during low output loads, the I TH voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continuous APPLICATIONS INFORMATION mode is disabled and inductor current is prevented from reversing until the L TM4616’s output voltage is in regulation. Each regulator can be confi gured for Forced Continuous mode. Multiphase Operation For output loads that demand more than 8A of current, two outputs in L TM4616 or even multiple L TM4616s can be cascaded to run out-of-phase to provide more output current without increasing input and output voltage ripple. The CLKIN pin allows the L TC4616 to synchronize to an external clock (between 0.75MHz and 2.25MHz) and the internal phase-locked loop allows the L TM4616 to lock onto CLKIN’s phase as well. The CLKOUT signal can be connected to the CLKIN pin of the following L TM4616 stage to line up both the frequency and the phase of the entire system. Tying the PHMODE pin to SV IN, SGND or SVIN/2 (fl oating) generates a phase difference (between CLKIN and CLKOUT) of 180°, 120° or 90° respectively, which corresponds to a 2-phase, 3-phase or 4-phase operation. A total of 12 phases can be cascaded to run simultaneously with respect to each other by programming the PHMODE pin of each L TM4616 to different levels. For a 6-phase example in Figure 2, the 2nd stage that is 120° out-of- phase from the 1st stage can generate a 240° (PHMODE = 0) CLKOUT signal for the 3rd stage, which then can generate a CLKOUT signal that’s 420°, or 60° (PHMODE = SV IN) for the 4th stage. With the 60° CLKIN input, the next two stages can shift 120° (PHMODE = 0) for each to generate a 300° signal for the 6th stage. Finally, the signal with a 60° phase shift on the 6th stage (PHMODE is fl oating) goes back to the 1st stage. Figure 3 shows the confi guration for 12-phase operation. A multiphase power supply signifi cantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used. The L TM4616 device is an inherently current mode con- trolled device, so parallel modules will have very good
Figure 2. 6-Phase Operation Figure 3. 12-Phase Operation
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output capacitor GND. See layout guideline in Figure 17. FB pins of the parallel module are tied together . reduction as a function of the number of interleaved phases. electromagnetic interference (EMI) is concerned. operating frequency (harmonics).
VTRACK is the track ramp applied to the slave’s track pin. Figure 5 will be equal to RFB for coincident tracking.
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Figure 4. Normalized Input RMS Ripple Current vs Duty Factor for One to Six Channels (Phases)
- Figure 6 shows the output voltage for coincident
Figure 5. Dual Outputs (3.3V and 1.5V) with T racking
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Figure 6. Output Voltage Coincident T racking will reach it fi nal value before the master output. TB = 22.1k. Solve for RTA to equal to 4.87k.
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- TIE TO VIN TO DISABLE TRACK WITH DEFAUL T 100μs SOFT START
- APPL Y A CONTROL RAMP WITH RSR AND CSR TIED TO V
- APPL Y AN EXTERNAL TRACKING RAMP DIRECTL Y
~100μs of internal soft-start during start-up. between the core and sub-power supplies. are disabled and PGOOD remains high.
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Figure 9. 5VIN to 3.3VOUT Figure 10. 5VIN to 1.2VOUT Figure 11. 5VIN to 3.3VOUT Figure 12. 5VIN to 1.2VOUT Figure 13. 3.3VIN to 1.2VOUT Figure 14. 3.3VIN to 2.5VOUT current or power while increasing ambient temperature. the power loss for the 5V to 1.2V at 10A output is ~3W. Table 5. At load currents on each channel from 3A to 8A resistance values in Tables 4 and 5 are closely accurate. resistance values for these lower currents is 15°C/W.
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0 LFM
200 LFM
400 LFM
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Table 4. 1.2V Output Table 5. 3.3V Output considerations are still necessary.
- Use large PCB copper areas for high current paths, including VIN1, VIN2, PGND1 and PGND2, V OUT1 and VOUT2. It helps to minimize the PCB conduction loss and thermal stress. Heatsink Manufacturer Wakefi eld Engineering Part No: L TN20069 Phone Number: 603-635-2800 AAVID Thermalloy Part No: 375424B000346 Phone Number: 603-224-9988 AMBIENT TEMPERATURE (°C) LOAD CURRENT (A) 120
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Figure 17. Recommended PCB Layout
- Place high frequency ceramic input and output capaci- tors next to the V IN, GND and V OUT pins to minimize high frequency noise.
- Place a dedicated power ground layer underneath the unit.
- To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
- Do not put vias directly on the pads, unless they are capped or plated over .
- Use a separated SGND ground copper area for com- ponents connected to signal pins. Connect the SGND to GND underneath the unit.
- For parallel modules, tie the I TH, FB and ITHM pins to- gether . Use an internal layer to closely connect these pins together . All of the I THM pins connect to the SGND of the master regulator , then the master SGND connects to GND. Figure 17 gives a good example of the recommended layout.
Figure 18. Typical 3.2V to 5VIN, to 1.8V, 1.5V Outputs
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5 PIN SC70 PACKAGE
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Figure 19. L TM4616 T wo Outputs Parallel, 1.5V at 16A Design Figure 20. L TM4616 Output Sequencing Application
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Figure 21. Four Phase in Parallel, 1.2V at 32A
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6 PIN SC70 PACKAGE
4616 F22
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION 144-Lead (15mm × 15mm × 2.82mm) (Reference L TC DWG # 05-08-1816 Rev A) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 144 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE SYMBOL aaa bbb eee TOLERANCE 0.10 0.10 0.05 2.72 – 2.92 DETAIL B DETAIL B SUBSTRATE MOLD CAP 0.27 – 0.37 2.45 – 2.55 bbb Z Z BSC PACKAGE TOP VIEW BSC PAD 1 CORNER X Y aaa Z aaa Z DETAIL A 13.97 BSC 1.27 BSC 13.97 BSC 0.12 – 0.28 PACKAGE BOTTOM VIEW3 PADS SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 LGA 144 0308 REV A L TMXXXXXX mModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” DIA 0.630 PAD 1 3x, C (0.22 x45°) DETAIL A 0.630 ±0.025 SQ. 143x S YXeee L K J H G F E D C B M A 1234567810 91112
Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2008 LT 1108 REV A • PRINTED IN USA PART NUMBER DESCRIPTION COMMENTS L TC2900 Quad Supply Monitor with Adjustable Reset Timer Monitors Four Supplies; Adjustable Reset Timer L TM4600 10A DC/DC μModule Basic 10A DC/DC μModule, LGA Package L TM4600HVMP Military Plastic 10A DC/DC μModule Guaranteed Operation from –55°C to 125°C Ambient, LGA Package L TM4601/ L TM4601A 12A DC/DC μModule with PLL, Output T racking/ Margining and Remote Sensing Synchronizable, PolyPhase Operation, L TM4601-1/L TM4601A-1 Version has no Remote Sensing, LGA Package L TM4602 6A DC/DC μModule Pin Compatible with the L TM4600, LGA Package L TM4603 6A DC/DC μModule with PLL and Outpupt T racking/ Margining and Remote Sensing Synchronizable, PolyPhase Operation, L TM4603-1 Version has no Remote Sensing, Pin Compatible with the L TM4601, LGA Package L TM4604A Low V IN 4A DC/DC μModule 2.375V ≤ VIN ≤ 5.5V, 0.8V ≤ VOUT ≤ 5V, 9mm × 15mm × 2.3mm LGA Package L TM4608A Low V IN 8A DC/DC μModule 2.7V ≤ VIN ≤ 5.5V; 0.6V ≤ VOUT ≤ 5V; 9mm × 15mm × 2.8mm LGA Package L TM8022/L TM8023 36VIN, 1A and 2A DC/DC μModule Pin Compatible; 4.5V ≤ VIN ≤ 36V; 9mm × 11.25mm × 2.8mm LGA Package PACKAGE DESCRIPTION Pin Assignment Table (Arranged by Pin Number) PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME A1 GND1 B1 GND1 C1 V IN1 D1 V IN1 E1 V IN1 F1 V IN1 A2 GND1 B2 GND1 C2 V IN1 D2 V IN1 E2 V IN1 F2 V IN1 A3 GND1 B3 GND1 C3 GND1 D3 GND1 E3 V IN1 F3 V IN1 A4 GND1 B4 GND1 C4 GND1 D4 GND1 E4 V IN1 F4 V IN1 A5 GND1 B5 GND1 C5 GND1 D5 GND1 E5 SV IN1 F5 SGND1 A6 BSEL1 B6 SW1 C6 GND1 D6 GND1 E6 PLLFL TR1 F6 RUN1 A7 CLKIN1 B7 GND1 C7 GND1 D7 GND1 E7 ITHM1 F7 CLKOUT1 A8 MODE1 B8 GND1 C8 GND1 D8 FB1 E8 TRACK1 F8 ITH1 A9 PHMODE1 B9 GND1 C9 GND1 D9 V OUT1 E9 V OUT1 F9 V OUT1 A10 MGN1 B10 GND1 C10 GND1 D10 V OUT1 E10 V OUT1 F10 V OUT1 A11 PGOOD1 B11 GND1 C11 GND1 D11 V OUT1 E11 V OUT1 F11 V OUT1 A12 GND1 B12 GND1 C12 GND1 D12 V OUT1 E12 V OUT1 F12 V OUT1 RELATED PARTS PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME G1 GND2 H1 GND2 J1 V IN2 K1 V IN2 L1 V IN2 M1 V IN2 G2 GND2 H2 GND2 J2 V IN2 K2 V IN2 L2 V IN2 M2 V IN2 G3 GND2 H3 GND2 J3 GND2 K3 GND2 L3 V IN2 M3 V IN2 G4 GND2 H4 GND2 J4 GND2 K4 GND2 L4 V IN2 M4 V IN2 G5 GND2 H5 GND2 J5 GND2 K5 GND2 L5 SV IN2 M5 SGND2 G6 BSEL2 H6 SW2 J6 GND2 K6 GND2 L6 PLLFL TR2 M6 RUN2 G7 CLKIN2 H7 GND2 J7 GND2 K7 GND2 L7 ITHM2 M7 CLKOUT2 G8 MODE2 H8 GND2 J8 GND2 K8 FB2 L8 TRACK2 M8 ITH2 G9 PHMODE2 H9 GND2 J9 GND2 K9 V OUT2 L9 V OUT2 M9 V OUT2 G10 MGN2 H10 GND2 J10 GND2 K10 V OUT2 L10 V OUT2 M10 V OUT2 G11 PGOOD2 H11 GND2 J11 GND2 K11 V OUT2 L11 V OUT2 M11 V OUT2 G12 GND2 H12 GND2 J12 GND2 K12 V OUT2 L12 V OUT2 M12 V OUT2