LTM4614

LTM4642 LINER | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 32

Technical content

For more information www.linear .com/L TM4642 Typical applicaTion

DescripTion

20VIN, Dual 4A or Single 8A DC/DC µModule Regulator The LT M®4642 is a complete dual 4A or single 8A step-down DC/DC μModule® (micromodule) regulator . Included in the package are the switching controller , power FETs, inductor , and all support components. Operating over input voltage ranges of 4.5V to 20V, (2.375V min with external CPWR bias), the LTM4642 supports two outputs with voltage ranges of 0.6V to 5.5V, set by a single external resistor . Its high efficiency design delivers 4A continuous current (5A peak) for each output. High switching frequency and a valley current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. The two outputs are interleaved with 180° phase to minimize the ripple noise and reduce the I/O capacitors. The power module is offered in a 9mm × 11.25mm × 4.92mm BGA package. The LTM4642 is RoHS compliant with Pb-free finish. Dual 4A 1V and 1.2V DC/DC µModule Regulator

FeaTures

applicaTions

n Small Form Factor Dual 4A Power Supply n Wide Input Voltage Range: 4.5V to 20V (2.375V Min with CPWR Bias) n Dual 180° Out-of-Phase Outputs with 4A DC n Dual Outputs with 0.6V to 5.5V Range n Output Voltage T racking n ±1.5% Maximum Total DC Output Voltage Error n Up to 95% Maximum Efficiency n Phase-Lockable Fixed Frequency 600kHz to 1.4MHz n Constant On-Time, Valley Current Mode Architecture n Selectable Burst Mode® Operation n Output Overvoltage and Overcurrent Protection n 9mm × 11.25mm × 4.92mm BGA Package n Telecom and Networking Equipment n Servers n FPGA Power Efficiency vs Load Current at 12V input L, L T , L TC, L TM, Linear Technology, the Linear logo, Burst Mode, µModule and L TpowerCAD are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 8163643. VIN1 VIN2 CPWR SGND PINS NOT USED: COMP1, COMP2, PHASEMD, CLKOUT , EXTVCC, SW1, SW2 GND L TM4642 4.7µF22µF 47µF 470pF VOUT1 470pF VOUT2 100µF 0.1µF VIN 4.75V TO 20V 2.2/uni03A9 DRVCC INTVCC RUN1 133k 10k 90.9k 61.9k 60.4k

4642 TA01a

VOUTS– VFB2 VFB1 VOUT2 1.2V AT 4A LOAD INTVCC 47µF 100µF0.1µF LOAD CURRENT (A) EFFICIENCY (%) 1 2 3 4

4642 TA01b

0.5 1.5 2.7 3.5 1.2V (650kHz) 1V (650kHz)

For more information www.linear .com/L TM4642 pin conFiguraTionabsoluTe MaxiMuM raTings INTVCC, DRVCC, PGOOD1,2, RUN1,2, EXTVCC, 3V to 2.7V MODE/PLLIN, FREQ, PHASMD, 3V to 5V Internal Operating Temperature Range (Note 2) C to 125°C 5°C C to 125°C (Note 1) A H G F E D C VOUT2 GND SW2 RUN2 PHASMD COMP2 CLKOUT RUN1 SW1 COMP1 FREQSGND VOUTS– VOUT1 MODE/PLLIN CPWR PGOOD2 TRACK/SS2 TRACK/SS1 GND GND GND GND GND VIN2 VFB2 VFB1 PGOOD1 DRVCC EXTVCC INTVCC VRNG1 VIN1 B 2 3 4 5 6 7 56-Lead (9mm × 11.25mm × 4.92mm) VOUTS1 TJMAX = 125°C, θJA = 15°C/W , θJP = 4°C/W θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS WEIGHT = 1.2635g SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN(DC) Input DC Voltage VIN ≤ 4.5V , Connect CPWR to a Bias > 4.5V l 2.375 20 V VOUT1,2(RANGE) Output Voltage Range VIN = 6V to 20V l 0.6 5.5 V VOUT1,2(DC) Output Voltage, Total Variation with Line and Load CIN = 10µF ×2, COUT = 47µF Ceramic, 100µF POSCAP , RSET = 40.2kΩ VIN = 12V , VOUT = 1.5V , IOUT = 4A l 1.4775 1.5 1.5225 V Input Specifications I INRUSH(VIN) Input Inrush Current at Start-Up I OUT = 0A, CIN = 10µF, COUT = 47µF Ceramic and 100µF POSCAP , VOUT = 1.5V VIN = 12V 0.25 A orDer inForMaTion elecTrical characTerisTics The l denotes the specifications which apply over the full internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application in Figure 27. Specified as each channel. (Note 3) PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE (SEE NOTE 2)DEVICE FINISH CODE LTM4642EY#PBF SAC305 (RoHS) LTM4642Y e1 BGA 3 –40°C to 125°C LTM4642IY#PBF SAC305 (RoHS) LTM4642Y e1 BGA 3 –40°C to 125°C LTM4642IY SnPb (63/37) LTM4642Y e0 BGA 3 –40°C to 125°C

• Consult Marketing for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Terminal Finish Part Marking: www.linear .com/leadfree
• Recommended LGA and BGA PCB Assembly and Manufacturing Procedures: www.linear .com/umodule/pcbassembly
• LGA and BGA Package and T ray Drawings: www.linear .com/packaging http://www.linear .com/product/LTM4642#orderinfo

For more information www.linear .com/L TM4642 elecTrical characTerisTics The l denotes the specifications which apply over the full internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application in Figure 27. Specified as each channel. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ICPWR CPWR Bias Current CPWR = 12V, MODE = Continuous 20 mA IQ(VIN) Input Supply Bias Current V IN = 12V , VOUT1 = 1.5V , Switching Continuous VIN = 12V , VOUT2 = 1.5V , Switching Continuous VIN = 20V , VOUT1 = 1.5V , Switching Continuous VIN = 20V , VOUT2 = 1.5V , Switching Continuous Shutdown, RUN = 0, VIN = 12V mA mA mA mA µA I Q(VIN) Input Supply Bias Current V IN = 12V , VOUT = 1.5V , IOUT = 4A VIN = 20V , VOUT = 1.5V , IOUT = 4A 0.6 0.356 A A DRV CC Internal VCC Voltage 6V < VIN < 20V, No Load 5 5.3 5.6 V IDRVCC(REG) DRVCC Load Regulation IDRVCC = 0 to 100mA –1.5 –3 % EXTVCC(HYS) EXTVCC Switchover Hysteresis 200 mV EXTVCC EXTVCC Switchover Voltage EXTV CC Ramping Positive 4.4 4.6 4.8 V Output Specifications IOUT1,2(DC) Output Continuous Current Range V IN = 12V , VOUT = 1.5V (Note 5) 0 4 A ΔVOUT1(LINE) VOUT(NOM) Line Regulation Accuracy V OUT = 1.5V , VIN from 4.5V to 20V, IOUT = 0A For Each Output l 0.1 0.2 % ΔVOUT2(LOAD) VOUT2(NOM) Load Regulation Accuracy For Each Output, V OUT = 1.5V , 0A to 4A (Note 5) VIN = 12V l ±0.3 ±0.5 VOUT1,2(AC) Output Ripple Voltage IOUT = 0A, COUT = 100µF X5R Ceramic VIN = 12V , VOUT = 1.5V VIN = 20V , VOUT = 1.5V mV mV f S Output Ripple Voltage Frequency I OUT = 2A, VIN = 12V, VOUT = 1.5V, FREQ = 49.9k to Ground 800 kHz ΔVOUT(START) Turn-On Overshoot COUT = 100µF and 47µF X5R Ceramic, VOUT = 1.5V , IOUT = 0A VIN = 12V VIN = 20V mV mV t START Turn-On Time COUT = 100µF X5R and 47µF Ceramic, VOUT = 1.5V , IOUT = 0A Resistive Load, TRACK/SS = 10nF VIN = 12V ms ΔV OUT(LS) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load COUT = 100µF and 47µF X5R Ceramic, VOUT = 1.5V , VIN = 12V mV t SETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load C OUT = 100µF and 47µF X5R Ceramic, VOUT = 1.5V , VIN = 12V µs I OUT(PK) Output Current Limit COUT = 100µF and 47µF X5R Ceramic, VIN = 6V , VOUT = 1.5V VIN = 20V , VOUT = 1.5V A A Control Section V OUTS1(REG) Regulated Differential Feedback VOUTS1-VOUTS– Sensed at Load Point with Resistive Divider l 0.592 0.6 0.608 V IVOUTS1 VOUTS1 Input Bias Current (Note 4) ±5 ±25 nA IVOUTS– VOUTS– Input Bias Current (Note 4) –25 –50 nA IVFB2 VFB2 Input Bias Current (Note 4) –5 ±50 nA VFB2 Voltage at VFB2 Pin IOUT = 0A, VOUT = 2.5V l 0.592 0.6 0.608 V

For more information www.linear .com/L TM4642 elecTrical characTerisTics The l denotes the specifications which apply over the full internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application in Figure 27. Specified as each channel. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ITRACK/SS1,2 Soft-Start Charge Current 0V < TRACK/SS1,2 < 0.6V 1.0 µA DFMAX Maximum Duty Factor In Dropout (Note 4) 97 % tON(MIN) Minimum On-Time (Note 4) 30 ns tOFF(MIN) Minimum Off-Time (Note 4) 90 ns fLOW Low Frequency RFREQ = 61.9k 600 650 700 kHz fNOM Nominal Frequency RFREQ = 49.9k 730 800 850 kHz fHIGH Highest Frequency RFREQ = 27.5k 1250 1400 1500 kHz RMODE/PLLIN MODE/PLLIN Input Resistance 600 kΩ VPLLIN(HIGH) MODE/PLLIN Clock In High 2 V VPLLIN(LOW) MODE/PLLIN Clock In Low 0.5 V VRUN1, 2 RUN Pin ON/OFF Threshold RUN Rising l 1.1 1.2 1.3 V VRUN1, 2(HYS) RUN1, 2, Threshold Hysteresis Delta RUN Rising to RUN Falling 200 mV IRUN1,2 RUN Pin Pull-Up Current When Off RUN1,2 at SGND 1.2 µA IRUN1,2(HYS) RUN1,2 Pull-Up Hysteresis I RUN1,2(HYST) = IRUN1,2(ON) – IRUN1,2(OFF) (Note 4) 5 µA RUN1,2 Res RUN1,2 Resistance to Ground 100 kΩ UVLO Undervoltage Lockout INTVCC Falling (Note 4) INTVCC Rising l l 3.3 3.7 4.2 4.5 V V RFB1, RFB2 Resistor Between VOUT and VFB Pins for Each Channel 60.1 60.4 60.7 kΩ VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V IPGOOD PGOOD Leakage Current V PGOOD = 5V ±2 µA ΔVPGOOD PGOOD Range VFB Ramping Negative VFB Ramping Positive –7.5 7.5 –10 Ch 2 Phase Channel 2 Phase (Relative to Channel 1) PHASMD = SGND PHASMD = Floating PHASMD = INT VCC 180 180 240 Deg Deg Deg CLKOUT Phase CLKOUT Phase (Relative to Channel 1) PHASMD = SGND PHASMD = Floating PHASMD = INT VCC 120 Deg Deg Deg Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4642E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the full –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4642I is guaranteed to meet specifications over the full internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: The two outputs are tested separately and the same testing condition is applied to each output. Note 4: 100% tested at wafer level only. Note 5: See Output Current Derating curves for different V IN, VOUT and TA. Note 6: Consult factory for operation down at 2.375V to 2.5V input. Operating frequency nominal will be reduced.

For more information www.linear .com/L TM4642 Typical perForMance characTerisTics 3.3VIN to 1.5VOUT T ransient Response 5VIN to 1.5VOUT T ransient Response 3.3VIN to 1VOUT T ransient Response Efficiency vs Load Current at 3.3VIN, CCM Mode, External 5V Bias 5VIN to 1VOUT T ransient Response Efficiency vs Load Current at IN, CCM Mode 12VIN to 1VOUT T ransient Response Efficiency vs Load Current at 12V IN, CCM Mode Efficiency vs Load Current at 20V IN, CCM Mode (Refer to Figures 19 and 20) TA = 25°C, unless otherwise noted. LOAD CURRENT (A) EFFICIENCY (%)

4642 G01

1 2 30.5 1.5 2.5 3.5 100 3.3V TO 2.5V (600kHz) 3.3V TO 1.8V (600kHz) 3.3V TO 1.5V (600kHz) 3.3V TO 1.2V (600kHz) 3.3V TO 1V (600kHz) LOAD CURRENT (A) EFFICIENCY (%)80

4642 G02

1 2 30.5 1.5 2.5 3.5 100 5V TO 3.3V (800kHz) 5V TO 2.5V (800kHz) 5V TO 1.8V (750kHz) 5V TO 1.5V (650kHz) 5V TO 1.2V (650kHz) 5V TO 1V (650kHz) LOAD CURRENT (A) EFFICIENCY (%)80 1 2 30.5 1.5 2.5 3.5 100 12V TO 5V (1.2MHz) 12V TO 3.3V (1MHz) 12V TO 2.5V (1MHz) 12V TO 1.8V (800kHz) 12V TO 1.5V (800kHz) 12V TO 1.2V (650kHz) 12V TO 1V (650kHz) LOAD CURRENT (A) EFFICIENCY (%)

4642 G04

1 2 30.5 1.5 2.5 3.5 100 20V TO 1.8V (800kHz) 20V TO 1.5V (800kHz) 20V TO 1.2V (650kHz) 20V TO 1V (650kHz) 20V TO 5V (1.2MHz) 20V TO 3.3V (1MHz) 20V TO 2.5V (1MHz) COUT = 100µF 15m/uni03A9 ESR POSCAP, 47µF CERAMIC C FF = 470pF fSW = 600kHz

4642 G05

ISTEP = 2A/µs 2A/DIV 20µs/DIV IN OUT COUT = 100µF 15m/uni03A9 ESR POSCAP, 47µF CERAMIC C FF = 470pF fSW = 650kHz

4642 G06

ISTEP = 2A/µs 2A/DIV 1VOUT 20mV/DIV 20µs/DIV IN OUT COUT = 100µF 15m/uni03A9 ESR POSCAP, 47µF CERAMIC C FF = 470pF fSW = 650kHz

4642 G07

ISTEP = 2A/µs 2A/DIV 1VOUT 20mV/DIV 20µs/DIV IN OUT COUT = 120µF 22m/uni03A9 ESR OSCON SVP, 47µF CERAMIC C FF = 470pF fSW = 600kHz

4642 G08

ISTEP = 2A/µs 2A/DIV 1.5VOUT 50mV/DIV 20µs/DIV IN OUT COUT = 120µF 22m/uni03A9 ESR OSCON SVP, 47µF CERAMIC C FF = 470pF fSW = 650kHz

4642 G09

ISTEP = 2A/µs 2A/DIV 1.5VOUT 50mV/DIV 20µs/DIV IN OUT

For more information www.linear .com/L TM4642 Typical perForMance characTerisTics 12VIN to 2.5VOUT T ransient Response 5VIN to 3.3VOUT T ransient Response 12VIN to 3.3VOUT T ransient Response 6VIN to 5VOUT T ransient Response 12VIN to 5VOUT T ransient Response Clock Synchronization 12VIN to 1.5VOUT T ransient Response 3.3VIN to 2.5VOUT T ransient Response 5VIN to 2.5VOUT T ransient Response COUT = 120µF 22m/uni03A9 ESR OSCON SVP, 47µF CERAMIC CFF = 470pF fSW = 800kHz

4642 G10

ISTEP = 2A/µs 2A/DIV 1.5VOUT 50mV/DIV 20µs/DIV IN OUT COUT = 47µF CERAMIC CFF = 68pF fSW = 600kHz

4642 G11

ISTEP = 2A/µs 2A/DIV 2.5VOUT 100mV/DIV 20µs/DIV IN OUT COUT = 47µF CERAMIC CFF = 68pF fSW = 800kHz

4642 G12

ISTEP = 2A/µs 2A/DIV 2.5VOUT 100mV/DIV 20µs/DIV IN OUT COUT = 47µF CERAMIC CFF = 68pF fSW = 1MHz

4642 G13

ISTEP = 2A/µs 2A/DIV 2.5VOUT 100mV/DIV 20µs/DIV IN OUT COUT = 47µF CERAMIC CFF = 68pF fSW = 800kHz

4642 G14

ISTEP = 2A/µs 2A/DIV 3.3VOUT 100mV/DIV 20µs/DIV IN OUT

4642 G15

ISTEP = 2A/µs 2A/DIV COUT = 47µF CERAMIC CFF = 68pF fSW = 1MHz 3.3VOUT 100mV/DIV 20µs/DIV IN OUT INPUT CAPACITOR 680µF 10V, LOW IMPEDANCE INPUT CAN USE MUCH LESS C OUT = 47µF CERAMIC CFF = 68pF fSW = 600kHz

4642 G16

ISTEP = 2A/µs 2A/DIV 5VOUT 100mV/DIV 20µs/DIV IN OUT COUT = 47µF CERAMIC CFF = 68pF fSW = 1.2MHz

4642 G17

ISTEP = 2A/µs 2A/DIV 5VOUT 100mV/DIV 20µs/DIV IN OUT

4642 G18

1µs/DIV (Refer to Figures 19 and 20) TA = 25°C, unless otherwise noted.

For more information www.linear .com/L TM4642 Typical perForMance characTerisTics Load Regulation and Current Limit (No Airflow) Output Ripple, 10mV Typical Shorted Output Start-Up, 20V to 1.5V at 4A 12V TO 1.5V AT 4A COUT = 100µF CERAMIC, 47µF CERAMIC fSW = 800kHz

4642 G19

1.5VOUT 10mV/DIV 2µs/DIV VIN = 20V VOUT = 1.5V

4642 G20

0.5V/DIV ISHORT 10A/DIV 50µs/DIV COUT = 100µF CERAMIC, 47µF CERAMIC CSS = 0.1µF

4642 G21

LOAD CURRENT (A) VOUT (V) 0.6 1.2

4642 G22

1.8 0.3 0.9 1.5 4.5VIN 12VIN 20VIN VOUT = 1.5V fSW = 1MHz MODE = CCM (Refer to Figures 19 and 20) TA = 25°C, unless otherwise noted.

For more information www.linear .com/L TM4642 pin FuncTions GND (A4-A7, C2, D1, D5, E1, E5, E7, F7, H4-H7): Power ground pins for both input and output returns. PHASMD (B4): Phase Mode Selection Pin for Program - ming Clock Out Phase. See Electrical Characteristics and Applications Information sections. MODE/PLLIN (C3 ): Mode Selection or External Synchroni- zation Pin. Tying this pin to SGND enables discontinuous mode. Tying this pin to INT VCC enables forced continuous operation. A clock on the pin will force the controller into the continuous mode of operation and synchronize the internal oscillator . The suitable synchronizable frequency range is 600kHz to 1400kHz subject to inductor ripple current limits described in the FREQ/PLLFL TR pin section. The external clock input high threshold is 2V, while the input low threshold is 0.5V. CPWR (C7): This pin is the main input power to the control IC. This pin normally connects to the input source directly. This pin can be biased at a voltage greater than 4.5V to allow the V IN1 and VIN2 to operate down to 2.375V input for applications that operate at 2.5V or 3.3V input. If the bias is less than or equal to 5.3V, connect DRV CC to this pin. SGND (D2, E2): Signal Ground Pins. Return ground path for all analog and low power circuitry. Tie a single connec- tion to PGND in the application. See the Recommended Layout section. CLKOUT (D4): Clock Out for Synchronizing Other Regula- tors to the Common Clock. Used for multiphase applica- tions. See Applications Information section. EXTVCC (D6): External Power Input to Controller . When EXTVCC is higher than 4.7V, the internal 5.3V regulator is disabled and the external source supplies current to reduce the power dissipation in the module. This will improve the efficiency more at high input voltages. INTV CC (D7): This pin powers the internal control circuits. Tie this pin to DRVCC with a 2.2Ω resistor . This pin requires a few milliamps. PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y . COMP1, COMP2 (E3, D3): Current Control Threshold and Error Amplifier Compensation Point. The module has been internally compensated for all I/O ranges. FREQ (E4): Frequency Selection Pin. Tie a resistor from this pin to SGND to set the frequency of operation between 600kHz to 1.4MHz for the specific output voltages. For 3.3V input applications, 650kHz is an optimized frequency. For 5V to 20V input applications, the optimized operating frequency for the output voltage is as follows: 0.8V to 1.2V (650kHz), 1.5V to 1.8V (800kHz), 2.0V to 5V (1.2MHz), 5V from 20V input (1.4MHz). The resistor equation: RFREQ kΩ( ) = 41550 FREQ kHz( ) – 2.2 DRVCC (E6): This pin is the LDO 5.3V regulator output used to power the internal control circuits and MOSFET drivers. This pin needs a 4.7µF ceramic decoupling capaci- tor to GND. For input voltages less than or equal to 5.3V, connect this pin directly to the input voltage. V OUTS1 (F2): Output Voltage Sense Point for Channel 1 Remote Sensing. This pin has a 49.9Ω resistor connected to VOUT1. This pin can be connected at the load point for accurate remote sensing. VOUTS– (F3): Remote Ground Sense Pin. Connect at remote ground point. V FB1, V FB2 (F4, C4): The negative input of the error amplifier . Internally, this pin is connected to V OUT with a 60.4k precision resistor . Different output voltages can be programmed with an additional resistor between V FB and SGND pins. See the Applications Information section for details. TRACK/SS1, TRACK/SS2 (F5, C5): Output Voltage T racking and Soft-Start Pins. Internal soft-start currents of 1.0µA charge the soft-start capacitors. See the Applications Information section to use the tracking function. PGOOD1, PGOOD2 (F6, C6): Output Voltage Power Good Indicator . Open-drain logic output that is pulled to ground when the output voltage is not within ±7.5% of the regula- tion point. In single output parallel operation when V FB2 is tied to INTVCC, the PGOOD2 pin is not to be used.

For more information www.linear .com/L TM4642 pin FuncTions RUN1, RUN2 (G3, B3): Run Control Pins. A source can be used to enable the RUN pins with an external pull-up resistor . Forcing either of these pins below 1.2V will shut down the corresponding outputs. An additional 5µA pull- up current is added to this pin, once the RUN pin rises above 1.2V. Also, active control or pull-up resistors can be used to enable the RUN pin. The maximum voltage is 6V on these pins. There are 100k resistors on RUN1,2 to ground. It is recommended to use an external pull-up resistor to V IN to enable the RUN pin. See the Applications Information section. VRNG1 (G4): Used at Final Test. Tie to INTV CC in normal operation. This pin can also be used to adjust the current limit of channel 1. An external resistive divider from INTVCC can be used to set the voltage on the V RNG pin between 0.6V to 1V, resulting in a maximum sense voltage between 30mV and 50mV. For applications that require less than 7A of the default peak current limit, the V RNG pin voltage can be scaled down to obtain a desired current limit level. VIN1 (G5, G6, 67), VIN2 (B5, B6, B7): Power Input Pins. Apply input voltage between these pins and GND pins. Recommend placing input decoupling capacitance directly between V IN pins and GND pins. VOUT1 (F1, G1, G2, H1, H2), VOUT2 (A1, A2, B1, B2, C1): Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and PGND pins. SW1, SW2 (H3, A3): Switching Test Pins. These pins are provided externally to check the operation frequency.

TA = 25°C. Use Figure 1 configuration. Figure 1. Simplified LTM4642 Block Diagram

4642 F01

For more information www.linear .com/L TM4642 operaTion The LTM4642 is a dual independent input 4A nonisolated switching mode DC/DC power supply. It can deliver up to 4A (DC current) for each output with few external input and output capacitors. This module provides precisely regulated output voltages programmable via external resistors from 0.6V to 5.5V over a 4.5V to 20V input voltage range. The Typical Application schematic is shown in Figure 27. The input voltage source can operate down to 2.375V with an external bias applied to the CPWR pin. The external bias needs to be 5V or higher . See the Typical Applications schematics for examples. The LTM4642 has integrated constant on-time valley cur- rent mode regulators and built-in power MOSFET devices with fast switching speed. To reduce switching noise, the two outputs are interleaved with 180° phase internally and can be synchronized externally using the MODE/PLLIN pin. With current mode control and internal feedback loop compensation, the LTM4642 module has sufficient stabil- ity margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit and current foldback in a short-circuit condition. In- ternal overvoltage and undervoltage comparators pull the open-drain PGOOD pins output low if the output feedback voltage exits a ± 7.5% window around the regulation point. The power good pin is disabled during start-up. Pulling the RUN pins below 1.2V forces the controller into its shutdown state, by turning off both MOSFETs. The TRACK/SS pins are used for programming the output voltage ramp and voltage tracking during start-up. See the Applications Information section. The LTM4642 is internally compensated to be stable over all operating conditions. L TpowerCAD ® is available for transient and stability analysis. The VFB pins are used to program the output voltage with a single external resistor to ground. Multiphase operation can be easily employed with clock synchronization. High efficiency at light loads can be accomplished with selectable discontinuous mode using the MODE/PLLIN pin. Efficiency graphs are provided for light load operations in the Typical Performance Characteristics section.

Figure 27. External component selection is primarily deter- mined by the maximum load current and output voltage. WM controller has an internal 0.6V reference voltage. Table 1. RSET Resistor Table vs Various Output Voltages Applications at the end of the data sheet. leads, traces or not enough source capacitance. case for each output at 4A maximum current is about 2A. at 4A load and no external input bulk capacitor is required. for output capacitor suggestions.

For more information www.linear .com/L TM4642 Mode Selections and Phase-Locked Loop The LTM4642 can be enabled to operate in discontinuous or forced continuous mode. To select the forced continuous operation, tie the MODE/PLLIN pin to INTV CC. To select discontinuous operation, or tie the MODE/PLLIN pin to ground. This will improve the light load efficiency. Frequency Selection and External Clock Synchronization An internal oscillator (clock generator) provides phase interleaved internal clock signals for individual channels to lock on to. The switching frequency and phase of each switching channel is independently controlled by adjust- ing the top MOSFET turn-on time (on-time) through the one-shot timer . This is achieved by sensing the phase relationship between a top MOSFET turn-on signal and its internal reference clock through a phase detector , and the time interval of the one-shot timer is adjusted on a cycle-by-cycle basis, so that the rising edge of the top MOSFET turn-on is always trying to synchronize to the internal reference clock signal for the respective channel. The frequency of the internal oscillator can be programmed from 600kHz to 1.4MHz by connecting a resistor , R FREQ, from the FREQ pin to signal ground (SGND). The equation: RFREQ kΩ( ) = 41550 FREQ kHz( ) – 2.2 For applications with stringent frequency or interference requirements, an external clock source connected to the MODE/PLLIN pin can be used to synchronize the internal clock signals through a clock phase-locked loop (Clock PLL). The LTM4642 operates in forced continuous mode of operation when it is synchronized to the external clock. The external clock frequency has to be within ±30% of the internal oscillator frequency for successful synchroniza- tion. The clock input levels should be no less than 2V for “high” and no greater than 0.5V for “low”. The MODE/ PLLIN pin has an internal 600k pull-down resistor . PHASMD Pin Programming The PHASMD pin determines the relative phases between the internal reference clock signals for the two channels applicaTions inForMaTion as well as the CLKOUT signal, as shown in Table 2. The phases tabulated are relative to zero degree (0°) being defined as the rising edge of the internal reference clock signal of channel 1. The CLKOUT signal can be used to synchronize additional power regulator modules. The system can be configured for up to 12-phase operation with a multichannel solution. Typical configurations are shown in Table 3 to interleave the phases of the channels. The applications will validate a 6 phase multiple regulator solution with multiple outputs. Each of the LTM4642 channels can be paralleled up to 8A of output, but cannot be paralleled from one module to the other modules. T welve phases can be paralleled with no more than two phases per module. Table 2 PHASMD SGND FLOAT INTVCC Channel 1 0° 0° 0° Channel 2 180° 180° 240° CLKOUT 60° 90° 120° Table 3 NUMBER OF PHASES NUMBER OF LTM4642* PIN CONNECTIONS [PIN NAME (CHIP NUMBER)] 2 1 PHASMD(1) = FLOA T or SGND 3 2 or 1 + ½(LTM4642) PHASMD(1) = INT VCC MODE/PLLIN(2) = CLKOUT(1) 4 2 PHASMD(1) = FLOA T PHASEMD(2) = FLOAT or SGND MODE/PLLIN(2) = CLKOUT(1) 6 3 PHASMD(1) = SGND PHASMD(2) = SGND MODE/PLLIN(2) = CLKOUT(1) PHASMD(3) = FLOA T or SGND MODE/PLLIN(3) = CLKOUT(2) *No more than two channels of any one module may be paralleled. Soft-Start and T racking The LTM4642 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. When one particular channel is configured to soft-start by itself, a capacitor should be connected to its TRACK/SS pin. This channel is in the shutdown state if its RUN pin voltage is below 1.2V. Its TRACK/SS pin is actively pulled to ground in this shutdown state.

Figure 2. Example of Coincident T racking the output voltages with coincident tracking.

4642 F02

4642 F03

For more information www.linear .com/L TM4642 slave output for the tracking to work. Master and slave data inputs can be used to implement the correct resistors values for coincident or ratiometric tracking. Multiphase Operation Multiphase operation with the LTM4642 two regulator channels in parallel will lower the effective input RMS ripple current as well as the output ripple current due to the interleaving operation of the regulators. Figure 4 provides a ratio of input RMS ripple current to DC load current as a function of duty cycle and the number of paralleled phases. Choose the corresponding duty cycle and the number of phases to get the correct ripple current value. For example, the 2-phase parallel for one LTM4642 design provides 8A at 2.5V output from a 12V input. The duty cycle is DC = 2.5V/12V = 0.21. The 2-phase curve has a ratio of ~0.25 for a duty cycle of 0.21. This 0.25 ratio of RMS ripple current to a DC load current of 8A equals ~2A of input RMS ripple current for the external input capacitors. No more than two phases of a module may be paralleled. The effective output ripple current is lowered with multiphase operations as well. Figure 5 provides a ratio of peak-to-peak output ripple current to the normalized output ripple current as a function of duty cycle and the number of paralleled phases. Choose the corresponding duty cycle and the number of phases to get the correct output ripple current ratio value. If a 2-phase operation is chosen at 12V IN to 2.5VOUT with a duty cycle of 21%, then 0.6 is the ratio of the normalized output ripple current to inductor ripple DIr at the corresponding duty cycle. This leads to ~1.3A of the effective output ripple current ΔI L if the DIr is at 2.2A. Refer to Application Note 77 for a detailed explanation of the output ripple current reduction as a function of paralleled phases. The output ripple voltage has two components that are related to the amount of bulk capacitance and effective series resistance (ESR) of the output bulk capacitance. Therefore, the output ripple voltage can be calculated with the known effective output ripple current. The equation: ΔVOUT(P-P) ≈ ΔIL/(8 • f • N • COUT) + ESR • ΔIL where f is frequency and N is the number of parallel phases. applicaTions inForMaTion RUN Pin The RUN pins can be used to enable or sequence the particular regulator channel. The RUN pins have their own internal 1.2µA current source to pull up the RUN pins to 1.2V, and the current will increase to 5µA above 1.2V. Board contamination or residue can load down these small pull-up currents, so a 100k resistor is placed from the RUN pins to ground. This 100k resistor can be used with a resistor to V IN to set the turn-on threshold for the RUN pins The resistor divider needs to be low enough resistance to swamp out the pull-up current sources to prevent unintended activation of the device. The RUN pin has a maximum rated voltage of 6V. See Figure 1 Block Diagram for set turn on equation. Power Good The PGOOD pin is connected to the open drain of an internal N-channel MOSFET . The MOSFET turns on and pulls the PGOOD pin low when either V FB pin voltage is not within ±7.5% of the 0.6V reference voltage. The PGOOD pin is also pulled low when either RUN pin is below 1.2V or when the LTM4642 is in the soft-start or tracking phase. When the V FB pin voltage is within the ±7.5% requirement, the MOSFET is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6V. The PGOOD pin will flag power good immediately when both V FB pins are within the ±7.5% window. However , there is an internal 17µs power bad mask when either VFB goes out of the ±7.5% window. In parallel single output operation, only use PGOOD1. CPWR, DRV CC, INTVCC and EXTVCC The CPWR is the main power input to the internal control IC. This pin is normally connected to the input voltage source. This pin can be biased with a 5V supply when operating at input voltages below 4.5V. When 4.5V < V IN < 5.3V, Then tie CPWR to DRVCC. See the Typical Applications. The DRVCC is the internal 5.3V regulator that powers the LTM4642 internal MOSFET drivers for the internal power MOSFETs. The DRV CC requires a 4.7µF ceramic capacitor to ground. INTVCC powers the internal controller circuits and is connected to DRVCC through a 2.2Ω resistor . This INTVCC bias is ≤ 20mA.

4642 F04

4642 F05

Figure 4. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six Phases* Figure 5. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOUT T/L

For more information www.linear .com/L TM4642 applicaTions inForMaTion A 5V output on channel 1 or 2 can be used to power the EXTVCC pin when the input voltage is at the high end of the supply range to reduce power dissipation in the module. For example, the dropout voltage for 20V input would be 20V – 5V = 15V. This 15V headroom then multiplied by the power MOSFET drive current of ~30mA would equal ~0.45W additional power dissipation. So utilizing a 5V output on the EXTV CC would improve design efficiency and reduce device temperature rise. Otherwise try to operate CWPR off of a 5V bias when operating at higher supply voltages. See the Typical Applications section. Fault Conditions: Current Limit and Overcurrent Foldback The LTM4642 has a current mode controller , which inher- ently limits the cycle-by-cycle inductor current not only in steady-state operation, but also in transient. To further limit current in the event of an overload condi- tion, the LTM4642 provides foldback current limiting. If the output voltage falls by more than 50%, then the maximum output current is progressively lowered to one-fourth of its full current limit value. Foldback current limiting is disabled during soft-start and tracking up. SW Pins The SW pins are generally for testing purposes by moni- toring these pins. These pins can also be used to dampen out switch node ringing caused by LC parasitic in the switched current paths. Usually a series R-C combina - tion is used called a snubber circuit. The resistor will dampen the resonance and the capacitor is chosen to only affect the high frequency ringing across the resistor. If the stray inductance or capacitance can be measured or approximated then a somewhat analytical technique can be used to select the snubber values. The inductance is usually easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond wire inductance. First the SW pin can be monitored with a wide bandwidth scope with a high frequency scope probe. The ring fre - quency can be measured for its value. The impedance Z can be calculated: Z(L) = 2πfL, where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to Z, then the ringing should be dampened. The snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. Calculated by: Z (C) = 1/(2πfC). These values are a good place to start with. Modification to these components should be made to attenuate the ringing with the least amount of power loss. Thermal Considerations and Output Current Derating In different applications, the LTM4642 operates in a variety of thermal environments. The maximum output current is limited by the environmental thermal condition. Sufficient cooling should be provided to ensure reliable operation. When the cooling is limited, proper output current derat- ing is necessary, considering the ambient temperature, ai rflow, input/output conditions, and the need for increased reliability. The two outputs of the LTM4642 are paralleled to charac- terize the output current derating curves. The power loss curves in Figure 8 to Figure 10 can be used in coordination with load current derating curves in Figure 11 to Figure 24 for calculating an approximate θ JA for the module with various cooling methods. Application Note 103 provides detailed explanation of the analysis for the thermal models and the derating curves. Tables 4 and 5 provide a sum - mary of the equivalent θ JA parameters are correlated to the measured values, and are improved with airflow. The power loss curves are taken at room temperature, and are increased with multiplicative factors according to the ambient temperature. The approximate factors are: 1.35 for 115°C and 1.4 for 120°C. The derating curves are plotted with CH1 and CH2 paralleled output current starting at 8A and the ambient temperature starting at 50°C. The derated and 5 specify the approximate θ JA with airflow conditions for 1V and 5V outputs. These two conditions are chosen to include the lower and higher output voltage ranges for cor- relating the thermal resistance, but any derating curve point along with power loss curve can be used to calculate the θJA. Thermal models are derived from several temperature measurements in a controlled temperature chamber along

Table 4. 1V Output Table 5. 5V Output Table 6. Output Voltage Response vs Component Matrix (Refer to Figure 27) 0A to 2A Load Step Typical Measured Values ** Bulk capacitance is optional if VIN has very low input impedance.

For more information www.linear .com/L TM4642 applicaTions inForMaTion with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 120°C maximum while lowering output current or power with increasing ambient temperature. The decreased output current will decrease the internal module loss as ambient temperature is increased. The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example in Figure 14 the load current is derated to ~7A at ~100°C with no air or heat sink and the power loss for the 12V to 1.0V at 7A output is about 1.2W (power loss at 3.5A load multiplied by 2). The 1.2W loss is multiplied by the 1.4 multiplying factor at 120°C junction to get 1.68W. If the 100°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 20°C divided by 1.68W equals a 12°C/W thermal resistance. Table 4 specifies a 13°C/W value which is very close. Table 4 and Table 5 provide equivalent thermal resistances for 1.0V and 5V outputs with and without airflow and heat sinking. The derived thermal resistances in Tables 4 and 5 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. The printed circuit board is a 1.6mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. The PCB dimensions are 95mm × 76mm. The BGA heat sinks are listed below Table 5. The thermal resistances reported in the Pin Configura - tion section of the data sheet are consistent with those parameters defined by JE SD51 -12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation per - formed on a µModule package mounted to a hardware test board defined by JE SD51 -9 (“Test Boards for Area Array Surface Mount Package Thermal Measurements”). The motivation for providing these thermal coefficients is found in JESD51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to anticipate the µModule regulator’s thermal performance in their ap- plication at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Con- figuration section are in-and-of themselves not relevant to providing guidance of thermal performance ; instead, the derating curves provided in the data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section gives four thermal coeffi - cients explicitly defined in JESD51-12; these coefficients are quoted or paraphrased below: θJA, the thermal resistance from junction to ambi - ent, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a JESD51-9 defined test board, which does not reflect an actual application or viable operating condition. θJCbottom, the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical µModule, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environ- ment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 3. θJCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application.

1. θJB, the thermal resistance from junction to the

board is described in JESD51-9. resistances are external to the µModule package. airflow, a majority of the heat flow is into the board.

4642 F06

Figure 6. Graphical Representation of JESD51-12 Thermal Coefficients

be performed by the user in a particular system. low thermal resistance paths to remove heat. Figure 7. Thermal Plot for the Specified Operation. The Temperature Rise About 25°C Ambient Is About 30°C Rise

Figure 8. 5V Input Power Loss Figure 9. 12V Input Power Loss Figure 10. 20V Input Power Loss

4642 F08

4642 F09

4642 F10

Figure 11. 5VIN, 1VOUT 650kHz, Figure 12. 5VIN, 1VOUT 650kHz, Figure 13. 12VIN, 1VOUT 650kHz,

4642 F11

0 LFM

200 LFM

400 LFM

4642 F12

4642 F13

Figure 14. 12VIN, 1VOUT 650kHz, Figure 15. 5VIN, 3.3VOUT 650kHz, Figure 16. 5VIN, 3.3VOUT 650kHz,

4642 F14

4642 F15

4642 F16

Figure 17. 12VIN, 2.5VOUT 1MHz, Figure 18. 12VIN, 2.5VOUT 1MHz, Figure 19. 20VIN, 2.5VOUT 1MHz, Figure 20. 20VIN, 2.5VOUT 1MHz, Figure 21. 12VIN, 5VOUT 1.2MHz, Figure 22. 12VIN, 5VOUT 1.2MHz, Figure 23. 20VIN, 5VOUT 1.2MHz, Figure 24. 20VIN, 5VOUT 1.2MHz,

4642 F17

4642 F18

4642 F19

4642 F20

4642 F21

4642 F22

4642 F23

4642 F24

Figure 25. Recommended PCB Layout

• Use large PCB copper areas for high current path, in - cluding VIN1, VIN2, PGND, VOUT1 and VOUT2. It helps to minimize the PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capaci- tors next to the VIN, PGND and VOUT pins to minimize high frequency noise.
• Place a dedicated power ground layer underneath the unit. To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnections between top layer and other power layers.
• Do not put vias directly on the pads.
• Use a separated SGND ground copper area for com - ponents connected to signal pins. Connect the SGND to PGND underneath the unit. Decouple the input and output grounds to lower the output ripple noise. Figure 25 gives a good example of the recommended layout. CIN3 CIN4 CIN1 VIN1 VIN2 RFB2RFREQRFB1 CTK/SS1 CTK/SS2 GND GND

4642 F25

Figure 26. 4.5V to 20V Input, 650kHz, 0.9V and 1.2V Outputs at 4A Each Figure 27. 5V Input, 800kHz, 2.5V and 1.8V Outputs at 4A Each

4642 F26

4642 F27

4642 F28

Figure 29. Output Paralleled LTM4642 Module for 3.3V at 8A Each

4642 F29

Figure 30. 3.3V Input to 1V and 1.8V at 4A Each, 1V Sequencing 1.8V Using PGOOD1 to Enable RUN2

4642 F30

Table 5. Pin Assignment

For more information www.linear .com/L TM4642 package DescripTion PACKAGE TOP VIEW PIN “A1” CORNER Y X aaa Z aaa Z DETAIL A PACKAGE BOTTOM VIEW SEE NOTES H G F E D C B A 1 2 3 4 5 6 7 PIN 1 BGA 56 1113 REV Ø TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE DETAIL A Øb (56 PLACES) DETAIL B SUBSTRATE 0.27 – 0.37 3.95 – 4.05 // bbb Z A ccc Z DETAIL B PACKAGE SIDE VIEW MOLD CAP Z M X Y Z ddd M Z eee SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 4.72 0.50 4.22 0.60 0.60 NOM 4.92 0.60 4.32 0.75 0.63 11.25 9.0 1.27 8.89 7.62 MAX 5.12 0.70 4.42 0.90 0.66 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 56 D E e b F G SUGGESTED PCB LAYOUT TOP VIEW 0.000 0.635 1.905 0.635 3.175 1.905 4.445 3.175 4.445 3.810 2.540 1.270 3.810 2.540 1.270 0.3175 0.3175 0.000 4.1275 4.7625 L TMXXXXXX µModule 56-Lead (11.25mm × 9.00mm × 4.92mm) (Reference L TC DWG# 05-08-1961 Rev Ø)

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES Please refer to http://www.linear .com/product/LTM4642#packaging for the most recent package drawings.

For more information www.linear .com/L TM4642 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER A 12/16 Absolute Maximum Rating VFB1, V FB2 changed to INTVCC to 0.3V 2 B 6/17 T welve phases can be paralleled with no more than two phases per regulator output 13

For more information www.linear .com/L TM4642  LINEAR TECHNOLOGY CORPORATION 2016 LT 0617 Rev B • PRINTED IN USA www.linear .com/L TM4642 package phoTograph relaTeD parTs PART NUMBER DESCRIPTION COMMENTS LTM4614 Dual, 4A, Low VIN, DC/DC µModule Regulator 2.375V ≤ V IN ≤ 5.5V, 0.8V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.82mm LGA LTM4615 T riple, Low VIN, DC/DC µModule Regulator T wo 4A Outputs and One 1.5A, 15mm × 15mm × 2.82mm LGA, 2.375V ≤ V IN ≤ 5.5V LTM4616 Dual, 8A, Low VIN, DC/DC µModule Regulator 2.7V ≤ V IN ≤ 5.5V, 0.6V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.82mm LGA LTM4628 Dual, 8A, 26V, DC/DC µModule Regulator 4.5V ≤ V IN ≤ 28.5V, 0.6V ≤ VOUT ≤ 5.5V, Remote Sense Amplifier , Internal Temperature Sensing Diode Output, 15mm × 15mm × 4.32mm LGA LTM4620A Dual, 16V, 13A, 26A, Step-Down µModule Regulator 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 5.3V, 15mm × 15mm × 4.41mm LGA Design resources SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:

• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Sear ch parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging.