LTM4612 LINER | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 24
Technical content
V OUT VFB VIN 0.01μF 10μF 100pF COUT VOUT 12V CIN VIN 22V TO 36V PLLIN CLOCK SYNC L TM4612 SGND VD PGND MARGIN CONTROL 100k2M 5.23k 392k 5% MARGIN
4612 TA01
FEATURES
APPLICATIONS
DESCRIPTION
36VIN, 15VOUT, 5A, DC/DC µModule The L TM®4612 is a complete, ultralow noise, high voltage input and output, 5A switching mode DC/DC power supply. Included in the package are the switching controller , power FETs, inductor and all support components. Operating over an input voltage range of 5V to 36V , the L TM4612 supports an output voltage range of 3.3V to 15V , set by a single resistor . Only bulk input and output capacitors are needed to fi nish the design. High switching frequency and an adaptive on-time current mode architecture enables a very fast transient response to line and load changes without sacrifi cing stability. The onboard input fi lter and noise cancellation circuits achieve low noise coupling, thus effectively reducing the electromagnetic interference (EMI)—see Figures 4 and 8. Furthermore, the DC/DC μModule TM can be synchronized with an external clock for reducing undesirable frequency harmonics and allows PolyPhase ® operation for high load currents. The L TM4612 is offered in a space saving and thermally enhanced 15mm × 15mm × 2.8mm LGA package, which enables utilization of unused space on the bottom of PC boards for high density point-of-load regulation. The L TM4612 is Pb-free and RoHS compliant. 12V/5A Ultralow Noise μModule with 22V to 36V Input n Complete Low EMI Switch Mode Power Supply n CISPR 22 Class B Compliant n Wide Input Voltage Range: 5V to 36V n 5A DC, 7A Peak Output Current n 3.3V to 15V Output Voltage Range n Low Input and Output Referred Noise n Output Voltage T racking and Margining n PLL Frequency Synchronization n ± 1.5% Set Point Accuracy n Power Good Tracks with Margining n Current Foldback Protection (Disabled at Start-Up) n Parallel/Current Sharing n Ultrafast T ransient Response n Current Mode Control n Programmable Soft-Start n Output Overvoltage Protection n –55°C to 125°C Operating Temperature Range (L TM4612MPV) n Small Surface Mount Footprint, Low Profi le (15mm × 15mm × 2.8mm) LGA Package n Telecom and Networking Equipment n Industrial and Avionic Equipment n RF Systems , L T , L TC, L TM and PolyPhase are registered trademarks of Linear Technology Corporation. μModule is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.Effi ciency vs Load Current at 12V Output OUTPUT CURRENT (A) EFFICIENCY (%) 100 1 2 3 4 5
4612 TA01b
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS PLLIN, FCB, TRACK/SS, MPGM, MARG0, Internal Operating Temperature Range (Note 2) (Note 1) MARG1 DRVCC VFB PGOOD SGND NC NC NC FCB V IN BANK 1 VD PGND BANK 2 VOUT BANK 3 fSET MARG0 RUN COMP MPGM PLLIN INTVCC TRACK/SS LGA PACKAGE 133-LEAD (15mm × 15mm × 2.8mm) TOP VIEW SGND 12214 35 6 9 81 0 1 17 A B C D E F G H J K L M TJMAX = 125°C, θJA = 15°C/W , θJC = 6°C/W θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS WEIGHT = 1.7g ORDER INFORMATION LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TM4612EV#PBF L TM4612EV#PBF L TM4612V 133-Lead (15mm × 15mm × 2.8mm) LGA –40°C to 125°C L TM4612IV#PBF L TM4612IV#PBF L TM4612V 133-Lead (15mm × 15mm × 2.8mm) LGA –40°C to 125°C L TM4612MPV#PBF L TM4612MPV#PBF L TM4612MPV 133-Lead (15mm × 15mm × 2.8mm) LGA –55°C to 125°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear .com/packaging/
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN(DC) Input DC Voltage l 53 6 V VOUT(DC) Output Voltage CIN = 10μF × 3, COUT = 300μF; FCB = 0 V IN = 24V , VOUT = 12V , IOUT = 0A V IN = 36V , VOUT=12V , IOUT = 0A l l 11.89 11.89 12.07 12.07 12.25 12.25 V V Input Specifi cations V IN(UVLO) Undervoltage Lockout Threshold I OUT = 0A 3.2 4.8 V IINRUSH(VIN) Input Inrush Current at Start-Up IOUT = 0A; CIN = 10μF × 2, COUT = 200μF; VOUT = 12V V IN = 24V V IN = 36V 0.6 0.7 A A The l denotes the specifi cations which apply over the full internal operating temperature range, otherwise specifi cations are at TA = 25°C, VIN = 24V , unless otherwise noted. Per Typical Application (front page) confi guration.
ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full internal operating temperature range, otherwise specifi cations are at TA = 25°C, VIN = 24V , unless otherwise noted. Per Typical Application (front page) confi guration. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IQ(VIN) Input Supply Bias Current V IN = 36V , No Switching VIN = 36V , VOUT = 12V , Switching Continuous VIN = 24V , No Switching VIN = 24V , VOUT = 12V , Switching Continuous Shutdown, RUN = 0, VIN = 36V 4.5 3.5 mA mA mA mA μA I S(VIN) Input Supply Current V IN = 36V , VOUT = 12V , IOUT = 5A VIN = 24V , VOUT = 12V , IOUT = 5A 1.85 2.72 A A VINTVCC Internal VCC Voltage V IN = 36V , RUN > 2V , IOUT = 0A 4.7 5 5.3 V Output Specifi cations I OUT(DC) Output Continuous Current Range V IN = 24V , VOUT = 12V (Note 4) 0 5 A ΔVOUT(LINE) VOUT Line Regulation Accuracy V OUT = 12V , FCB = 0V , VIN = 22V to 36V , IOUT = 0A l 0.05 0.3 % ΔVOUT(LOAD) VOUT Load Regulation Accuracy V OUT = 12V , FCB = 0V , IOUT = 0A to 5A (Note 4) V IN = 36V V IN = 24V l l 0.3 0.3 0.6 0.6 VIN(AC) Input Ripple Voltage I OUT = 0A, CIN = 2 × 10μF X5R Ceramic and 1 × 100μF Electrolytic, 1 × 10μF X5R Ceramic on VD Pins V IN = 24V , VOUT = 5V V IN = 24V , VOUT = 12V 7.2 3.4 mVP-P mVP-P VOUT(AC) Output Ripple Voltage I OUT = 0A, COUT = 2 × 22μF , 2 × 47μF X5R Ceramic V IN = 24V , VOUT = 5V V IN = 24V , VOUT = 12V 17.5 12.5 mVP-P mVP-P fS Output Ripple Voltage Frequency I OUT = 1A, VIN = 24V , VOUT = 12V 940 kHz ΔVOUT(START) Turn-On Overshoot, TRACK/SS = 10nF COUT = 200μF , VOUT = 12V , IOUT = 0A V IN = 36V V IN = 24V mV mV tSTART Turn-On Time, TRACK/SS = Open C OUT = 300μF , VOUT = 12V , IOUT = 1A Resistive Load V IN = 36V V IN = 24V 0.5 0.5 ms ms ΔVOUT(LS) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load COUT = 2 × 22μF Ceramic, 150μF Bulk V IN = 24V , VOUT = 12V 153 mV tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, VIN = 24V 37 μs IOUT(PK) Output Current Limit C OUT = 200μF V IN = 36V , VOUT = 12V V IN = 24V , VOUT = 12V A A Control Section VFB Voltage at VFB Pin I OUT = 0A, VOUT = 12V l 0.594 0.6 0.606 V VRUN RUN Pin On/Off Threshold 1 1.5 1.9 V ISS / TRACK Soft-Start Charging Current V SS/TRACK = 0V –1 –1.5 –2 μA VFCB Forced Continuous Threshold 0.57 0.6 0.63 V IFCB Forced Continuous Pin Current V FCB = 0V –1 –2 μA tON(MIN) Minimum On-Time (Note 3) 50 100 ns tOFF(MIN) Minimum Off-Time (Note 3) 250 400 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TM4612E is guaranteed to meet performance specifi cations over the 0°C to 125°C internal operating temperature range. Specifi cations over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The L TM4612I is guaranteed to meet specifi cations over the SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS RPLLIN PLLIN Input Resistor 50 kΩ IDRVCC Current into DRVCC Pin V OUT = 12V , IOUT = 1A 22 30 mA RFBHI Resistor Between VOUT and VFB Pins 99.5 100 100.5 kΩ VMPGM Margin Reference Voltage 1.18 V VMARG0, VMARG1 MARG0, MARG1 Voltage Thresholds 1.4 V PGOOD ΔVFBH PGOOD Upper Threshold V FB Rising 7 10 13 % ΔVFBL PGOOD Lower Threshold V FB Falling –7 –10 –13 % ΔVFB(HYS) PGOOD Hysteresis V FB Returning 1.5 % VPGL PGOOD Low Voltage I PGOOD = 5mA 0.15 0.4 V ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the –40°C to 85°C operating temperature range, otherwise specifi cations are at TA = 25°C, VIN = 24V , unless otherwise noted. Per Typical Application (front page) confi guration. –40°C to 125°C internal operating temperature range. The L TM4612MP is guaranteed and tested over the full –55°C to 125°C internal operating temperature range. Note that the maximum ambient temperature is determined by specifi c operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: 100% tested at die level only. Note 4: See the Output Current Derating curves for different V IN, VOUT and TA.
TYPICAL PERFORMANCE CHARACTERISTICS Effi ciency vs Load Current with 3.3VOUT (FCB = 0) Effi ciency vs Load Current with 5VOUT (FCB = 0) Effi ciency vs Load Current with 12VOUT (FCB = 0) Effi ciency vs Load Current with 15VOUT (FCB = 0, Refer to Figure 20) T ransient Response from 12VIN to 3.3VOUT T ransient Response from 12VIN to 5VOUT T ransient Response from 24VIN to 12VOUT Start-Up with 24VIN to 12VOUT at IOUT = 0A Start-Up with 24VIN to 12VOUT at IOUT = 5A (Refer to Figure 18) LOAD CURRENT (A) EFFICIENCY (%) 100 1 2 3 4 5
4612 G01
5VIN 3.3VOUT 12VIN 3.3VOUT 24VIN 3.3VOUT 36VIN 3.3VOUT LOAD CURRENT (A) EFFICIENCY (%) 1 2 3 4 5
4612 G02
LOAD CURRENT (A) EFFICIENCY (%) 100 1 2 3 4 5
4612 G03
LOAD CURRENT (A) EFFICIENCY (%) 100 1 2 3 4 5
4612 G04
50μs/DIV 2A/DIV 100mV/DIV
4612 G05
LOAD STEP: 0A to 3A COUT = 2 s 22μF CERAMIC CAPACITORS AND 2 s 47μF CERAMIC CAPACITORS 50μs/DIV 2A/DIV 100mV/DIV
4612 G06
LOAD STEP: 0A to 3A COUT = 2 s 22μF CERAMIC CAPACITORS AND 2 s 47μF CERAMIC CAPACITORS 50μs/DIV 2A/DIV 200mV/ DIV
4612 G07
LOAD STEP: 0A to 3A C OUT = 2 s 22μF CERAMIC CAPACITORS AND 2 s 47μF CERAMIC CAPACITORS 500μs/DIV IIN 0.2A/DIV VOUT 5V/DIV
4612 G08
SOFT-START CAPACITOR: 3.9nF CIN = 3 s 10μF CERAMIC CAPACITORS AND 1 s 47μF OSCON CAPACITOR 500μs/DIV IIN 1A/DIV VOUT 5V/DIV
4612 G09
SOFT-START CAPACITOR: 3.9nF CIN = 3 s 10μF CERAMIC CAPACITORS AND 1 s 47μF OSCON CAPACITOR
TYPICAL PERFORMANCE CHARACTERISTICS Start-Up with 24VIN to 12VOUT at IOUT = 5A, TA = –55°C Short-Circuit with 24VIN to 12VOUT at IOUT = 0A Short-Circuit with 24VIN to 12VOUT at IOUT = 5A VIN to VOUT Step-Down Ratio Input Ripple Output Ripple 500μs/DIV IIN 1A/DIV VOUT 5V/DIV
4612 G10
SOFT-START CAPACITOR: 3.9nF CIN = 3 s 10μF CERAMIC CAPACITORS AND 1 s 47μF OSCON CAPACITOR 50μs/DIV IIN 0.2A/DIV VOUT 5V/DIV
4612 G11
COUT = 2 s 22μF CERAMIC CAPACITORS AND 2 s 47μF CERAMIC CAPACITORS 20μs/DIV IIN 2A/DIV VOUT 5V/DIV
4612 G12
COUT = 2 s 22μF CERAMIC CAPACITORS AND 2 s 47μF CERAMIC CAPACITORS 3.3 61 04 81 2 1 4 1 5
4612 G13
SEE FREQUENCY ADJUSTMENT SECTION FOR OPERATIONS OUTSIDE THIS REGION OPERATING REGION WITH DEFAUL T FREQUENCY V OUT (V) VIN (V) 1μs/DIV 50mV/DIV
4612 G14
VIN = 24V VOUT = 12V AT 5A RESISTIVE LOAD CIN = 3 s 10μF 50V CERAMIC 1 s 100μF BULK 1μs/DIV 10mV/DIV
4612 G15
VIN = 24V VOUT = 12V AT 5A RESISTIVE LOAD COUT = 2 s 22μF 16V CERAMIC AND 2 s 47μF 16V CERAMIC
VIN (Bank 1): Power Input Pins. Apply input voltage be- tween these pins and PGND pins. Recommend placing input decoupling capacitance directly between V IN pins and PGND pins. PGND (Bank 2): Power Ground Pins for Both Input and Output Returns. VOUT (Bank 3): Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and GND pins (see the L TM4612 Pin Confi guration below). V D (Pins B7, C7): Top FET Drain Pins. Add more capa- citors between VD and ground to handle the input RMS current and reduce the input ripple further . DRVCC (Pins C10, E11, E12): These pins normally con- nect to INTVCC for powering the internal MOSFET drivers. They can be biased up to 6V from an external supply with about 50mA capability. This improves effi ciency at the higher input voltages by reducing power dissipation in the module. INTV CC (Pin A7): This pin is for additional decoupling of the 5V internal regulator . PLLIN (Pin A8): External Clock Synchronization Input to the Phase Detector . This pin is internally terminated to SGND with a 50k resistor . Apply a clock above 2V and below INTV CC. See the Applications Information section. FCB (Pin M12): Forced Continuous Input. Connect this pin to SGND to force continuous synchronization operation at low load, to INTVCC to enable discontinuous mode opera- tion at low load or to a resistive divider from a secondary output when using a secondary winding. TRACK/SS (Pin A9): Output Voltage T racking and Soft-Start Pin. When the module is confi gured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. A soft-start capacitor can be used for soft-start turn-on as a standalone regulator . Slave operation is performed by putting a resistor divider from the master output to the ground, and connecting the center point of the divider to this pin. See the Applications Information section. MPGM (Pins A12, B11): Programmable Margining Input. A resistor from these pins to ground sets a current that is equal to 1.18V/R. This current multiplied by 10k will equal a value in millivolts that is a percentage of the 0.6V refer- ence voltage. See the Applications Information section. To parallel L TM4612s, each requires an individual MPGM resistor . Do not tie MPGM pins together . f SET (Pin B12): Frequency Set Internally to 850kHz at 12V Output. An external resistor can be placed from this pin to ground to increase frequency. This pin can be decoupled with a 1000pF capacitor . See the Applications Information section for frequency adjustment. V FB (Pin F12): The Negative Input of the Error Amplifi er . Internally, this pin is connected to VOUT with a 100k preci- sion resistor . Different output voltages can be programmed with an additional resistor between the V FB and SGND pins. See the Applications Information section. MARG0 (Pin C12): LSB Logic Input for the Margining Function. Together with the MARG1 pin, the MARG0 pin will determine if a margin high, margin low, or no margin state is applied. The pin has an internal pull-down resistor of 50k. See the Applications Information section. MARG1 (Pins C11, D12): MSB Logic Input for the Margin- ing Function. Together with the MARG0 pin, the MARG1 pin will determine if a margin high, margin low, or no margin state is applied. The pins have an internal pull-down resistor of 50k. See the Applications Information section. SGND (Pins D9, H12): Signal Ground Pins. These pins connect to PGND at output capacitor point. L TM4612 Pin Confi guration (See Package Description for Pin Assignments) MARG1 DRVCC VFB PGOOD SGND NC NC NC FCB V IN BANK 1 VD PGND BANK 2 VOUT BANK 3 fSET MARG0 RUN COMP MPGM PLLIN INTVCC TRACK/SS LGA PACKAGE 133-LEAD (15mm × 15mm × 2.8mm) TOP VIEW SGND 12214 35 6 9 81 0 1 17 A B C D E F G H J K L M
to zero sense voltage (zero current). PGOOD (Pin G12): Output Voltage Power Good Indicator . after a 25μs power bad mask timer expires. a 5.1V zener to ground. Maximum pin voltage is 5V . NC (Pins J12, K12, L12): No Connect Pins. Specifi cations are at T A = 25°C. Use Figure 1 confi guration. Figure 1. Simplifi ed Block Diagram
The L TM4612 is a standalone nonisolated switching mode DC/DC power supply. It can deliver 5A of DC output current with some external input and output capacitors. This module provides precisely regulated output voltage programmable via one external resistor from 3.3V DC to 15VDC over a 5V to 36V wide input voltage. The typical application schematic is shown in Figure 18. The L TM4612 has an integrated constant on-time current mode regulator , ultralow RDS(ON) FETs with fast switch- ing speed and integrated Schottky diodes. The typical switching frequency is 850kHz at full load. With current mode control and internal feedback loop compensation, the L TM4612 module has suffi cient stability margins and good transient performance under a wide range of operat- ing conditions and with a wide range of output capacitors, even all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limiting. Moreover , foldback current limiting is provided in an overcurrent condition while V FB drops. Internal overvoltage and undervoltage comparators pull the open- drain PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. Furthermore, in an overvoltage condition, internal top FET M1 is turned off and bottom FET M2 is turned on and held on until the overvoltage condition clears. Input fi lter and noise cancellation circuitry reduce the noise coupling to I/O sides, and ensure the electromag- netic interference (EMI) meets the limits of CISPR 22 and CISPR 25. Pulling the RUN pin below 1V forces the controller into its shutdown state, turning off both M1 and M2. At low load currents, discontinuous mode (DCM) operation can be enabled to achieve higher effi ciency compared to continu- ous mode (CCM) by setting FCB pin higher than 0.6V . When the DRV CC pin is connected to INTVCC, an integrated 5V linear regulator powers the internal gate drivers. If a 5V external bias supply is applied on DRV CC pin, then an effi ciency improvement will occur due to the reduced power loss in the internal linear regulator . This is especially true at the higher input voltage range. The MPGM, MARG0, and MARG1 pins are used to sup- port voltage margining, where the percentage of margin is programmed by the MPGM pin, and the MARG0 and MARG1 selected margining. The PLLIN pin provides fre- quency synchronization of the device to an external clock. The TRACK/SS pin is used for power supply tracking and soft-start programming.
Figure 18. External component selection is primarily requirements for a particular application. down ratio that can be achieved for a given input voltage. Derating section in this data sheet. The PWM controller has an internal 0.6V reference voltage. Table 1. RFB Standard 1% Resistor Values vs VOUT PGM resistor on the MPGM pin programs the current. Figure 2. Operating Frequency vs Output Voltage The output margining will be ± margining of the value. output ripple voltage while still keeping high effi ciency. additional frequency adjusting is required. Figure 3. Inductor Current Ripple vs Output Voltage
4612 F02
4612 F03
Figure 4. Conducted Emission Scan with 24VIN to Pads and 1 × 10μF Ceramic Capacitor on VD Pads). pin and SGND, as shown in Figure 19. higher than 1MHz, thus reducing the effi ciency signifi cantly. from the fSET pin to VIN, as shown in Figure 20. EMI noise due to the fast switching of turn-on and turn-off. is needed for capacitor C1 selection. or X7R, 10μF ceramic capacitor is recommended for C1. different conducted EMI limits.
4612 F04
The L TM4612 is designed for low output voltage ripple. to maximize transient performance. series resistance (ESR) of the output bulk capacitance.
4612 F05
Figure 5. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI
state operation, but also in transient. of its full current limit value. the ramp of the internal reference and the output voltage. another regulator can be easily tracked. that is the same as the slave regulator’s feedback divider . different resistor values to change the output tracking ratio. driven with 5V logic levels. where R1 is the top resistor , and R2 is the bottom resistor . Figure 6. Coincident T racking Figure 7. Coincident Output T racking
4612 F07
4612 F06
be provided for more control loop optimization. to be locked to the rising edge of the external clock. clock on the PLLIN pin to turn on the phase-locked loop. phase-locked loop function is disabled. mended to connect the DRVCC pin to the external 5V rail. design. Figure 21 shows a schematic of the parallel design. N is the number of paralleled modules. meet the most applications with low noise requirements. CISPR 22 radiated emission limit. Figure 8. Radiated Emission Scan with 24VIN to
4612 F08
Figure 9. Power Loss at Figure 10. Power Loss at 5VOUT Figure 11. No Heat Sink Figure 12. BGA Heat Sink Figure 13. No Heat Sink Figure 14. BGA Heat Sink
4612 F09
4612 F10
4612 F11
4612 F12
4612 F13
4612 F14
Figure 15. No Heat Sink Figure 16. BGA Heat Sink Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 20) Table 3. 12V and 15V Outputs
4612 F15
4612 F16
erations are still necessary.
- Use large PCB copper areas for high current path, in- cluding V IN, PGND and VOUT. It helps to minimize the PCB conduction loss and thermal stress.
- Place high frequency ceramic input and output capaci- tors next to the VD, PGND and VOUT pins to minimize high frequency noise.
- Place a dedicated power ground layer underneath the unit.
- Use round corners for the PCB copper layer to minimize the radiated noise.
- To minimize the EMI noise and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
- Do not put vias directly on pads.
- If vias are placed onto the pads, the the vias must be capped.
- Interstitial via placement can also be used if necessary.
- Use a separated SGND ground copper area for com- ponents connected to signal pins. Connect the SGND to PGND underneath the unit.
- Place one or more high frequency ceramic capacitors close to the connection into the system board. Figure 17 gives a good example of the recommended layout.
Table 4. 5V Output Figure 17. Recommended PCB Layout
4612 F17
Figure 19. Typical 5V to 36VIN, 3.3V at 5A Design with 400kHz Frequency Figure 18. Typical 22V to 36VIN, 12V at 5A Design
4612 F19
4612 F18
4612 F21
Figure 21. 2-Phase, Parallel 12V at 10A Design Figure 20. 26V to 36VIN, 15V at 4A Design with Reduced Frequency
4612 F20
4612 F22
Figure 22. 2-Phase, 12V and 10V at 5A Design
4612 F23
Figure 23. 2-Phase, 5V and 3.3V at 5A Design with 500kHz Frequency
V IN VIN VIN VIN VIN VIN V IN VIN VIN VIN VIN VIN V IN VIN VIN VIN VIN VIN Pin Assignment Tables (Arranged by Pin Function) PIN NAME PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND G10 G11 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND H10 H11 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PIN NAME J10 J11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT K10 K11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT L10 L11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT M10 M11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT PIN NAME A10 A11 A12 INTV CC PLLIN TRACK/SS RUN COMP MPGM B10 B11 B12 V D RUN MPGM f SET C10 C11 C12 V D DRV CC MARG1 MARG0 D10 D11 D12 SGND COMP MARG1 E10 E11 E12 DRV CC DRVCC F10 F11 F12 V FB G12 PGOOD H12 SGND J12 NC K12 NC L12 NC M12 FCB PACKAGE DESCRIPTION
133-Lead (15mm × 15mm × 2.82mm) (Reference L TM DWG # 05-08-1766 Rev Ø) LKJHGFEDCBMA NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 133 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE SYMBOL aaa bbb eee TOLERANCE 0.10 0.10 0.05 2.72 – 2.92 DETAIL B DETAIL B SUBSTRATE MOLD CAP 0.27 – 0.37 2.45 – 2.55 bbb Z Z BSC PACKAGE TOP VIEW BSC PAD 1 CORNER X Y aaa Z aaa Z DETAIL A 13.97 BSC 1.27 BSC 13.97 BSC 0.12 – 0.28 PACKAGE BOTTOM VIEW C(0.30) PAD 1 PADS SEE NOTES DETAIL A 0.630 ±0.025 SQ. 133x S YXeee SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 LGA 133 1107 REV Ø L TMXXXXXX μModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2008 LT 0808 • PRINTED IN USA RELATED PARTS PACKAGE PHOTOGRAPH
4612 F24
2.8mm PART NUMBER DESCRIPTION COMMENTS L TC2900 Quad Supply Monitor with Adjustable Reset Timer Monitors Four Supplies; Adjustable Reset Timer L TM4600 10A DC/DC μModule Basic 10A DC/DC μModule, LGA Package L TM4600HVMP Military Plastic 10A DC/DC μModule Guaranteed Operation from –55°C to 125°C Ambient, LGA Package L TM4601/ L TM4601A 12A DC/DC μModule with PLL, Output T racking/ Margining and Remote Sensing Synchronizable, PolyPhase Operation, L TM4601-1/L TM4601A-1 Version Has No Remote Sensing, LGA Package L TM4602 6A DC/DC μModule Pin Compatible with the L TM4600, LGA Package L TM4603 6A DC/DC μModule with PLL and Output T racking/ Margining and Remote Sensing Synchronizable, PolyPhase Operation, L TM4603-1 Version Has No Remote Sensing, Pin Compatible with the L TM4601, LGA Package L TM4604A Low V IN 4A DC/DC μModule 2.375V ≤ VIN ≤ 5.5V , 0.8V ≤ VOUT ≤ 5V , 9mm × 15mm × 2.3mm LGA Package L TM4606 Ultralow Noise 6A, DC/DC μModule Ultralow Noise, with PLL, Output T racking and Margining, L TM4612 Pin Compatible L TM4608A Low V IN 8A DC/DC μModule 2.4V ≤ VIN ≤ 5.5V; 0.6V ≤ VOUT ≤ 5V; 9mm × 15mm × 2.8mm LGA Package L TM8022/L TM8023 36VIN, 1A and 2A DC/DC μModule Pin Compatible; 4.5V ≤ VIN ≤ 36V; 9mm × 11.25mm × 2.8mm LGA Package