LTM4612

LTM4613_V01 LINER | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 30

Technical content

4613fdFor more information www.linear .com/L TM4613 PGOOD RUN COMP INTV CC DRVCC fSET TRACK/SS FCB MARG0 MARG1 MPGM VOUT VFB VIN 0.1µF 10µF × 3 22pF COUT VOUT 12V C IN VIN 24V TO 36V PLLIN CLOCK SYNC L TM4613 SGND VD PGND MARGIN CONTROL 51k 5.23k 392k 5% MARGIN

4613 TA01

FEATURES

APPLICATIONS

DESCRIPTION

36VIN, 15VOUT, 8A, DC/DC µModule Regulator The LT M®4613 is a complete, ultralow noise, 8A switch mode DC/DC power supply. Included in the package are the switching controller, power FETs, inductor and all support components. Operating over an input voltage range of 5V to 36V, the LTM4613 supports an output voltage range of 3.3V to 15V, set by a single external resistor. Only bulk input and output capacitors are needed to finish the design. High switching frequency and an adaptive on-time current mode architecture enables a very fast transient response to line and load changes without sacrificing stability. The onboard input filter and noise cancellation circuits achieve low noise coupling, thus effectively reducing the electromagnetic interference (EMI)—see Figure 7. Furthermore, the DC/DC µModule ® regulator can be syn- chronized with an external clock to reduce undesirable frequency harmonics and allow PolyPhase ® operation for high load currents. The LTM4613 is offered in 15mm × 15mm × 4.32mm LGA and 15mm × 15mm × 4.92mm BGA packages. The LTM4613 is available with SnPb (BGA) or RoHS compli- ant terminal finish. 12V/8A Ultralow Noise µModule with 24V to 36V Input n Complete Low EMI Switch Mode Power Supply n EN55022 Class B Compliant n Wide Input Voltage Range: 5V to 36V n 8A Output Current n 3.3V to 15V Output Voltage Range n Low Input and Output Referred Noise n Output Voltage T racking and Margining n PLL Frequency Synchronization n 2% Maximum Total DC Error n Power Good Tracks with Margining n Current Foldback Protection n Parallel/Current Sharing n Ultrafast T ransient Response n Current Mode Control n Programmable Soft-Start n Output Overvoltage Protection n –55°C to 125°C Operating Temperature Range TM4613MPV , L TM4613MPY) n 15mm × 15mm × 4.32mm LGA and 15mm × 15mm × 4.92mm BGA Packages n SnPb (BGA) or RoHS Compliant (LGA and BGA) Finish n Telecom and Networking Equipment n Industrial and Avionic Equipment n RF Systems Radiated Emission Scan with 24VIN to 12VOUT at 8A L, LT, LT C, LT M, µModule, PolyPhase, Linear Technology, and the Linear logo are registered trademarks and L TpowerCAD is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.

30 SIGNAL AMPLITUDE (dB uV/m)

30 226.2 422.4 613.6 FREQUENCY (MHz) 4613 TA01b 814.3 1010.0 –10 EN55022B LIMIT

4613fd For more information www.linear .com/L TM4613 PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS PLLIN, FCB, TRACK/SS, MPGM, MARG0, 0.3V to 5V (Note 1) MARG1 DRVCC VFB PGOOD SGND NC NC NC FCB V IN BANK 1 VD PGND BANK 2 VOUT BANK 3 fSET MARG0 RUN COMP MPGM PLLIN INTVCC VD TRACK/SS LGA PACKAGE 133-LEAD (15mm × 15mm × 4.32mm) TOP VIEW SGND 122 1 4 3 5 6 9 8 10 117 A B C D E F G H J K L M TJMAX = 125°C, θJCtop = 17°C/w, θJCbottom = 2.3°C/W, θJA = 10°C/W, θJB = 2.5°C/W, θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS WEIGHT = 2.5g MARG1 DRVCC VFB PGOOD SGND NC NC NC FCB V IN BANK 1 VD PGND BANK 2 VOUT BANK 3 fSET MARG0 RUN COMP MPGM PLLIN INTVCC VD TRACK/SS BGA PACKAGE 133-LEAD (15mm × 15mm × 4.92mm) TOP VIEW SGND 122 1 4 3 5 6 9 8 10 117 A B C D E F G H J K L M TJMAX = 125°C, θJCtop = 17°C/w, θJCbottom = 2.3°C/W, θJA = 10°C/W, θJB = 2.5°C/W, θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS WEIGHT = 2.7g PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE (Note 2)DEVICE FINISH CODE LTM4613EV#PBF Au (RoHS) LTM4613V e4 LGA 3 –40°C to 125°C LTM4613IV#PBF Au (RoHS) LTM4613V e4 LGA 3 –40°C to 125°C LTM4613MPV#PBF Au (RoHS) LTM4613V e4 LGA 3 –55°C to 125°C LTM4613EY#PBF SAC305 (RoHS) LTM4613Y e1 BGA 3 –40°C to 125°C LTM4613IY#PBF SAC305 (RoHS) LTM4613Y e1 BGA 3 –40°C to 125°C LTM4613IY SnPb (63/37) LTM4613Y e0 BGA 3 –40°C to 125°C LTM4613MPY#PBF SAC305 (RoHS) LTM4613Y e1 BGA 3 –55°C to 125°C LTM4613MPY SnPb (63/37) LTM4613Y e0 BGA 3 –55°C to 125°C

• Consult Marketing for parts specified with wider operating temperature ranges. *Device temperature grade is indicated by a label on the shipping container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Terminal Finish Part Marking: www.linear.com/leadfree
• Recommended LGA and BGA PCB Assembly and Manufacturing Procedures: www.linear.com/umodule/pcbassembly
• LGA and BGA Package and T ray Drawings: www.linear.com/packaging Internal Operating Temperature Range (Note 2) E- an C to 125°C MP- C to 125°C C to 125°C 5°C ORDER INFORMATIONhttp://www.linear.com/product/LTM4613#orderinfo

4613fdFor more information www.linear .com/L TM4613 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 24V, unless otherwise noted. Per Typical Application (front page) configuration. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN(DC) Input DC Voltage l 5 36 V VOUT(DC) Output Voltage, Total Variation with Line and Load CIN = 10µF × 3, COUT = 47µF × 4; FCB = 0, VIN = 24V to 36V, VOUT = 12V l 11.83 12.07 12.31 V Input Specifications VIN(UVLO) Undervoltage Lockout Threshold I OUT = 0A 3.2 4.8 V IINRUSH(VIN) Input Inrush Current at Start-Up I OUT = 0A; CIN = 10µF × 3, COUT = 47µF × 4; CSS = 22nF VOUT = 12V VIN = 24V VIN = 36V 150 120 mA mA I Q(VIN) Input Supply Bias Current V IN = 36V, VOUT = 12V, Switching Continuous, IOUT = 0A VIN = 24V, VOUT = 12V, Switching Continuous, IOUT = 0A Shutdown, RUN = 0, VIN = 36V mA mA µA I S(VIN) Input Supply Current VIN = 36V, VOUT = 12V, IOUT = 8A VIN = 24V, VOUT = 12V, IOUT = 8A 2.90 4.26 A A V INTVCC Internal VCC Voltage VIN = 36V, RUN > 2V, IOUT = 0A 4.7 5 5.5 V Output Specifications IOUT(DC) Output Continuous Current Range V IN = 24V, VOUT = 12V (Note 4) 0 8 A ∆VOUT(LINE) VOUT Line Regulation Accuracy V OUT = 12V, FCB = 0V, VIN = 24V to 36V, IOUT = 0A l 0.05 0.3 ∆VOUT(LOAD) VOUT Load Regulation Accuracy V OUT = 12V, FCB = 0V, IOUT = 0A to 8A (Note 4) VIN = 36V VIN = 24V l l 0.5 0.5 0.75 0.75 V IN(AC) Input Ripple Voltage IOUT = 0A, CIN = 1 × 10µF X5R Ceramic and 1 × 100µF Electrolytic, 3 × 10µF X5R Ceramic on VD Pins VIN = 24V, VOUT = 12V (Note 5) mV P-P VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 1 × 10µF, 4 × 47µF X5R Ceramic VIN = 24V, VOUT = 12V mV P-P fS Output Ripple Voltage Frequency V IN = 24V, VOUT = 12V, IOUT = 0A 600 kHz ∆VOUT(START) Turn-On Overshoot COUT = 47µF × 4, VOUT = 12V, IOUT = 0A, CSS = 22nF VIN = 36V VIN = 24V mV mV t START Turn-On Time COUT = 47µF × 4, VOUT = 12V, IOUT = 0A, CSS = Open VIN = 36V VIN = 24V 0.3 0.3 ms ms OUT(LS) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load COUT = 1 × 10µF, 3 × 47µF X5R Ceramic, 1 × 47µF POSCAP VIN = 24V, VOUT = 12V 250 mV tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load C OUT = 1 × 10µF, 3 × 47µF X5R Ceramic, 1 × 47µF POSCAP VIN = 24V, VOUT = 12V 100 µs IOUT(PK) Output Current Limit COUT = 47µF × 4 VIN = 36V, VOUT = 12V VIN = 24V, VOUT = 12V A A

4613fd For more information www.linear .com/L TM4613 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4613 is tested under pulsed load conditions such that T J ≈ TA. The LTM4613E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4613I is guaranteed to meet specifications over the –40°C to 125°C internal operating temperature range. The LTM4613MP SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Control Section VFB Voltage at VFB Pin IOUT = 0A, VOUT = 12V l 0.591 0.6 0.609 V VRUN RUN Pin On/Off Threshold 1 1.5 1.9 V ITRACK/SS Soft-Start Charging Current V TRACK/SS = 0V –1 –1.5 –2 µA VFCB Forced Continuous Threshold 0.57 0.6 0.63 V IFCB Forced Continuous Pin Current V FCB = 0V –1 –2 µA tON(MIN) Minimum On-Time (Note 3) 50 100 ns tOFF(MIN) Minimum Off-Time (Note 3) 250 400 ns RPLLIN PLLIN Input Resistor 50 kΩ IDRVCC Current into DRVCC Pin VOUT = 12V, IOUT = 0A, DRVCC = 5V 22 30 mA RFBHI Resistor Between VOUT and VFB Pins 99.5 100 100.5 kΩ VMPGM Margin Reference Voltage 1.18 V VMARG0, VMARG1 MARG0, MARG1 Voltage Thresholds 1.4 V PGOOD ∆VFBH PGOOD Upper Threshold V FB Rising 7 10 13 % ∆VFBL PGOOD Lower Threshold V FB Falling –7 –10 –13 % ∆VFB(HYS) PGOOD Hysteresis VFB Returning 1.5 % VPGL PGOOD Low Voltage IPGOOD = 5mA 0.2 0.4 V ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 24V, unless otherwise noted. Per Typical Application (front page) configuration. is guaranteed and tested over the full –55°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: 100% tested at die level only. Note 4: See the Output Current Derating curves for different V IN, VOUT and TA. Note 5: Guaranteed by design.

4613fdFor more information www.linear .com/L TM4613 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Load Current with 3.3VOUT (FCB = 0) Efficiency vs Load Current with OUT (FCB = 0) Efficiency vs Load Current with 12V OUT (FCB = 0) Efficiency vs Load Current with 15V OUT (FCB = 0) T ransient Response from 12VIN to 3.3VOUT T ransient Response from 12VIN to 5VOUT T ransient Response from 24VIN to 12VOUT Start-Up with 24VIN to 12VOUT at IOUT = 0A Start-Up with 24VIN to 12VOUT at IOUT = 8A (Refer to Figure 18) LOAD CURRENT (A) EFFICIENCY (%)

4613 G01

5VIN, 3.3VOUT 12VIN, 3.3VOUT 24VIN, 3.3VOUT 36VIN, 3.3VOUT LOAD CURRENT (A) EFFICIENCY (%)

4613 G02

12VIN, 5VOUT 24VIN, 5VOUT 36VIN, 5VOUT LOAD CURRENT (A) EFFICIENCY (%)

4613 G03

20VIN, 12VOUT 24VIN, 12VOUT 28VIN, 12VOUT 36VIN, 12VOUT LOAD CURRENT (A) EFFICIENCY (%)

4613 G04

24VIN, 15VOUT 28VIN, 15VOUT 32VIN, 15VOUT 36VIN, 15VOUT IOUT 5A/DIV VOUT 100mV/DIV AC 100µs/DIV LOAD STEP: 0A TO 4A COUT = 1 × 47µF POSCAP 1 × 10µF CERAMIC CAPACITOR AND 3 × 47µF CERAMIC CAPACITORS

4613 G05

100µs/DIV LOAD STEP: 0A TO 4A C OUT = 1 × 47µF POSCAP 1 × 10µF CERAMIC CAPACITOR AND × 47µF CERAMIC CAPACITORS

4613 G06

100µs/DIV LOAD STEP: 0A TO 4A C OUT = 1 × 47µF POSCAP 1 × 10µF CERAMIC CAPACITOR AND × 47µF CERAMIC CAPACITORS

4613 G07

SOFT-START CAPACITOR: 0.1µF C IN = 2 × 10µF CERAMIC CAPACITORS AND 1 × 100µF OS-CON CAPACITOR

4613 G08

SOFT-START CAPACITOR: 0.1µF C IN = 2 × 10µF CERAMIC CAPACITORS AND 1 × 100µF OS-CON CAPACITOR

4613 G09

4613fd For more information www.linear .com/L TM4613 TYPICAL PERFORMANCE CHARACTERISTICS Start-Up with 24VIN to 12VOUT at IOUT = 8A, TA = –55°C Short-Circuit with 24VIN to 12VOUT at IOUT = 0A Short-Circuit with 24VIN to 12VOUT at IOUT = 8A VIN to VOUT Step-Down Ratio Input Ripple Output Ripple VIN 100mV/DIV AC 1µs/DIV VIN = 24V VOUT = 12V AT 8A RESISTIVE LOAD CIN = 2 × 10µF CERAMIC CAPACITORS AND 1 × 100µF OS-CON CAPACITOR

4613 G14

1µs/DIV VIN = 24V VOUT = 12V AT 8A RESISTIVE LOAD COUT = 1 × 47µF POSCAP 1 × 10µF CERAMIC CAPACITOR AND 3 × 47µF CERAMIC CAPACITORS

4613 G15

4613 G10

SOFT-START CAPACITOR: 0.1µF CIN = 2 × 10µF CERAMIC CAPACITORS AND 1 × 100µF OS-CON CAPACITOR IIN 500mA/DIV VOUT 5V/DIV 20µs/DIV

4613 G11

COUT = 1 × 47µF POSCAP , 1 × 10µF CERAMIC CAPACITORS AND 3 × 47µF CERAMIC CAPACITORS IIN 2A/DIV VOUT 5V/DIV 20µs/DIV

4613 G12

COUT = 1 × 47µF POSCAP , 1 × 10µF CERAMIC CAPACITORS AND 3 × 47µF CERAMIC CAPACITORS OUTPUT VOLTAGE (V) 3.3 INPUT VOLTAGE (V) 5 7 9 11

4613 G13

4613fdFor more information www.linear .com/L TM4613 PIN FUNCTIONS VIN (Bank 1): Power Input Pins. Apply input voltage be - tween these pins and PGND pins. Recommend placing input decoupling capacitance directly between V IN pins and PGND pins. PGND (Bank 2): Power Ground Pins for Both Input and Output Returns. VOUT ( Bank 3): Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and PGND pins (see the LTM4613 Pin Configuration below). VD (Pins C1 to C7, B6 to B7, A6): Top FET Drain Pins. Add more high frequency ceramic decoupling capacitors between V D and PGND to handle the input RMS current and reduce the input ripple further. DRVCC (Pins C10, E11, E12): These pins normally connect to INTVCC for powering the internal MOSFET drivers. They can be biased up to 6V from an external supply with about 50mA capability. This improves efficiency at the higher input voltages by reducing power dissipation in the module. See the Applications Information section. INTV CC (Pin A7): This pin is for additional decoupling of the 5V internal regulator. PLLIN (Pin A8): External Clock Synchronization Input to the Phase Detector. This pin is internally terminated to SGND with a 50k resistor. Apply a clock above 2V and below INTV CC subject to minimum on-time and minimum off-time requirements. See the Applications Information section. FCB (Pin M12): Forced Continuous Input. Connect this pin to SGND to force continuous synchronization operation at light load or to INTVCC to enable discontinuous mode operation at light load. TRACK/SS (Pin A9): Output Voltage T racking and Soft-Start Pin. When the module is configured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. A soft-start capacitor can be used for soft-start turn-on as a standalone regulator. Slave operation is performed by putting a resistor divider from the master output to the ground, and connecting the center point of the divider to this pin. See the Applications Information section. MPGM (Pins A12, B11): Programmable Margining In - put. A resistor from these pins to ground sets a current that is equal to 1.18V/R. This current multiplied by 10k will equal a value in millivolts that is a percentage of the 0.6V reference voltage. Leave floating if margining is not used. See the Applications Information section. To parallel LTM4613s, each requires an individual MPGM resistor. Do not tie MPGM pins together. f SET (Pin B12): Frequency Set Internally to 600kHz at 12V Output. An external resistor can be placed from this pin to ground to increase frequency or from this pin to V IN to reduce frequency. See the Applications Information section for frequency adjustment. LTM4613 Pin Configuration (See Package Description for Pin Assignments) MARG1 DRVCC VFB PGOOD SGND NC NC NC FCB V IN BANK 1 VD PGND BANK 2 VOUT BANK 3 fSET MARG0 RUN COMP MPGM PLLIN INTVCC VD TRACK/SS LGA PACKAGE 133-LEAD (15mm × 15mm × 4.32mm) TOP VIEW SGND 122 1 4 3 5 6 9 8 10 117 A B C D E F G H J K L M

4613fd For more information www.linear .com/L TM4613 VFB (Pin F12): The Negative Input of the Error Ampli - fier. Internally, this pin is connected to VOUT with a 100k 0.5% precision resistor. Different output voltages can be programmed with an additional resistor between the VFB and SGND pins. See the Applications Information section. MARG0 (Pin C12): LSB Logic Input for the Margining Function. Together with the MARG1 pin, the MARG0 pin will determine if a margin high, margin low, or no margin state is applied. The pin has an internal pull-down resistor of 50k. See the Applications Information section. MARG1 (Pins C11, D12): MSB Logic Input for the Margin- ing Function. Together with the MARG0 pin, the MARG1 pin will determine if a margin high , margin low, or no margin state is applied. The pins have an internal pull-down resistor of 50k. See the Applications Information section. SGND (Pins D9, H12): Signal Ground Pins. These pins connect to PGND at output capacitor point. COMP (Pins A11, D11): Current Control Threshold and Error Amplifier Compensation Point. The current com - parator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.7V corresponding to zero sense voltage (zero current). PGOOD (Pin G12): Output Voltage Power Good Indicator. Open-drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point, after a 25µs power bad mask timer expires. RUN (Pins A10, B9): Run Control Pins. A voltage above 1.9V will turn on the module, and below 1V will turn off the module. A programmable UVLO function can be ac - complished with a resistor from V IN to this pin that has a 5.1V Zener to ground. Maximum pin voltage is 5V. MTP (Pins J12, K12, L12): No Connect Pins. Leave float- ing. Used for mounting to PCB. PIN FUNCTIONS

Specifications are at TA = 25°C. Use Figure 1 configuration.

4613 F01

Figure 1. Simplified Block Diagram

4613fd For more information www.linear .com/L TM4613 OPERATION Power Module Description The LTM4613 is a standalone nonisolated switch mode DC/DC power supply. It can deliver 8A of DC output cur- rent with minimal external input and output capacitors. This module provides a precisely regulated output voltage programmable via one external resistor from 3.3V DC to 15VDC over a wide 5V to 36V input voltage. The typical application schematic is shown in Figure 18. The LTM4613 has an integrated constant on-time current mode regulator, ultralow RDS(ON) FETs with fast switching speed and integrated Schottky diodes. The typical switching frequency is 600kHz at full load at 12V output. With current mode control and internal feedback loop compensation, the LTM4613 module has sufficient stability margins and good transient performance under a wide range of operat- ing conditions and with a wide range of output capacitors, even all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limiting. Moreover, foldback current limiting is provided in an overcurrent condition when VFB drops. Internal over- voltage and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. Furthermore, in an overvoltage condition, internal top FET M1 is turned off and bottom FET M2 is turned on and held on until the overvoltage condition clears. Input filter and noise cancellation circuitry reduce the noise coupling to inputs and outputs, and ensure the electromagnetic interference (EMI) meets the limits of EN55022 Class B (see Figure 7). Pulling the RUN pin below 1V forces the controller into its shutdown state, turning off both M1 and M2. At light load currents, discontinuous mode (DCM) operation can be enabled to achieve higher efficiency compared to con- tinuous mode (CCM) by setting FCB pin higher than 0.6V. When the DRV CC pin is connected to INTVCC, an integrated 5V linear regulator powers the internal gate drivers. If a 5V external bias supply is applied on DRVCC pin, then an efficiency improvement will occur due to the reduced power loss in the internal linear regulator. This is especially true at the higher input voltage range. The MPGM, MARG0, and MARG1 pins are used to sup - port voltage margining, where the percentage of margin is programmed by the MPGM pin, while the MARG0 and MARG1 select positive or negative margining. The PLLIN pin provides frequency synchronization of the device to an external clock. The TRACK/SS pin is used for power supply tracking and soft-start programming. The typical LTM4613 application circuit is shown in Fig- ure 18. External component selection is primarily deter - mined by the input voltage , the maximum load current and the output voltage. Refer to Table 2 for specific external capacitor requirements for a particular application. VIN to VOUT Step-Down Ratios There are restrictions in the maximum VIN and VOUT step down ratio that can be achieved for a given input voltage. These constraints are shown in the Typical Performance Characteristic curve labeled “V IN to V OUT Step-Down Ratio.” Note that additional thermal derating may be ap- plied. See the Thermal Considerations and Output Current Derating section in this data sheet. APPLICATIONS INFORMATION Output Voltage Programming and Margining The PWM controller has an internal 0.6V reference volt - age. As shown in the Block Diagram, a 100k 0.5% internal feedback resistor connects the VOUT and VFB pins together. Adding a resistor, RFB, from the VFB pin to the SGND pin programs the output voltage. VOUT = 0.6V •100k+RFB RFB or equivalently, RFB = 100k VOUT 0.6V − 1

Figure 2. Operating Frequency vs Output Voltage output ripple voltage while still keeping high efficiency. with different output voltages. additional frequency adjusting is required. pin and SGND, as shown in Figure 19. Figure 3. Pk-Pk Inductor Current Ripple vs Output Voltage Table 1. RFB Standard 1% Resistor Values vs VOUT PGM resistor on the MPGM pin programs the current.

• 10k Where RPGM is the resistor value to place on the MPGM pin to ground. The margining voltage, V OUT(MARGIN), will be added or subtracted from the nominal output voltage as determined by the state of the MARG0 and MARG1 pins. See the truth table below: MARG1 MARG0 MODE LOW LOW NO MARGIN LOW HIGH MARGIN UP HIGH LOW MARGIN DOWN HIGH HIGH NO MARGIN Parallel Operation The LTM4613 device is an inherently current mode con- trolled device. This allows the paralleled modules to have very good current sharing and balanced thermals on the design. Figure 21 shows a schematic of the parallel design. The voltage feedback equation changes with the variable N as modules are paralleled: RFB = 100k N VOUT 0.6V − 1 where N is the number of paralleled modules. OUTPUT VOLTAGE (V) 2 4 FREQUENCY (kHz) 400 1000 6 10 12

4613 F02

4613 F03

4613fd For more information www.linear .com/L TM4613 APPLICATIONS INFORMATION For output voltages more than 12V, the frequency can be higher than 600kHz, thus reducing the efficiency sig - nificantly. Additionally, the minimum off-time of 400ns normally limits the operation when the input voltage is close to the output voltage . Therefore, it is recommended to lower the frequency in these conditions by connecting a resistor (R fSET) from the f SET pin to V IN as shown in Figure 20, where: f = VOUT 5•10 −11 3•R fSET •133k RfSET −2•133k ⎜⎜⎜ ⎟⎟⎟ [Hz] The load current can affect the frequency due to its con- stant on-time control. If constant frequency is a necessity, the PLLIN pin can be used to synchronize the frequency of the LTM4613 to an external clock subject to minimum on-time and off-time limits, as shown in Figures 21 to 23. Input Capacitors LTM4613 is designed to achieve low input conducted EMI noise due to the fast switching of turn-on and turn- off. Additionally, a high-frequency inductor is integrated into the input line for noise attenuation. V D and VIN pins are available for external input capacitors to form a high frequency π filter. As shown in Figure 18, the ceramic capacitors, C1-C3, on the V D pins are used to handle most of the RMS current into the converter, so careful attention is needed for capacitors C1-C3 selection. For a buck converter, the switching duty cycle can be estimated as: D= VOUT VIN Without considering the inductor current ripple, the RMS current of the input capacitor can be estimated as: ICIN(RMS) = IOUT(MAX) η • D• 1–D( ) In this equation, η is the estimated efficiency of the power module. Note the capacitor ripple current ratings are often based on temperature and hours of life. This makes it advisable to properly derate the input capacitor, or choose a capacitor rated at a higher temperature than required. Always contact the capacitor manufacturer for derating requirements. In a typical 8A output application, three very low ESR, X5R or X7R, 10µF ceramic capacitors are recommended for C1-C3. This decoupling capacitance should be placed directly adjacent to the module V D pins in the PCB layout to minimize the trace inductance and high frequency AC noise. Each 10µF ceramic is typically good for 2A of RMS ripple current. Refer to your ceramics capacitor catalog for the RMS current ratings. To attenuate the high frequency noise, extra input capacitors should be connected to the V IN pads and placed before the high frequency inductor to form the π filter. One of these low ESR ceramic input capacitors is recommended to be close to the connection into the system board. A large bulk 100µF capacitor is only needed if the input source imped- ance is compromised by long inductive leads or traces. Output Capacitors The LTM4613 is designed for low output voltage ripple. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be low ESR tantalum capacitor, low ESR polymer capaci- tor or ceramic capacitor. The typical capacitance is 4 × 47µF if all ceramic output capacitors are used. Additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. Table 2 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 4A load transient. The table optimizes total equivalent ESR and total bulk capacitance to maximize transient performance. Multiphase operation with multiple LTM4613 devices in parallel will also lower the effective output ripple current due to the phase interleaving operation. Refer to Figure 4 for the normalized output ripple current versus the duty cycle. Figure 4 provides a ratio of peak-to-peak output ripple current to the inductor ripple current as functions of duty cycle and the number of paralleled phases. Pick the corresponding duty cycle and the number of phases to get the correct output ripple current value. For example, each

Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 19) Figure 4. Normalized Output Ripple Current vs Duty Cycle, ∆IL = VOT/LI

4612 F04

L at 5.0A equals 1.65A of output ripple current (∆IO). series resistance (ESR) of the output bulk capacitance. plished by using L TpowerCAD™. state operation, but also in response to transients. of its full current limit value. coincident output tracking characteristics. Figure 5. Coincident T racking Schematic Figure 6. Coincident Output T racking Characteristics

4613 F05

4613 F06

4613fdFor more information www.linear .com/L TM4613 APPLICATIONS INFORMATION Ratiometric tracking can be achieved by a few simple cal- culations and the slew rate value applied to the master’s TRACK/ SS pin. The TRACK/SS pin has a control range from 0 to 0.6V. The master’s TRACK/SS pin slew rate is directly equal to the master’s output slew rate in Volts/ Time. The equation: MR SR •100k =R2 where MR is the master’s output slew rate and SR is the slave’s output slew rate in Volts/Time. When coincident tracking is desired, then MR and SR are equal, thus R2 is equal to 100k. R1 is derived from equation: R1= 0.6V VFB 100k + VFB RFB – VTRACK where VFB is the feedback voltage reference of the regula- tor, and VTRACK is 0.6V. Since R2 is equal to the 100k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then R1 is equal to R FB with VFB = VTRACK. Therefore R2 = 100k, and R1 = 5.23k in Figure 5. In ratiometric tracking, a different slew rate maybe desired for the slave regulator. R2 can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach its final value before the master output. For example, MR = 1.5V/1ms, and SR = 1.2V/1ms. Then R2 = 125k. Solve for R1 to equal 5.18k. Each of the TRACK/SS pins will have the 1.5µA current source on when a resistive divider is used to implement tracking on that specific channel. This will impose an offset on the TRACK/SS pin input. Smaller values resistors with the same ratios as the resistor values calculated from the above equation can be used. For example, where the 100k is used then a 10k value can be used to reduce the TRACK/SS pin offset to a negligible value. RUN Enable The RUN pin is used to enable the power module. The pin has an internal 5.1V Zener to ground. The pin can be driven with 5V logic levels. The RUN pin can also be used as an undervoltage lockout (UVLO) function by connecting a resistor divider from the input supply to the RUN pin. The equation for UVLO threshold: VUVLO = RA +RB RB

• 1.5V where RA is the top resistor, and RB is the bottom resistor. Refer to Figure 1, Simplified Block Diagram. Power Good The PGOOD pin is an open-drain pin that can be used to monitor valid output voltage regulation. This pin monitors a ±10% window around the regulation point and tracks with margining. COMP Pin This pin is the external compensation pin. The module has already been internally compensated for most output voltages. L TpowerCAD is available for other control loop optimization. FCB Pin The FCB pin determines whether the bottom MOSFET remains on when current reverses in the inductor. Tying this pin above its 0.6V threshold enables discontinuous operation where the bottom MOSFET turns off when in - ductor current reverses. FCB pin below the 0.6V threshold forces continuous synchronous operation , allowing current to reverse at light loads and maintaining high frequency operation. PLLIN Pin The power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. This allows the internal top MOSFET turn-on to be locked to the rising edge of an external clock. The external clock frequency range must be within ±30% around the set operating frequency. A pulse detection circuit is used to detect a clock on the PLLIN pin to turn on the phase-locked loop. The pulse width of the clock has to be at least 400ns. The clock high level must be above 2V and clock low level below 0.3V. The PLLIN pin

the regulator, the phase-locked loop function is disabled. mended to connect the DRVCC pin to the external 5V rail. applications with low noise requirements . Figure 7. Radiated Emission Scan with 24VIN to

operating conditions to compliment any FEA activities. not relevant to providing guidance of thermal performance. to correlate thermal performance to one’s own application.

• θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo- sure. This environment is sometimes referred to as “still air ” although natural convection causes the air to move. This value is determined with the part mounted to a 95mm × 76mm PCB with 4 layers. θJCbottom , the thermal resistance from the junction to the bottom of the product case , is determined with all of the component power dissipation flowing through the bottom of the package . In the typical µModule regulator , the bulk of the heat flows out of the bottom of the package , but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages, but the test conditions do not generally match the user ’s application . θJCtop, the thermal resistance from the junction to the top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θ JCbottom, this value may be useful for comparing packages, but the test conditions do not generally match the user’s application. θJB, the thermal resistance from the junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule regulator and into the board. It is really the sum of the θ JCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package. A graphical representation of the aforementioned thermal resistances is given in Figure 8. Blue resistances are contained within the µModule package, whereas green resistances are external to the µModule package.

Figure 8. Graphical Representation of JESD51-12 Thermal Coefficients

4613 F08

4613fd For more information www.linear .com/L TM4613 As a practical matter, it should be clear to the reader that no individual or subgroup of the four thermal resistance parameters defined by JESD51-12, or provided in the Pin Configuration section, replicates or conveys normal operating conditions of a µModule regulator. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the package—as the standard defines for θ JCtop and θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package. Granted, in the absence of a heat sink and airflow, the majority of the heat flow is into the board. Within the LTM4613, be aware that there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplic - ity—but also, not ignoring practical realities —an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: 1. Initially, FEA software is used to accurately build the mechanical geometry of the LTM4613 and the specified PCB with all of the correct material coefficients, along with accurate power loss source definitions. 2. This model simulates a software-defined JEDEC envi- ronment consistent with JESD51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC- defined thermal resistance values. APPLICATIONS INFORMATION 3. The model and FEA software is used to evaluate the LTM4613 with heat sink and airflow. 4. Having solved for, and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled-environment chamber while operat- ing the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields the set of derating curves provided in this data sheet. The power loss curves in Figures 9 and 10 can be used in coordination with the load current derating curves in Figures 11 to 16 for calculating an approximate θ JA for the LTM4613. Each figure has three curves that are taken at three different airflow conditions. Graph designation delineates between no heat sink, and a BGA heat sink. Each of the load current derating curves will lower the maxi - mum load current as a function of the increased ambient temperature to keep the maximum junction temperature of the power module at 120° C maximum. This will main- tain the maximum operating temperature below 125°C. Table 3 provides the approximate θJA for Figures 11 to 16. A complete explanation of the thermal characteristics is provided in the thermal application note, AN110. Safety Considerations The LTM4613 does not provide galvanic isolation from V IN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure.

Figure 9. Power Loss at 12VOUT and 15VOUT Figure 10. Power Loss at 5VOUT Figure 11. No Heat Sink with 36VIN Figure 12. BGA Heat Sink with 36VIN to 5VOUT Figure 13. No Heat Sink Figure 14. BGA Heat Sink Figure 15. No Heat Sink with 36VIN to 15VOUT Figure 16. BGA Heat Sink with 36VIN to 15VOUT

4613 F09

4613 F10

4613 F11

4613 F12

4613 F13

4613 F14

4613 F15

4613 F16

Figure 18. Typical 22V to 36VIN, 12V at 8A Design

4613 F18

Figure 17. Recommended PCB Layout (LGA Shown, for BGA Use Circle Pads)

4613 F17

Figure 20. 26V to 36VIN, 15V at 5A Design with 600kHz Frequency

4613 F20

Figure 19. Typical 5V to 36VIN, 3.3V at 8A Design with 400kHz Frequency

4613 F19

4613 F21

Figure 21. 2-Phase, Parallel 12V at 16A Design with 600kHz Frequency

4613 F22

Figure 22. 2-Phase, 12V and 10V at 6A Design with 600kHz Frequency and Output Voltage T racking

4613 F23

Figure 23. 2-Phase, 5V and 3.3V at 8A Design with 500kHz Frequency and Output Voltage T racking

4613fd For more information www.linear .com/L TM4613 PIN NAME V IN VIN VIN VIN VIN V IN VIN VIN VIN VIN Pin Assignment Tables (Arranged by Pin Function) PIN NAME PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND G10 G11 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND H10 H11 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PIN NAME J10 J11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT K10 K11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT L10 L11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT M10 M11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT PIN NAME A10 A11 A12 V D INTVCC PLLIN TRACK/SS RUN COMP MPGM B10 B11 B12 V D VD RUN MPGM f SET C10 C11 C12 V D VD VD VD VD VD VD DRV CC MARG1 MARG0 D10 D11 D12 SGND COMP MARG1 E10 E11 E12 DRV CC DRVCC F10 F11 F12 V FB G12 PGOOD H12 SGND J12 NC K12 NC L12 NC M12 FCB PACKAGE DESCRIPTION

4613fdFor more information www.linear .com/L TM4613 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTM4613#packaging for the most recent package drawings. DETAIL B DETAIL B SUBSTRATEMOLD CAP // bbb Z Z A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 133 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW PAD “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW DETAIL A F G H L M J K E A B C D 2 14 312 11 9 510 6 7 8 D 0.630 ±0.025 Ø 133x E b e e b F G LGA 133 1212 REV A TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” SYMBOL A b D E e F G aaa bbb eee MIN 4.22 0.60 0.27 3.95 NOM 4.32 0.63 15.0 15.0 1.27 13.97 13.97 0.32 4.00 MAX 4.42 0.66 0.37 4.05 0.15 0.10 0.05 NOTES DIMENSIONS TOTAL NUMBER OF LGA PADS: 133 L TMXXXXXX µModule DETAIL A 0.630 ±0.025 SQ. 133x S Y X eee C(0.30) PAD 1 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 133-Lead (15mm × 15mm × 4.32mm) (Reference LTC DWG # 05-08-1884 Rev A)

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES

4613fd For more information www.linear .com/L TM4613 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTM4613#packaging for the most recent package drawings. PIN “A1” CORNER NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW BGA 133 1114 REV Ø L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” DETAIL A PIN 1 0.0000 0.0000 DETAIL A Øb (133 PLACES) D A DETAIL B PACKAGE SIDE VIEW Z M X Y Z ddd M Z eee 0.630 ±0.025 Ø 133x SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 4.72 0.50 4.22 0.60 0.60 NOM 4.92 0.60 4.32 0.75 0.63 15.0 15.0 1.27 13.97 13.97 0.32 4.00 MAX 5.12 0.70 4.42 0.90 0.66 0.37 4.05 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 133 E b e e b F G 133-Lead (15mm × 15mm × 4.92mm) (Reference LTC DWG # 05-08-1992 Rev Ø) 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 6.9850 G F E A B D C H M L K J 2 14 35 6 712 8 9 10 11 AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTES 0.27 3.95 DETAIL B SUBSTRATE ccc Z MOLD CAP // bbb Z Z

4613fdFor more information www.linear .com/L TM4613 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 06/15 Added BGA Package 2, 28 B 09/15 Added LTM4613IY (SnPb) 2 C 07/16 Added MP-Grade 2 D 09/16 Changed Max value of V INTVCC of 5.3 to 5.5 3

4613fd For more information www.linear .com/L TM4613 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2011 LT 0916 REV D • PRINTED IN USA (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L TM4613 RELATED PARTS PACKAGE PHOTOGRAPH PART NUMBER DESCRIPTION COMMENTS LTM4612 Lower IOUT Than LTM4613, EN55022B Compliant, 36VIN, 5A µModule Regulator 5V ≤ VIN ≤ 36V, 3.3V ≤ VOUT ≤ 15V, 15mm × 15mm × 2.82mm (LGA) LTM4606 EN55022B Compliant, 28VIN, 6A µModule Regulator 4.5V ≤ V IN ≤ 28V, 0.5V ≤ VOUT ≤ 5V, 15mm × 15mm × 2.82mm (LGA), 15mm × 15mm × 3.42mm (BGA) LTM8031 EN55022B Compliant, 36VIN, 1A µModule Regulator 3.6V ≤ V IN ≤ 36V, 0.8V ≤ VOUT ≤ 10V, 9mm × 15mm × 2.82mm (LGA), 9mm × 15mm × 3.42mm (BGA) LTM8032 EN55022B Compliant, 36VIN, 2A µModule Regulator 3.6V ≤ V IN ≤ 36V, 0.8V ≤ VOUT ≤ 10V, 9mm × 15mm × 2.82mm (LGA), 9mm × 15mm × 3.42mm (BGA) LTM8033 EN55022B Compliant, 36VIN, 3A µModule Regulator 3.6V ≤ V IN ≤ 36V, 0.8V ≤ VOUT ≤ 24V, 11.25mm × 15mm × 4.32mm (LGA), 11.25mm × 15mm × 4.92mm (BGA) LTM8028 Low Output Noise, 36VIN, 5A µModule Regulator 6V ≤ V IN ≤ 36V, 0.8V ≤ VOUT ≤ 1.8V, 15mm × 15mm × 4.92mm (BGA) LTM4601AHV 28VIN, 12A µModule Regulator with PLL, T racking and Margining 4.5V VIN 28V, 0.6V VOUT 5V, 15mm × 15mm × 2.82mm (LGA), 15mm × 15mm × 3.42mm (BGA) LTM4641 38VIN, 10A µModule Regulator with Input and Load Protection 4.5V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 6V, 15mm × 15mm × 5.01mm (BGA) LTM8003 FMEA Compliant Pinout, 150°C Operation, 40VIN, 3.5A µModule Regulator 3.4V ≤ VIN ≤ 40V, 0.97V ≤ VOUT ≤ 18V, 6.25mm × 9mm × 3.32mm (BGA) LTM8053 40VIN, 3.5A µModule Regulator in 6.25mm × 9mm BGA Package 3.4V ≤ VIN ≤ 40V, 0.97V ≤ VOUT ≤ 15V, 6.25mm × 9mm × 3.32mm (BGA) DESIGN RESOURCES SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design:

• Selector Guides
• Demo Boards and Gerber Files
• Free Simulation Tools Manufacturing:
• Quick Start Guide
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability µModule Regulator Products Sear ch 1. Sort table of products by parameters and download the result as a spread sheet. 2. Search using the Quick Power Search parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging.