LTM4606 LINER | Alldatasheet
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FREQUENCY (MHz) FIELD STRENGTH (dBμV/m) 100 500 900300 700
4606 TA01b
CISPR.22, CLASS B, 3 METERS n ASICs or FPGA T ransceivers n Telecom, Servers and Networking Equipment n Industrial Equipment n Rf Equipment PGOOD RUN COMP INTV CC DRVCC fSET TRACK/SS V D FCB MARG0 MARG1 MPGM V OUT VFB VIN TRACK/SS CONTROL 47pF COUT 2.5V AT 6A CIN 10μF 35V CERAMIC 4.5V TO 28V PLLIN CLOCK SYNC ON/OFF L TM4606 SGND PGND MARGIN CONTROL RFB 19.1k 392k 5% MARGIN
4606 TA01
10μF 35V TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Ultralow EMI 28VIN, 6A DC/DC µModule The L TM®4606 is a complete ultralow noise high voltage 6A switching mode DC/DC power supply. Included in the package are the switching controller , power FETs, inductor , and all support components. The on-board input fi lter and noise cancellation circuits achieve low noise operation, thus effectively reducing the electromagnetic interference (EMI). Operating over an input voltage range of 4.5V to 28V , the L TM4606 supports an output voltage range of 0.6V to 5V , set by a single resistor . This high effi ciency design deliv- ers 6A continuous current (8A peak). Only bulk input and output capacitors are needed to fi nish the design. High switching frequency and an adaptive on-time current mode architecture enables a very fast transient response to line and load changes without sacrifi cing stability. The device supports output voltage tracking and output volt- age margining. Furthermore, the μModule™ can be synchronized with an external clock for reducing undesirable frequency harmonics and allows PolyPhase ® operation for high load currents. The L TM4606 is offered in a space saving and thermally enhanced 15mm × 15mm × 2.8mm LGA package, which enables utilization of unused space on the bottom of PC boards for high density point of load regulation. The L TM4606 is Pb-free and RoHS compliant. Ultralow Noise 2.5V/6A Power Supply with 4.5V to 28V Input n Complete Low EMI Switch Mode Power Supply n Wide Input Voltage Range: 4.5V to 28V n 6A DC Typical, 8A Peak Output Current n 0.6V to 5V Output Voltage Range n Low Input and Output Referred Noise n Output Voltage T racking and Margining n PLL Frequency Synchronization n ±1.5% Total DC Error n Power Good Output n Current Foldback Protection (Disabled at Start-Up) n Parallel/Current Sharing n Ultrafast T ransient Response n Current Mode Control n Up to 93% Effi ciency at 5VIN, 3.3VOUT n Programmable Soft-Start n Output Overvoltage Protection n –55°C to 125°C Operating Temperature Range (L TM4606MPV) n Small Surface Mount Footprint, Low Profi le Package (15mm × 15mm × 2.8mm) Radiated Emission Scan at 12VIN, 2.5VOUT/6A L, L T , L TC, L TM and PolyPhase are registered trademarks of Linear Technology Corporation. μModule is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS PLLIN, FCB, TRACK/SS, MPGM, MARG0, Internal Operating Temperature Range (Note 2) (Note 1) LGA PACKAGE 133-LEAD (15mm × 15mm × 2.8mm) TOP VIEWMARG1 DRVCC VFB PGOOD SGND NC NC NC FCB VIN BANK 1 VD PGND BANK 2 VOUT BANK 3 fSET MARG0 RUN COMP MPGM PLLIN INTVCC TRACK/SS SGND L K J H G F E D CBMA TJMAX = 125°C, θJA = 15°C/W , θJC = 6°C/W θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS WEIGHT = 1.7g ORDER INFORMATION LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TM4606EV#PBF L TM4606EV#PBF L TM4606V 133-Lead (15mm × 15mm × 2.8mm) LGA –40°C to 125°C L TM4606IV#PBF L TM4606IV#PBF L TM4606V 133-Lead (15mm × 15mm × 2.8mm) LGA –40°C to 125°C L TM4606MPV#PBF L TM4606MPV#PBF L TM4606MPV 133-Lead (15mm × 15mm × 2.8mm) LGA –55°C to 125°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container . Consult L TC Marketing for information on non-standard lead based fi nish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://linear .com/packaging/
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN(DC) Input DC Voltage l 4.5 28 V VOUT(DC) Output Voltage, Total Variation with Line and Load CIN = 10μF x2, COUT = 200μF; FCB = 0 VIN = 5V to 28V , IOUT = 0A to 6A, (Note 4) l 1.478 1.5 1.522 V Input Specifi cations VIN(UVLO) Undervoltage Lockout Threshold I OUT = 0A 3.2 4 V IINRUSH(VIN) Input Inrush Current at Start-Up I OUT = 0A, CIN = 10μF x2, COUT = 200μF , VOUT = 1.5V V IN = 5V V IN = 12V 0.6 0.7 A A The l denotes the specifi cations which apply over the full internal operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 12V , unless otherwise noted. Per typical application (front page) confi guration, RFB = 40.2k.
ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full internal operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 12V , unless otherwise noted. Per typical application (front page) confi guration, RFB = 40.2k. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IQ(VIN) Input Supply Bias Current V IN = 5V , No Switching VIN = 5V , VOUT = 1.5V , Switching Continuous VIN = 12V , No Switching VIN = 12V , VOUT = 1.5V , Switching Continuous Shutdown, RUN = 0, VIN = 12V 1.5 2.5 mA mA mA mA μA I S(VIN) Input Supply Current VIN = 12V , VOUT = 1.5V , IOUT = 6A VIN = 5V , VOUT = 1.5V , IOUT = 6A 0.96 2.18 A A INTVCC VIN = 12V , RUN > 2V No Load 4.7 5 5.3 V Output Specifi cations I OUT(DC) Output Continuous Current Range V IN = 12V , VOUT = 1.5V (Note 4) 0 6 A ΔVOUT(LINE)/VOUT Line Regulation Accuracy V OUT = 1.5V , FCB = 0V , VIN = 4.5V to 28V , IOUT = 0A l 0.05 0.3 % ΔVOUT(LOAD)/VOUT Load Regulation Accuracy V OUT = 1.5V , FCB = 0V , IOUT = 0A to 6A V IN = 12V (Note 4) l 0.3 % VIN(AC) Input Ripple Voltage I OUT = 0A, CIN = 10μF X5R Ceramic x3 and 100μF Electrolytic V IN = 5V , VOUT = 1.5V V IN = 12V , VOUT = 1.5V mVP-P mVP-P VOUT(AC) Output Ripple Voltage I OUT = 0A, COUT = 22μF X5R Ceramic x3 and 100μF X5R Ceramic V IN = 5V , VOUT = 1.5V V IN = 12V , VOUT = 1.5V mVP-P mVP-P fS Output Ripple Voltage Frequency I OUT = 5A, VIN = 12V , VOUT = 1.5V 900 kHz ΔVOUT(START) Turn-On Overshoot, TRACK/SS = 10nF COUT = 200μF , VOUT = 1.5V , IOUT = 0A V IN = 12V V IN = 5V mV mV tSTART Turn-On Time, TRACK/SS = Open C OUT = 200μF; VOUT = 1.5V , IOUT = 1A Resistive Load V IN = 5V V IN = 12V 0.5 0.5 ms ms ΔVOUT(LS) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load COUT = 22μF Ceramic, 470μF x2 V IN = 12V V OUT = 1.5V 35 mV tSETTLE Settling Time for Dynamic Load Step VIN = 12V Load: 0% to 50% to 0% of Full Load, VIN = 12V 25 μs IOUT(PK) Output Current Limit C OUT = 200μF V IN = 5V , VOUT = 1.5V V IN = 12V , VOUT = 1.5V A A Control Section VFB Voltage at VFB Pin I OUT = 0A, VOUT = 1.5V l 0.594 0.6 0.606 V VRUN RUN Pin On/Off Threshold 1 1.5 1.9 V ISS / TRACK Soft-Start Charging Current V SS/TRACK = 0V –1 –1.5 –2 μA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TM4606E is guaranteed to meet performance specifi cations over the 0°C to 125°C internal operating temperature range. Specifi cations over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The L TM4606I is guaranteed to meet specifi cations over the SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VFCB Forced Continuous Threshold 0.57 0.6 0.63 V IFCB Forced Continuous Pin Current V FCB = 0V –1 –2 μA tON(MIN) Minimum On Time (Note 3) 50 100 ns tOFF(MIN) Minimum Off Time (Note 3) 250 400 ns RPLLIN PLLIN Input Resistor 50 kΩ IDRVCC Current into DRVCC Pin V OUT = 1.5V , IOUT = 1A 15 25 mA RFBHI Resistor Between VOUT and VFB Pins 60.098 60.4 60.702 kΩ RUNMAX Volts From RUN to GND Maximum 5.1V Zener Clamp 5 V Margin Section MPGM Margin Reference Voltage Sets a Current 1.18 V MARG0, MARG1 Voltage Thresholds 1.4 V PGOOD ΔV FBH PGOOD Upper Threshold V FB Rising 7 10 13 % ΔVFBL PGOOD Lower Threshold V FB Falling –7 –10 –13 % ΔVFB(HYS) PGOOD Hysteresis V FB Returning 1.5 % VPGL PGOOD Low Voltage I PGOOD = 5mA 0.15 0.4 V ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full internal operating temperature range, otherwise specifi cations are at TA = 25°C. VIN = 12V , unless otherwise noted. Per typical application (front page) confi guration, RFB = 40.2k. –40°C to 125°C internal operating temperature range. The L TM4606MP is guaranteed and tested over the –55°C to 125°C internal operating temperature range. Note that the maximum ambient temperature is determined by specifi c operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: 100% tested at die level only. Note 4: See output current derating curves for different V IN, VOUT and TA.
TYPICAL PERFORMANCE CHARACTERISTICS Effi ciency vs Load Current with 5VIN (FCB = 0) Effi ciency vs Load Current with 12VIN (FCB = 0) Effi ciency vs Load Current with 24VIN (FCB = 0) 1.2V T ransient Response 1.5V T ransient Response 1.8V T ransient Response 2.5V T ransient Response 3.3V T ransient Response –55°C, Start-Up, I OUT = 0A
4606 G05
50μs/DIV 1.5V AT 3.5A/μs LOAD STEP COUT = 2x 22μF , 10V CERAMIC 1x 100μF , 6.3V CERAMIC IOUT 2A/DIV VOUT 50mV/DIV
4606 G04
50μs/DIV 1.2V AT 3.5A/μs LOAD STEP COUT = 2x 22μF , 10V CERAMIC 1x 100μF , 6.3V CERAMIC IOUT 2A/DIV VOUT 50mV/DIV
4606 G06
50μs/DIV 1.8V AT 3.5A/μs LOAD STEP COUT = 2x 22μF , 10V CERAMIC 1x 100μF , 6.3V CERAMIC IOUT 2A/DIV VOUT 50mV/DIV
4606 G07
50μs/DIV 2.5V AT 3.5A/μs LOAD STEP COUT = 2x 22μF , 10V CERAMIC 1x 100μF , 6.3V CERAMIC IOUT 2A/DIV VOUT 50mV/DIV
4606 G08
50μs/DIV 3.3V AT 3.5A/μs LOAD STEP COUT = 2x 22μF , 10V CERAMIC 1x 100μF , 6.3V CERAMIC IOUT 2A/DIV VOUT 100mV/DIV LOAD CURRENT (A) EFFICIENCY (%) 100
4606 G01
0.6VOUT 1.2VOUT 1.8VOUT 2.5VOUT 3.3VOUT LOAD CURRENT (A) EFFICIENCY (%) 100
4606 G02
1.2VOUT 1.5VOUT 2.5VOUT 3.3VOUT 5VOUT LOAD CURRENT (A) EFFICIENCY (%) 100
4606 G03
2.5VOUT 3.3VOUT 5VOUT VOUT 0.5V/DIV IIN 0.5A/DIV 1ms/DIV
4606 G16
VIN = 12V VOUT = 1.5V COUT = 2x 22μF , 10V CERAMIC 1x 100μF , 6.3V CERAMIC SOFT-START = 3.9nF
0.5V/DIV IIN 0.5A/DIV 1ms/DIV
4606 G10
VIN = 12V VOUT = 1.5V COUT = 1x 22μF , 6.3V CERAMIC 1x 330μF , 4V SANYO POSCAP SOFT-START = 3.9nF TYPICAL PERFORMANCE CHARACTERISTICS Start-Up, IOUT = 6A (Resistive Load) Short-Circuit Protection, IOUT = 0A Short-Circuit Protection, IOUT = 6A VIN to VOUT Step-Down Operation Region Input Ripple Output Ripple VOUT 2V/DIV IIN 0.2A/DIV 50μs/DIV
4606 G11
VIN = 12V VOUT = 2.5V COUT = 2x 22μF , 10V CERAMIC 1x 100μF , 6.3V CERAMIC SOFT-START = 0.1μF VOUT 1V/DIV IIN 2A/DIV 50μs/DIV
4606 G12
VIN = 12V VOUT = 2.5V COUT = 2x 22μF , 10V CERAMIC 1x 100μF , 6.3V CERAMIC SOFT-START = 0.1μF VIN 10mV/DIV 2μs/DIV
4606 G14
VIN = 5V VOUT = 1V AT 6A CIN = 3x 10μF , 25V CERAMIC 1x 150μF BULK BW = 300MHz VOUT 2mV/DIV 2μs/DIV
4606 G15
VIN = 5V VOUT = 1V AT 6A COUT = 2x 22μF , 6.3V CERAMIC 1x 100μF , 6.3V CERAMIC BW = 300MHz VOUT (V) 0.6 VIN (V) 4.5 2.5 4.51.5 3.5
4606 G13
SEE FREQUENCY ADJUSTMENT SECTION FOR OPERATIONS OUTSIDE THIS REGION OPERATION REGION WITH DEFAUL T FREQUENCY Start-Up, IOUT = 0A VOUT 0.5V/DIV IIN 0.5A/DIV 1ms/DIV
4606 G09
VIN = 12V VOUT = 1.5V COUT = 1x 22μF , 6.3V CERAMIC 1x 330μF , 4V SANYO POSCAP SOFT-START = 3.9nF –55°C, Start-Up, IOUT = 6A VOUT 0.5V/DIV IIN 0.5A/DIV 1ms/DIV
4606 G17
VIN = 12V VOUT = 1.5V COUT = 2x 22μF , 10V CERAMIC 1x 100μF , 6.3V CERAMIC SOFT-START = 3.9nF VFB vs Temperature TEMPERATURE (°C) –55 0.594 0.596 0.598 VFB (V) 5–25
4606 G18
0.606 0.604 0.602 0.600 125956535
VIN (Bank 1): Power Input Pins. Apply input voltage be- tween these pins and PGND pins. Recommend placing input decoupling capacitance directly between V IN pins and PGND pins. VOUT (Bank 3): Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and PGND pins (see fi gure below). PGND (Bank 2): Power Ground Pins for Both Input and Output Returns. V D (Pins B7 , C7): Top FET Drain Pins. Add more capacitors between VD and ground to handle the input RMS current and reduce the input ripple further . DRVCC (Pins C10, E11, E12): These pins normally connect to INTVCC for powering the internal MOSFET drivers. They can be biased up to 6V from an external supply with about 50mA capability, or an external circuit as shown in Figure 18. This improves effi ciency at the higher input voltages by reducing power dissipation in the modules. INTV CC (Pin A7): This pin is for additional decoupling of the 5V internal regulator . PLLIN (Pin A8): External Clock Synchronization Input to the Phase Detector . This pin is internally terminated to SGND with a 50k resistor . Apply a clock above 2V and below INTV CC. See the Applications Information section. FCB (Pin M12): Forced Continuous Input. Connect this pin to SGND to force continuous synchronization operation at low load, to INTVCC to enable discontinuous mode opera- tion at low load or to a resistive divider from a secondary output when using a secondary winding. TRACK/SS (Pin A9): Output Voltage T racking and Soft-Start Pin. When the module is confi gured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. A soft-start capacitor can be used for soft-start turn-on as a standalone regulator . Slave operation is performed by putting a resistor divider from the master output to ground, and connecting the center point of the divider to this pin. See the Applications Information section. MPGM (Pins A12, B11): Programmable Margining Input. A resistor from these pins to ground sets a current that is equal to 1.18V/R. This current multiplied by 10kΩ will equal a value in millivolts that is a percentage of the 0.6V reference voltage. See the Applications Information section. To parallel L TM4606s, each requires an individual MPGM resistor . Do not tie MPGM pins together . f SET (Pin B12): Frequency set internally to 800kHz. An external resistor can be placed from this pin to ground to increase frequency. This pin can be decoupled with a 1000pF capacitor . See the Applications Information section for frequency adjustment. V FB (Pin F12): The Negative Input of the Error Amplifi er . Internally, this pin is connected to VOUT with a 60.4k preci- sion resistor . Different output voltages can be programmed with an additional resistor between the V FB and SGND pins. See the Applications Information section. MARG0 (Pin C12): LSB Logic Input for the Margining Function. Together with the MARG1 pin, the MARG0 pin will determine if a margin high, margin low, or no margin state is applied. The pin has an internal pulldown resistor of 50k. See the Applications Information section. MARG1 (Pins C11, D12): MSB Logic Input for the Margin- ing Function. Together with the MARG0 pin, the MARG1 pins will determine if a margin high, margin low, or no margin state is applied. The pins have an internal pulldown resistor of 50k. See the Applications Information section. SGND (Pins D9, H12): Signal Ground Pins. These pins connect to PGND at output capacitor point. TOP VIEWMARG1 DRVCC VFB PGOOD SGND NC NC NC FCB VIN BANK 1 VD PGND BANK 2 VOUT BANK 3 fSET MARG0 RUN COMP MPGM PLLIN INTVCC TRACK/SS SGND LKJHGFEDCBMA
sense voltage (zero current). PGOOD (Pin G12): Output Voltage Power Good Indicator . after a 25μs power bad mask timer expires. 5.1V zener to ground. Maximum pin voltage is 5V . TA = 25°C. Use Figure 1 confi guration.
4606 F01
Figure 1. Simplifi ed Block Diagram
The L TM4606 is a standalone non-isolated switching mode DC/DC power supply. It can deliver up to 6A of DC output current with some external input and output capacitors. This module provides precisely regulated output voltage programmable via one external resistor from 0.6V DC to 5.0VDC over a 4.5V to 28V input voltage range. The typical application schematic is shown in Figure 20. The L TM4606 has an integrated constant on-time current mode regulator , ultralow RDS(ON) FETs with fast switching speed and integrated Schottky diodes. The typical switch- ing frequency is 800kHz. With current mode control and internal feedback loop compensation, the L TM4606 module has suffi cient stability margins and good transient per- formance under a wide range of operating conditions and with a wide range of output capacitors, even all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limiting. Besides, foldback current limiting is provided in an overcurrent condition while V FB drops. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. Furthermore, in an overvoltage condition, internal top FET M1 is turned off and bottom FET M2 is turned on and held on until the overvoltage condition clears. Input fi lter and noise cancellation circuits reduce the noise coupling to I/O sides, and ensure the electromagnetic interference (EMI) to meet the limits of CISPR 22 and CISPR 25. Pulling the RUN pin below 1V forces the controller into its shutdown state, turning off both M1 and M2. At low load currents, discontinuous mode (DCM) operation can be enabled to achieve higher effi ciency compared to continuous mode (CCM) by setting the FCB pin higher than 0.6V . When the DRV CC pin is connected to INTVCC an integrated 5V linear regulator powers the internal gate drivers. If a 5V external bias supply is applied on the DRV CC pin, then an effi ciency improvement will occur due to the reduced power loss in the internal linear regulator . This is especially true at the higher input voltage range. The MPGM, MARG0, and MARG1 pins are used to sup- port voltage margining, where the percentage of margin is programmed by the MPGM pin, and the MARG0 and MARG1 selected margining. The PLLIN pin provides fre- quency synchronization of the device to an external clock. The TRACK/SS pin is used for power supply tracking and soft-start programming.
Figure 20. External component selection is primarily requirements for a particular application. down ratio that can be achieved for a given input voltage. section in this data sheet for the current restrictions. The PWM controller has an internal 0.6V reference voltage. Table 1. RFB Standard 1% Resistor Values vs VOUT RPGM resistor on the MPGM pin programs the current. The output margining will be ± margining of the value. is needed for capacitor C1 selection.
Figure 2. Conducted Emission Scan with 12VIN to 2.5VOUT at 6A catalog for the RMS current ratings. be placed close to the connection into the system board. different conducted EMI limits. to maximize transient performance. series resistance (ESR) of the output bulk capacitance. in steady-state operation, but also in transient. of its full current limit value.
4606 F02
The L TM4606 is designed for low output voltage ripples.
the ramp of the internal reference and the output voltage. so that another regulator can be easily tracked to it.
4612 F05
Figure 3. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI Figure 4. Output Voltage Coincident T racking
4606 F04
to reverse at light loads and maintain low output ripple. internal voltage controlled oscillator and a phase detector . the regulator , the phase-lock loop function is disabled. pin with an external circuit as shown in Figure 18. N is the number of paralleled modules. Figure 5. Coincident T racking Characteristics
4606 F05
driven with a logic input not to exceed 5V . top resistor of the divider . provided for other control loop optimization.
tion temperature of the power module at 125°C maximum. Figure 9. BGA Heat Sink Figure 10. No Heat Sink Figure 11. BGA Heat Sink
4606 F06
4606 F07
4606 F08
0 MAXIMUM LOAD CURRENT (A)1
4606 F09
4606 F10
4606 F11
Figure 12. No Heat Sink Figure 13. BGA Heat Sink
4606 F12
4606 F13
Figure 15. BGA Heat Sink Figure 14. No Heat Sink
4606 F14
provided to protect each unit from catastrophic failure. meet the Class B of CISPR 22 radiated emission limit. Figure 16. Radiated Emission Scan with 12VIN to 2.5VOUT at 6A.
4606 F16
Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 20)
siderations are still necessary.
- Use large PCB copper areas for high current path, in- cluding V IN, PGND and VOUT. It helps to minimize the PCB conduction loss and thermal stress.
- Place high frequency ceramic input and output capaci- tors next to the VD, PGND and VOUT pins to minimize high frequency noise.
- Place a dedicated power ground layer underneath the unit.
- Use round corners for the PCB copper layer to minimize the radiated noise.
- To minimize the EMI noise and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers on different locations.
- Do not put vias directly on pads, unless they are capped.
- Use a separated SGND ground copper area for com- ponents connected to signal pins. Connect the SGND to PGND underneath the unit.
- Place one or more high frequency ceramic capacitors close to the connection into the system board. Figure 17 gives a good example of the recommended layout. For load current below 3A, decouple the input and output grounds. Use vias to connect GND pads to the bottom layer , then connect to the right side of the module as the output GND.
Figure 17. Recommended PCB Layout
4606 F17
Table 4. 3.3V Output Table 3. 1.5V Output
The L TM4606 is designed to typically operate at 800kHz across most input conditions. The fSET pin is typically left open or decoupled with an optional 1000pF capacitor . The switching frequency has been optimized for maintaining constant output ripple noise over most operating ranges. The 800kHz switching frequency and the 400ns minimum off time can limit operation at higher duty cycles like 5V to 3.3V , and produce excessive inductor ripple currents for lower duty cycle applications like 28V to 5V . Example for 5V Output L TM4606 minimum on-time = 100ns; t ON = ((4.8 • 10pf)/IfSET) L TM4606 minimum off-time = 400ns; t OFF = t – tON, where t = 1/Frequency Duty Cycle = t ON/t or VOUT/VIN Equations for setting frequency: I fSET = (VIN/(3 • RfSET)), where the internal RfSET is 41.2k. For 28V input operation, IfSET = 227μA. tON = ((4.8 • 10pF)/ IfSET), tON = 211ns. Frequency = (VOUT/(VIN • tON)) = (5V/(28
- 211ns)) ~ 850kHz. The inductor ripple current begins to get high at the higher input voltages due to a larger voltage across the inductor . The current ripple is ~5A at 20% duty cycle if the integrated inductor is 1μH. The inductor ripple current can be lowered at the higher input voltages by add- ing an external resistor from f SET to ground to increase the switching frequency. A 4A ripple current is chosen, and the total peak current is equal to 1/2 of the 4A ripple current plus the output current. For 5V output, current is limited to 5A, so the total peak current is less than 7A. This is below the 8A peak specifi ed value. A 150k resistor is placed from f SET to ground, and the parallel combination of 150k and 41.2k equates to 32.3k. The I fSET calculation with 32.3k and 28V input voltage equals 289μA. This equates to a tON of 166ns. This will increase the switching frequency from 850kHz to ~1MHz for the 28V to 5V conversion. The minimum on time is above 100ns at 28V input. Since the switching frequency is approximately constant over input and output conditions, then the lower input voltage range is limited to 8V for the 1MHz operation due to the 400ns minimum off time. Equation: t ON = (VOUT/VIN) • (1/Frequency) equates to a 375ns on time, and a 400ns off time. Figure 18 shows an operating range of 10V to 28V for 1MHz operation with a 150k resistor to ground, and an 8V to 16V operating range for f SET fl oating. These modifi cations are made to provide wider input voltage ranges for the 5V output designs while limiting the inductor ripple current, and maintaining the 400ns minimum off time. Example for 3.3V Output L TM4606 minimum on-time = 100ns; t ON = ((3.3 • 10pF)/IfSET) L TM4606 minimum off-time = 400ns; t OFF = t – tON, where t = 1/Frequency Duty Cycle (DC) = t ON/t or VOUT/VIN Equations for setting frequency: I fSET = (VIN/(3 • RfSET)), for 28V input operation, I fSET = 227μA, tON = ((3.3 • 10pf)/IfSET), tON = 145ns, where the internal RfSET is 41.2k. Frequency = (V OUT/(VIN • tON)) = (3.3V/(28 • 145ns)) ~ 810kHz. The minimum on-time and minimum-off time are within specifi cation at 146ns and 1089ns. But the 4.5V minimum input for converting 3.3V output will not meet the minimum off-time specifi cation of 400ns. t ON = 905ns, Frequency = 810kHz, tOFF = 329ns. Solution Lower the switching frequency at lower input voltages to allow for higher duty cycles, and meet the 400ns mini- mum off-time at 4.5V input voltage. The off-time should be about 500ns with 100ns guard band. The duty cycle for (3.3V/4.5V) = ~73%. Frequency = (1 – DC)/t OFF or (1 – 0.73)/500ns = 540kHz. The switching frequency needs to be lowered to 540kHz at 4.5V input. t ON = DC/ frequency, or 1.35μs. The f SET pin voltage compliance is 1/3 of VIN, and the IfSET current equates to 36μA with the internal 41.2k. The IfSET current needs to be 24μA for 540kHz operation. A resistor can be placed from VOUT to fSET to lower the effective IfSET current out of the fSET pin to 24μA. The f SET pin is 4.5V/3 =1.5V and V OUT = 3.3V , therefore an 150k resistor will source 12μA into the fSET node and lower the IfSET current to 24μA. This enables the 540kHz operation and the 4.5V to 28V input operation for down converting to 3.3V output as shown in Figure 19. The frequency will scale from 540kHz to 950kHz over this input range. This provides for an effective output current of 5A over the input range.
Figure 19. 3.3V at 5A Design Figure 18. 10V to 28VIN, 5V at 5A Design
4606 TA03
4606 TA02
4606 TA05
Figure 21. 2-Phase, Parallel 2.5V at 12A Design Figure 20. Typical 4.5V to 28VIN, 2.5V at 6A Design
4606 TA04
4606 TA06
4606 TA07
Figure 22. 2-Phase, 3.3V and 2.5V Outputs at 6A with T racking and Margining Figure 23. 2-Phase, 1.8V and 1.5V Outputs at 6A with T racking and Margining
V IN VIN VIN VIN VIN VIN V IN VIN VIN VIN VIN VIN V IN VIN VIN VIN VIN VIN Pin Assignment Tables (Arranged by Pin Function) PIN NAME PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND G10 G11 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND H10 H11 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PIN NAME J10 J11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT K10 K11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT L10 L11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT M10 M11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT PIN NAME A10 A11 A12 INTV CC PLLIN TRACK/SS RUN COMP MPGM B10 B11 B12 V D RUN MPGM f SET C10 C11 C12 V D DRV CC MARG1 MARG0 D10 D11 D12 SGND COMP MARG1 E10 E11 E12 DRV CC DRVCC F10 F11 F12 V FB G12 PGOOD H12 SGND J12 NC K12 NC L12 NC M12 FCB PACKAGE DESCRIPTION
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION LKJHGFEDCBMA NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 133 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE SYMBOL aaa bbb eee TOLERANCE 0.10 0.10 0.05 2.72 – 2.92 DETAIL B DETAIL B SUBSTRATE MOLD CAP 0.27 – 0.37 2.45 – 2.55 bbb Z Z BSC PACKAGE TOP VIEW BSC PAD 1 CORNER X Y aaa Z aaa Z DETAIL A 13.97 BSC 1.27 BSC 13.97 BSC 0.12 – 0.28 PACKAGE BOTTOM VIEW C(0.30) PAD 1 PADS SEE NOTES DETAIL A 0.630 ±0.025 SQ. 133x S YXeee SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 LGA 133 1107 REV Ø L TMXXXXXX μModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” 133-Lead (15mm × 15mm × 2.82mm) (Reference L TC DWG # 05-08-1766 Rev Ø)
Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com © LINEAR TECHNOLOGY CORPORATION 2008 LT 0708 • PRINTED IN USA RELATED PARTS PACKAGE PHOTOGRAPH PART NUMBER DESCRIPTION COMMENTS L TC2900 Quad Supply Monitor with Adjustable Reset Timer Monitors Four Supplies; Adjustable Reset Timer L TM4600 10A DC/DC μModule Basic 10A DC/DC μModule, LGA Package L TM4600HVMP Military Plastic 10A DC/DC μModule Guaranteed Operation from –55°C to 125°C Ambient, LGA Package L TM4601/ L TM4601A 12A DC/DC μModule with PLL, Output T racking/ Margining and Remote Sensing Synchronizable, PolyPhase Operation, L TM4601-1/L TM4601A-1 Version has no Remote Sensing, LGA Package L TM4602 6A DC/DC μModule Pin Compatible with the L TM4600, LGA Package L TM4603 6A DC/DC μModule with PLL and Outpupt T racking/ Margining and Remote Sensing Synchronizable, PolyPhase Operation, L TM4603-1 Version has no Remote Sensing, Pin Compatible with the L TM4601, LGA Package L TM4604/ L TM4604A Low V IN 4A DC/DC μModule 2.375V ≤ VIN ≤ 5.5V , 0.8V ≤ VOUT ≤ 5V , 9mm × 15mm × 2.3mm LGA Package L TM4608/ L TM4608A Low VIN 8A DC/DC μModule 2.375V ≤ VIN ≤ 5.5V; 0.6V ≤ VOUT ≤ 5V; 9mm × 15mm × 2.8mm LGA Package L TM4612 Low Noise 4.5A, 15V OUT DC/DC μModule Low Noise, with PLL, Output T racking and Margining, L TM4606 Pin-Compatible L TM8022/L TM8023 36VIN, 1A and 2A DC/DC μModule Pin Compatible; 4.5V ≤ VIN ≤ 36V; 9mm × 11.25mm × 2.8mm LGA Package