LTM4605

LTC3789 LINER | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 28

Technical content

FeaTures

applicaTions

DescripTion

ficiency, Synchronous, 4-Switch Buck-Boost Controller The L TC®3789 is a high performance buck-boost switch- ing regulator controller that operates from input volt- ages above, below or equal to the output voltage. The constant-frequency, current mode architecture allows a phase-lockable frequency of up to 600kHz, while an output current feedback loop provides support for battery charg- ing. With a wide 4V to 38V (40V maximum) input and output range and seamless, low noise transitions between operating regions, the L TC3789 is ideal for automotive, telecom and battery-powered systems. The operating mode of the controller is determined through the MODE/PLLIN pin. The MODE/PLLIN pin can select between pulse-skipping mode and forced continuous mode operation and allows the IC to be synchronized to an external clock. Pulse-skipping mode offers the lowest ripple at light loads, while forced continuous mode operates at a constant frequency for noise-sensitive applications. A power good output pin indicates when the output is within 10% of its designed set point. The L TC3789 is avail- able in low profile 28-pin 4mm × 5mm QFN and narrow SSOP packages. Efficiency and Power Loss n Single Inductor Architecture Allows VIN Above, Below or Equal to Regulated VOUT n Programmable Input or Output Current Feedback Loop n Wide VIN Range: 4V to 38V n 1% Output Voltage Accuracy: 0.8V < VOUT < 38V n Synchronous Rectification: Up to 98% Efficiency n Current Mode Control n Phase-Lockable Fixed Frequency: 200kHz to 600kHz n No Reverse Current During Start-Up n Power Good Output Voltage Monitor n Internal 5.5V LDO n Quad N-Channel MOSFET Synchronous Drive n VOUT Disconnected from VIN During Shutdown n Adjustable Soft-Start Output Ramping n Available in 28-Lead QFN (4mm × 5mm) and 28-Lead SSOP Packages n Automotive Systems n Distributed DC Power Systems n High Power Battery-Operated Devices n Industrial Control VIN VINSNS VOUTSNS ILIM PGOOD 0.1µF 0.1µF 121k BOOST1 TG1 SW1 BG1 TG2 BOOST2 SW2 BG2 MODE/PLLIN RUN VFB ITH SS 0.010/uni03A9 4.7µF A B D C 2200pF 1000pF 1µF CER 10µF 16V CER 330µF 16V ON/OFF 0.01µF 4.7µH L TC3789 INTV CC EXTVCC SENSE+ IOSENSE– IOSENSE+ FREQSGND SENSE– PGND 7.5k

3789 TA01

0.010/uni03A9 22µF 50V CER L, L T , L TC, L TM, Linear Technology, the Linear logo, µModule and Burst Mode are registered trademarks and ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5408150, 5481178, 5929620, 6580258, 7365525, 7394231. VIN (V) EFFICIENCY (%) POWER LOSS (W) 10 15 255 20 30 35 40 100

3789 TA01b

VOUT = 12V ILOAD = 5A

oltages (IOSENSE+, IOSENSE–) ...40V to –0.3V EXT VCC to –0.3V (Note 1) VCC to –0.3V Operating Junction T emperature Range Storage T INT Lead Temperature (Soldering, 10 sec.) orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TC3789EGN#PBF L TC3789EGN#TRPBF L TC3789 28-Lead Narrow Plastic SSOP –40°C to 125°C L TC3789IGN#PBF L TC3789IGN#TRPBF L TC3789 28-Lead Narrow Plastic SSOP –40°C to 125°C L TC3789EUFD#PBF L TC3789EUFD#TRPBF 3789 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C L TC3789IUFD#PBF L TC3789IUFD#TRPBF 3789 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/ TOP VIEW GN PACKAGE 28-LEAD NARROW PLASTIC SSOP V FB SS SENSE+ SENSE– ITH SGND MODE/PLLIN FREQ RUN VINSNS VOUTSNS ILIM IOSENSE+ IOSENSE– PGOOD SW1 TG1 BOOST1 PGND BG1 V IN INTVCC EXTVCC BG2 BOOST2 TG2 SW2 TRIM TJMAX = 125°C, θJA = 80°C/W 9 10 TOP VIEW UFD PACKAGE 28-LEAD (4mm × 5mm) PLASTIC QFN 11 12 13 28 27 26 25 24 1SENSE– ITH SGND MODE/PLLIN FREQ RUN VINSNS VOUTSNS BOOST1 PGND BG1 V IN INTVCC EXTVCC BG2 BOOST2 SENSE+ SS V FB PGOOD SW1 TG1 I LIM IOSENSE+ IOSENSE– TRIM SW2 TG2 8 15 SGND TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 29) IS SGND, MUST BE SOLDERED TO PCB pin conFiguraTion

elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input Supply Voltage 4 38 V VOUT Output Voltage 0.8 38 V VFB Regulated Feedback Voltage I TH Voltage = 1.2V (Note 4), TA = –40°C to 85°C ITH = 1.2V , TA = 125°C, TA = –40°C to 125°C l l 0.792 0.788 0.800 0.800 0.808 0.812 V V I FB Feedback Current (Note 4) –15 –50 nA VREFLNREG Reference Voltage Line Regulation V IN = 4V to 38V (Note 4) 0.002 0.02 %/V VLOADREG Output Voltage Load Regulation (Note 4) Measured in Servo Loop, ∆ITH Voltage = 1.4V to 2V Measured in Servo Loop, ∆ITH Voltage = 2V to 2.6V l l 0.01 –0.01 0.1 –0.1 g m T ransconductance Amplifier gm ITH = 1.2V , Sink/Source 5µA (Note 4) 1.5 mmho IQ Input DC Supply Current Normal Mode Shutdown (Note 5) V RUN = 0V mA µA UVLO Undervoltage Lockout INTV CC Ramping Down 3.4 3.6 V UVLO Hyst Undervoltage Hysteresis 0.4 V ISENSE+ ISENSE– SENSE Pins Current VSENSE– = VSENSE+ = 0V 0.2 ±1 µA IIOSENSE+ IIOSENSE– IOSENSE Pins Current VIOSENSE– = VIOSENSE+ = 10V 10 14 µA ISS Soft-Start Charge Current V SS = 0V 2 3 4 µA VRUN(ON) RUN Pin On-Threshold VRUN Rising 1.22 V VRUN(HYS) RUN Pin On-Hysteresis 150 mV IRUN RUN Pin Source Current 1.2 µA IRUN(HYS) RUN Pin Hysteresis Current 5 µA VSENSE(MAX) Maximum Current Sense Threshold Buck Region Boost Region V FB = 0.7V VFB = 0.7V l l 110 140 110 165 mV mV V SENSE(IAVG) Maximum Input/Output Average Current Sense Threshold I LIM = 0V ILIM Floating ILIM = INTVCC 130 100 145 106 160 mV mV mV R DSPFET(ON) Driver Pull-Up On-Resistance 2.6 Ω RDSNFET(ON) Driver Pull-Down On-Resistance 1.5 Ω TG tr TG tf Top Gate Rise Time Top Gate Fall Time ns ns BG t r BG tf Bottom Gate Rise Time Bottom Gate Fall Time ns ns TG/BG t 1D Top Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time C LOAD = 3300pF Each Driver (Note 6) 60 ns BG/TG t1D Bottom Gate Off to Top Gate On Delay Top Switch-On Delay Time C LOAD = 3300pF Each Driver (Note 6) 60 ns DFMAX,BOOST Maximum Duty Factor % Switch C On 90 % DON(MIN,BOOST) Minimum Duty Factor for Main Switch in Boost Operation % Switch C On 9 % D ON(MIN,BUCK) Minimum Duty Factor for Main Switch in Buck Operation % Switch B On 9 % The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V , VRUN = 5V , unless otherwise noted.

elecTrical characTerisTics The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 15V , VRUN = 5V , unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS INTVCC Linear Regulator VINTVCCVIN Internal VCC Voltage 6.5V < VIN < 40V , VEXTVCC = 0V 5.2 5.5 5.8 V VLDOVIN INTVCC Load Regulation ICC = 0mA to 20mA, VEXTVCC = 0V 0.2 1.0 % VINTVCCEXT Internal VCC Voltage 6.5V < VEXTVCC < 14V 5.2 5.5 5.8 V VLDOEXT INTVCC Load Regulation ICC = 0mA to 20mA, VEXTVCC = 12V 0.2 1.0 % VEXTVCC EXTVCC Switchover Voltage I CC = 0mA to 20mA, EXTVCC Ramping Positive 4.7 4.8 V VLDOHYS EXTVCC Hysteresis 0.25 V Oscillator and Phase-Locked Loop fNOM Nominal Frequency VFREQ = 1.2V , RFREQ = 1.22k 350 400 440 kHz fLOW Low Fixed Frequency VFREQ = 0V 175 200 225 kHz fHIGH High Fixed Frequency VFREQ = 2.4V 570 640 710 kHz fSYNC Synchronizable Frequency MODE/PLLIN = External Clock l 200 600 kHz RMODE/PLLIN MODE/PLLIN Input Resistance 220 kΩ IFREQ Frequency Setting Current 8 10 12 µA PGOOD Output V PGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V IPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 µA VPG PGOOD T rip Level VFB with Respect to Set Output Voltage VFB Ramping Negative VFB Ramping Positive –10 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TC3789 is tested under pulse load conditions such that T J ≈ TA. The L TC3789E is guaranteed to meet performance specifications from 0°C to 85°C operating junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The L TC3789I is guaranteed to meet performance specifications over the full –40°C to 125°C operating junction temperature range. Note 3: T J is calculated from the ambient temperature TA and power dissipation PD according to the following formula: L TC3789GN: TJ = TA + (PD • 80°C/W) L TC3789UFD: TJ = TA + (PD • 34°C/W) Note 4: The L TC3789 is tested in a feedback loop that servos VITH to a specified voltage and measures the resultant VFB. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See the Applications Information section.

Typical perForMance characTerisTics Efficiency vs Output Current (Boost Region) Efficiency vs Output Current (Buck-Boost Region) Efficiency vs Output Current (Buck Region) Efficiency vs V IN Internal 5.5V LDO Line Regulation EXTV CC LDO Line Regulation INTVCC and EXTVCC Switch Voltage vs Temperature Supply Current vs Input Voltage RUN Pin Threshold vs Temperature T A = 25°C unless otherwise noted. LOAD CURRENT (mA) EFFICIENCY (%) 100 1000 10000 100

3789 G01

VIN = 6V VOUT = 12V DCM FCM DCM FCMCIRCUIT OF FIGURE 13 LOAD CURRENT (mA) EFFICIENCY (%) 100 1000 10000 100

3789 G02

VIN = 12V VOUT = 12V DCM FCMCIRCUIT OF FIGURE 13 LOAD CURRENT (mA) EFFICIENCY (%) 100 1000 10000 100

3789 G03

VIN = 18V VOUT = 12V DCM FCMCIRCUIT OF FIGURE 13 VIN (V) EFFICIENCY (%) 10 20 4030

3789 G04

INPUT VOL TAGE (V) 3.5 INTVCC VOLTAGE (V) 4.0 4.5 6.0 5.5 14 24 29 5.0 9 19 34

3789 G05 EXTVCC (V)

INTVCC (V) 6 85 137 9 1210 14

3789 G06

TEMPERATURE (°C) –60 INTVCC AND EXTVCC SWITCH VOL TAGE (V) –20 0 40–40 20 60 80 100

3789 G07

INPUT VOL TAGE (V) SUPPLY CURRENT (mA) 0.5 1.5 2.0 2.5 4.0 3.5 14 24 29 1.0 3.0 9 19 34

3789 G08 TEMPERATURE (°C)

–60 0.5 UNDERVOLTAGE RESET VOLTAGE AT RUN (V) 0.7 0.9 1.1 –40 –20 0 20 60 40 80 1.3 1.5 0.6 0.8 1.0 1.2 1.4 100

3789 G09

Forced Continuous Mode Forced Continuous Mode Forced Continuous Mode Pulse-Skipping Mode Pulse-Skipping Mode Pulse-Skipping Mode Typical perForMance characTerisTics TA = 25°C unless otherwise noted. Oscillator Frequency vs Temperature Undervoltage Threshold at INTVCC vs Temperature Undervoltage Threshold at VIN vs Temperature 4µs/DIV SW1 10V/DIV SW2 10V/DIV IL 1A/DIV

3789 G10

VIN = 6V VOUT = 12V 4µs/DIV SW1 10V/DIV SW2 10V/DIV IL 1A/DIV

3789 G11

VIN = 12V VOUT = 12V 4µs/DIV IL 1A/DIV SW1 10V/DIV SW2 10V/DIV

3789 G12

VIN = 18V VOUT = 12V 4µs/DIV IL 1A/DIV SW1 10V/DIV SW2 10V/DIV

3789 G13

VIN = 6V VOUT = 12V 2µs/DIV IL 1A/DIV SW1 10V/DIV SW2 10V/DIV

3789 G14

VIN = 12V VOUT = 12V 2µs/DIV IL 1A/DIV SW1 10V/DIV SW2 10V/DIV

3789 G15

VIN = 18V VOUT = 12V TEMPERATURE (°C) –60 UNDERVOLTAGE (V) 1.0 2.0 3.0 –40 –20 0 20 60 40 80 4.0 5.0 0.5 1.5 2.5 3.5 4.5 100

3789 G17

TEMPERATURE (°C) –60 UNDERVOLTAGE (V) 1.0 2.0 3.0 –40 –20 0 20 60 40 80 4.0 5.0 0.5 1.5 2.5 3.5 4.5 100

3789 G18

TEMPERATURE (°C) –50 OSCILLATOR FREQUENCY (kHz) 200 400 600 0 50 150100 700 100 300 500

3789 G16

VFREQ = 2.4V VFREQ = 0V VFREQ = 1.2V

Threshold vs Duty Factor (Boost) Maximum Current Sense Threshold vs Duty Factor (Buck) Maximum Current Limit vs Temperature Peak Current Threshold vs V ITH (Boost) Valley Current Threshold vs V ITH (Buck) Current Foldback Limit Typical perForMance characTerisTics TA = 25°C unless otherwise noted. Load Step Load Step Load Step VFB (V) CURRENT LIMIT (mV) 120 140 0.7 100 160

3789 G24

DUTY FACTOR (%) CURRENT LIMIT (mV) 110 20 40 60 80 130 150 100 120 140 100

3789 G19 DUTY FACTOR (%)

CURRENT LIMIT (mV) 110 20 40 60 80 130 150 100 120 140 100

3789 G20

VITH (V) –200 CURRENT LIMIT (mV)–100 100 0.5 1 1.5 2 2.5 200 –150 –50 150

3789 G22

VITH (V) –100 CURRENT LIMIT (mV) 100 0.5 1 1.5 2 200 –50 150 2.5

3789 G23

400µs/DIV IL 2A/DIV VOUT 200mV/DIV

3789 G25

VIN = 6V VOUT = 12V LOAD STEP = 200mA TO 2A 400µs/DIV IL 2A/DIV VOUT 200mV/DIV

3789 G26

VIN = 12V VOUT = 12V LOAD STEP = 300mA TO 3A 400µs/DIV IL 2A/DIV VOUT 200mV/DIV

3789 G27

VIN = 18V VOUT = 12V LOAD STEP = 300mA TO 3A TEMPERATURE (°C) –50 MAXIMUM CURRENT LIMIT (mV) 120 130 140 110 100 –10 30–30 10 50 11070 130 150

3789 G21

Line T ransient Line T ransient Typical perForMance characTerisTics TA = 25°C unless otherwise noted. (SSOP/QFN) VFB (Pin 1/Pin 26): Error Amplifier Feedback Pin. Receives the feedback voltage for the controller from an external resistive divider across the output. SS (Pin 2/Pin 27): External Soft-Start Input. The L TC3789 regulates the V FB voltage to the smaller of 0.8V or the voltage on the SS pin. A internal 3µA pull-up current source is connected to this pin. A capacitor to ground at this pin sets the ramp time to final regulated output voltage. SENSE + (Pin 3/Pin 28): The (+) Input to the Current Sense Comparator . The ITH pin voltage and controlled offsets between the SENSE – and SENSE + pins, in conjunction with RSENSE, set the current trip threshold. SENSE– (Pin 4/Pin 1): The (–) Input to the Current Sense Comparator . I TH (Pin 5/Pin 2): Error Amplifier Output and Switching Regulator Compensation Point. The channel’s current com- parator trip point increases with this control voltage. SGND (Pin 6/Pins 3, Exposed Pad Pin 29): Small Signal Ground. Must be routed separately from high current grounds to the common (–) terminals of the C IN capacitors. In the QFN package, the exposed pad is SGND. It must be soldered to PCB ground for rated thermal performance. MODE/PLLIN (Pin 7/Pin 4): Mode Selection or External Synchronization Input to Phase Detector . This is a dual- purpose pin. When external frequency synchronization is not used, this pin selects the operating mode. The pin can be tied to SGND or INTV CC. SGND or below 0.8V enables forced continuous mode. INTVCC enables pulse-skipping mode. For external sync, apply a clock signal to this pin; the internal PLL will synchronize the internal oscillator to the clock. The PLL composition network is integrated into the IC. FREQ (Pin 8/Pin 5): Frequency Set Pin. There is a precision 10µA current flowing out of this pin. A resistor to ground sets a voltage which, in turn, programs the frequency. Alternatively, this pin can be driven with a DC voltage to vary the frequency of the internal oscillator . RUN (Pin 9/Pin 6): Run Control Input. Forcing the pin below 0.5V shuts down the controller , reducing quiescent current. There are 1.2µA pull-up currents for this pin. Once the RUN pin rises above 1.22V , the IC is turned on, and an additional 5µA pull-up current is added to the pin. V INSNS (Pin 10/Pin 7): VIN Sense Input to the Buck-Boost T ransition Comparator . Connect this pin to the drain of the top N-channel MOSFET on the input side. IL 2A/DIV VITH VIN 30V TO 5V VOUT (AC) 500mV/DIV

3789 G28

VOUT (AC) 500mV/DIV

3789 G29

pin FuncTions (SSOP/QFN) VOUTSNS (Pin 11/Pin 8): V OUT Sense Input to the Buck- Boost T ransition Comparator . Connect this pin to the drain of the top N-channel MOSFET on the output side. ILIM (Pin 12/Pin 9): Input/Output Average Current Sense Range Input. This pin tied to SGND, INTVCC or left floating, sets the maximum average current sense threshold. I OSENSE+ (Pin 13/Pin 10): The (+) Input to the Input/Output Average Current Sense Amplifier . I OSENSE– (Pin 14/Pin 11): The (–) Input to the Input/Output Average Current Sense Amplifier . TRIM (Pin 15/Pin 12): Tie this pin to GND for normal operation. Do not allow this pin to float. EXTV CC (Pin 20/Pin 17): External Power Input to an Internal LDO Connected to INTV CC. This LDO supplies INTVCC power , bypassing the internal LDO powered from VIN whenever EXTV CC is higher than 4.8V . See EXTV CC Connection in the Applications Information section. Do not exceed 14V on this pin. INTVCC (Pin 21/Pin 18): Output of the Internal Linear Low Dropout Regulator . The driver and control circuits are powered from this voltage source. Must be bypassed to power ground with a minimum of 4.7µF tantalum, ceramic, or other low ESR capacitor . V IN (Pin 22/Pin 19): Main Supply Pin. A bypass capa- citor should be tied between this pin and the signal ground pin. BG1, BG2 (Pins 23, 19/Pins 20, 16): High Current Gate Drives for Bottom (Synchronous) N-Channel MOSFETs. Voltage swing at these pins is from ground to INTV CC. PGND (Pin 24/Pin 21): Driver Power Ground. Connects to C OUT and RSENSE (–) terminal(s) of CIN. BOOST1, BOOST2 (Pins 25, 18/Pins 22, 15): Bootstrapped Supplies to the Top Side Floating Drivers. Capacitors are connected between the BOOST and SW pins and Schottky diodes are tied between the BOOST and INTV CC pins. Voltage swing at the BOOST pins is from INTVCC to (VIN + INTVCC). TG1, TG2 (Pins 26, 17/Pins 23, 14): High Current Gate Drives for Top N-Channel MOSFETs. These are the outputs of floating drivers with a voltage swing equal to INTV CC – 0.5V superimposed on the switch node voltage SW . SW1, SW2 (Pins 27, 16/Pins 24, 13): Switch Node Connections to Inductors. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to V IN. PGOOD (Pin 28/Pin 25): Open-Drain Logic Output. PGOOD is pulled to ground when the voltage on the V FB pin is not within ±10% of its regulation window, after the internal 20µs power-bad mask timer expires.

–++ BOOST1 INTVCC VIN TG1 BG1 BG2 RSENSE RSENSE2 PGND FCB FCB INTVCC INTVCC INTVCC IDREV SW1 SW2 TG2 BOOST2 IOSENSE+ IOSENSE– IOS SS ITH VFB VOUT 0.80V 3789 BD OV EA BUCK LOGIC CHARGE PUMP BOOST1 CHARGE PUMP BOOST2 BOOST LOGIC SENSE+ SENSE– IREV ICMP VFLD VIN SW1 1.2µA SHDN RUN 4.8V 5.5V VIN VIN INTERNAL SUPPLY EXTVCC INTVCC SGND 5.5V LDO REG EXTVCC 5.5V LDO REG 0.86V OV 0.74V VFB OSCILLATOR PHASE DET FREQ MODE/ PLLIN 220k FIN PGOOD 3µA ILIMSLOPE 10µA

The L TC3789 is a current mode controller that provides an output voltage above, equal to or below the input voltage. The L TC proprietary topology and control architecture employs a current-sensing resistor . The inductor current is controlled by the voltage on the I TH pin, which is the output of the error amplifier EA. The VFB pin receives the voltage feedback signal, which is compared to the internal reference voltage by the EA. If the input/output current regulation loop is implemented, the sensed inductor cur- rent is controlled by either the sensed feedback voltage or the input/output current. INTV CC/EXTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTV CC pin. When the EXTV CC is left open or tied to a voltage less than 4.5V , an internal 5.5V low dropout (LDO) regulator supplies INTV CC power from VIN. If EXTVCC is taken above 4.8V , the 5.5V regulator is turned off, and another LDO regulates INTV CC from EXTVCC. The EXTVCC LDO allows the INTVCC power to be derived from a high efficiency external source such as the L TC3789 regulator output. The absolute maximum voltage on EXTV CC is 14V . Internal Charge Pump Each top MOSFET driver is biased from the floating boot- strap capacitors CA and CB, which are normally recharged by INTVCC through an external diode when the top MOSFET is turned off. When the L TC3789 operates exclusively in the buck or boost regions, one of the top MOSFETs is constantly on. An internal charge pump recharges the bootstrap capacitor to compensate for the small leakage current through the bootstrap diode so that the MOSFET can be kept on. However , if a high leakage diode is used such that the internal charge pump cannot provide sufficient charges to the external bootstrap capacitor , an internal UVLO comparator , which constantly monitors the drop across the capacitor , will sense the (BOOST – SW) voltage when it is below 3.6V . It will turn off the top MOSFET for about one-twelfth of the clock period every four cycles to allow C A or CB to recharge. Shutdown and Start-Up The controller can be shut down by pulling the RUN pin low. When the RUN pin voltage is below 0.5V , the LTC3789 goes into low quiescent current mode. Releas- ing RUN allows an internal 1.2µA current to pull up the pin and enable the controller . When RUN is above the accurate threshold of 1.22V , the internal LDO will power up the INTV CC. At the same time, a 6µA pull-up current will kick in to provide more RUN pin hysteresis. The RUN pin may be externally pulled up or driven directly by logic. Be careful not to exceed the absolute maximum rating of 6V on this pin. The start-up of the controller’s output voltage V OUT is controlled by the voltage on the SS pin. When the voltage on the SS pin is less than the 0.8V internal reference, the L TC3789 regulates the V FB voltage to the SS voltage instead of the 0.8V reference. This allows the SS pin to be used to program soft-start by connecting an external capacitor from the SS pin to SGND. An internal 3µA pull-up current charges this capacitor , creating a voltage ramp on the SS pin. As the SS voltage rises linearly from 0V to 0.8V (and beyond), the output voltage V OUT rises smoothly from zero to its final value. Alternatively, the SS pin can be used to cause the start-up of V OUT to track that of another supply. When RUN is pulled low to disable the controller , or when INTV CC is below the undervoltage lockout threshold of 3.4V , the SS pin is pulled low by an internal MOSFET . In undervoltage lockout, the controller is disabled and the external MOSFETs are held off.

Figure 3. Buck Region (VIN >> VOUT) approaches VOUT, the buck-boost region is reached. Figure 1. Simplified Diagram of the Output Switches Figure 2. Operating Region vs Duty Cycle

3789 F01

3789 F02

3780 F03

approaches VOUT, the buck-boost region is reached. Figure 4. Buck-Boost Region region, the inductor current is not allowed to reverse.

3789 F04a

3789 F04b

3789 F05

Constant-Current Regulation The L TC3789 provides a constant-current regulation loop for either input or output current. A sensing resistor close to the input or output capacitor will sense the input or output current. When the current exceeds the programmed current limit, the voltage on the I TH pin will be pulled down to maintain the desired maximum input or output current. The input current limit function prevents overloading the DC input source, while the output current limit provides a building block for battery charger or LED driver applica- tions. It can also serve as an extra current limit protection for a constant-voltage regulation application. The input/ output current limit function has an operating voltage range of GND to the absolute maximum V OUT (VIN). Frequency Selection and Phase-Locked Loop (FREQ and MODE/PLLIN Pins) The selection of switching frequency is a trade-off between efficiency and component size. Low frequency opera- tion increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. The switching frequency of the L TC3789’s controllers can be selected using the FREQ pin. If the MODE/PLLIN pin is not being driven by an external clock source, the FREQ pin can be used to program the controller’s operating frequency from 200kHz to 600kHz. Switching frequency is determined by the voltage on the FREQ pin. Since there is a precision 10µA current flowing out of the FREQ pin, the user can program the controller’s switching frequency with a single resistor to SGND. A curve is provided in the Applications Information section to show the relationship between the voltage on the FREQ pin and the switching frequency. A phase-locked loop (PLL) is integrated on the L TC3789 to synchronize the internal oscillator to an external clock source driving the MODE/PLLIN pin. The controller oper- ates in forced continuous mode when it is synchronized. The PLL filter network is integrated inside the L TC3789. The PLL is capable of locking to any frequency within the range of 200kHz to 600kHz. The frequency setting resis- tor should always be present to set the controller’s initial switching frequency before locking to the external clock. Power Good (PGOOD) Pins The PGOOD pin is connected to the open drain of an internal N-channel MOSFET . When V FB is not within ±10% of the 0.8V reference voltage, the PGOOD pin is pulled low. The PGOOD pin is also pulled low when RUN is below 1.22V or when the L TC3789 is in the soft-start phase. There is an internal 20µs power good or bad mask when V FB goes in or out of the ±10% window. The PGOOD pin is allowed to be pulled up by an external resistor to INTV CC or an external source of up to 6V . Short-Circuit Protection, Current Limit and Current Limit Foldback The maximum current threshold of the controller is limited by a voltage clamp on the ITH pin. In every boost cycle, the sensed maximum peak voltage is limited to 140mV . In every buck cycle, the sensed maximum volt- age is limited to 90mV . In the buck-boost region, only peak sensed voltage is limited by the same threshold as in the boost region. The L TC3789 includes current foldback to help limit load current when the output is shorted to ground. If the out- put falls below 50% of its nominal output level, then the maximum sense voltage is progressively lowered from its maximum value to one-third of the maximum value. Foldback current limiting is disabled during the soft-start. Under short-circuit conditions, the L TC3789 will limit the current by operating as a buck with very low duty cycles, and by skipping cycles. In this situation, synchronous switch B will dissipate most of the power (but less than in normal operation).

to an input voltage of 38V . RSENSE is chosen based on the required output current. varies with input and output voltage. to 30% margin is usually recommended. shorted to either VOUT or VIN. Figure 6. Load Current vs VIN/VOUT

100 ILOAD(MAX) • RSENSE (mV)

3789 F06

Figure 7. Programming Output Current Limit Figure 8. Programming Input Current Limit

3789 F07

3789 F08

ing frequency, and gain should decrease by 20dB/decade. ensure overall system stability. by 20% to 30% due to process variation. signal at lower than 40% duty cycles in the buck region. false locking to harmonics of the external clock.

3789 F09

Figure 9. Relationship Between Oscillator

ESR capacitor sized to handle the maximum RMS current.

• VIN VOUT – 1 This formula has a maximum at V IN = 2V OUT, where IRMS = I OUT(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple cur- rent ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor . DIGITAL PHASE/ FREQUENCY DETECTOR VCO 2.4V 10µA RSET

3789 F10

Figure 10. Phase-Locked Loop Block Diagram the filter capacitor holds the voltage. maximum inductor current in the boost region at VIN(MIN).

where COUT is the output filter capacitor . meet the ESR and RMS current handling requirements. characteristics but can have a high voltage coefficient. current ratings, such as OS-CON and POSCAP .

• IOUT(MAX)
• ρt • RDS(ON) where ρt is a normalization factor (unity at 25°C) ac- counting for the significant variation in on-resistance with temperature, typically about 0.4%/°C, as shown in Figure 11. For a maximum junction temperature of 125°C, using a value ρt = 1.5 is reasonable. JUNCTION TEMPERATURE (°C) –50 ρT NORMALIZED ON-RESISTANCE (/uni03A9) 1.0 1.5 150

3789 F11

Figure 11. Normalized RDS(ON) vs Temperature

• IOUT(MAX) 2 • ρt • RDS(ON) Switch C operates in the boost region as the control switch. Its power dissipation at maximum current is given by: PC,BOOST = VOUT – VIN( ) VOUT VIN 2 • IOUT(MAX) 2 • ρt
• RDS(ON) + k • VOUT 3 • IOUT(MAX) VIN
• CRSS • f

where CRSS is usually specified by the MOSFET manufactur- ers. The constant k, which accounts for the loss caused by reverse recovery current, is inversely proportional to the gate drive current and has an empirical value of 1.7. For switch D, the maximum power dissipation happens in the boost region, when its duty cycle is higher than 50%. Its maximum power dissipation at maximum output current is given by: PD,BOOST = VIN VOUT

• VOUT VIN
• IOUT(MAX)
• ρt • RDS(ON) For the same output voltage and current, switch A has the highest power dissipation and switch B has the lowest power dissipation unless a short occurs at the output. From a known power dissipated in the power MOSFET , its junction temperature can be obtained using the following formula: TJ = TA + P • RTH(JA) The RTH(JA) to be used in the equation normally includes the RTH(JC) for the device plus the thermal resistance from the case to the ambient temperature (RTH(JC)). This value of TJ can then be compared to the original, assumed value used in the iterative calculation process. Schottky Diode (D1, D2) Selection The Schottky diodes, D1 and D2, shown in Figure 13, conduct during the dead time between the conduction of the power MOSFET switches. They are intended to prevent the body diode of synchronous switches B and D from turning on and storing charge during the dead time. In particular , D2 significantly reduces reverse recover y current between switch D turn-off and switch C turn-on, which improves converter efficiency and reduces switch C voltage stress. In order for the diode to be effective, the inductance between it and the synchronous switch must be as small as possible, mandating that these components be placed adjacently. INTV CC Regulators and EXTVCC The L TC3789 features a true PMOS LDO that supplies power to INTVCC from the VIN supply. INTVCC powers the gate drivers and much of the L TC3789’s internal circuitry. The linear regulator regulates the voltage at the INTV CC pin to 5.5V when VIN is greater than 6.5V . EXTVCC can supply the needed power when its voltage is higher than 4.8V through another on-chip PMOS LDO. Each of these can supply a peak current of 100mA and must be bypassed to ground with a minimum of 1µF ceramic capacitor or low ESR electrolytic capacitor . No matter what type of bulk capacitor is used, an additional 0.1µF ceramic capacitor placed directly adjacent to the INTV CC and PGND pins is highly recommended. Good bypassing is needed to supply the high transient current required by the MOSFET gate drivers and to prevent interaction between the channels. High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maxi- mum junction temperature rating for the L TC3789 to be exceeded. The INTV CC current, which is dominated by the gate charge current, may be supplied by either the 5.5V linear regulator from V IN or the 5.5V LDO from EXTVCC . When the voltage on the EXTVCC pin is less than 4.5V , the linear regulator from VIN is enabled. Power dissipation for the IC in this case is highest and is equal to VIN • IINTVCC. The gate charge current is dependent on operating frequency, as discussed in the Efficiency Considerations section. The junction temperature can be estimated by using the equa- tions given in Note 3 of the Electrical Characteristics. For example, the L TC3789 INTV CC current is limited to less than 24mA from a 24V supply in the SSOP package and not using the EXTV CC supply: To prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (MODE/PLLIN = SGND) at maximum VIN. When the voltage applied to EXTVCC rises above 4.8V , the INTVCC linear regulator from VIN is turned off and the linear regulator from EXTVCC is turned on and remains on as long as the voltage applied to EXTVCC remains above 4.5V . Using EXTVCC allows the MOSFET driver and control power to be derived from the L TC3789’s switching regulator output during normal operation and from the VIN when the output is out of regulation (e.g., start-up, short-circuit). Do not apply more than 14V to EXTVCC.

Significant efficiency and thermal gains can be realized by powering INTVCC from the output, since the VIN current resulting from the driver and control currents will be scaled by a factor of (Duty Cycle)/(Switcher Efficiency). Tying the EXTVCC pin to a 12V output reduces the junc- tion temperature in the previous example from 125°C to 97°C: Powering INTVCC from the output can also provide enough gate drive when VIN drops below 5V . This allows a wider operating range for VIN after the controller start into regulation. The following list summarizes the three possible connec- tions for EXTVCC: 1. EXT VCC left open (or grounded). This will cause INTVCC to be powered from the internal 5.5V regulator at the cost of a small efficiency penalty. EXT VCC connected directly to VOUT (4.7V < VOUT < 14V). This is the normal connection for the 5.5V regulator and provides the highest efficiency. EXT VCC connected to an external supply. If an external supply is available in the 4.7V to 14V range, it may be used to power EXTV CC provided it is compatible with the MOSFET gate drive requirements. Note that there is an internal body diode from INTVCC to VIN. When INTVCC is powered from EXTVCC and VIN drops lower than 4.5V , the diode will create a back-feeding path from EXTV CC to VIN. To limit this back-feeding current, a 10Ω ~ 15Ω resistor is recommended between the system V IN voltage and the chip VIN pin. Output Voltage The L TC3789 output voltage is set by an external feedback resistive divider carefully placed across the output capacitor . The resultant feedback signal is compared with the internal precision 0.8V voltage reference by the error amplifier . The output voltage is given by the equation: VOUT = 0.8V • 1+ R2 where R1 and R2 are defined in Figure 13. Topside MOSFET Driver Supply (CA, DA, CB, DB) Referring to Figure 13, the external bootstrap capacitors CA and C B connected to the BOOST1 and BOOST2 pins supply the gate drive voltage for the topside MOSFET switches A and D. When the top switch A turns on, the switch node SW2 rises to V IN and the BOOST2 pin rises to approximately VIN + INTVCC. When the bottom switch B turns on, the switch node SW2 drops to low and the boost capacitor C B is charged through D B from INTVCC. When the top switch D turns on, the switch node SW1 rises to V OUT and the BOOST1 pin rises to approximately VOUT + INTVCC. When the bottom switch C turns on, the switch node SW1 drops to low and the boost capacitor CA is charged through DA from INTVCC. The boost capacitors CA and CB need to store about 100 times the gate charge required by the top switches A and D. In most applica- tions, a 0.1µF to 0.47µF , X5R or X7R dielectric capacitor is adequate. Undervoltage Lockout The L TC3789 has two functions that help protect the controller in case of undervoltage conditions. A precision UVLO comparator constantly monitors the INTV CC voltage to ensure that an adequate gate-drive voltage is present. It locks out the switching action when INTV CC is below 3.4V . To prevent oscillation when there is a disturbance on the INTV CC, the UVLO comparator has 400mV of precision hysteresis. Another way to detect an undervoltage condition is to moni- tor the VIN supply. Because the RUN pin has a precision turn-on reference of 1.22V , one can use a resistor divider to V IN to turn on the IC when VIN is high enough. An extra 5µA of current flows out of the RUN pin once its voltage passes 1.22V . One can program the hysteresis of the run comparator by adjusting the values of the resistive divider . Soft-Start Function When a capacitor is connected to the SS pin, a soft-start current of 3µA starts to charge the capacitor . A soft-start function is achieved by controlling the output ramp volt- age according to the ramp rate on the SS pin. Current foldback is disabled during this phase to ensure smooth soft-start. When the chip is in the shutdown state with its RUN pin voltage below 1.22V , the SS pin is actively pulled

to ground. The soft-start range is defined to be the voltage range from 0V to 0.8V on the SS pin. The total soft-start time can be calculated as: tSOFTSTART = 0.8 • CSS 3µA Regardless of the mode selected by the MODE/PLLIN pin, the regulator will always start in pulse-skipping mode up to SS = 0.8V . Fault Conditions: Current Limit and Current Foldback The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the boost region, maximum sense voltage and the sense resistance determine the maximum allowed inductor peak current, which is: IL(MAX,BOOST) = 140mV RSENSE In the buck region, maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current, which is: IL(MAX,BUCK) = 90mV RSENSE To further limit current in the event of a short circuit to ground, the L TC3789 includes foldback current limiting. If the output falls by more than 50%, then the maximum sense voltage is progressively lowered to about one-third of its full value. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in circuit produce losses, four main sources account for most of the losses in L TC3789 circuits: DC I2R losses. These arise from the resistances of the MOSFETs, sensing resistor , inductor and PC board traces and cause the efficiency to drop at high output currents. 2. T ransition loss. This loss arises from the brief amount of time switch A or switch C spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input voltages above 20V and can be estimated from: T ransition Loss ≈ 1.7A–1 • VIN2 • IOUT • CRSS • f where CRSS is the reverse transfer capacitance. 3. INT VCC current. This is the sum of the MOSFET driver and control currents. This loss can be reduced by sup- plying INTV CC current through the EXTVCC pin from a high efficiency source, such as the output (if 4.7V < V OUT < 14V) or alternate supply if available. 4. CIN and COUT loss. The input capacitor has the difficult job of filtering the large RMS input current to the regula- tor in buck mode. The output capacitor has the more difficult job of filtering the large RMS output current in boost mode. Both C IN and COUT are required to have low ESR to minimize the AC I 2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. Other losses. Schottky diodes D1 and D2 are respon- sible for conduction losses during dead time and light load conduction periods. Inductor core loss occurs predominately at light loads. Switch C causes reverse recover y current loss in boost mode. When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If one makes a change and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no change in efficiency.

VIN = 5V to 18V VOUT = 12V IOUT(MAX) = 5A f = 400kHz Maximum ambient temperature = 60°C Set the frequency at 400kHz by applying 1.2V on the FREQ pin (see Figure 7). The 10µA current flowing out of the FREQ pin will give 1.2V across a 120k resistor to GND. The inductance value is chosen first based on a 30% ripple cur- rent assumption. In the buck region, the ripple current is: ∆IL,BUCK = VOUT f • L • 1– VOUT VIN IRIPPLE,BUCK = ∆IL,BUCK • 100 IOUT The highest value of ripple current occurs at the maximum input voltage. In the boost region, the ripple current is: ∆I L,BOOST = VIN f • L

• 1 – VIN VOUT IRIPPLE,BOOST = ∆I L,BOOST • 100 IIN The highest value of ripple current occurs at V IN = VOUT/2. A 6.8µH inductor will produce 11% ripple in the boost region (VIN = 6V) and 29% ripple in the buck region (VIN = 18V). The RSENSE resistor value can be calculated by using the maximum current sense voltage specification with some accommodation for tolerances. RSENSE = 2 • 140mV • VIN(MIN) 2 •IOUT(MAX,BOOST) • VOUT + ∆IL,BOOST • VIN(MIN) Select an RSENSE of 10mΩ. Output voltage is 12V . Select R1 as 20k. R2 is: R2 = VOUT • R1 0.8 – R1 Select R2 as 280k. Both R1 and R2 should have a toler - ance of no more than 1%. Selecting MOSFET Switches The MOSFETs are selected based on voltage rating and RDS(ON) value. It is important to ensure that the part is speci- fied for operation with the available gate voltage amplitude. In this case, the amplitude is 5.5V and MOSFETs with an R DS(ON) value specified at VGS = 4.5V can be used. Select QA and QB. With 18V maximum input voltage MOSFETs with a rating of at least 30V are used. As we do not yet know the actual thermal resistance (circuit board design and airflow have a major impact) we assume that the MOSFET thermal resistance from junction to ambient is 50°C/W . If we design for a maximum junction temperature, T J(MAX) = 125°C, the maximum RDS(ON) value can be calculated. First, calculate the maximum power dissipation: PD(MAX) = TJ(MAX) − TA(MAX) R(j−a) PD(MAX) = (125 − 60) 50 = 1.3W The maximum dissipation in QA occurs at minimum input voltage when the circuit operates in the boost region and QA is on continuously. The input current is then: VOUT •IOUT(MAX) VIN(MIN) , OR 12A We calculate a maximum value for RDS(ON): RDS(ON) (125°C) < PD(MAX) IIN(MAX) RDS(ON) (125°C) < 1.3W (12A)2 = 0.009Ω

The Vishay SiR422DP has a typical RDS(ON) of 0.010Ω at TJ = 125°C and VGS = 4.5V . The maximum dissipation in QB occurs at maximum input voltage when the circuit is operating in the buck region. The dissipation is: PB,BUCK = VIN − VOUT VIN

• IOUT(MAX) 2 • ρt • RDS(ON) RDS(ON) (125 °C) < 1.3W 18V TO −12V 18V
• (5A) 2 = 0.156 Ω This seems to indicate that a quite small MOSFET can be used for QB if we only look at power loss. However , with 5A current the voltage drop across 0.156Ω is 0.78V , which means the MOSFET body diode is conducting. To avoid body diode current flow we should keep the maximum voltage drop well below 0.5V , using, for example, Vishay Si4840BDY in the SO-8 package (R DSON(MAX) = 0.012Ω). Select QC and QD. With 12V output voltage we need MOSFETs with 20V or higher rating. The highest dissipation occurs at minimum input voltage when the inductor current is highest. For switch QC the dissipation is: PC,BOOST = (VOUT − VIN )VOUT VIN
• IOUT(MAX) 2 • ρt • RDS(ON) + k • VOUT 3 • IOUT(MAX) VIN
• CRSS • f where CRSS is usually specified by the MOSFET manufactur- ers. The constant k, which accounts for the loss caused by reverse recovery current, is inversely proportional to the gate drive current and has an empirical value of 1.7. The dissipation in switch QD is: PD,BOOST = VIN VOUT
• VOUT VIN
• IOUT(MAX)
• ρt • RDS(ON) Vishay SiR484OY is a possible choice for QC and QD. The calculated power loss at 5V input voltage is then 1.3W for QC and 0.84W for QD. C IN is chosen to filter the square current in the buck region. In this mode, the maximum input current peak is: IIN,PEAK(MAX,BUCK) = 5A • 1+ 29%  = 5.7A A low ESR (10mΩ) capacitor is selected. Input voltage ripple is 57mV (assuming ESR dominates the ripple). COUT is chosen to filter the square current in the boost region. In this mode, the maximum output current peak is: IOUT,PEAK(MAX,BOOST) = 12
• 5 • 1+ 11%  = 10.6A A low ESR (5mΩ) capacitor is suggested. This capacitor will limit output voltage ripple to 53mV (assuming ESR dominates the ripple). PC Board Layout Checklist The basic PC board layout requires a dedicated ground plane layer . Also, for high current, a multilayer board provides heat sinking for power components. The ground plane layer should not have any traces and should be as close as possible to the layer with power MOSFETs.
• Place CIN, switch A, switch B and D1 in one com- pact area. Place C OUT, switch C, switch D and D2 in one compact area. One layout example is shown in Figure 12.
• Use immediate vias to connect the components (in- cluding the L TC3789’s SGND and PGND pins) to the ground plane. Use several large vias for each power component.

• Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low.
• Flood all unused areas on all layers with copper . Flooding with copper will reduce the temperature rise of power components. Connect the copper areas to any DC net (V IN or GND). When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the L TC3789. These items are also illustrated in Figure 13. Segregate the signal and power grounds. All small- signal components should return to the SGND pin at one point, which is then tied to the PGND pin close to the inductor current sense resistor R SENSE.
• Place switch B and switch C as close to the controller as possible, keeping the PGND, BG and SW traces short. Keep the high dV/dT SW1, SW2, BOOST1, BOOST2, TG1 and TG2 nodes away from sensitive small-signal nodes. The path formed by switch A, switch B, D1 and the CIN capacitor should have short leads and PC trace lengths. The path formed by switch C, switch D, D2 and the C OUT capacitor also should have short leads and PC trace lengths.
• The output capacitor (–) terminals should be connected as closely as possible to the (–) terminals of the input capacitor .
• Connect the top driver boost capacitor CA closely to the BOOST1 and SW1 pins. Connect the top driver boost capacitor C B closely to the BOOST2 and SW2 pins.
• Connect the input capacitors CIN and output capacitors COUT closely to the power MOSFETs. These capacitors carry the MOSFET AC current in the boost and buck region. Connect VFB pin resistive dividers to the (+) terminals of COUT and signal ground. A small VFB bypass capacitor may be connected closely to the L TC3789 SGND pin. The R2 connection should not be along the high current or noise paths, such as the input capacitors. Route SENSE– and SENSE+ leads together with mini- mum PC trace spacing. Avoid having sense lines pass through noisy areas, such as switch nodes. The filter capacitor between SENSE + and SENSE– should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the SENSE resistor . One layout example is shown in Figure 14. Connect the ITH pin compensation network closely to the IC, between I TH and the signal ground pins. The capacitor helps to filter the effects of PCB noise and output voltage ripple voltage from the compensa- tion loop. Connect the INTVCC bypass capacitor , CVCC, closely to the IC, between the INTV CC and the power ground pins. This capacitor carries the MOSFET drivers’ current peaks. An additional 1µF ceramic capacitor placed im- mediately next to the INTV CC and PGND pins can help improve noise performance substantially. applicaTions inForMaTion GND VOUT COUT L RSENSE

3789 F12

Figure 12. Switches Layout

Figure 13. L TC3789 12V/5A, Buck-Boost Regulator

3789 F13

3789 F14

Figure 14. Sense Lines Layout

28-Lead Plastic SSOP (Narrow .150 Inch) (Reference L TC DWG # 05-08-1641) .386 – .393* (9.804 – 9.982) GN28 (SSOP) 0204 1 2 3 4 5 6 7 8 9 10 11 12 .229 – .244 (5.817 – 6.198) .150 – .157** (3.810 – 3.988) 20 21 22 23 24 25 26 27 2819 18 17 13 14 1615 .016 – .050 (0.406 – 1.270) .015 .004 (0.38 0.10) ¥ 45∞ 0 – 8 TYP.0075 – .0098 (0.19 – 0.25) .0532 – .0688 (1.35 – 1.75) .008 – .012 (0.203 – 0.305) TYP .004 – .0098 (0.102 – 0.249) .0250 (0.635) BSC .033 (0.838) REF .254 MIN RECOMMENDED SOLDER PAD LAYOUT .150 – .165 .0250 BSC.0165 .0015 .045 .005 INCHES (MILLIMETERS) NOTE: 1. CONTROLLING DIMENSION: INCHES 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package DescripTion 28-Lead Plastic QFN (4mm × 5mm) (Reference L TC DWG # 05-08-1712 Rev B) 4.00 ± 0.10 (2 SIDES)

2.50 REF

5.00 ± 0.10 (2 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ± 0.10 27 28 BOTTOM VIEW—EXPOSED PAD

3.50 REF

0.75 ± 0.05 R = 0.115 TYP R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UFD28) QFN 0506 REV B RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 4.10 ± 0.05 5.50 ± 0.05 2.65 ± 0.05 3.10 ± 0.05 4.50 ± 0.05 PACKAGE OUTLINE 2.65 ± 0.10 3.65 ± 0.10 3.65 ± 0.05

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com  LINEAR TECHNOLOGY CORPORATION 2010 LT 1210 • PRINTED IN USA relaTeD parTs Typical applicaTion PART NUMBER DESCRIPTION COMMENTS L TC3780 High Efficiency (Up to 98%) Synchronous, 4-Switch Buck-Boost DC/DC Controller 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 30V, 5mm × 5mm QFN-32 and SSOP-24 Packages L TC3785 High Efficiency (Up to 98%) Synchronous, 4-Switch Buck-Boost DC/DC Controller 2.7V ≤ V IN ≤ 30V, 2.7V ≤ VOUT ≤ 10V, 4mm × 4mm L TM4605 High Efficiency Buck-Boost DC/DC µModule™ 4.5V ≤ VIN ≤ 20V, 0.8V ≤ VOUT ≤ 16V, 15mm × 15mm × 2.8mm LGA Package L TM4607 High Efficiency Buck-Boost DC/DC µModule 4.5V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 25V, 15mm × 15mm × 2.8mm LGA Package L TM4609 High Efficiency Buck-Boost DC/DC µModule 4.5V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 34V, 15mm × 15mm × 2.8mm LGA Package L TC3533 2A Synchronous Buck-Boost Monolithic DC/DC Converter 1.8V ≤ VIN ≤ 5.5V, 1.8V ≤ VOUT ≤ 5.25V, IQ = 40µA, ISD < 1µA, 3mm × 4mm DFN-14 Package LTC3789EGN DFLS160 DFLS160 3 1 BAS16 SiR422DP Si4840BDY B240A V OS+ VIN+ VOUT VIN BZX84- C5V1 C11, OPT

3789 TA02

5.5µH SiR422DPVFB SS SENSE1+ SENSE1– ITH SGND MODE/PLLIN FREQ RUN V INSNS VOUTSNS ILIM PGOOD SW1 TG1 BOOST1 PGND1 BG1 VIN INTVCC EXTVCC INTVCC BG2 BOOST2 I OSENSE+ IOSENSE– TG2 SW2 TRIM R4, 100/uni03A9 R3, 100/uni03A9 R9, 1.24k R10, 1.24k RC, 15k RFB2 8.06k RFB1 232k R2 0.010/uni03A9 10/uni03A9, 0805 CC1, 1000pF CC2, 0.01µF R21 121k, 1% R31 12.1k 0.01µF R30 68.1k C7, 0.1µF C8, 0.1µF R13, 100/uni03A9 R14 100/uni03A9 C10, 2.2µF C24, 1µF R11, 0/uni03A9 C4 0.22µF, 16V C22 0.22µF, 16V C18 10µF, 1206 R1, 5.6/uni03A9 R18 8m/uni03A9 2.2µF, 50V X5R COUT2 330µF 34V 2.2µF 50V X5R 10/uni03A9 3.3µF 50V 1210 C15 1µF 50V 1210 C IN1 270µF 50V OPT C IN2 270µF 50V VIN 9V TO 35V V IN J3 B240A 100k + + R25 0/uni03A9 VOUT VOUT 24V AT V OS+ VOUT VOS+ L1: WÜRTH 7443630550 24V/5A Buck-Boost Regulator