LTM4606_1 LINER | Alldatasheet

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Technical content

Ultralow EMI 28VIN, 6A DC/DC µModule Regulator The L TM®4606 is a complete EN55022 Class B certified noise high voltage 6A switching mode DC/DC power supply. Included in the package are the switching controller , power FETs, inductor , and all support components. The on-board input filter and noise cancellation circuits achieve low noise operation, thus effectively reducing the electromagnetic interference (EMI). Operating over an input voltage range of 4.5V to 28V , the L TM4606 supports an output voltage range of 0.6V to 5V , set by a single resistor . This high ef- ficiency design delivers 6A continuous current (8A peak). Only bulk input and output capacitors are needed to finish the design. High switching frequency and an adaptive on-time current mode architecture enables a very fast transient response to line and load changes without sacrificing stability. The device supports output voltage tracking and output volt- age margining. Furthermore, the µModule ® regulator can be synchronized with an external clock for reducing undesirable frequency harmonics and allows PolyPhase® operation for high load currents. The L TM4606 is offered in a space saving and thermally enhanced 15mm × 15mm × 2.8mm LGA package, which enables utilization of unused space on the bottom of PC boards for high density point of load regulation. The L TM4606 is Pb-free and RoHS compliant.

applicaTions

n Complete Low EMI Switch Mode Power Supply n Wide Input Voltage Range: 4.5V to 28V n 6A DC Typical, 8A Peak Output Current n 0.6V to 5V Output Voltage Range n EN55022 Class B Certified n Output Voltage T racking and Margining n PLL Frequency Synchronization n ±1.75% Total DC Error n Power Good Output n Current Foldback Protection (Disabled at Start-Up) n Parallel/Current Sharing n Ultrafast T ransient Response n Current Mode Control n Up to 93% Efficiency at 5VIN, 3.3VOUT n Programmable Soft-Start n Output Overvoltage Protection n –55°C to 125°C Operating Temperature Range TM4606MPV) n Small Surface Mount Footprint, Low Profile Package (15mm × 15mm × 2.8mm) n ASICs or FPGA T ransceivers n Telecom, Servers and Networking Equipment n Industrial Equipment n RF Equipment L, L T , L TC, L TM, Linear Technology, the Linear logo, µModule and PolyPhase are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Ultralow Noise 2.5V/6A Power Supply with 4.5V to 28V Input Radiated Emission Scan at 12VIN, 2.5VOUT/6A PGOOD RUN COMP INTV CC DRVCC fSET TRACK/SS V D FCB MARG0 MARG1 MPGM V OUT VFB VIN TRACK/SS CONTROL 47pF COUT 2.5V AT 6A CIN 10µF 35V CERAMIC 4.5V TO 28V PLLIN CLOCK SYNC ON/OFF L TM4606 SGND PGND MARGIN CONTROL RFB 19.1k 392k 5% MARGIN

4606 TA01a

10µF 35V FREQUENCY (MHz) 128.1 226.2 324.3 520.5 422.4 618.6 716.7 814.8 912.9 1010

4606 TA01b

SIGNAL AMPLITUDE (dBµV/m) –10 –20 –30

pin conFiguraTionabsoluTe MaxiMuM raTings (Note 1) PLLIN, FCB, TRACK/SS, MPGM, MARG0, 0.3V to INTVCC + 0.3V Internal Operating Temperature Range (Note 2) E and I G 40°C to 125°C 55°C to 125°C 25°C 45°C to 125°C LGA PACKAGE 133-LEAD (15mm × 15mm × 2.8mm) TOP VIEW MARG1 DRVCC VFB PGOOD SGND NC NC NC FCB VIN BANK 1 VD PGND BANK 2 VOUT BANK 3 fSET MARG0 RUN COMP MPGM PLLIN INTVCC TRACK/SS SGND L K J H G F E D C BMA TJMAX = 125°C, θJA = 15°C/W , θJCbottom = 6°C/W , θJCtop = 16°C/W θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS WEIGHT = 1.7g orDer inForMaTion LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TM4606EV#PBF L TM4606EV#PBF L TM4606V 133-Lead (15mm × 15mm × 2.8mm) LGA –40°C to 125°C L TM4606IV#PBF L TM4606IV#PBF L TM4606V 133-Lead (15mm × 15mm × 2.8mm) LGA –40°C to 125°C L TM4606MPV#PBF L TM4606MPV#PBF L TM4606MPV 133-Lead (15mm × 15mm × 2.8mm) LGA –55°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear .com/packaging/ SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN(DC) Input DC Voltage l 4.5 28 V VOUT(DC) Output Voltage, Total Variation with Line and Load C IN = 10µF x2, COUT = 200µF; FCB = 0 VIN = 5V to 28V , IOUT = 0A to 6A, (Note 4) l 1.474 1.5 1.526 V Input Specifications VIN(UVLO) Undervoltage Lockout Threshold I OUT = 0A 3.2 4 V IINRUSH(VIN) Input Inrush Current at Start-Up I OUT = 0A, CIN = 10µF x2, COUT = 200µF , VOUT = 1.5V VIN = 5V VIN = 12V 0.6 0.7 A A The l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V , unless otherwise noted. Per typical application (front page) configuration, RFB = 40.2k.

elecTrical characTerisTics

elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V , unless otherwise noted. Per typical application (front page) configuration, RFB = 40.2k. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IQ(VIN) Input Supply Bias Current VIN = 5V , VOUT = 1.5V , Switching Continuous VIN = 12V , VOUT = 1.5V , Switching Continuous Shutdown, RUN = 0, VIN = 12V mA mA µA I S(VIN) Input Supply Current V IN = 12V , VOUT = 1.5V , IOUT = 6A VIN = 5V , VOUT = 1.5V , IOUT = 6A 0.96 2.18 A A INTV CC VIN = 12V , RUN > 2V No Load 4.7 5 5.3 V Output Specifications IOUT(DC) Output Continuous Current Range V IN = 12V , VOUT = 1.5V (Note 4) 0 6 A DVOUT(LINE)/VOUT Line Regulation Accuracy VOUT = 1.5V , FCB = 0V , VIN = 4.5V to 28V , IOUT = 0A l 0.05 0.3 % DVOUT(LOAD)/VOUT Load Regulation Accuracy VOUT = 1.5V , FCB = 0V , IOUT = 0A to 6A VIN = 12V (Note 4) l 0.3 VIN(AC) Input Ripple Voltage IOUT = 0A, CIN = 10µF X5R Ceramic x3 and 100µF Electrolytic VIN = 5V , VOUT = 1.5V VIN = 12V , VOUT = 1.5V mV P-P mVP-P VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 22µF X5R Ceramic x3 and 100µF X5R Ceramic VIN = 5V , VOUT = 1.5V VIN = 12V , VOUT = 1.5V mV P-P mVP-P fS Output Ripple Voltage Frequency I OUT = 5A, VIN = 12V , VOUT = 1.5V 900 kHz DVOUT(START) Turn-On Overshoot, TRACK/SS = 10nF C OUT = 200µF , VOUT = 1.5V , IOUT = 0A VIN = 12V VIN = 5V mV mV t START Turn-On Time, TRACK/SS = Open C OUT = 200µF; VOUT = 1.5V , IOUT = 1A Resistive Load VIN = 5V VIN = 12V 0.5 0.5 ms ms DV OUT(LS) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load COUT = 22µF Ceramic, 470µF x2 VIN = 12V VOUT = 1.5V mV tSETTLE Settling Time for Dynamic Load Step V IN = 12V Load: 0% to 50% to 0% of Full Load, V IN = 12V 25 µs IOUT(PK) Output Current Limit COUT = 200µF VIN = 5V , VOUT = 1.5V VIN = 12V , VOUT = 1.5V A A Control Section V FB Voltage at VFB Pin IOUT = 0A, VOUT = 1.5V l 0.591 0.6 0.609 V VRUN RUN Pin On/Off Threshold 1 1.5 1.9 V ISS / TRACK Soft-Start Charging Current V SS/TRACK = 0V –1 –1.5 –2 µA VFCB Forced Continuous Threshold 0.57 0.6 0.63 V IFCB Forced Continuous Pin Current V FCB = 0V –1 –2 µA tON(MIN) Minimum On Time (Note 3) 50 100 ns tOFF(MIN) Minimum Off Time (Note 3) 250 400 ns RPLLIN PLLIN Input Resistor 50 kW

elecTrical characTerisTics The l denotes the specifications which apply over the specified internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V , unless otherwise noted. Per typical application (front page) configuration, RFB = 40.2k. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IDRVCC Current into DRVCC Pin VOUT = 1.5V , IOUT = 1A 15 25 mA RFBHI Resistor Between VOUT and VFB Pins 60.098 60.4 60.702 kW RUNMAX Volts From RUN to GND Maximum 5.1V Zener Clamp 5 V Margin Section MPGM Margin Reference Voltage Sets a Current 1.18 V MARG0, MARG1 Voltage Thresholds 1.4 V PGOOD DVFBH PGOOD Upper Threshold VFB Rising 7 10 13 % DVFBL PGOOD Lower Threshold VFB Falling –7 –10 –13 % DVFB(HYS) PGOOD Hysteresis VFB Returning 1.5 % VPGL PGOOD Low Voltage IPGOOD = 5mA 0.15 0.4 V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TM4606E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The L TM4606I is guaranteed to meet specifications over the –40°C to 125°C internal operating temperature range. The L TM4606MP is guaranteed and tested over the –55°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: 100% tested at die level only. Note 4: See output current derating curves for different V IN, VOUT and TA.

Typical perForMance characTerisTics Efficiency vs Load Current with 5VIN (FCB = 0) Efficiency vs Load Current with 12V IN (FCB = 0) Efficiency vs Load Current with 24V IN (FCB = 0) 1.2V T ransient Response 1.5V T ransient Response 1.8V T ransient Response 2.5V T ransient Response 3.3V T ransient Response –55°C, Start-Up, IOUT = 0A LOAD CURRENT (A) EFFICIENCY (%) 100

4606 G01

0.6VOUT 1.2VOUT 1.8VOUT 2.5VOUT 3.3VOUT LOAD CURRENT (A) EFFICIENCY (%) 100

4606 G02

1.2VOUT 1.5VOUT 2.5VOUT 3.3VOUT 5VOUT LOAD CURRENT (A) EFFICIENCY (%) 100

4606 G03

2.5VOUT 3.3VOUT 5VOUT

4606 G04

50µs/DIV 1.2V AT 3.5A/µs LOAD STEP COUT = 2× 22µF , 10V CERAMIC 1× 100µF , 6.3V CERAMIC IOUT 2A/DIV VOUT 50mV/DIV

4606 G05

50µs/DIV 1.5V AT 3.5A/µs LOAD STEP C OUT = 2× 22µF , 10V CERAMIC 1× 100µF , 6.3V CERAMIC IOUT 2A/DIV VOUT 50mV/DIV

4606 G06

50µs/DIV 1.8V AT 3.5A/µs LOAD STEP C OUT = 2× 22µF , 10V CERAMIC 1× 100µF , 6.3V CERAMIC IOUT 2A/DIV VOUT 50mV/DIV

4606 G07

50µs/DIV 2.5V AT 3.5A/µs LOAD STEP C OUT = 2× 22µF , 10V CERAMIC 1× 100µF , 6.3V CERAMIC IOUT 2A/DIV VOUT 50mV/DIV

4606 G08

50µs/DIV 3.3V AT 3.5A/µs LOAD STEP C OUT = 2× 22µF , 10V CERAMIC 1× 100µF , 6.3V CERAMIC IOUT 2A/DIV VOUT 100mV/DIV VOUT 0.5V/DIV IIN 0.5A/DIV 1ms/DIV

4606 G09

VIN = 12V VOUT = 1.5V COUT = 2× 22µF , 10V CERAMIC 1× 100µF , 6.3V CERAMIC SOFT-START = 3.9nF

Typical perForMance characTerisTics Start-Up, IOUT = 6A (Resistive Load) Short-Circuit Protection, IOUT = 0A Short-Circuit Protection, I OUT = 6A VIN to VOUT Step-Down Operation Region Input Ripple Output Ripple Start-Up, IOUT = 0A–55°C, Start-Up, IOUT = 6A VFB vs Temperature VOUT 0.5V/DIV IIN 0.5A/DIV 1ms/DIV

4606 G10

VIN = 12V VOUT = 1.5V COUT = 2× 22µF , 10V CERAMIC 1× 100µF , 6.3V CERAMIC SOFT-START = 3.9nF VOUT 0.5V/DIV IIN 0.5A/DIV 1ms/DIV

4606 G11

VIN = 12V VOUT = 1.5V COUT = 1× 22µF , 6.3V CERAMIC 1× 330µF , 4V SANYO POSCAP SOFT-START = 3.9nF VOUT 0.5V/DIV IIN 0.5A/DIV 1ms/DIV

4606 G12

VIN = 12V VOUT = 1.5V COUT = 1× 22µF , 6.3V CERAMIC 1× 330µF , 4V SANYO POSCAP SOFT-START = 3.9nF VOUT 2V/DIV IIN 0.2A/DIV 50µs/DIV

4606 G13

VIN = 12V VOUT = 2.5V COUT = 2× 22µF , 10V CERAMIC 1× 100µF , 6.3V CERAMIC SOFT-START = 0.1µF VOUT 1V/DIV IIN 2A/DIV 50µs/DIV

4606 G14

VIN = 12V VOUT = 2.5V COUT = 2× 22µF , 10V CERAMIC 1× 100µF , 6.3V CERAMIC SOFT-START = 0.1µF VOUT (V) 0.6 VIN (V) 4.5 2.5 4.51.5 3.5

4606 G15

SEE FREQUENCY ADJUSTMENT SECTION FOR OPERATIONS OUTSIDE THIS REGION OPERATION REGION WITH DEFAUL T FREQUENCY TEMPERATURE (°C) –55 0.594 0.596 0.598 VFB (V) 5 –25

4606 G16

0.606 0.604 0.602 0.600 125 95 65 35 VIN 10mV/DIV 2µs/DIV

4606 G17

VIN = 5V VOUT = 1V AT 6A CIN = 3× 10µF , 25V CERAMIC 1× 150µF BULK BW = 300MHz VOUT 2mV/DIV 2µs/DIV

4606 G18

VIN = 5V VOUT = 1V AT 6A COUT = 2× 22µF , 6.3V CERAMIC 1× 100µF , 6.3V CERAMIC BW = 300MHz

VIN (Bank 1): Power Input Pins. Apply input voltage be- tween these pins and PGND pins. Recommend placing input decoupling capacitance directly between V IN pins and PGND pins. VOUT (Bank 3): Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and PGND pins (see figure below). PGND (Bank 2): Power Ground Pins for Both Input and Output Returns. V D (Pins B7 , C7): Top FET Drain Pins. Add more capacitors between VD and ground to handle the input RMS current and reduce the input ripple further . DRV CC (Pins C10, E11, E12): These pins normally con- nect to INTVCC for powering the internal MOSFET drivers. They can be biased up to 6V from an external supply with about 50mA capability, or an external circuit as shown in Figure 18. This improves efficiency at the higher input voltages by reducing power dissipation in the modules. INTVCC (Pin A7): This pin is for additional decoupling of the 5V internal regulator . PLLIN (Pin A8): External Clock Synchronization Input to the Phase Detector . This pin is internally terminated to SGND with a 50k resistor . Apply a clock with high level above 2V and below INTV CC. See the Applications Infor- mation section. FCB (Pin M12): Forced Continuous Input. Connect this pin to SGND to force continuous synchronization operation at low load, to INTV CC to enable discontinuous mode opera- tion at low load or to a resistive divider from a secondary output when using a secondary winding. TRACK/SS (Pin A9): Output Voltage T racking and Soft-Start Pin. When the module is configured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. A soft-start capacitor can be used for soft-start turn-on as a standalone regulator . Slave operation is performed by putting a resistor divider from the master output to ground, and connecting the center point of the divider to this pin. See the Applications Information section. MPGM (Pins A12, B11): Programmable Margining Input. A resistor from these pins to ground sets a current that is equal to 1.18V/R. This current multiplied by 10kW will equal a value in millivolts that is a percentage of the 0.6V reference voltage. See the Applications Information section. To parallel L TM4606s, each requires an individual MPGM resistor . Do not tie MPGM pins together . f SET (Pin B12): Frequency set internally to 800kHz in continuous conducting mode at light load. An external resistor can be placed from this pin to ground to increase frequency. This pin can be decoupled with a 1000pF capacitor . See the Applications Information section for frequency adjustment. V FB (Pin F12): The Negative Input of the Error Amplifier . Internally, this pin is connected to VOUT with a 60.4k preci- sion resistor . Different output voltages can be programmed with an additional resistor between the VFB and SGND pins. See the Applications Information section. MARG0 (Pin C12): LSB Logic Input for the Margining Function. Together with the MARG1 pin, the MARG0 pin will determine if a margin high, margin low, or no margin state is applied. The pin has an internal pulldown resistor of 50k. See the Applications Information section. MARG1 (Pins C11, D12): MSB Logic Input for the Margin- ing Function. Together with the MARG0 pin, the MARG1 pins will determine if a margin high, margin low, or no margin state is applied. The pins have an internal pull-down resistor of 50k. See the Applications Information section. SGND (Pins D9, H12): Signal Ground Pins. These pins connect to PGND at output capacitor point. COMP (Pins A11, D11): Current Control Threshold and Error Amplifier Compensation Point. The current com- parator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.7V corresponding to zero sense voltage (zero current). PGOOD (Pin G12): Output Voltage Power Good Indicator . Open-drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point, after a 25µs power bad mask timer expires.

RUN (Pins A10, B9): Run Control Pins. A voltage above 1.9V will turn on the module, and below 1V will turn off the module. A programmable UVLO function can be ac- complished with a resistor from V IN to this pin that has a 5.1V Zener to ground. Maximum pin voltage is 5V . pin FuncTions NC (Pins J12, K12, L12): These pads must be left floating (electrical open circuit) and are used for increased solder integrity strength. MARG1 DRVCC VFB PGOOD SGND NC NC NC FCB VIN BANK 1 VD PGND BANK 2 VOUT BANK 3 fSET MARG0 RUN COMP MPGM PLLIN INTVCC TRACK/SS SGND L K J H G F E D C BMA

TA = 25°C. Use Figure 1 configuration. Figure 1. Simplified Block Diagram

4606 F01

The L TM4606 is a standalone non-isolated switching mode DC/DC power supply. It can deliver up to 6A of DC output current with some external input and output capacitors. This module provides precisely regulated output voltage programmable via one external resistor from 0.6V DC to 5.0VDC over a 4.5V to 28V input voltage range. The typical application schematic is shown in Figure 20. The L TM4606 has an integrated constant on-time current mode regulator , ultralow RDS(ON) FETs with fast switch- ing speed and integrated Schottky diodes. With current mode control and internal feedback loop compensation, the L TM4606 module has sufficient stability margins and good transient performance under a wide range of operat- ing conditions and with a wide range of output capacitors, even all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limiting. Besides, foldback current limiting is provided in an overcurrent condition while V FB drops. Internal over- voltage and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. Furthermore, in an overvoltage condition, internal top FET M1 is turned off and bottom FET M2 is turned on and held on until the overvoltage condition clears. Input filter and noise cancellation circuits reduce the noise coupling to I/O sides, and ensure the electromagnetic interference (EMI) to meet EN55022 Class B limits. Pulling the RUN pin below 1V forces the controller into its shutdown state, turning off both M1 and M2. At low load currents, discontinuous mode (DCM) operation can be enabled to achieve higher efficiency compared to continu- ous mode (CCM) by setting the FCB pin higher than 0.6V . When the DRV CC pin is connected to INTVCC an integrated 5V linear regulator powers the internal gate drivers. If a 5V external bias supply is applied on the DRVCC pin, then an efficiency improvement will occur due to the reduced power loss in the internal linear regulator . This is especially true at the higher input voltage range. The MPGM, MARG0 and MARG1 pins are used to sup- port voltage margining, where the percentage of margin is programmed by the MPGM pin, and the MARG0 and MARG1 selected margining. The PLLIN pin provides fre- quency synchronization of the device to an external clock. The TRACK/SS pin is used for power supply tracking and soft-start programming.

mined by the maximum load current and output voltage. for a particular application. The PWM controller has an internal 0.6V reference voltage. Table 1. RFB Standard 1% Resistor Values vs VOUT RPGM resistor on the MPGM pin programs the current.

  • VOUT where %V OUT is the percentage of V OUT you want to margin, and VOUT(MARGIN) is the margin quantity in volts: RPGM = VOUT 0.6V
  • 1.18V VOUT(MARGIN)
  • 10k where RPGM is the resistor value to place on the MPGM pin to ground. The output margining will be ± margining of the value. This is controlled by the MARG0 and MARG1 pins. See the truth table below: MARG1 MARG0 MODE LOW LOW NO MARGIN LOW HIGH MARGIN UP HIGH LOW MARGIN DOWN HIGH HIGH NO MARGIN Input Capacitors and Input EMI Noise Attenuation The L TM4606 is designed to achieve low input conducted EMI noise due to the fast switching of turn-on and turn-off. In the L TM4606, a high frequency inductor is integrated to the input line for noise attenuation. V D and V IN pins are available for external input capacitors to form a high frequency π filter . As shown in Figure 19, the ceramic capacitor C1 on the V D pins is used to handle most of the RMS current into the converter , so careful attention is needed for capacitor C1 selection. For a buck converter , the switching duty cycle can be estimated as: D = VOUT VIN
  • D • 1– D( ) In the above equation, η is the estimated efficiency of the power module. Note the capacitor ripple current ratings are often based on temperature and hours of life. This makes it advisable to properly derate the capacitor , or choose a capacitor rated at a higher temperature than required. Always contact the capacitor manufacturer for derating requirements. In a typical 6A output application, one or two very low ESR X5R or X7R, 10µF ceramic capacitors are recom- mended for C1. This decoupling capacitor should be placed directly adjacent to the module V D pins in the PCB layout to minimize the trace inductance and high frequency AC noise. Each 10µF ceramic is typically good for 2 to 3 amps of RMS ripple current. Refer to your ceramics capacitor catalog for the RMS current ratings. To attenuate high frequency noise, extra input capacitors should be connected to the V IN pads and placed before the high frequency inductor to form the π filter . One of these low ESR ceramic capacitors is recommended to be placed close to the connection into the system board. A large bulk 100µF capacitor is only needed if the input source impedance is compromised by long inductive leads or traces. Figure 2 shows the radiated EMI test results to applicaTions inForMaTion meet EN55022 Class B. For different applications, input capacitance may be varied to meet different radiated EMI limits. Output Capacitors The L TM4606 is designed for low output voltage ripple. The bulk output capacitors defined as C OUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. C OUT can be a low ESR tantalum capacitor , low ESR polymer capacitor or ceramic capacitor . The typical capacitance is 200µF if all ceramic output capacitors are used. Additional output filtering may be required by the system designer , if further reduction of output ripple or dynamic transient spike is required. Table 2 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 3A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance to maximize transient performance. Multiphase operation with multiple L TM4606 devices in parallel will lower the effective output ripple current due to the phase interleaving operation. Refer to Figure 3 for the normalized output ripple current versus the duty cycle. Figure 3 provides a ratio of peak-to-peak output ripple current to the inductor ripple current as functions of duty cycle and the number of paralleled phases. Pick the corresponding duty cycle and the number of phases to get the correct output ripple current value. For example, each phase’s inductor ripple current DIr at zero duty cycle is ~2.5A for a 12V to 2.5V design. The duty cycle is about 0.21. The 2-phase curve has a ratio of ~0.58 for a duty cycle of 0.21. This 0.58 ratio of output ripple current to the inductor ripple current DIr at 2.5A equals ~1.5A of the output ripple current (∆I L). The output voltage ripple has two components that are related to the amount of bulk capacitance and effective series resistance (ESR) of the output bulk capacitance. The equation is: DVOUT(P −P) ≈ DIL 8 • f • N • COUT ⎟+ESR • DIL where f is the frequency and N is the number of paralleled phases. FREQUENCY (MHz) 128.1 226.2 324.3 520.5 422.4 618.6 716.7 814.8 912.9 1010

4606 F02

Figure 2. Radiated Emission Scan with 12VIN

in steady-state operation, but also in transient. of its full current limit value. the regulator or track it to a different power supply. time, so that another regulator can be easily tracked to it.

4612 F05

Figure 3. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI

driven with a logic input not to exceed 5V .

  • 1.5V where R2 is the bottom resistor of the divider , R1 is the top resistor of the divider . Power Good The PGOOD pin is an open-drain pin that can be used to monitor valid output voltage regulation. This pin monitors a ±10% window around the regulation point and tracks with margining. COMP Pin This pin is the external compensation pin. The module has already been internally compensated for most output voltages. Table 2 is provided for most application require- ments. L TpowerCAD™ is available for other control loop optimization. FCB Pin The FCB pin determines whether the bottom MOSFET remains on when current reverses in the inductor . Tying this pin above its 0.6V threshold enables discontinuous operation where the bottom MOSFET turns off when in- ductor current reverses. FCB pin below the 0.6V threshold forces continuous synchronous operation, allowing current to reverse at light loads and maintain low output ripple. applicaTions inForMaTion PGOOD VD RUN COMP INTV CC DRVCC TRACK/SS fSET VOUT VFB FCB MARG0 MARG1 MPGM TRACK CONTROL PLLIN L TM4606 19.1k 100k 19.1k MASTER OUTPUT R2 60.4k C OUT SLAVE OUTPUT 2.5V4606 F04 CIN VIN PGNDSGND VIN

Figure 4. Output Voltage Coincident T racking Figure 5. Coincident T racking Characteristics

4606 F05

The power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector . This allows the internal top MOSFET turn-on to be locked to the rising edge of the external clock. The frequency range is ±30% around the operating frequency. A pulse detection circuit is used to detect a clock on the PLLIN pin to turn on the phase lock loop. The pulse width of the clock has to be at least 400ns and 2V in amplitude. During the start-up of the regulator , the phase-lock loop function is disabled. INTV CC and DRVCC Connection An internal low dropout regulator produces an internal 5V supply that powers the control circuitry and DRV CC for driving the internal power MOSFETs. Therefore, if the system does not have a 5V power rail, the L TM4606 can be directly powered by Vin. The gate driver current through the LDO is about 20mA. The internal LDO power dissipation can be calculated as: PLDO_LOSS = 20mA • (VIN – 5V) The L TM4606 also provides an external gate driver voltage pin DRVCC. If there is a 5V rail in the system, it is recom- mended to connect DRVCC pin to the external 5V rail. This is especially true for higher input voltages. Do not apply more than 6V to the DRV CC pin. A 5V output can be used to power the DRVCC pin with an external circuit as shown in Figure 18. Parallel Operation of the Module The L TM4606 device is an inherently current mode con- trolled device. Parallel modules will have very good current sharing. This will balance the thermals on the design. The voltage feedback equation changes with the variable N as modules are paralleled: VOUT = 0.6V 60.4k N + RFB RFB N is the number of paralleled modules. Thermal Considerations and Output Current Derating In different applications, L TM4606 operates in a variety of thermal environments. The maximum output current is limited by the environment thermal condition. Sufficient cooling should be provided to help ensure reliable opera- tion. When the cooling is limited, proper output current derating is necessary, considering ambient temperature, airflow, input/output condition, and the need for increased reliability. The power loss curves in Figures 6 and 7 can be used in coordination with the load current derating curves in Figures 8 to 15 for calculating an approximate θ JA for the module. The graphs delineate between no heat sink, and a BGA heat sink. Each of the load current derating curves will lower the maximum load current as a function of the increased ambient temperature to keep the maximum junc- tion temperature of the power module at 125°C maximum. Each of the derating curves and the power loss curve that corresponds to the correct output voltage can be used to solve for the approximate θ JA of the condition. Each figure has three curves that are taken at three different air flow conditions. Tables 3 and 4 provide the approximate θ JA for Figures 8 to 15. A complete explanation of the thermal characteristics is provided in the thermal application note AN110. Safety Considerations The L TM4606 modules do not provide isolation from V IN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. Radiated EMI Noise High radiated EMI noise is a disadvantage for switching regulators by nature. Fast switching turn-on and turn-off make large di/dt change in the converters, which act as the radiation sources in most systems. The L TM4606 integrates the feature to minimize the radiated EMI noise for applications with low noise requirements. Optimized gate driver for the MOSFET and noise cancellation network are installed inside the L TM4606 to achieve low radiated EMI noise. Figure 16 shows a typical example for L TM4606 to meet the Class B of EN55022 radiated emission limit.

Figure 6. 1.5V Power Loss Figure 7. 3.3V Power Loss Figure 8. No Heat Sink Figure 9. BGA Heat Sink Figure 10. No Heat Sink Figure 11. BGA Heat Sink

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0 MAXIMUM LOAD CURRENT (A)1

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Figure 12. No Heat Sink Figure 13. BGA Heat Sink Figure 15. BGA Heat SinkFigure 14. No Heat Sink

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Figure 16. Radiated Emission Scan with 12VIN

Table 2. Output Voltage Response vs Component Matrix (Refer to Figure 20)

Table 3. 1.5V Output Table 4. 3.3V Output siderations are still necessary. PCB conduction loss and thermal stress.

  • Place high frequency ceramic input and output capaci- tors next to the VD, PGND and VOUT pins to minimize high frequency noise.
  • Place a dedicated power ground layer underneath the unit.
  • Use round corners for the PCB copper layer to minimize the radiated noise.
  • To minimize the EMI noise and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers on different locations.
  • Do not put vias directly on pads, unless they are capped.
  • Use a separated SGND ground copper area for com- ponents connected to signal pins. Connect the SGND to PGND underneath the unit. Place one or more high frequency ceramic capacitors close to the connection into the system board. Figure 17 gives a good example of the recommended layout. For load current below 3A, decouple the input and output grounds. Use vias to connect GND pads to the bottom layer , then connect to the right side of the module as the output GND. SIGNAL GND VOUT VIN GND COUT CIN CIN COUT

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Figure 17. Recommended PCB Layout

The L TM4606 is designed to typically operate at 800kHz across most input conditions. The fSET pin is typically left open or decoupled with an optional 1000pF capacitor . The switching frequency has been optimized for maintaining constant output ripple noise over most operating ranges. The 800kHz switching frequency and the 400ns minimum off time can limit operation at higher duty cycles like 5V to 3.3V , and produce excessive inductor ripple currents for lower duty cycle applications like 28V to 5V . Example for 5V Output L TM4606 minimum on-time = 100ns; tON = ((4.8 • 10pF)/IfSET) L TM4606 minimum off-time = 400ns; tOFF = t – tON, where t = 1/Frequency Duty Cycle = tON/t or VOUT/VIN Equations for setting frequency: IfSET = (VIN/(3 • RfSET)), where the internal RfSET is 41.2k. For 28V input operation, IfSET = 227µA. tON = ((4.8 • 10pF)/ IfSET), tON = 211ns. Frequency = (VOUT/(VIN • tON)) = (5V/ (28 • 211ns)) ~ 850kHz. The inductor ripple current begins to get high at the higher input voltages due to a larger volt- age across the inductor . The current ripple is ~5A at 20% duty cycle if the integrated inductor is 1µH. The inductor ripple current can be lowered at the higher input voltages by adding an external resistor from f SET to ground to increase the switching frequency. A 4A ripple current is chosen, and the total peak current is equal to 1/2 of the 4A ripple current plus the output current. For 5V output, current is limited to 5A, so the total peak current is less than 7A. This is below the 8A peak specified value. A 150k resistor is placed from f SET to ground, and the parallel combination of 150k and 41.2k equates to 32.3k. The I fSET calculation with 32.3k and 28V input voltage equals 289µA. This equates to a tON of 166ns. This will increase the switching frequency from 850kHz to ~1MHz for the 28V to 5V conversion. The minimum on time is above 100ns at 28V input. Since the switching frequency is approximately constant over input and output conditions, then the lower input voltage range is limited to 8V for the 1MHz operation due to the 400ns minimum off time. Equation: t ON = (VOUT/VIN) • (1/ Frequency) equates to a 375ns on time, and a 400ns off time. Figure 18 shows an operating range of 10V to 28V for 1MHz operation with a 150k resistor to ground, and an 8V to 16V operating range for f SET floating. These modifications are made to provide wider input voltage ranges for the 5V output designs while limiting the inductor ripple current, and maintaining the 400ns minimum off-time. Example for 3.3V Output L TM4606 minimum on-time = 100ns; tON = ((3.3 • 10pF)/IfSET) L TM4606 minimum off-time = 400ns; tOFF = t – tON, where t = 1/Frequency Duty Cycle (DC) = tON/t or VOUT/VIN Equations for setting frequency: IfSET = (VIN/(3 • RfSET)), for 28V input operation, I fSET = 227µA, tON = ((3.3 • 10pF)/IfSET), tON = 145ns, where the internal RfSET is 41.2k. Frequency = (V OUT/(VIN • tON)) = (3.3V/(28 • 145ns)) ~ 810kHz. The minimum on-time and minimum-off time are within specification at 146ns and 1089ns. But the 4.5V minimum input for converting 3.3V output will not meet the minimum off-time specification of 400ns. t ON = 905ns, Frequency = 810kHz, tOFF = 329ns. Solution Lower the switching frequency at lower input voltages to allow for higher duty cycles, and meet the 400ns mini- mum off-time at 4.5V input voltage. The off-time should be about 500ns with 100ns guard band. The duty cycle for (3.3V/4.5V) = ~73%. Frequency = (1 – DC)/t OFF or (1 – 0.73)/500ns = 540kHz. The switching frequency needs to be lowered to 540kHz at 4.5V input. t ON = DC/ frequency, or 1.35µs. The f SET pin voltage compliance is 1/3 of VIN, and the IfSET current equates to 36µA with the internal 41.2k. The IfSET current needs to be 24µA for 540kHz operation. A resistor can be placed from VOUT to fSET to lower the effective IfSET current out of the fSET pin to 24µA. The f SET pin is 4.5V/3 =1.5V and V OUT = 3.3V , therefore a 150k resistor will source 12µA into the f SET node and lower the IfSET current to 24µA. This enables the 540kHz operation and the 4.5V to 28V input operation for down converting to 3.3V output as shown in Figure 19. The frequency will scale from 540kHz to 950kHz over this input range. This provides for an effective output current of 5A over the input range. applicaTions inForMaTion

Figure 19. 3.3V at 5A Design Figure 18. 10V to 28VIN, 5V at 5A Design

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Figure 21. 2-Phase, Parallel 2.5V at 12A Design Figure 20. Typical 4.5V to 28VIN, 2.5V at 6A Design

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Figure 22. 2-Phase, 3.3V and 2.5V Outputs at 6A with T racking and Margining

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Figure 23. 2-Phase, 1.8V and 1.5V Outputs at 6A with T racking and Margining

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V IN VIN VIN VIN VIN VIN V IN VIN VIN VIN VIN VIN V IN VIN VIN VIN VIN VIN Pin Assignment Tables (Arranged by Pin Function) PIN NAME PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND G10 G11 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND H10 H11 PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PIN NAME J10 J11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT K10 K11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT L10 L11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT M10 M11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT PIN NAME A10 A11 A12 INTV CC PLLIN TRACK/SS RUN COMP MPGM B10 B11 B12 V D RUN MPGM f SET C10 C11 C12 V D DRV CC MARG1 MARG0 D10 D11 D12 SGND COMP MARG1 E10 E11 E12 DRV CC DRVCC F10 F11 F12 V FB G12 PGOOD H12 SGND J12 NC K12 NC L12 NC M12 FCB

133-Lead (15mm × 15mm × 2.82mm) (Reference L TC DWG # 05-08-1766 Rev Ø) L K J H G F E D C BM A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 133 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE SYMBOL aaa bbb eee TOLERANCE 0.10 0.10 0.05 2.72 – 2.92 DETAIL B DETAIL B SUBSTRATE MOLD CAP 0.27 – 0.37 2.45 – 2.55 bbb Z Z BSC PACKAGE TOP VIEW BSC PAD 1 CORNER X Y aaa Z aaa Z DETAIL A 13.97 BSC 1.27 BSC 13.97 BSC 0.12 – 0.28 PACKAGE BOTTOM VIEW C(0.30) PAD 1 PADS SEE NOTES DETAIL A 0.630 ±0.025 SQ. 133x S Y X eee SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 LGA 133 1107 REV Ø L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1”

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER A 3/10 Change to Features. Change to Absolute Maximum Ratings. Changes to Electrical Characteristics. Changes to Related Parts. 2, 3 B 3/11 Text updated throughout the data sheet. Graph replaced on the front page, Figure 2, and Figure 16. Added value of 1µH to inductor on Figure 1. Updated Related Parts. 1-28 1, 12, 17

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com  LINEAR TECHNOLOGY CORPORATION 2008 LT 0311 REV B • PRINTED IN USA relaTeD parTs package phoTograph PART NUMBER DESCRIPTION COMMENTS L TM4601/ L TM4601A 12A DC/DC µModule Regulator with PLL, Output T racking/Margining and Remote Sensing Synchronizable, PolyPhase Operation, L TM4601-1/L TM4601A-1 Version Has No Remote Sensing, LGA Package L TM4618 6A DC/DC µModule Regulator with PLL, Output T racking 4.5V ≤ V IN ≤ 26.5V , 0.8V ≤ VOUT ≤ 5V , Synchronizable, 9mm × 15mm × 4.3mm L TM4604A Low V IN 4A DC/DC µModule Regulator 2.375V ≤ VIN ≤ 5.5V , 0.8V ≤ VOUT ≤ 5V , 9mm × 15mm × 2.3mm LGA Package L TM4608A Low V IN 8A DC/DC µModule Regulator 2.375V ≤ VIN ≤ 5.5V , 0.6V ≤ VOUT ≤ 5V , 9mm × 15mm × 2.8mm LGA Package L TM4612 Low Noise 5A, 15V OUT DC/DC µModule Regulator Low Noise, with PLL, Output T racking and Margining, L TM4606 Pin-Compatible L TM4627 15A DC/DC µModule Regulator 4.5V ≤ VIN ≤ 20V , 0.6V ≤ VOUT ≤ 5V , ±1.5% Total DC Output Accuracy, 15mm × 15mm × 4.32mm LGA Package EN55022 Class B Certified DC/DC µModule Regulators L TM8022/ L TM8023 36VIN, 1A and 2A DC/DC µModule Regulators Pin Compatible, 4.5V ≤ V IN ≤ 36V , 9mm × 11.25mm × 2.8mm LGA Package L TM8031/ L TM8032 1A, 2A EMC DC/DC µModule Regulators EN55022 Class B Compliant, 3.6V ≤ V IN ≤ 36V , 0.8V ≤ VOUT ≤ 10V , Pin Compatible, 9mm × 15mm × 2.82mm LGA Package L TM8033 3A EMC DC/DC µModule Regulator 3.6V ≤ VIN ≤ 36V , 0.8V ≤ VOUT ≤ 24V , 11.25mm × 15mm × 4.32mm LGA Package