LTM4603

LTM4603 LINER | Alldatasheet

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Technical content

6A DC/DC µModule with PLL, Output Tracking and Margining ■ Telecom and Networking Equipment ■ Servers ■ Industrial Equipment ■ Point of Load Regulation ■ Complete Switch Mode Power Supply ■ Wide Input Voltage Range: 4.5V to 20V ■ 6A DC Typical, 8A Peak Output Current ■ 0.6V to 5V Output Voltage ■ Output Voltage Tracking and Margining ■ Remote Sensing for Precision Regulation (LTM4603 Only) ■ Typical Operating Frequency: 1MHz ■ PLL Frequency Synchronization ■ 1.5% Regulation ■ Current Foldback Protection (Disabled at Start-Up) ■ Pin Compatible with the LTM4601 ■ Pb-Free (e4) RoHS Compliant Package with Gold Finish Pads ■ Ultrafast Transient Response ■ Current Mode Control ■ Up to 93% Effi ciency at 5VIN, 3.3VOUT ■ Programmable Soft-Start ■ Output Overvoltage Protection ■ Small Footprint, Low Profi le (15mm × 15mm × 2.8mm) Surface Mount LGA Package 1.5V/6A Power Supply with 4.5V to 20V Input APPLICATIO SU FEATURES DESCRIPTIO U TYPICAL APPLICATIO U Effi ciency vs Load Current with 12VIN The LTM®4603 is a complete 6A step-down switch mode DC/DC power supply with onboard switching controller, MOSFETs, inductor and all support components. The µModule TM is housed in a small surface mount 15mm × 15mm × 2.8mm LGA package. Operating over an input voltage range of 4.5 to 20V, the LTM4603 supports an output voltage range of 0.6V to 5V as well as output voltage tracking and margining. The high effi ciency design deliv- ers 6A continuous current (8A peak). Only bulk input and output capacitors are needed to complete the design. The low profi le (2.8mm) and light weight (1.73g) package easily mounts on the unused space on the back side of PC boards for high density point of load regulation. The µModule can be synchronized with an external clock for reducing undesirable frequency harmonics and allows PolyPhase ® operation for high load currents. A high switching frequency and adaptive on-time current mode architecture deliver a very fast transient response to line and load changes without sacrifi cing stability. An onboard remote sense amplifi er can be used to accurately regulate an output voltage independent of load current. The onboard remote sense amplifi er is not available in the LTM4603-1. The LTM4603/LTM4603-1 are pin compatible with the 12A LTM4601/LTM4601-1. , LT, LTC, LTM and PolyPhase are registered trademarks of Linear Technology Corporation. µModule is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS– PGOOD RUN COMP INTV CC DRVCC MPGM TRACK/SSPLLIN LTM4603 ON/OFF 392k 13.3k MARGIN CONTROL COUT

4603 TA01a

1.5V CLOCK SYNC TRACK/SS CONTROL 100pF CIN VIN fSETPGNDSGND 5% MARGIN VIN 4.5V TO 20V OUTPUT CURRENT (A) EFFICIENCY (%)0.60 0.90 0.95 1.00 2 4 5

4603 TA01b

0.50 0.45 0.80 0.70 0.55 0.85 0.40 0.75 0.65 1 3 6 7 12VIN, 1.2VOUT 12VIN, 1.5VOUT 12VIN, 1.8VOUT 12VIN, 2.5VOUT 12VIN, 3.3VOUT 12VIN, 5VOUT

INTVCC, DRVCC, VOUT_LCL, VOUT (VOUT ≤ 3.3V PLLIN, TRACK/SS, MPGM, MARG0, MARG1, PGOOD, f V Operating Temperature Range (Note 2) ... –40°C to 85°C (Note 1) The ● denotes the specifi cations which apply over the –40°C to 85°C temperature range, otherwise specifi cations are at TA = 25°C, VIN = 12V. Per typical application (front page) confi guration.

ELECTRICAL CHARACTERISTICS

ABSOLUTE AXI U RATI GSW WW U PACKAGE/ORDER I FOR ATIOUU W SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN(DC) Input DC Voltage ● 4.5 20 V VOUT(DC) Output Voltage C IN = 10µF ×2, COUT = 2×, 100µF/X5R/ Ceramic V IN = 5V, VOUT = 1.5V, IOUT = 0A V IN = 12V, VOUT = 1.5V, IOUT = 0A 1.478 1.478 1.5 1.5 1.522 1.522 V V Input Specifi cations VIN(UVLO) Undervoltage Lockout Threshold I OUT = 0A 3.2 4 V IINRUSH(VIN) Input Inrush Current at Startup I OUT = 0A. VOUT = 1.5V V IN = 5V V IN = 12V 0.6 0.7 A A IQ(VIN,NOLOAD) Input Supply Bias Current V IN = 12V, VOUT = 1.5V, No Switching VIN = 12V, VOUT = 1.5V, Switching Continuous V IN = 5V, VOUT = 1.5V, No Switching VIN = 5V, VOUT = 1.5V, Switching Continuous Shutdown, RUN = 0, V IN = 12V 3.8 2.5 mA mA mA mA µA MARG1 DRVCC VFB PGOOD SGND V OSNS+/NC2* DIFFVOUT/NC3* VOUT_LCL VOSNS–/NC1* VIN PGND VOUT fSET MARG0 RUN COMP MPGM PLLIN INTVCC TRACK/SS LGA PACKAGE 118-LEAD (15mm /KB4 15mm /KB4 2.8mm) TOP VIEW TJMAX = 125°C, θJA = 15°C/W, θJC = 6°C/W, θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS, WEIGHT = 1.7g *LTM4603-1 Only ORDER PART NUMBER LGA PART MARKING* LTM4603EV#PBF LTM4603IV#PBF LTM4603EV-1#PBF LTM4603IV-1#PBF LTM4603V LTM4603V LTM4603V-1 LTM4603V-1 Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IS(VIN) Input Supply Current V IN = 12V, VOUT = 1.5V, IOUT = 6A VIN = 12V, VOUT = 3.3V, IOUT = 6A VIN = 5V, VOUT = 1.5V, IOUT = 6A 0.85 1.78 2.034 A A A INTV CC VIN = 12V, RUN > 2V No Load 4.7 5 5.3 V Output Specifi cations I OUTDC Output Continuous Current Range (See Output Current Derating Curves for Different V IN, VOUT and TA) VIN = 12V, VOUT = 1.5V 0 6 A VOUT(NOM) – VOUT(ΔLINE) VOUT(NOM) Line Regulation Accuracy V OUT = 1.5V, IOUT = 0A, VIN = 4.5V to 20V ● 0.3 % VOUT(NOM) – VOUT(ΔLOAD) VOUT(NOM) Load Regulation Accuracy V OUT = 1.5V, IOUT = 0A to 6A V IN = 12V, with Remote Sense Amp V IN = 12V, LTM4603-1 0.25 0.5 VOUT(AC) Output Ripple Voltage I OUT = 0A, COUT = 2×, 100µF/X5R/Ceramic VIN = 12V, VOUT = 1.5V VIN = 5V, VOUT = 1.5V mVP-P mVP-P fS Output Ripple Voltage Frequency I OUT = 3A, VIN = 12V, VOUT = 1.5V 1000 kHz ΔVOUT(START) Turn-On Overshoot, TRACK/SS = 10nF COUT = 2×, 100µF/X5R/Ceramic, VOUT = 1.5V, IOUT = 0A VIN = 12V VIN = 5V mV mV tSTART Turn-On Time, TRACK/SS = Open C OUT = 2×, 100µF/X5R/Ceramic, VOUT = 1.5V, IOUT = 1A Resisitive Load VIN = 12V VIN = 5V 0.5 0.7 ms ms ΔVOUTLS Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load, COUT = 2 × 22µF/Ceramic, 470µF, 4V Sanyo POSCAP V IN = 12V VIN = 5V mV mV tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 10% of Full Load VIN = 12V 25 µs IOUTPK Output Current Limit C OUT = 2×, 100µF/X5R/Ceramic VIN = 12V, VOUT = 1.5V VIN = 5V, VOUT = 1.5V A A Remote Sense Amp (LTM4603 Only, Not Supported in the LTM4603-1) (Note 3) VOSNS+, VOSNS– CM Range Common Mode Input Voltage Range V IN = 12V, RUN > 2V 0 INTV CC – 1 V DIFFVOUT Range Output Voltage Range V IN = 12V, DIFF OUT Load = 100k 0 INTV CC V VOS Input Offset Voltage Magnitude 1.25 mV AV Differential Gain 1 V/V GBP Gain Bandwidth Product 3 MHz SR Slew Rate 2 V/µs R IN Input Resistance V OSNS+ to GND 20 k Ω CMRR Common Mode Rejection Ratio 100 dB The ● denotes the specifi cations which apply over the –40°C to 85°C temperature range, otherwise specifi cations are at TA = 25°C, VIN = 12V. Per typical application (front page) confi guration.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Control Stage V FB Error Amplifi er Input Voltage Accuracy IOUT = 0A, VOUT = 1.5V ● 0.594 0.6 0.606 V VRUN RUN Pin On/Off Threshold 1 1.5 1.9 V ISS/TRACK Soft-Start Charging Current V SS/TRACK = 0V –1 –1.5 –2 µA tON(MIN) Minimum On Time (Note 4) 50 100 ns tOFF(MIN) Minimum Off Time (Note 4) 250 400 ns RPLLIN PLLIN Input Resistance 50 k Ω IDRVCC Current into DRVCC Pin V OUT = 1.5V, IOUT = 1A, Frequency = 1MHz, DRVCC = 5V 18 25 mA RFBHI Resistor Between VOUT and VFB 60.098 60.4 60.702 k Ω VMPGM Margin Reference Voltage 1.18 V VMARG0, VMARG1 MARG0, MARG1 Voltage Thresholds 1.4 V PGOOD Output ΔV FBH PGOOD Upper Threshold V FB Rising 7 10 13 % ΔVFBL PGOOD Lower Threshold V FB Falling –7 –10 –13 % ΔVFB(HYS) PGOOD Hysteresis V FB Returning 1.5 3 % VPGL PGOOD Low Voltage I PGOOD = 5mA 0.15 0.4 V The ● denotes the specifi cations which apply over the –40°C to 85°C temperature range, otherwise specifi cations are at TA = 25°C, VIN = 12V. Per typical application (front page) confi guration. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4603E/LTM4603-1 are guaranteed to meet performance specifi cations from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4603E/LTM4603-1 are guaranteed and tested over the –40°C to 85°C temperature range. Note 3: Remote sense amplifi er recommended for ≤3.3V output. Note 4: 100% tested at wafer level only.

Effi ciency vs Load Current with 5VIN TYPICAL PERFOR A CE CHARACTERISTICSUW Effi ciency vs Load Current with 12VIN Effi ciency vs Load Current with 20V IN 1.2V Transient Response 1.5V Transient Response 2.5V Transient Response 3.3V Transient Res ponse (See Figure 18 for all curves) 1.8V Transient Response OUTPUT CURRENT (A)

0.50 EFFICIENCY (%)

0.55 0.65 0.70 0.75 1.00 0.85 2 4 5

4603 G01

0.60 0.90 0.95 0.80 1 3 6 7 5VIN, 0.6VOUT 5VIN, 1.2VOUT 5VIN, 1.5VOUT 5VIN, 1.8VOUT 5VIN, 2.5VOUT 5VIN, 3.3VOUT OUTPUT CURRENT (A) EFFICIENCY (%)0.60 0.90 0.95 1.00 2 4 5

4603 G02

0.50 0.45 0.80 0.70 0.55 0.85 0.40 0.75 0.65 1 3 6 7 12VIN, 1.2VOUT 12VIN, 1.5VOUT 12VIN, 1.8VOUT 12VIN, 2.5VOUT 12VIN, 3.3VOUT 12VIN, 5VOUT OUTPUT CURRENT (A) EFFICIENCY (%) 0.55 0.85 0.90 0.95 2 4 5

4603 G03

0.45 0.75 0.65 0.50 0.80 0.40 0.70 0.60 1 3 6 7 20VIN, 1.5VOUT 20VIN, 1.8VOUT 20VIN, 2.5VOUT 20VIN, 3.3VOUT 20VIN, 5VOUT LOAD STEP 1A/DIV VOUT 50mV/DIV 25µs/DIV

4603 G04

1.2V AT 3A/µs LOAD STEP COUT: 1x 22µF, 6.3V CERAMIC 1x 330µF, 4V SANYO POSCAP LOAD STEP 1A/DIV VOUT 50mV/DIV 25µs/DIV

4603 G05

1.5V AT 3A/µs LOAD STEP COUT: 1x 22µF, 6.3V CERAMIC 1x 330µF, 4V SANYO POSCAP LOAD STEP 1A/DIV VOUT 50mV/DIV 25µs/DIV

4603 G07

2.5V AT 3A/µs LOAD STEP COUT: 1x 22µF, 6.3V CERAMIC 1x 330µF, 4V SANYO POSCAP LOAD STEP 1A/DIV VOUT 50mV/DIV 25µs/DIV

4603 G08

3.3V AT 3A/µs LOAD STEP COUT: 1x 22µF, 6.3V CERAMIC 1x 330µF, 4V SANYO POSCAP LOAD STEP 1A/DIV VOUT 50mV/DIV 25µs/DIV

4603 G06

1.8V AT 3A/µs LOAD STEP COUT: 1x 22µF, 6.3V CERAMIC 1x 330µF, 4V SANYO POSCAP

TYPICAL PERFOR A CE CHARACTERISTICSUW (See Figure 18 for all curves) Start-Up, IOUT = 6A (Resistive Load)Start-Up, IOUT = 0A VIN to VOUT Step-Down Ratio VOUT 0.5V/DIV IIN 0.5A/DIV 1ms/DIV

4603 G09

VIN = 12V VOUT = 1.5V COUT = 1x 22µF, 6.3V CERAMIC 1x 330µF, 4V SANYO POSCAP SOFT-START = 3.9nF VOUT 0.5V/DIV IIN 0.5A/DIV 1ms/DIV

4603 G10

VIN = 12V VOUT = 1.5V COUT = 1x 22µF, 6.3V CERAMIC 1x 330µF, 4V SANYO POSCAP SOFT-START = 3.9nF VOUT 0.5V/DIV IIN 2A/DIV 100µs/DIV

4603 G11

VIN = 12V VOUT = 1.5V COUT = 1x 22µF, 6.3V CERAMIC 1x 330µF, 4V SANYO POSCAP SOFT-START = 3.9nF Short-Circuit Protection, IOUT = 0A Short-Circuit Protection, IOUT = 6A VOUT 0.5V/DIV IIN 2A/DIV 100µs/DIV

4603 G12

VIN = 12V VOUT = 1.5V COUT = 1x 22µF, 6.3V CERAMIC 1x 330µF, 4V SANYO POSCAP SOFT-START = 3.9nF INPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 3.0 4.0 5.5 5.0

4603 G13

2.0 1.0 2.5 3.5 4.5 1.5 0.5 42 86 12 14 1810 20 3.3V OUTPUT WITH 82.5k FROM VOUT TO fSET 5V OUTPUT WITH 150k RESISTOR ADDED FROM fSET TO GND 5V OUTPUT WITH NO RESISTOR ADDED FROM fSET TO GND 2.5V OUTPUT 1.8V OUTPUT 1.5V OUTPUT 1.2V OUTPUT

(See Package Description for Pin Assignment) VIN (Bank 1): Power Input Pins. Apply input voltage be- tween these pins and PGND pins. Recommend placing input decoupling capacitance directly between V IN pins and PGND pins. VOUT (Bank 3): Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and PGND pins. Review the fi gure below. PGND (Bank 2): Power ground pins for both input and output returns. V OSNS– (Pin M12): (–) Input to the Remote Sense Amplifi er. This pin connects to the ground remote sense point. The remote sense amplifi er is used for V OUT ≤3.3V. NC1 (Pin M12): No Connect on the LTM4603-1. VOSNS+ (Pin J12): (+) Input to the Remote Sense Amplifi er. This pin connects to the output remote sense point. The remote sense amplifi er is used for V OUT ≤3.3V. NC2 (Pin J12): No Connect on the LTM4603-1. DIFFVOUT (Pin K12): Output of the Remote Sense Ampli- fi er. This pin connects to the VOUT_LCL pin. NC3 (Pin K12): No Connect on the LTM4603-1. DRVCC (Pin E12): This pin normally connects to INTVCC for powering the internal MOSFET drivers. This pin can be biased up to 6V from an external supply with about 50mA capability, or an external circuit shown in Figure 16. This improves effi ciency at the higher input voltages by reducing power dissipation in the modules. INTV CC (Pin A7): This pin is for additional decoupling of the 5V internal regulator. PLLIN (Pin A8): External Clock Synchronization Input to the Phase Detector. This pin is internally terminated to SGND with a 50k resistor. Apply a clock above 2V and below INTV CC. See Applications Information. TRACK/SS (Pin A9): Output Voltage Tracking and Soft- Start Pin. When the module is confi gured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. A soft-start capacitor can be used for soft-start turn on as a stand alone regulator. Slave operation is performed by putting a resistor divider from the master output to the ground, and connecting the center point of the divider to this pin. See Applications Information. MPGM (Pin A12): Programmable Margining Input. A re- sistor from this pin to ground sets a current that is equal to 1.18V/R. This current multiplied by 10k Ω will equal a value in millivolts that is a percentage of the 0.6V refer- ence voltage. See Applications Information. To parallel LTM4603s, each requires an individual MPGM resistor. Do not tie MPGM pins together. f SET (Pin B12): Frequency Set Internally to 1MHz. An external resistor can be placed from this pin to ground to increase frequency. This pin can be decoupled with a 1000pF capacitor. See Applications Information for fre- quency adjustment. V FB (Pin F12): The Negative Input of the Error Ampli- fi er. Internally, this pin is connected to VOUT_LCL with a 60.4k precision resistor. Different output voltages can be MARG1 DRVCC VFB PGOOD SGND V OSNS+ (NC2, LTM4603-1) DIFFVOUT (NC3, LTM4603-1) VOUT_LCL VOSNS– (NC1, LTM4603-1) VIN BANK 1 PGND BANK 2 A B C D E F G H J K L M V OUT BANK 3 fSET MARG0 RUN COMP MPGM PLLIN INTVCC TRACK/SS 1234567 TOP VIEW 8 9 10 11 12

Figure 1. Simplifi ed LTM4603/LTM4603-1 Block Diagram SGND pins. See Applications Information. 50k. See Applications Information. 50k. See Applications Information. PGND at output capacitor point. sense voltage (zero current). PGOOD (Pin G12): Output Voltage Power Good Indicator. after a 25µs power bad mask timer expires. a 5.1V zener to ground. Maximum pin voltage is 5V. nects to this pin when remote sense amplifi er is used. VOUT_LCL can be connected to V OUT on the LTM4603-1.

4603 F01

W UDECOUPLI G REQUIRE E TSU SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CIN External Input Capacitor Requirement (VIN = 4.5V to 20V, VOUT = 1.5V) IOUT = 6A 20 µF COUT External Output Capacitor Requirement (VIN = 4.5V to 20V, VOUT = 1.5V) IOUT = 6A 100 200 µF T A = 25°C, VIN = 12V. Use Figure 1 confi guration. OPERATIOU Power Module Description The LTM4603 is a standalone nonisolated switching mode DC/DC power supply. It can deliver up to 6A of DC output current with few external input and output capacitors. This module provides precisely regulated output voltage programmable via one external resistor from 0.6V DC to 5.0VDC over a 4.5V to 20V wide input voltage. The typical application schematic is shown in Figure 18. The LTM4603 has an integrated constant on-time current mode regulator, ultralow RDS(ON) FETs with fast switching speed and integrated Schottky diodes. The typical switching frequency is 1MHz at full load. With current mode control and internal feedback loop compensation, the LTM4603 module has suffi cient stability margins and good transient performance under a wide range of operating conditions and with a wide range of output capacitors, even all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit. Besides, foldback current limiting is provided in an overcurrent condition while V FB drops. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. Furthermore, in an overvoltage condition, internal top FET Q1 is turned off and bottom FET Q2 is turned on and held on until the overvoltage condition clears. Pulling the RUN pin below 1V forces the controller into its shutdown state, turning off both Q1 and Q2. At low load current, the module works in continuous current mode by default to achieve minimum output voltage ripple. When DRV CC pin is connected to INTV CC an integrated 5V linear regulator powers the internal gate drivers. If a 5V external bias supply is applied on the DRV CC pin, then an effi ciency improvement will occur due to the reduced power loss in the internal linear regulator. This is especially true at the higher input voltage range. The LTM4603 has a very accurate differential remote sense amplifi er with very low offset. This provides for very accurate remote sense voltage measurement. The MPGM pin, MARG0 pin and MARG1 pin are used to sup- port voltage margining, where the percentage of margin is programmed by the MPGM pin, and the MARG0 and MARG1 select margining. The PLLIN pin provides frequency synchronization of the device to an external clock. The TRACK/SS pin is used for power supply tracking and soft-start programming.

Figure 18. External component selection is primarily requirements for a particular application. down ratio that can be achieved for a given input voltage. Table 1. Standard 1% Resistor Values RPGM resistor on the MPGM pin programs the current. The output margining will be ± margining of the value. long inductive leads or traces.

current for the external input capacitors. The LTM4603 is designed for low output voltage ripple. to maximize transient performance. output at 21% duty cycle is ~2.5A in Figure 3. Figure 2. Normalized Input RMS Ripple Current

4603 F02

4603 F03

Figure 3. Inductor Ripple Current vs Duty Cycle

current reduction as a function of paralleled phases. series resistance (ESR) of the output bulk capacitance. steady-state operation, but also in transient. of its full current limit value. Figure 4. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI

4603 F04

APPLICATIO S I FOR ATIOWU UU the ramp of the internal reference and the output voltage. The total soft-start time can be calculated as: tV V V C µSOFTSTART OUT MARGIN When the RUN pin falls below 1.5V, then the SS pin is reset to allow for proper soft-start control when the regulator is enabled again. Current foldback and force continuous mode are disabled during the soft-start process. The soft-start function can also be used to control the output ramp up time, so that another regulator can be easily tracked to it. Output Voltage Tracking Output voltage tracking can be programmed externally using the TRACK/SS pin. The output can be tracked up and down with another regulator. The master regulator’s output is divided down with an external resistor divider that is the same as the slave regulator’s feedback divider. Figure 5 shows an example of coincident tracking. Ratiometric modes of tracking can be achieved by selecting different resistor values to change the output tracking ratio. The master output must be greater than the slave output for the tracking to work. Figure 6 shows the coincident output tracking characteristics. Run Enable The RUN pin is used to enable the power module. The pin has an internal 5.1V zener to ground. The pin can be driven with a logic input not to exceed 5V. The RUN pin can also be used as an undervoltage lock out (UVLO) function by connecting a resistor divider from the input supply to the RUN pin: V RR R VUVLO = +12 2 15. Power Good The PGOOD pin is an open-drain pin that can be used to monitor valid output voltage regulation. This pin monitors a ±10% window around the regulation point and tracks with margining. COMP Pin This pin is the external compensation pin. The module has already been internally compensated for most output voltages. Table 2 is provided for most application require- ments. A spice model will be provided for other control loop optimization. PLLIN The power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector. This allows the internal top MOSFET turn-on to be locked Figure 5 Figure 6 VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS– PGOOD MPGM RUN COMP INTV CC DRVCC TRACK/SS TRACK CONTROL PLLIN LTM4603 RSET 40.2k 100k 40.2k MASTER OUTPUT 60.4k C OUT SLAVE OUTPUT

4603 F05

60.4k FROM VOUT TO VFB CIN VIN fSETPGNDSGND VIN OUTPUT VOLTAGE TIME

4603 F06

range is ±30% around the operating frequency of 1MHz. of the clock has to be at least 400ns and 2V in amplitude. η is the number of paralleled modules. maintained at 100°C or below for the derating curves. to a total of 124°C at the junction of the device.

4603 F07

4603 F08

4603 F09

4603 F11

Figure 10. BGA Heat Sink Figure 11. No Heat Sink Figure 12. BGA Heat Sink Figure 13. No Heat Sink Figure 14. BGA Heat Sink

4603 F10

4603 F12

4603 F13

4603 F14

Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 18)

provided to protect each unit from catastrophic failure.

• Use large PCB copper areas for high current path, in- cluding V IN, PGND and VOUT. It helps to minimize the PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capaci- tors next to the VIN, PGND and VOUT pins to minimize high frequency noise.
• Place a dedicated power ground layer underneath the unit.
• To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers.
• Do not put vias directly on pads.
• If vias are placed onto the pads, the the vias must be capped.
• Interstitial via placement can also be used if necessary.
• Use a separated SGND ground copper area for com- ponents connected to signal pins. Connect the SGND to PGND underneath the unit. Figure 15 gives a good example of the recommended layout. Frequency Adjustment The LTM4603 is designed to typically operate at 1MHz across most input conditions. The f SET pin is typically left open or decoupled with an optional 1000pF capacitor. The switching frequency has been optimized for maintaining constant output ripple noise over most operating ranges. The 1MHz switching frequency and the 400ns minimum off time can limit operation at higher duty cycles like 5V to 3.3V, and produce excessive inductor ripple currents for lower duty cycle applications like 20V to 5V. The 5V and 3.3V drop out curves are modifi ed by adding an external resistor on the f SET pin to allow for lower input voltage operation, or higher input voltage operation. SIGNAL GND VOUT VIN GND COUT CIN CIN COUT

4603 F15

Figure 15. Recommended Layout

APPLICATIO S I FOR ATIOWU UU Example for 5V Output LTM4603 minimum on-time = 100ns; t ON = ((4.8 • 10pf)/IfSET) LTM4603 minimum off-time = 400ns; t OFF = t – tON, where t = 1/Frequency Duty Cycle = t ON/t or VOUT/VIN Equations for setting frequency: I fSET = (VIN/(3 • RfSET)), for 20V operation, ISET = 201µA, tON = ((4.8 • 10pF)/IfSET), tON = 239ns, where the internal RfSET is 33.2k. Frequency = (VOUT/(VIN • tON)) = (5V/(20 • 239ns)) ~ 1MHz. The inductor ripple current begins to get high at the higher input voltages due to a larger voltage across the in- ductor. This is noted in the “Typical Inductor Ripple Current verses Duty Cycle graph” at ~4.5A at 25% duty cycle. The inductor ripple current can be lowered at the higher input voltages by adding an external resistor from f SET to ground to increase the switching frequency. A 3A ripple current is chosen, and the total peak current is equal to 1/2 of the 3A ripple current plus the output current. The 5V output current is limited to 5A, so total peak current is less than 6.5A. This is below the 7A peak specifi ed value. A 150k resistor is placed from f SET to ground, and the parallel combination of 150k and 33.2k equates to 27.2k. The IfSET calculation with 27.2k and 20V input voltage equals 245µA. This equates to a tON of 196ns. This will increase the switching frequency from 1MHz to ~1.28MHz for the 20V to 5V conversion. The minimum on time is above 100ns at 20V input. Since the switching frequency is approximately constant over input and output conditions, then the lower input voltage range is limited to 10V for the 1.28MHz operation due to the 400ns minimum off time. Equation: t ON = (VOUT/VIN)

• (1/Frequency) equates to a 382ns on time, and a 400ns off time. The “V IN to VOUT Step Ratio Curve” refl ects an operating range of 10V to 20V for 1.28MHz operation with a 150k resistor to ground, and an 8V to 16V operation for f SET fl oating. These modifi cations are made to provide wider input voltage ranges for the 5V output designs while limiting the inductor ripple current, and maintaining the 400ns minimum off time. Example for 3.3V Output LTM4603 minimum on-time = 100ns; t ON = ((3.3 • 10pF)/IfSET) LTM4603 minimum off-time = 400ns; t OFF = t – tON, where t = 1/Frequency Duty Cycle (DC) = t ON/t or VOUT/VIN Equations for setting frequency: I fSET = (VIN/(3 • RfSET)), for 20V operation, IfSET = 201µA, tON = ((3.3 • 10pf)/IfSET), tON = 164ns, where the internal RfSET is 33.2k. Frequency = (VOUT/(VIN • tON)) = (3.3V/(20
• 164ns)) ~ 1MHz. The minimum on-time and minimum- off time are within specifi cation at 164ns and 836ns. The 4.5V minimum input for converting 3.3V output will not meet the minimum off-time specifi cation of 400ns. t ON = 733ns, Frequency = 1MHz, tOFF = 267ns. Solution Lower the switching frequency at lower input voltages to allow for higher duty cycles, and meet the 400ns mini- mum off-time at 4.5V input voltage. The off-time should be about 500ns with 100ns guard band. The duty cycle for (3.3V/4.5) = ~73%. Frequency = (1 – DC)/t OFF, or (1 – 0.73)/500ns = 540kHz. The switching frequency needs to be lowered to 540kHz at 4.5V input. t ON = DC/frequency, or 1.35µs. The fSET pin voltage compliance is 1/3 of VIN, and the I fSET current equates to 45µA with the internal 33.2k. The I fSET current needs to be 24µA for 540kHz operation. A resistor can be placed from V OUT to fSET to lower the effective IfSET current out of the fSET pin to 24µA. The fSET pin is 4.5V/3 =1.5V and V OUT = 3.3V, therefore 82.5k will source 21µA into the f SET node and lower the IfSET current to 24µA. This enables the 540kHz operation and the 4.5V to 20V input operation for down converting to 3.3V output. The frequency will scale from 540kHz to 1.2MHz over this input range. This provides for an effective output current of 5A over the input range.

Figure 17. 3.3V at 5A Design Figure 16. 5V at 5A Design Without Differential Amplifi er

4603 F16

4603 F17

Figure 19. 2-Phase, 2.5V and 1.2V at 6A with Tracking Figure 18. Typical 4.5V-20VIN, 1.5V at 6A Design *C11 OPTIONAL TO REDUCE LC RINGING.

4603 F19

4603 F18

4-Phase, Four Outputs (3.3V, 2.5V, 1.8V and 1.5V) with Tracking VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS– PGOOD MPGM RUN COMP INTV CC DRVCC TRACK/SSPLLIN LTM4603 392k R11 100k R10 100k R18 19.1k C16 22µF 6.3V C14 10µF 25V 3.3V 2.5V AT 6A R23 60.4k C15 470µF 6.3VMARGIN CONTROL CLOCK SYNC 2 C18 100pF REFER TO TABLE 2 V IN fSETPGNDSGND 5% MARGIN +PGOOD 3.3V 8V TO 16V ON/OFF VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS– PGOOD MPGM RUN COMP INTV CC DRVCC TRACK/SSPLLIN LTM4603 R14 392k R16 100k R15 100k R13 40.2k C16 22µF 6.3V C14 10µF 25V 3.3V R25 60.4k C15 470µF 6.3VMARGIN CONTROL 1.5V AT 6A CLOCK SYNC 4 C24 100pF REFER TO TABLE 2 V IN fSETPGNDSGND 5% MARGIN +PGOOD 8V TO 16V3.3V ON/OFF VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS– PGOOD MPGM RUN COMP INTV CC DRVCC TRACK/SSPLLIN LTM4603 392k 100k 100k R12 30.1k 22µF 6.3V 10µF 25V 3.3V R21 60.4k R19 30.1k 470µF 6.3VMARGIN CONTROL 1.8V AT 6A CLOCK SYNC 3 TRACK 2.5V C8 100pF REFER TO TABLE 2 V IN fSETPGNDSGND 5% MARGIN +PGOOD 8V TO 16V ON/OFF R17 59k C26 0.1µF LTC6902 4-PHASE OSCILLATOR 3.3V AT 5A DIV PH OUT1 OUT2 SET MOD GND OUT4 OUT3 VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS– PGOOD MPGM RUN COMP INTV CC DRVCC TRACK/SSPLLIN LTM4603 R27 392k 100k 100k 13.3k 22µF 6.3V 0.15µF 10µF 25V C11 100µF 35V OPT C10 470µF 6.3VMARGIN CONTROL TRACK/SS CONTROL CLOCK SYNC 1 C12 100pF REFER TO TABLE 2 V IN fSETPGNDSGND 5% MARGIN +PGOOD 3.3V OR APPROPRIATE 3.3V 8V TO 16V 8V TO 16V ON/OFF INTERMEDIATE BUS –48V INPUT R24 19.1k R26 40.2k UTYPICAL APPLICATIO

118-Lead (15mm × 15mm) (Reference LTM DWG # 05-05-1801 Rev Ø) PACKAGE DESCRIPTIO U NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 118 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE SYMBOL aaa bbb eee TOLERANCE 0.10 0.10 0.03 2.72 – 2.92 DETAIL BDETAIL A DETAIL B SUBSTRATE MOLD CAP 0.27 – 0.37 2.45 – 2.55 bbb Z Z BSC TOP VIEW BSC PAD 1 CORNER X Y aaa Z aaa Z 13.97 BSC 1.27 BSC 13.97 BSC 0.12 – 0.28 23 45 678 9 1 0 1 1 BOTTOM VIEW C(0.30) PAD 1 PADS SEE NOTES1 SUGGESTED SOLDER PAD LAYOUT TOP VIEW A B C D E F G H K J L M DETAIL A 0.60 – 0.66 0.60 – 0.66 M YXeee 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 LGA 118 0306 REV Ø Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

© LINEAR TECHNOLOGY CORPORATION 2007 LT 0307 • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2900 Quad Supply Monitor with Adjustable Reset Timer Monitors Four Supplies; Adjustable Reset Timer LTC2923 Power Supply Tracking Controller Tracks Both Up and Down; Power Supply Sequencing LT3825/LT3837 Synchronous Isolated Flyback Controllers No Optocoupler Required; 3.3V, 12A Output; Simple Design LTM4600 10A DC/DC µModule Basic 10A Power Supply LTM4601 12A DC/DC µModule with PLL, Output Tracking and Margining, LTM4603 Pin Compatible LTM4602 6A DC/DC µModule Basic 6A Power Supply TYPICAL APPLICATION 3.3V at 5A, LTM4603-1 (No Remote Sense Amplifi er) VOUT VFB MARG0 MARG1 VOUT_LCL NC3 NC2 NC1 PGOOD MPGM RUN COMP INTV CC DRVCC TRACK/SSPLLIN LTM4603-1 392k 100k 100k RSET 13.3k RfSET 82.5k MARGIN CONTROL 100µF 6.3V

4603 TA05

3.3V TRACK/SS CONTROL 100pFC2 10µF 35V 10µF 35V VIN fSETPGNDSGND 5% MARGIN VIN 4.5V TO 20V REVIEW TEMPERATURE DERATING CURVE +PGOOD