LTM4601A

LTM4601A LINER | Alldatasheet

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12A DC/DC µModules with PLL, Output Tracking and Margining n Telecom and Networking Equipment n Servers n Complete Switch Mode Power Supply n Wide Input Voltage Range: 4.5V to 20V n 12A DC Typical, 14A Peak Output Current n 0.6V to 5V Output Voltage n Output Voltage T racking and Margining n Redundant Mounting Pads for Enhanced Solder- Joint Strength n Parallel Multiple μModules for Current Sharing n Differential Remote Sensing for Precision Regulation (L TM4601A Only) n PLL Frequency Synchronization n ±1.5% Total DC Error n Current Foldback Protection (Disabled at Start-Up) n Pb-Free (e4) RoHS Compliant Package with Gold Finish Pads n UltraFast™ T ransient Response n Current Mode Control n Up to 95% Effi ciency at 5VIN, 3.3VOUT n Programmable Soft-Start n Output Overvoltage Protection n Enhanced (15mm × 15mm × 2.8mm) Surface Mount 1.5V/12A Power Supply with 4.5V to 20V Input Effi ciency and Power Loss vs Load Current The L TM®4601A is a complete 12A step-down switch mode DC/DC power supply with onboard switching controller , MOSFETs, inductor and all support components. The μModule™ is housed in a small surface mount 15mm × 15mm × 2.8mm LGA package. The L TM4601A LGA package is designed with redundant mounting pads to enhance solder-joint strength for extended temperature cycling endurance. Operating over an input voltage range of 4.5 to 20V, the L TM4601A supports an output voltage range of 0.6V to 5V as well as output voltage tracking and margining. The high effi ciency design delivers 12A continuous current (14A peak). Only bulk input and output capacitors are needed to complete the design. The low profi le (2.8mm) and light weight (1.7g) package easily mounts on the back side of PC boards. The μModule can be synchronized with an external clock for reducing undesirable frequency harmonics and allows PolyPhase operation for high load currents. An onboard differential remote sense amplifi er can be used to accurately regulate an output voltage independent of load current. The onboard remote sense amplifi er is not available in the L TM4601A-1. TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

L, L T , L TC, L TM and PolyPhase are registered trademarks of Linear Technology Corporation. μModule and UltraFast are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 5847554, 6304066, 6476589, 6580258, 6677210, 6774611. VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS– PGOOD RUN COMP INTV CC DRVCC MPGM TRACK/SSPLLIN L TM4601A ON/OFF 392k RSET 40.2k MARGIN CONTROL COUT 4601A TA01a VOUT 1.5V 12A CLOCK SYNC TRACK/SS CONTROL 100pF CIN VIN fSETPGNDSGND 5% MARGIN VIN 4.5V TO 20V LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W) 4601A TA01b 24 68 10 12 14 0.5 1.0 2.0 4.0 1.5 2.5 3.0 3.5 12VIN 12VIN 5VIN 5VIN EFFICIENCY POWER LOSS

INTVCC, DRVCC, VOUT_LCL, VOUT (VOUT ≤ 3.3V with PLLIN, TRACK/SS, MPGM, MARG0, MARG1, PGOOD, f V Operating Temperature Range (Note 2).... –40°C to 85°C (Note 1) The l denotes the specifi cations which apply over the –40°C to 85°C temperature range, otherwise specifi cations are at TA = 25°C, VIN = 12V . Per typical application (front page) confi guration. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN(DC) Input DC Voltage l 4.5 20 V VOUT(DC) Output Voltage, Total Variation with Line and Load CIN = 10μF ×3, COUT = 200μF, RSET = 40.2k V IN = 5V to 20V, IOUT = 0A to 12A (Note 5) l 1.478 1.5 1.522 V Input Specifi cations VIN(UVLO) Undervoltage Lockout Threshold I OUT = 0A 3.2 4 V IINRUSH(VIN) Input Inrush Current at Startup I OUT = 0A. VOUT = 1.5V V IN = 5V V IN = 12V 0.6 0.7 A A VIN PGND VOUT VOSNS+/NC2* VOSNS–/NC1* DIFFVOUT/NC3* VOUT_LCL SGND fSET MARG0 MARG1 DRVCC INTVCC VFB PGOOD INTVCC PLLIN TRACK/SS RUN COMP MPGM LGA PACKAGE 133-LEAD (15mm × 15mm × 2.8mm) TOP VIEW MTP1 MTP2 MTP3 TJMAX = 125°C, θJA = 15°C/W, θJC = 6°C/W, θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS WEIGHT = 1.7g *L TM4601A-1 ONL Y LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TM4601AEV#PBF L TM4601AEV#PBF L TM4601AV 133-Lead (15mm × 15mm × 2.8mm) LGA –40°C to 85°C L TM4601AIV#PBF L TM4601AIV#PBF L TM4601AV 133-Lead (15mm × 15mm × 2.8mm) LGA –40°C to 85°C L TM4601AEV-1#PBF L TM4601AEV-1#PBF L TM4601AV-1 133-Lead (15mm × 15mm × 2.8mm) LGA –40°C to 85°C L TM4601AIV-1#PBF L TM4601AIV-1#PBF L TM4601AV-1 133-Lead (15mm × 15mm × 2.8mm) LGA –40°C to 85°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear .com/packaging/ PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS ORDER INFORMATION

ELECTRICAL CHARACTERISTICS

(See Table 5. Pin Assignment)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IQ(VIN,NOLOAD) Input Supply Bias Current V IN = 12V, No Switching VIN = 12V, VOUT = 1.5V, Switching Continuous VIN = 5V, No Switching VIN = 5V, VOUT = 1.5V, Switching Continuous Shutdown, RUN = 0, VIN = 12V 3.8 2.5 mA mA mA mA μA I S(VIN) Input Supply Current V IN = 12V, VOUT = 1.5V, IOUT = 12A VIN = 12V, VOUT = 3.3V, IOUT = 12A VIN = 5V, VOUT = 1.5V, IOUT = 12A 1.81 3.63 4.29 A A A INTV CC VIN = 12V, RUN > 2V No Load 4.7 5 5.3 V Output Specifi cations I OUTDC Output Continuous Current Range V IN = 12V, VOUT = 1.5V (Note 5) 0 12 A ΔVOUT(LINE) VOUT Line Regulation Accuracy V OUT = 1.5V, IOUT = 0A, VIN from 4.5V to 20V l 0.3 % ΔVOUT(LOAD) VOUT Load Regulation Accuracy V OUT = 1.5V, 0A to 12A (Note 5) V IN = 12V, with Remote Sense Amplifi er V IN = 12V (L TM4601A-1) l l 0.25 VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 2×, 100μF X5R Ceramic VIN = 12V, VOUT = 1.5V VIN = 5V, VOUT = 1.5V mVP-P mVP-P fS Output Ripple Voltage Frequency I OUT = 5A, VIN = 12V , VOUT = 1.5V 850 kHz ΔVOUT(START) Turn-On Overshoot, TRACK/SS = 10nF COUT = 200μF , VOUT = 1.5V, IOUT = 0A VIN = 12V VIN = 5V mV mV tSTART Turn-On Time, TRACK/SS = Open C OUT = 200μF , VOUT = 1.5V, IOUT = 1A Resisitive Load V IN = 12V VIN = 5V 0.5 0.5 ms ms ΔVOUTLS Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load, COUT = 2 × 22μF Ceramic, 470μF 4V Sanyo POSCAP V IN = 12V VIN = 5V mV mV tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50%, or 50% to 0% of Full Load VIN = 12V 25 μs IOUTPK Output Current Limit C OUT = 200μF , Table 2 VIN = 12V, VOUT = 1.5V VIN = 5V, VOUT = 1.5V A A Remote Sense Amp (Note 3) (L TM4601A Only, Not Supported in the L TM4601A-1) VOSNS+, VOSNS– CM Range Common Mode Input Voltage Range V IN = 12V, RUN > 2V 0 INTV CC – 1 V DIFFVOUT Range Output Voltage Range V IN = 12V, DIFF OUT Load = 100k 0 INTV CC V VOS Input Offset Voltage Magnitude 1.25 mV AV Differential Gain 1V / V GBP Gain-Bandwidth Product 3 MHz The l denotes the specifi cations which apply over the – 40°C to 85°C temperature range, otherwise specifi cations are at TA = 25°C, VIN = 12V. Per typical application (front page) confi guration.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SR Slew Rate 2 V/μs RIN Input Resistance V OSNS+ to GND 20 kΩ CMRR Common Mode Rejection Mode 100 dB Control Stage V FB Error Amplifi er Input Voltage Accuracy IOUT = 0A, VOUT = 1.5V l 0.594 0.6 0.606 V VRUN RUN Pin On/Off Threshold 1 1.5 1.9 V ISS/TRACK Soft-Start Charging Current V SS/TRACK = 0V –1 –1.5 –2 μA tON(MIN) Minimum On-Time (Note 4) 50 100 ns tOFF(MIN) Minimum Off-Time (Note 4) 250 400 ns RPLLIN PLLIN Input Resistance 50 kΩ IDRVCC Current into DRVCC Pin V OUT = 1.5V, IOUT = 1A, DRVCC = 5V 18 25 mA RFBHI Resistor Between VOUT_LCL and VFB 60.098 60.4 60.702 kΩ VMPGM Margin Reference Voltage 1.18 V VMARG0, VMARG1 MARG0, MARG1 Voltage Thresholds 1.4 V PGOOD Output ΔVFBH PGOOD Upper Threshold V FB Rising 7 10 13 % ΔVFBL PGOOD Lower Threshold V FB Falling –7 –10 –13 % ΔVFB(HYS) PGOOD Hysteresis V FB Returning 1.5 % VPGL PGOOD Low Voltage I PGOOD = 5mA 0.15 0.4 V The l denotes the specifi cations which apply over the –40°C to 85°C temperature range, otherwise specifi cations are at TA = 25°C, VIN = 12V. Per typical application (front page) confi guration. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TM4601AE/L TM4601AE-1 are guaranteed to meet performance specifi cations from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The L TM4601AI/L TM4601AI-1 are guaranteed and tested over the –40°C to 85°C temperature range. Note 3: Remote sense amplifi er recommended for ≤3.3V output. Note 4: 100% tested at wafer level only. Note 5: See Output Current Derating curves for different V IN, VOUT and TA.

Effi ciency vs Load Current with 5VIN Effi ciency vs Load Current with 12VIN Effi ciency vs Load Current with 20V IN 1.2V T ransient Response 1.5V T ransient Response 2.5V T ransient Response 3.3V T ransient Res ponse (See Figure 18 for all curves) 1.8V T ransient Response TYPICAL PERFORMANCE CHARACTERISTICS LOAD CURRENT (A) EFFICIENCY (%) 4601A G01 51 0 100 0.6VOUT 1.2VOUT 1.5VOUT 2.5VOUT 3.3VOUT LOAD CURRENT (A) EFFICIENCY (%) 100 5 10 4601A G02 0.6VOUT 1.2VOUT 1.5VOUT 2.5VOUT 3.3VOUT 5VOUT LOAD CURRENT (A) 100 4601A G03 5 10 15 EFFICIENCY (%) 1.2VOUT 1.5VOUT 2.5VOUT 3.3VOUT 5.0VOUT VOUT 50mV/DIV 20μs/DIV 4601A G04 IOUT 5A/DIV 1.2V AT 6A/μs LOAD STEP COUT = 3 • 22μF 6.3V CERAMICS 470μF 4V SANYO POSCAP C3 = 100pF VOUT 50mV/DIV 20μs/DIV 4601A G05 IOUT 5A/DIV 1.5V AT 6A/μs LOAD STEP COUT = 3 • 22μF 6.3V CERAMICS 470μF 4V SANYO POSCAP C3 = 100pF VOUT 50mV/DIV 20μs/DIV 4601A G06 IOUT 5A/DIV 1.8V AT 6A/μs LOAD STEP COUT = 3 • 22μF 6.3V CERAMICS 470μF 4V SANYO POSCAP C3 = 100pF VOUT 50mV/DIV 20μs/DIV 4601A G07 IOUT 5A/DIV 2.5V AT 6A/μs LOAD STEP COUT = 3 • 22μF 6.3V CERAMICS 470μF 4V SANYO POSCAP C3 = 100pF VOUT 50mV/DIV 20μs/DIV 4601A G08 IOUT 5A/DIV 3.3V AT 6A/μs LOAD STEP COUT = 3 • 22μF 6.3V CERAMICS 470μF 4V SANYO POSCAP C3 = 100pF

(See Figure 18 for all curves) Start-Up, IOUT = 12A (Resistive Load)Start-Up, IOUT = 0A VIN to VOUT Step-Down Ratio Short-Circuit Protection, IOUT = 0A Short-Circuit Protection, IOUT = 12A T rack, IOUT = 12A TYPICAL PERFORMANCE CHARACTERISTICS VOUT 0.5V/DIV 5ms/DIV 4601A G09 IIN 0.5A/DIV VIN = 12V VOUT = 1.5V COUT = 470μF 3 s 22μF SOFT-START = 10nF VOUT 0.5V/DIV 2ms/DIV 4601A G10 IIN 1A/DIV VIN = 12V VOUT = 1.5V COUT = 470μF 3 s 22μF SOFT-START = 10nF INPUT VOL TAGE (V) OUTPUT VOL TAGE (V) 3.0 4.0 5.5 5.0 4601A G11 2.0 1.0 2.5 3.5 4.5 1.5 0.5 42 86 12 14 1810 20 3.3V OUTPUT WITH 130k ADDED FROM VOUT TO fSET 5V OUTPUT WITH 100k RESISTOR ADDED FROM fSET TO GND 5V OUTPUT WITH NO RESISTOR ADDED FROM fSET TO GND 2.5V OUTPUT 1.8V OUTPUT 1.5V OUTPUT 1.2V OUTPUT VFB 0.5V/DIV TRACK/SS 0.5V/DIV 2ms/DIV 4601A G12 VOUT 1V/DIV VIN = 12V VOUT = 1.5V COUT = 470μF 3 s 22μF SOFT-START = 10nF VOUT 0.5V/DIV 50μs/DIV 4601A G13 IIN 1A/DIV VIN = 12V VOUT = 1.5V COUT = 470μF 3 s 22μF SOFT-START = 10nF VOUT 0.5V/DIV 50μs/DIV 4601A G14 IIN 1A/DIV VIN = 12V VOUT = 1.5V COUT = 470μF 3 s 22μF SOFT-START = 10nF

(See Package Description for Pin Assignment) VIN (Bank 1): Power Input Pins. Apply input voltage be- tween these pins and PGND pins. Recommend placing input decoupling capacitance directly between V IN pins and PGND pins. VOUT (Bank 3): Power Output Pins. Apply output load between these pins and PGND pins. Recommend placing output decoupling capacitance directly between these pins and PGND pins. Review the fi gure below. PGND (Bank 2): Power ground pins for both input and output returns. V OSNS– (Pin M12): (–) Input to the Remote Sense Amplifi er . This pin connects to the ground remote sense point. The remote sense amplifi er is used for V OUT ≤3.3V . NC1 (Pin M12): No Connect On the L TM4601A-1. VOSNS+ (Pin J12): (+) Input to the Remote Sense Amplifi er . This pin connects to the output remote sense point. The remote sense amplifi er is used for V OUT ≤3.3V . NC2 (Pin J12): No Connect On the L TM4601A-1. DIFFVOUT (Pin K12): Output of the Remote Sense Ampli- fi er . This pin connects to the VOUT_LCL pin. NC3 (Pin K12): No Connect On the L TM4601A-1. DRVCC (Pin E12): This pin normally connects to INTV CC for powering the internal MOSFET drivers. This pin can be biased up to 6V from an external supply with about 50mA capability, or an external circuit shown in Figure 16. This improves effi ciency at the higher input voltages by reducing power dissipation in the module. INTV CC (Pin A7, D9): This pin is for additional decoupling of the 5V internal regulator . These pins are internally connected. Pin A7 is a test pin. PLLIN (Pin A8): External Clock Synchronization Input to the Phase Detector . This pin is internally terminated to SGND with a 50k resistor . Apply a clock above 2V and below INTV CC. See Applications Information. TRACK/SS (Pin A9): Output Voltage T racking and Soft- Start Pin. When the module is confi gured as a master output, then a soft-start capacitor is placed on this pin to ground to control the master ramp rate. A soft-start capacitor can be used for soft-start turn on as a stand alone regulator . Slave operation is performed by putting a resistor divider from the master output to the ground, and connecting the center point of the divider to this pin. See Applications Information. MPGM (Pins A12, B11): Programmable Margining Input. A resistor from this pin to ground sets a current that is equal to 1.18V/R. This current multiplied by 10kΩ will equal a value in millivolts that is a percentage of the 0.6V reference voltage. See Applications Information. To parallel L TM4601As, each requires an individual MPGM resistor . Do not tie MPGM pins together . Both pins are internally connected. Pin A12 is a test pin. f SET (Pins B12, C11): Frequency Set Internally to 850kHz. An external resistor can be placed from this pin to ground to increase frequency. This pin can be decoupled with a 1000pF capacitor . See Applications Information for fre- quency adjustment. Both pins are internally connected. Pin B12 is a test pin. V FB (Pin F12): The Negative Input of the Error Amplifi er . Internally, this pin is connected to V OUT_LCL pin with a 60.4k precision resistor . Different output voltages can be programmed with an additional resistor between V FB and SGND pins. See Applications Information. MARG0 (Pin C12): This pin is the LSB logic input for the margining function. Together with the MARG1 pin will determine if margin high, margin low or no margin state is applied. The pin has an internal pull-down resistor of 50k. See Applications Information. PIN FUNCTIONS VIN BANK 1 A B C D E F G H J K L M 234567 *L TM4601A-1 ONL Y 8 9 10 11 12 PGND BANK 2 VOUT BANK 3 VOSNS+/NC2* VOSNS–/NC1* DIFFVOUT/NC3* VOUT_LCL SGND fSET MARG0 MARG1 DRVCC INTVCC VFB PGOOD INTVCC PLLIN TRACK/SS RUN COMP MPGM TOP VIEW MTP1 MTP2 MTP3

Figure 1. Simplifi ed L TM4601A/L TM4601A-1 Block Diagram 50k. See Applications Information. connect to PGND at output capacitor point. See Figure 15. sense voltage (zero current). tion point, after a 25μs power bad mask timer expires. current into the RUN pin to less than 1mA. nects to this pin when remote sense amplifi er is used. pads must remain fl oating (electrical open circuit).

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CIN External Input Capacitor Requirement (VIN = 4.5V to 20V, VOUT = 1.5V) IOUT = 12A , 3× 10μF Ceramics 20 30 μF COUT External Output Capacitor Requirement (VIN = 4.5V to 20V, VOUT = 1.5V) IOUT = 12A 100 200 μF T A = 25°C, VIN = 12V . Use Figure 1 confi guration. Power Module Description The L TM4601A is a standalone nonisolated switching mode DC/DC power supply. It can deliver up to 12A of DC output current with few external input and output capacitors. This module provides precisely regulated output voltage programmable via one external resistor from 0.6V DC to 5.0VDC over a 4.5V to 20V wide input voltage. The typical application schematic is shown in Figure 18. The L TM4601A has an integrated constant on-time current mode regulator, ultralow RDS(ON) FETs with fast switch- ing speed and integrated Schottky diodes. The typical switching frequency is 850kHz at full load. With current mode control and internal feedback loop compensation, the L TM4601A module has suffi cient stability margins and good transient performance under a wide range of operat- ing conditions and with a wide range of output capacitors, even all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit. Besides, foldback current limiting is provided in an overcurrent condition while V FB drops. Internal overvoltage and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. Furthermore, in an overvoltage condition, internal top FET Q1 is turned off and bottom FET Q2 is turned on and held on until the overvoltage condition clears. Pulling the RUN pin below 1V forces the controller into its shutdown state, turning off both Q1 and Q2. At low load current, the module works in continuous current mode by default to achieve minimum output voltage ripple. When DRV CC pin is connected to INTV CC an integrated 5V linear regulator powers the internal gate drivers. If a 5V external bias supply is applied on the DRV CC pin, then an effi ciency improvement will occur due to the reduced power loss in the internal linear regulator . This is especially true at the higher input voltage range. The L TM4601A has a very accurate differential remote sense amplifi er with very low offset. This provides for very accurate remote sense voltage measurement. The MPGM pin, MARG0 pin and MARG1 pin are used to sup- port voltage margining, where the percentage of margin is programmed by the MPGM pin, and the MARG0 and MARG1 select margining. The PLLIN pin provides frequency synchronization of the device to an external clock. The TRACK/SS pin is used for power supply tracking and soft-start programming. DECOUPLING REQUIREMENTS OPERATION

Figure 18. External component selection is primarily requirements for a particular application. down ratio that can be achieved for a given input voltage. The PWM controller has an internal 0.6V reference voltage. Table 1. RSET Standard 1% Resistor Values vs VOUT RPGM resistor on the MPGM pin programs the current. The output margining will be ± margining of the value. by long inductive leads or traces.

current for the external input capacitors. The L TM4601A is designed for low output voltage ripple. to maximize transient performance. Figure 2. Normalized Input RMS Ripple Current

The RUN pin is used to enable the power module. The pin has an internal 5.1V zener to ground. The pin can be driven with a logic input not to exceed 5V . The RUN pin can also be used as an undervoltage lockout (UVLO) function by connecting a resistor divider from the input supply to the RUN pin: VUVLO = R1+R2 R2 • 1.5V See Figure 1, Simplifi ed Block Diagram. Power Good The PGOOD pin is an open-drain pin that can be used to monitor valid output voltage regulation. This pin monitors a ±10% window around the regulation point and tracks with margining. COMP Pin This pin is the external compensation pin. The module has already been internally compensated for most output voltages. Table 2 is provided for most application require- ments. A spice model will be provided for other control loop optimization. PLLIN The power module has a phase-locked loop comprised of an internal voltage controlled oscillator and a phase detector . This allows the internal top MOSFET turn-on to be locked to the rising edge of the external clock. The frequency range is ±30% around the operating frequency of 850kHz. A pulse detection circuit is used to detect a clock on the PLLIN pin to turn on the phase-lock loop. The pulse width of the clock has to be at least 400ns and 2V in amplitude. During the start-up of the regulator , the phase-lock loop function is disabled. INTV CC and DRVCC Connection An internal low dropout regulator produces an internal 5V supply that powers the control circuitry and DRV CC for driving the internal power MOSFETs. Therefore, if the system does not have a 5V power rail, the L TM4601A can be directly powered by V IN. The gate driver current through the LDO is about 20mA. The internal LDO power dissipation can be calculated as: P LDO_LOSS = 20mA • (VIN – 5V) The L TM4601A also provides the external gate driver voltage pin DRVCC. If there is a 5V rail in the system, it is recommended to connect DRV CC pin to the external 5V rail. This is especially true for higher input voltages. Do not apply more than 6V to the DRV CC pin. A 5V output can be used to power the DRV CC pin with an external circuit as shown in Figure 16. Parallel Operation of the Module The L TM4601A device is an inherently current mode controlled device. Parallel modules will have very good current sharing. This will balance the thermals on the de- sign. Figure 19 shows a schematic of the parallel design. The voltage feedback equation changes with the variable N as modules are paralleled: VOUT = 0.6V 60.4k N +RSET RSET N is the number of paralleled modules. Figure 19 shows an L TM4601A and an L TM4601A-1 used in a parallel design. The 2nd L TM4601A device does not require the remote sense amplifi er, therefore, the L TM4601A-1 device is used. An L TM4601A device can be used without the diff amp. V OSNS+ can be tied to ground and the VOSNS– can be tied to INTVCC. DIFFVOUT can fl oat. When using multiple L TM4601A-1 devices in parallel with an L TM4601A, limit the number to fi ve for a total of six modules in parallel. Thermal Considerations and Output Current Derating The power loss curves in Figures 7 and 8 can be used in coordination with the load current derating curves in Figures 9 to 14 for calculating an approximate θ JA for the module with various heat sinking methods. Thermal models are derived from several temperature measurements at the bench and thermal modeling analysis. Thermal Ap- plication Note 103 provides a detailed explanation of the analysis for the thermal models and the derating curves. APPLICATIONS INFORMATION

Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 18), 0A to 6A Load Step

The L TM4601A is designed to typically operate at 850kHz across most input conditions. The fSET pin is normally left open or decoupled with an optional 1000pF capacitor. The switching frequency has been optimized for maintaining constant output ripple noise over most operating ranges. The 850kHz switching frequency and the 400ns minimum off time can limit operation at higher duty cycles like 5V to 3.3V , and produce excessive inductor ripple currents for lower duty cycle applications like 20V to 5V. The 5V and 3.3V drop out curves are modifi ed by adding an external resistor on the f SET pin to allow for lower input voltage operation, or higher input voltage operation. Example for 5V Output L TM4601A minimum on time = 100ns; t ON = ((4.8 • 10pf)/IfSET) L TM4601A minimum off time = 400ns; t OFF = t – tON, where t = 1/Frequency Duty Cycle = t ON/t or VOUT/VIN Equations for setting frequency: I fSET = (VIN/(3 • RfSET)), for 20V operation, IfSET = 170μA, tON = ((4.8 • 10pF)/IfSET), tON = 282ns, where the internal RfSET is 39.2k. Frequency = (VOUT/(VIN • tON)) = (5V/(20

• 282ns)) ≈ 886kHz. The inductor ripple current begins to get high at the higher input voltages due to a larger voltage across the inductor . This is noted in the “Induc- tor Ripple Current vs Duty Cycle” graph (Figure 3) where I L ≈ 10A at 25% duty cycle. The inductor ripple current can be lowered at the higher input voltages by adding an external resistor from f SET to ground to increase the switch- ing frequency. An 8A ripple current is chosen, and the total peak current is equal to 1/2 of the 8A ripple current plus the output current. The 5V output current is limited to 8A, so the total peak current is less than 12A. This is below the 14A peak specifi ed value. A 100k resistor is placed from f SET to ground, and the parallel combination of 100k and 39.2k equates to 28k. The IfSET calculation with 28k and 20V input voltage equals 238μA. This equates to a tON of 200ns. This will increase the switching frequency from ~886kHz to ~1.25MHz for the 20V to 5V conversion. The minimum on time is above 100ns at 20V input. Since the switching frequency is approximately constant over input and output conditions, then the lower input voltage range is limited to 10V for the 1.25MHz operation due to the 400ns minimum off time. Equation: t ON = (VOUT/VIN)
• (1/Frequency) equates to a 400ns on time, and a 400ns off time. The “V IN to VOUT Step-Down Ratio” curve refl ects an operating range of 10V to 20V for 1.25MHz operation with a 100k resistor to ground, and an 8V to 16V operation for f SET fl oating. These modifi cations are made to provide wider input voltage ranges for the 5V output designs while limiting the inductor ripple current, and maintaining the 400ns minimum off time. Example for 3.3V Output L TM4601A minimum on time = 100ns; t ON = ((3.3 • 10pF)/IfSET) L TM4601A minimum off time = 400ns; t OFF = t – tON, where t = 1/Frequency Duty Cycle (DC) = t ON/t or VOUT/VIN Equations for setting frequency: I fSET = (VIN/(3 • RfSET)), for 20V operation, IfSET = 170μA, tON = ((3.3 • 10pf)/IfSET), tON = 195ns, where the internal RfSET is 39.2k. Frequency = (VOUT/(VIN • tON)) = (3.3V/(20
• 195ns)) ≈ 846kHz. The minimum on time and minimum off time are within specifi cation at 195ns and 980ns. The 4.5V minimum input for converting 3.3V output will not meet the minimum off-time specifi cation of 400ns. t ON = 868ns, Frequency = 850kHz, tOFF = 315ns. APPLICATIONS INFORMATION

Figure 16. 5V at 8A Design Without Differential Amplifi er the IfSET current equates to 38μA with the internal 39.2k. The IfSET current needs to be 24μA for 540kHz operation. current of 8A over the input range.

Figure 19. 2-Phase Parallel, 1.5V at 24A Design *C5 OPTIONAL TO REDUCE ANY LC RINGING.

4-Phase, Four Outputs (3.3V, 2.5V, 1.8V and 1.5V) with T racking TYPICAL APPLICATIONS VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS– PGOOD MPGM RUN COMP INTV CC DRVCC TRACK/SSPLLIN L TM4601A 392k R11 100k R10 100k R18 19.1k C16 22μF 6.3V C14 10μF 25V 3.3V 2.5V AT 12A R23 60.4k C15 470μF 6.3VMARGIN CONTROL CLOCK SYNC 2 C18 100pF REFER TO TABLE 2 V IN fSETPGNDSGND 5% MARGIN +PGOOD 8V TO 16V ON/OFF VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS– PGOOD MPGM RUN COMP INTV CC DRVCC TRACK/SSPLLIN L TM4601A R14 392k R16 100k R15 100k R13 40.2k C16 22μF 6.3V C14 10μF 25V 3.3V R25 60.4k C15 470μF 6.3VMARGIN CONTROL 1.5V AT 12A CLOCK SYNC 4 C24 100pF REFER TO TABLE 2 V IN fSETPGNDSGND 5% MARGIN 4601A TA04 +PGOOD 8V TO 16V ON/OFF VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS– PGOOD MPGM RUN COMP INTV CC DRVCC TRACK/SSPLLIN L TM4601A 392k 100k 100k R12 30.1k 22μF 6.3V 10μF 25V 3.3V R21 60.4k R19 30.1k 470μF 6.3VMARGIN CONTROL 1.8V AT 12A CLOCK SYNC 3 TRACK 2.5V C8 100pF REFER TO TABLE 2 V IN fSETPGNDSGND 5% MARGIN +PGOOD 8V TO 16V ON/OFF R17 59k C26 0.1μF L TC6902 4-PHASE OSCILLATOR 3.3V AT 10A DIV PH OUT1 OUT2 SET MOD GND OUT4 OUT3 VOUT VFB MARG0 MARG1 VOUT_LCL DIFFVOUT VOSNS+ VOSNS– PGOOD MPGM RUN COMP INTV CC DRVCC TRACK/SSPLLIN L TM4601A R27 392k 100k 100k 13.3k 22μF 6.3V 0.15μF 10μF 25V C11 100μF 35V OPT C10 470μF 6.3VMARGIN CONTROL TRACK/SS CONTROL CLOCK SYNC 1 C12 100pF REFER TO TABLE 2 V IN 3.3V fSETPGNDSGND 5% MARGIN +PGOOD 8V TO 16V 8V TO 16V ON/OFF INTERMEDIATE BUS –48V INPUT R24 19.1k R26 40.2k 3.3V 3.3V 3.3V

133-Lead (15mm × 15mm × 2.82mm) (Reference L TM DWG # 05-08-1755, Rev Ø) PACKAGE DESCRIPTION NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222, SPP-010 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 133 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE SYMBOL aaa bbb eee TOLERANCE 0.10 0.10 0.05 2.72 – 2.92 DETAIL B DETAIL B SUBSTRATE MOLD CAP 0.27 – 0.37 2.45 – 2.55 bbb Z Z BSC PACKAGE TOP VIEW BSC PAD 1 CORNER X Y aaa Z aaa Z DETAIL A 13.97 BSC 1.27 BSC 13.97 BSC 0.12 – 0.28 LK JH GFE D CB PACKAGE BOTTOM VIEW C(0.30) PAD 1 PADS SEE NOTES MA DETAIL A 0.630 ±0.025 SQ. 133x S YXeee SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.6350 0.6350 1.9050 1.9050 3.1750 3.1750 4.4450 4.4450 5.7150 5.7150 6.9850 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 6.9850 LGA 133 0807 REV Ø L TMXXXXXX μModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1”

PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME A1 V IN B1 V IN C1 V IN D1 PGND E1 PGND F1 PGND A2 V IN B2 V IN C2 V IN D2 PGND E2 PGND F2 PGND A3 V IN B3 V IN C3 V IN D3 PGND E3 PGND F3 PGND A4 V IN B4 V IN C4 V IN D4 PGND E4 PGND F4 PGND A5 V IN B5 V IN C5 V IN D5 PGND E5 PGND F5 PGND A6 V IN B6 V IN C6 V IN D6 PGND E6 PGND F6 PGND A7 INTV CC B7 PGND C7 PGND D7 - E7 PGND F7 PGND A8 PLLIN B8 - C8 - D8 PGND E8 - F8 PGND A9 TRACK/SS B9 PGND C9 PGND D9 INTV CC E9 PGND F9 PGND A10 RUN B10 - C10 MTP1 D10 MPT2 E10 - F10 - A11 COMP B11 MPGM C11 f SET D11 MPT3 E11 - F11 PGOOD A12 MPGM B12 f SET C12 MARG0 D12 MARG1 E12 DRV CC F12 V FB PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME G1 PGND H1 PGND J1 V OUT K1 V OUT L1 V OUT M1 V OUT G2 PGND H2 PGND J2 V OUT K2 V OUT L2 V OUT M2 V OUT G3 PGND H3 PGND J3 V OUT K3 V OUT L3 V OUT M3 V OUT G4 PGND H4 PGND J4 V OUT K4 V OUT L4 V OUT M4 V OUT G5 PGND H5 PGND J5 V OUT K5 V OUT L5 V OUT M5 V OUT G6 PGND H6 PGND J6 V OUT K6 V OUT L6 V OUT M6 V OUT G7 PGND H7 PGND J7 V OUT K7 V OUT L7 V OUT M7 V OUT G8 PGND H8 PGND J8 V OUT K8 V OUT L8 V OUT M8 V OUT G9 PGND H9 PGND J9 V OUT K9 V OUT L9 V OUT M9 V OUT G10 - H10 - J10 V OUT K10 V OUT L10 V OUT M10 V OUT G11 SGND H11 SGND J11 - K11 V OUT L11 V OUT M11 V OUT G12 PGOOD H12 SGND J12 V OSNS+ K12 DIFFV OUT L12 V OUT_LCL M12 V OSNS– Pin Assignment Table 5 (Arranged by Pin Number) PACKAGE DESCRIPTION

V IN VIN VIN VIN VIN VIN V IN VIN VIN VIN VIN VIN V IN VIN VIN VIN VIN VIN Pin Assignment Table 6 (Arranged by Pin Function) PIN NAME PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PGND PIN NAME J10 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT K10 K11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT L10 L11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT M10 M11 V OUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT VOUT PIN NAME A10 A11 A12 INTVCC PLLIN TRACK/SS RUN COMP MPGM B12 f SET C12 MARG0 D12 MARG1 E12 DRV CC F12 V FB G12 PGOOD H12 SGND J12 V OSNS+ K12 DIFFV OUT L12 V OUT_LCL M12 V OSNS– PIN NAME B10 B11 PGND PGND MPGM C10 C11 PGND PGND MTP1 f SET D10 D11 PGND INTVCC MTP2 MTP3 E10 E11 PGND F10 F11 PGOOD G10 G11 SGND H10 H11 SGND J11 - Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION

© LINEAR TECHNOLOGY CORPORATION 2007 LT 1108 REV B • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com RELATED PARTS PART NUMBER DESCRIPTION COMMENTS L TC2900 Quad Supply Monitor with Adjustable Reset Timer Monitors Four Supplies; Adjustable Reset Timer L TC2923 Power Supply T racking Controller T racks Both Up and Down; Power Supply Sequencing L T3825/L T3837 Synchronous Isolated Flyback Controllers No Optocoupler Required; 3.3V, 12A Output; Simple Design L TM4600 10A DC/DC μModule Basic 10A DC/DC μModule L TM4601 12A DC/DC μModule with PLL, Output T racking/ Margining and Remote Sensing Synchronizable, PolyPhase Operation to 48A, L TM4601-1 Version has no Remote Sensing L TM4602 6A DC/DC μModule Pin Compatible with the L TM4600 L TM4603 6A DC/DC μModule with PLL and Output T racking/ Margining and Remote Sensing Synchronizable, PolyPhase Operation, L TM4603-1 Version has no Remote Sensing, Pin Compatible with the L TM4601 L TM4604A 4A Low Voltage DC/DC μModule 2.7V ≤ V IN ≤ 5.5V; 0.8V ≤ VOUT ≤ 5V , 9mm × 15mm × 2.3mm (Ultra-thin) LGA Package L TM4608A 8A Low Voltage DC/DC μModule 2.7V ≤ V IN ≤ 5.5V; 0.6V ≤ VOUT ≤ 5V; 9mm × 15mm × 2.8mm LGA Package This product contains technology licensed from Silicon Semiconductor Corporation.