LTM2895 LINER | Alldatasheet
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2895faFor more information www.linear.com/LTM2895 TYPICAL APPLICATION FEATURES DESCRIPTION 100MHz Isolated DAC SPI Serial Interface The LTM®2895 is a high speed isolated µModule® (micro- module) SPI interface with DAC control signals designed to isolate LT C’s family of general purpose DACs and to isolate general purpose SPI interfaces. The LTM2895 works with DACs and general purpose devices that have a mode (0, 0) SPI interface. The interface enables fast data throughput, which makes the LTM2895 ideally suited for a wide variety of applica- tions. The high speed SPI-compatible serial port supports 1.71V to 5.5V logic supplies. The LTM2895 is targeted at generic SPI and digital-to-analog converter applications. The isolation barrier tolerates large voltage ground varia- tions between the logic interface and the isolated side of the LTM2895. Uninterrupted communication is maintained during voltage transients greater than 50kV/µs. LTC2642-16 DAC Isolation
APPLICATIONS
n Isolated Interface: 6000VRMS for 1 Minute n CSA (IEC/UL) Approved, File #255632 n 100MHz SPI-Compatible I/O n Configurable SPI Word-Length: 8 to 32 Bits n Supports T wo Isolated Chip Selects n Falling Edge Sensitive Low Jitter LOAD n Three Isolated Control or Multiplexer Signals n 1.71V to 5.5V I/O Voltages n 3V to 5.5V Supply Voltages n High Common Mode T ransient Immunity n 15mm × 6.25mm BGA Package n Remote Interface Control n Industrial Process Control and Automation n Test and Measurement Equipment n Breaking Ground Loops All registered trademarks and trademarks are the property of their respective owners. 10µF 10k VOUT GND VIN L T6654-5 8Vi VL2 VCC2 ON2 LOAD2 SS2 SSB2 SCK2 MOSI2 MISO2 SA2 SB2 SC2 GND2 VL VCC ON SSB SCK MOSI MISO SA SB SC GND LOAD BUSY FAULT SS ISOLATION BARRIER ON CLR CS2 SCK MOSI LOAD SYSINT FL TINT CS MISO VDD GND 5Vi 3.3V L TM2895 /uni03BCP CONFIGURATION REGISTERS: WRITE 0x30H AND 0x83H Vi = ISOLATED VOL TAGE SUPPL Y SETS SCK2 TO 33MHz AND WORDLENGTH TO 16-BIT 2895 TA01 100k VOUT INV RFB REF VDD CS SCK DIN CLR GND L TC2642-16 5Vi 27pF OUT 8Vi –8Vi L T1468
2895fa For more information www.linear .com/L TM2895 ABSOLUTE MAXIMUM RATINGS Supply Voltages Isolated Supply Voltages Logic Signals ON, LO AD, BUSY, SA, SB, SC, SS, SSB SCK, MOS D – 0.3V to VL + 0.3V D – 0.3V to 6.3V (Note 1) ORDER INFORMATION Isolated Signals SS2, SSB 2, MISO2, ON2, LOAD2, SCK2 SA2, D2 – 0.3V to VL2 + 0.3V Operating Temperature Range (Note 10) LTM28 °C to 70°C LTM28 0°C to 85°C LTM28 0°C to 125°C 55°C to 125°C 5°C 0°C PIN CONFIGURATION BGA PACKAGE 36-LEAD (15mm × 6.25mm × 2.06mm) TOP VIEW R P N M L K J H G F E D C B A LOAD FAUL T SC SCK SSB SA BUSY SB GND MOSI GNDGND SS GNDMISO ON VCCVL SC2 DNC LOAD2 SA2 SSB2 SCK2 SB2 DNCGND2 GND2 MOSI2GND2 GND2 SS2MISO2 VCC2 ON2 VL2 TJMAX = 125°C, θJA = 36°C/W, θJCTOP = 27.5°C/W, θJCBOTTOM = 17.5°C/W θJB = 19.1°C/W, WEIGHT = 0.36g PART NUMBER PACKAGE TYPE BALL FINISH PA RT MARKING* MSL RATING TEMPERATURE RANGE (SEE NOTE 2)DEVICE FINISH CODE LTM2895CY#PBF BGA SAC305 (RoHS) LTM2895Y e1 3 0°C to 70°C LTM2895IY#PBF –40°C to 85°C LTM2895HY#PBF –40°C to 125°C
- Device temperature grade is indicated by a label on the shipping container.
- Pad or ball finish code is per IPC/JEDEC J-STD-609.
- Terminal Finish Part Marking: www.linear.com/leadfree
- This product is not recommended for second side reflow. For more information, go to www.linear.com/BGA-assy
- Recommended BGA PCB Assembly and Manufacturing Procedures: www.linear.com/BGA-assy ray Drawings: www.linear.com/packaging
- This product is moisture sensitive. For more information, go to: www.linear.com/BGA-assy http://www.linear.com/product/LTM2895#orderinfo
2895faFor more information www.linear.com/LTM2895 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full specified operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, GND = 0V, VCC2 = 5V, VL2 = 3.3V, GND2 = 0V unless otherwise noted. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supplies VCC Operating Supply Range l 3.0 5.5 V ICC Operating Supply Current Idle l 9 12 mA Operating Supply Current, Max DAC Conversion Rate 32-Bit Write/1μs, 20pF Loads, SCK = 50MHz l 12 15 mA VCC2 Isolated Operating Supply Range l 3.0 5.5 V ICC2 Isolated Operating Supply Current Idle l 9 12 mA Isolated Operating Supply Current, Max DAC Conversion Rate 32-Bit Write/1μs, 20pF Loads, SCK = 50MHz l 12 15 mA VL Logic Interface Supply Range l 1.71 3.3 5.5 V IL Logic Interface Supply Current Inputs and Outputs Static at GND or VL l ±200 µA Logic Interface Supply Current, Max Conversion Rate 32-Bit Write/1μs, 20pF Loads, SCK = 50MHz l 2 5 mA VL2 Isolated Interface Supply Range l 1.71 3.3 5.5 V IL2 Isolated Interface Supply Current Inputs and Outputs Static at GND2 or VL2 l ±200 µA Isolated Interface Supply Current, Max Conversion Rate 32-Bit Write/1μs, 20pF Loads, SCK = 50MHz l 2 5 mA Digital Inputs and Digital Outputs (Logic Side) VIH High Level Input Voltage 1.71V ≤ VL ≤ 5.5V l 0.8 • VL V VIL Low Level Input Voltage 1.71V ≤ VL ≤ 5.5V l 0.2 • VL V Digital Input Current (MOSI, SCK, LOAD) V IN = 0V to VL, SS = VL l ±1 µA Digital Input Current (SS, SSB, SA, SB, SC, ON) V IN = 0V to VL l ±60 µA Digital Input Capacitance (Note 7) 5 pF VOH High Level Output Voltage IOUT = –500µA, 1.71V ≤ VL ≤ 5.5V l VL – 0.2 V VOL Low Level Output Voltage IOUT = 500µA, 1.71V ≤ VL ≤ 5.5V l 0.2 V High-Z Output Leakage Current MISO SS = VL l ±1 μA Output Source Current (Short-Circuit) MISO, BUSY VOUT = 0V (Note 7) −80 mA Output Sink Current (Short-Circuit) MISO, BUSY, FAUL T VOUT = VL (Note 7) 80 mA Digital Inputs and Digital Outputs (Isolated Side) VIH High Level Input Voltage 1.71V ≤ VL2 ≤ 5.5V l 0.8 • VL2 V VIL Low Level Input Voltage 1.71V ≤ VL2 ≤ 5.5V l 0.2 • VL2 V Digital Input Current (ON2) VIN = 0V to VL2 l ±60 μA Digital Input Current (MISO2) VIN = 0V to VL2 l ±10 µA Digital Input Capacitance (Note 7) 5 pF VOH High Level Output Voltage IOUT = −500μA, 1.71V ≤ VL2 ≤ 5.5V l VL2 – 0.2 V VOL Low Level Output Voltage IOUT = 500μA, 1.71V ≤ VL2 ≤ 5.5V l 0.2 V Output Source Current (Short-Circuit) VOUT = 0V (Note 7) −80 mA Output Sink Current (Short-Circuit) VOUT = VL2 (Note 7) 80 mA
2895fa For more information www.linear .com/L TM2895 SWITCHING CHARACTERISTICS The l denotes specifications that apply over the full specified operating temperature range, otherwise specifications are at TA = 25°C, CL = 20pF, VCC = 5V, VL = 3.3V, GND = 0V, VCC2 = 5V, VL2 = 3.3V, GND2 = 0V; unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tLOADL LOAD Low Pulse Width l 20 ns tDL YLOAD2 LOAD↓ to LOAD2↓ Delay (Aperture Delay) l 12 21 33 ns tPWLOAD2 LOAD2 Low Pulse Width (SCK2 Frequency ≥ 40MHz) l 20 52 ns (SCK2 Frequency ≤ 33MHz) l 35 80 ns LOAD to LOAD2 Falling Edge Jitter RMS (Note 7) 30 ps LOAD High Time l 100 ns SPI Timing tSCK SCK Input Period SCK2 Frequency 50MHz (Note 8) l 20 2300 ns tSCKH SCK Input High Time SCK2 Frequency 50MHz l 9 ns tSCKL SCK Input Low Time SCK2 Frequency 50MHz l 9 ns tSUMOSI MOSI Setup Time to SCK↑ (Note 2) l 1.5 ns tHMOSI MOSI Hold Time to SCK↑ (Note 2) l 1 ns tDL YSSLOAD SS or SSB Delay to LOAD↓ Quiet Time l 100 ns tDMISO MISO Data Valid Delay from SCK↑, SCK2 Selection > 50MHz VL = 5.5V (Note 2) VL = 2.5V (Note 2) VL = 1.71V (Note 2) l l l 5 7.5 9.5 ns ns ns t DMISO MISO Data Valid Delay from SCK↓, SCK2 Selection ≤ 50MHz V L = 5.5V (Note 2) VL = 2.5V (Note 2) VL = 1.71V (Note 2) l l l 5 7.5 9.5 ns ns ns t HMISO MISO Data Remains Valid Delay from SCK↑ SCK2 ≥ 50MHz (Note 2) l 1.8 ns tHMISO MISO Data Remains Valid Delay from SCK↓ SCK2 < 50MHz (Note 2) l 1.8 ns tDMISOSSF MISO Data Valid Delay from SS↓ l 9.5 ns tSCK2L SCK2 Low Time SCK2 Frequency 50MHz (Notes 2, 8) l 9.1 ns tSUMISO2 MISO2 Data Setup Time to SCK2↑ (Note 7) l 1.5 ns tHMISO2 MISO2 Data Hold Time from SCK2↑ (Note 7) l 1 ns tHMOSI2 MOSI2 Data Remains Valid Delay from SCK2↓ (Note 7) l 1 ns tDMOSI2 MOSI2 Data Valid Delay from SCK2↓ VL2 = 5.5V (Note 2) VL2 = 2.5V (Note 2) VL2 = 1.71V (Note 2) l l l 1.5 3.5 ns ns ns t SSFSCK SS↓ or SSB↓ Delay to SCK↑ SCK2 Frequency 50MHz (Note 8) l 20 2300 ns SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Isolation Barrier Logic Side I/O Pins Isolated Side I/O Pins From GND, V L, or VCC to GND2, VL2, or VCC2 GND, VL, VCC GND2, VL2, VCC2 ±15 kV kV kV ESD PERFORMANCE (Note 7)
2895faFor more information www.linear.com/LTM2895 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tDIS Bus Relinquish Time After SS↑ l 35 ns tSCKSSDIS last SCK↑ to SS↑ or SSB↑ SCK2 Frequency 50MHz (Note 8) l 25 2300 ns tDL YSS2 Delay from SS to SS2 or SSB to SSB2 SSB to SSB2 with DAC 2nd Channel 22 ns tSCKRSCK2F Delay SCK↑ to SCK2↓ SCK2 Frequency 50MHz 22 ns tDL YSCKMOSI2 Delay SCK↑ to MOSI2 Valid 24 ns tDL YMOSI2SCK2 Setup MOSI2 to SCK2↑ (Note 2) l 1.5 ns tSSSPACE SS↑ or SSB↑ Space to SS↓ or SSB↓ l 60 ns tSS2FSCK2 SS2↓ or SSB2↓ Delay to SCK2↑ SCK2 Frequency 50MHz l 45 ns tSCK2SS2DIS Last SCK2↑ to SS2↑ or SSB2↑ SCK2 Frequency 50MHz l 32 ns MISO Rise/Fall Time (Note 7) 500 ps LOAD2, SS2, SSB2, MOSI2, SCK2 Rise/Fall Time (Note 7) 500 ps Select Signals SA, SB, SC Propagation Delay 1.71V ≤ VL ≤ 5.5V l 40 80 150 ns SA2, SB2, SC2 Rise/Fall Time 1.71V ≤ VL2 ≤ 5.5V l 10 20 ns SWITCHING CHARACTERISTICS The l denotes specifications that apply over the full specified operating temperature range, otherwise specifications are at TA = 25°C, CL = 20pF, VCC = 5V, VL = 3.3V, GND = 0V, VCC2 = 5V, VL2 = 3.3V, GND2 = 0V; unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VISO Rated Dielectric Insulation Voltage (Notes 4, 5, 6)
1 Minute, Derived from 1 Second 6000 V
1 Second 7200 VRMS
Common Mode T ransient Immunity V CC = VL = ON = 5V to GND, VCC2 = VL2 = ON2 = 5V to GND2, 1000V in 20ns T ransient Between GND and GND2 (Note 7) 50 100 kV/μs V IORM Maximum Working Insulation Voltage (Note 2) 1000 690 VPEAK, VDC VRMS Partial Discharge VPD = 1830VPEAK (Note 4) 5 pC CTI Comparative T racking Index IEC 60112 (Note 2) 600 VRMS Depth of Erosion IEC 60112 (Note 2) 0.017 mm DTI Distance Through Insulation (Note 2) 0.2 mm Input to Output Resistance (Notes 2, 4) 1 5 TΩ Input to Output Capacitance (Notes 2, 4) 3 pF Creepage Distance (Note 2) 9.2 mm ISOLATION CHARACTERISTICS TA = 25°C
2895fa For more information www.linear .com/L TM2895 CSA (Note 11) CSA 60950-1-07+A1+A2 and IEC 60950-1, second edition, +A1 +A2: Basic Insulation at 910VRMS Reinforced Insulation at 455VRMS CSA 62368-1-14 and IEC 62368-1-14:2014, second edition: Basic Insulation at 600VRMS Reinforced Insulation at 455VRMS CSA 60601-1:14 and IEC 60601-1, third edition, +A1: Tw o means of patient protection (2 MOPP) at 287.5VRMS UL 1577-2015: Single Protection, 6000VRMS Isolation Voltage File 255632 REGULATORY INFORMATION Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Guaranteed by design, not production tested. Note 3: Maximum data rate is guaranteed by other measured parameters and is not directly tested. Note 4: Device considered a 2-terminal device. Measurement between groups of pins A1 through C6 shorted together and pins N1 through R6 shorted together. Note 5: The rated dielectric insulation voltage should not be interpreted as a continuous voltage rating. Note 6: In accordance with UL1577, each device is proof tested for the 6000V RMS rating by applying an RMS voltage multiplied by an acceleration factor of 1.2 for one second. Note 7: Evaluated by Design, not production tested. Note 8: See Table 4 and Table 5 for minimum and maximum timing specifications affected by the selection of SCK2 frequencies in the configuration register. Note 9: All currents into device pins are positive; all currents out of device are negative. All voltages are referenced to their corresponding ground unless otherwise specified. Note 10: Continuous operation above specified maximum operating junction temperature may result in device degradation or failure. Note 11: Ratings are for pollution degree 2, material group 3 and overvoltage category II where applicable. Ratings for other environmental and electrical conditions to be determined from the appropriate safety standard.
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Figure 1. Voltage Levels for Timing Specifications Specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, GND = 0V, VCC2 = 5V, VL2 = 5.0V, GND2 = 0V, unless otherwise noted.
2895fa For more information www.linear .com/L TM2895 SA, SB, SC, SA2, SB2, or SC2 as Outputs VOL/VOH vs VL or VL2 Voltage LOAD2, BUSY, MISO, SS2, SSB2, or MOSI2 V OL/VOH vs VL or VL2 Voltage SCK2 Frequency Variation vs Temperature TYPICAL PERFORMANCE CHARACTERISTICS Specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, GND = 0V, VCC2 = 5V, VL2 = 5.0V, GND2 = 0V, unless otherwise noted. VOH (4mA) VOH (1mA) VOH (0.5mA) VOL (4mA) VOL (1mA) VOL (0.5mA) V L OR V SUPPL Y (V) 1.5 2.5 3.5 4.5 5.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VOL TAGE OUT (V) VOL & VOH Versus V L or V Voltage
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VOH (4mA) VOH (1mA) VOH (0.5mA) VOL (4mA) VOL (1mA) VOL (0.5mA) V L OR V SUPPL Y (V) 1.5 2.5 3.5 4.5 5.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VOL TAGE OUT (V) L
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Supply Current vs Sampling Rate Temperature Derating Curve V L = 3.3V V CC = 5.0V V CC2 = V = 5.0V θ JA = 32°C/W C-Grade I-Grade H-Grade TEMPERATURE (°C) 100 125 150 0.50 1.00 1.50 SAMPLES PER SECOND (Msps) at 100MHz per 1us)
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TEMPERATURE (°C) –60 –40 –20 100 120 140 100 101 102 103 103 104 105 106 107 108 109 FREQUENCY PERCENTAGE (%)
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V CC = 5V V CC2 = 5V V = 5V V L = 5V IV CC IV CC2 IV IV L SAMPLES PER SECOND (ksps) 200 400 600 800 1000 CURRENT (mA)
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2895faFor more information www.linear.com/LTM2895 PIN FUNCTIONS Logic Side (All Logic Side Inputs and Outputs Referenced to V L and GND). ON (A1): LTM2895 Enable. A high input enables the LTM2895 logic side. Do not float. When ON is low and V L is high, the logic side is in reset, MOSI, SCK, LOAD, and MISO are high impedance, an external pull-up or pull-down resistor (100k or greater) is required on each pin to minimize possible internal shoot though current if these pins float. SS (A2): Slave Select Input (Low T rue Slave Chip Select). A low on the SS input enables MISO. Frame each word written or read through the isolator with the SS input. SS contains a weak pull-up to V L. SSB must be high for SS to be enabled. MOSI (A3): Master Out Slave In Input. Serial data to be written to the isolated DAC side (MOSI2). MOSI is also the serial data input for the configuration registers. Add a weak pull-up or pull-down resistor to MOSI pin to set valid logic condition during the high impedance state. SCK (A4): Serial Port Clock Input. MISO data changes after a rising edge of the SCK input. MOSI data is read in on the rising edge of the SCK input. Add a weak pull-down resistor to SCK to set a valid logic condition if in a high impedance state. BUSY (A5): Busy Output. A High on the BUSY output indicates the isolator is in progress of startup and the isolated side is not ready. When BUSY goes low, the system is ready. LOAD (A6): DAC Load Input. The falling edge of the LOAD signal is transferred to the LOAD2 output with low jitter creating a narrow 25ns to 80ns pulse. Do not change the LOAD input during a read or write of the serial digital interface. LOAD is not necessary and is dependent on the DAC requirements. If the LTM2895 is in a generic SPI ap- plication or the DAC does not use a LOAD signal, connect LOAD to VL. Do not float. VL (B1): Logic Interface Supply. Recommended operat- ing voltage is 1.71V to 5.5V. Interface supply voltage for pins SA, SB, SC, ON, MISO, MOSI, SCK, SS, SSB, BUSY, LOAD. Internally bypassed to GND with 1μF. MISO (B2): Master In Slave Out Output. Serial data output containing the DAC result from MISO2. MISO is high im- pedance when SS is high. Add a weak pull-up or pull-down resistor to MISO pin to set a valid logic condition during the high impedance state. GND (B3, B5, C2, C3): Circuit Ground. Return for V L logic supply and VCC supply. SSB (B4): Chip Select Configuration Input (SSB Chip Select). A low on the SSB input enables access to the configuration register. If configured for a 2nd DAC chan- nel, the SSB signal is configured as a second slave select. Configuration Registers section describes configurable options. SSB contains a weak pull-up to VL. SS must be high for SSB to be enabled. FAULT (B6): Fault Output Open Drain. A low on the FAUL T output indicates a communication or command error. Connect to an external 10k pull-up to VL to monitor fault events. V CC (C1): Supply Voltage. Recommended operating volt- age is 3.0 V to 5.5V. Internally bypassed to GND with 1μF. SA (C4): Select Enable Channel A. Select signal pass through to SA2 to control an external multiplexer or programmable gain amplifier. T ransitions must not occur within 150ns of a LOAD, SSB, or SS edge. See section SA, SB, SC Safe T ransition Regions for timing constraints. Do not use as a general purpose asynchronous signal. SA contains a weak pull-down. Direction is set in the configuration register. Connect to GND when not used. SB (C5): Select Enable Channel B. Select signal pass through to SB2 to control an external multiplexer or programmable gain amplifier. T ransitions must not occur within 150ns of a LOAD, SSB, or SS edge. See section SA, SB, SC Safe T ransition Regions for timing constraints. Do not use as a general purpose asynchronous signal. SB contains a weak pull-down. Direction is set in the configuration register. Connect to GND when not used.
2895fa For more information www.linear .com/L TM2895 SC (C6): Select Enable Channel C. Select signal pass through to SC2 to control an external multiplexer or programmable gain amplifier. T ransitions must not occur within 150ns of a LOAD, SSB, or SS edge. See section SA, SB, SC Safe T ransition Regions for timing constraints. Do not use as a general purpose asynchronous signal. SC contains a weak pull-down. Direction is set in the configuration register. Connect to GND when not used. Isolated Side (All Isolated Side Inputs and Outputs Referenced to V and GND2). V CC2 (N1): Isolated Voltage Supply. Recommended op- erating voltage is 3.0V to 5.5V. Internally bypassed to GND2 with 1μF. GND2 (N2, N3, P3, P5): Isolated Ground Return. Keep separate from GND. SA2 (N4): Select Enable Channel A. Select signal pass through from SA to control an external multiplexer or programmable gain amplifier. See section SA, SB, SC Safe T ransition Regions for timing constraints. Do not use as a general purpose asynchronous signal. SA2 contains a weak pull-down. Direction is set in the configuration register. SB2 (N5): Select Enable Channel B. Select signal pass through from SB to control an external multiplexer or programmable gain amplifier. See section SA, SB, SC Safe T ransition Regions For timing constraints. Do not use as a general purpose asynchronous signal. SB2 contains a weak pull-down. Direction is set in the configuration register. SC2 (N6): Select Enable Channel C. Select signal pass through from SC to control an external multiplexer or programmable gain amplifier. See section SA, SB, SC Safe T ransition Regions for timing constraints. Do not use as a general purpose asynchronous signal. SC2 contains a weak pull-down. Direction is set in the configuration register. V L2 (P1): Interface Supply Voltage. Recommended operat- ing voltage is 1.71V to 5.5V. Interface supply voltage for pins ON2, SA2, SB2, SC2, MISO2, MOSI2, SCK2, SS2, SSB2 and LOAD2. Internally bypassed to GND2 with 1μF. MISO2 (P2): Master In Slave Out Input. Serial data input receiving the results from a general SPI device or a read back from a DAC. MISO2 is high impedance when SS2 and SSB2 are high. MISO2 has a weak pull-down to maintain a valid logic low during high impedance conditions when ON2 is high. Connect to GND if not used. SSB2 (P4): Isolated Side Second Slave Select Output (Slave Chip Select 2). Output controlled by internal communication functions to write data to a second DAC or SPI interface. DNC (P6): Do Not Connect. ON2 (R1): Isolated Interface Enable. A high input enables the isolated side communication interface. Do not float. When ON2 is low and V L2 is high, the isolated side is in reset, LOAD2, MOSI2, SCK2, and MISO2 are high imped- ance, an external pull-up or pull-down resistor (100k or greater) is required on each pin to minimize possible internal shoot though current if these pins float. SS2 (R2): Isolated Side Slave Select Output (Slave Chip Select). Output controlled by internal communication functions to write data to slave DAC. MOSI2 (R3): Isolated Master Out Slave In Output. Serial data output sending command data to the DAC. SCK2 (R4): Isolated Serial Clock Output. Serial clock output to the SPI interface. SCK2 is low when SS2 is high. DNC (R5): Do Not Connect. LOAD2 (R6): Isolated Load DAC Output. Connect to DAC LDAC input. If unused connect to V L2 with a 100k pull-up. Do not float. PIN FUNCTIONS
2895faFor more information www.linear.com/LTM2895 BLOCK DIAGRAM 1µF 1µF 1µF 1µF 2895 BD RX TX RX TX FAUL T ON LOAD BUSY SS SSB SCK MOSI MISO SA SB SC GND GND GND GND VCC VL SPI SLAVE CONTROLLER SPI BUFFER SELECT CONTROL SELECT2 CONTROL SPI MASTER CONTROLLER LOAD2 CONTROL SC2 SB2 SA2 MISO2 MOSI2 SCK2 SSB2 SS2 LOAD2 ON2 DNC DNC VL2 VCC2 GND2 GND2 GND2 GND2 = LOGIC SIDE COMMON = ISOLATED SIDE COMMON
2895fa For more information www.linear .com/L TM2895 APPLICATIONS INFORMATION OVERVIEW The LTM2895 μModule transceiver provides a galvani- cally isolated robust SPI interface including decoupling capacitors. This flexible device can support a variety of configurations and SCK frequencies. The LTM2895 is ideal for breaking ground loops, noise isolation, protecting equipment, or level shifting to a different ground refer - ence. Error free operation is maintained through common mode events exceeding 50kV/µs, providing excellent noise isolation. The LTM2895 can drop into most 4-wire SPI applica - tions from 500 kHz to 50MHz, without any configuration required. To meet the specific needs of other SPI and DAC applications, the LTM2895 can be personalized with a configuration register allowing eight frequency and eight word-length choices. The LTM2895 operates as a slave SPI interface on the logic side and as a master SPI interface on the isolated side. Only the necessary signal edges are transferred across the isolation barrier and the SPI pat - tern is recreated on the isolated side. Data read back from the isolated side is temporarily stored in a buffer and the result is delayed by one word-length. See Figure 9 for a timing diagram of the SPI interface across the LTM2895. Additional isolated signals are included to support
features
of an isolated SPI device. DACs that support a LOAD DAC input can use the low jitter LOAD signal for updating their outputs. Reset, clear, or multiplexer functions are sup - ported with the bidirectional select signals SA, SB, and SC. A fault detection system watches for errors in input condi- tions and isolated data corruption and reports on a single open drain FAUL T output. ISOLATOR μModule TECHNOLOGY The LTM2895 utilizes isolator μModule technology to trans- late signals across an isolation barrier. Signals on either side of the barrier are encoded into pulses and translated across the isolation boundary using differential signaling through coreless transformers formed in the μModule substrate. This system, complete with error checking, fault detection on fail, and extremely high common mode im- munity, provides a robust solution for bidirectional signal isolation. The μModule technology provides the means to combine the isolated signaling with our SPI transceiver in one small package. SPI REQUIREMENTS The SPI bus lacks a formal standard and, therefore, various implementations of protocol, bit lengths, and signal polari- ties exist. In the universe of devices with serial peripheral inter faces (SPI), a nominal set of requirements must be met to operate properly with the LTM2895. The signal flow of a standard SPI protocol is used with a requirement that the SS (Chip Select) signal frames the transaction. The LTM2895 supports SPI mode (0, 0), where SCK captures data on the rising edge (CPHA = 0) and SCK starts low and transitions high (CPOL = 0). The following list summarizes the requirements for using the LTM2895. n Configure the SCK2 frequency to the master and ap- plication device requirements n SPI operates in mode (0, 0) (rising edge SCK captures data) n Chip Select signal (SS or SSB ) frames SPI pattern and meets watchdog timeout requirements First, the SCK2 frequency is selected to operate with the device connected to the isolated side of the LTM2895. The SCK2 frequency sets the low time of the clock signal (tSCK2L) out of the LTM2895 and into the isolated SPI interface. See section SCK2 FREQUENCY for specific timing information. The master SCK frequency must be equal or slower than the SCK2 frequency and greater than the watchdog timeout. Second, the LTM2895 logic side operates in mode (0, 0) with a variation on which edge of the SCK data shifts out on. For configured SCK2 frequencies of 100MHz and 66MHz, the MOSI data is captured and the MISO data is shifted on the rising edge of SCK, as shown in Figure 2. This variation allows for additional propagation and setup time to the next rising clock (SCK) edge. All setup and hold timing characteristics are related to the rising edge of
shifted on the falling edge of SCK, as shown in Figure 3. captured on the rising edge of SCK2. last SCK rising edge transition, see Figure 4.
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Figure 2. SCK and Data with SCK2 Frequency Figure 3. SCK and Data with SCK2 Frequency Figure 4. SPI T ransaction with SS or SSB Framing SCK device. When LOAD is unused connect it to VL. transactions when the primary chip select, SS, is active. buffer after a startup is all “0”s. end on a wordlength boundary. The read back data on MISO is one word-length delayed. the relationship of words into and out of the LTM2895.
goes low, the system is ready. tine. Monitor the BUSY output as a system ready signal. an explanation of situations that cause a watchdog timeout. new transition on one of these signals. Table 1. Fault Reporting to less than tWATCHDOG_TIMEOUT ns. SC < 150ns to SSB, SS, SCK or LOAD. ter and re-writing the configuration registers is necessary.
SB, SC = 0, and the wordlength is 8 bits. to SA2, SB2, SC2 signals, and the length of the SPI word. from the rising edge of SCK as shown in Figure 5.
- SCK2. This guarantees the internal SPI transfer will not under-run or exceed a watchdog timeout and assert a FAUL T. In the case of an under-run, the FAUL T flag will assert low.
Table 2. SCK2 Selection to Margin Setup and Low Time
Figure 5. SCK to SCK2 and MOSI to MOSI2 Data T ransfer Relationship and the internal oscillator creating the low time of SCK2. are examples of devices to use with the select signals. tions within 150ns of the LOAD, SSB or SS signal. delay may cause a perceived jitter or uncertainty of 80ns. default direction for each select signal is logic-to-isolated. select signal will become and input.
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Table 3. Configuration Registers
0 OSCDIV2 OSCDIV1 OSCDIV0 Reserved
Table 4. SCK2 Frequency Selection Table (Configuration Register 0 BIT 6, 5, and 4) Note: Factory default setting is bold (50MHz). Table 5. SCK Frequency Selection Timing Specifications Note: Exceeding Max of tSCK, tSSFSCK, or tSCKSSDIS will result in a watchdog timeout setting FAUL T low, BUSY high and will require reconfiguration. to a specific DAC data length to maximize throughput. a byte size boundary (8, 16, 24, or 32). are also configured with a wordlength of 16. in a number of flexible applications. and 5.5V, including 2.5V and 3.3V systems.
Table 6. SPI WORDLENGTH Selection Table (Configuration Register 1 Bit 2, 1, 0) Note: Factory default setting is bold (8 bits). signed per the data sheet PCB layout recommendations. Table 7. Immunity Testing The high integration of the LTM2895 simplifies PCB layout. withstand the rated isolation voltage. and εR is the dielectric constant of the PCB.
communicated to the isolated side. Figure 6. Writing Configuration Registers Timing Diagram
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requirements of the attached device. Figure 7. Logic Side Interface
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40MHz or lower frequency will result in a ~60ns tPWLOAD2. FREQUENCY to select the proper operating frequency. Figure 8. Logic Isolated Side Interface
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an SCK edge to the isolated side is approximately 22ns. edge of SCK2 will occur tSCK2L time later. Figure 9. Logic and Isolated Side Interaction
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Figure 10. Dual DAC Write
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Figure 11. SA, SB, SC Safe T ransition Regions loss to important conversion or result information. resets, or power down signals to a DAC or related circuits.
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Figure 12. Isolated Dual-Channel 18-Bit DAC with Read Back
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Figure 13. Isolated System Measurement with 24-Bit SDM ADC
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Figure 14. FPGA to Isolated FPGA with Page Mode Data T ransfer
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2895fa For more information www.linear .com/L TM2895 PACKAGE DESCRIPTION PACKAGE TOP VIEW PIN “A1” CORNER Y X aaa Z aaa Z 36-Lead (15mm × 6.25mm × 2.06mm) (Reference LTC DWG# 05-08-1987 Rev A) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE DETAIL A Øb (36 PLACES) A DETAIL B PACKAGE SIDE VIEW M X Y Z ddd M Z eee D E SUGGESTED PCB LAYOUT TOP VIEW 0.00 5.875 6.875 4.875 1.50 1.50 0.50 2.50 2.50 0.50 0.00 6.875 5.875 4.875 6.675 6.125 0.50 ±0.025 Ø 36x 2.75 2.25 BGA 36 0517 REV A TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule PACKAGE BOTTOM VIEW R P N M L K J H G F E D C B A 1 2 3 4 5 6 DETAIL A SEE NOTES PIN 1 e e F G b SEE NOTES b SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 1.86 0.40 1.46 0.50 0.47 0.51 0.95 NOM 2.06 0.50 1.56 0.60 0.50 15.00 6.25 1.00 13.75 5.00 0.56 1.00 MAX 2.26 0.60 1.66 0.70 0.53 0.61 1.05 0.15 0.10 0.15 0.15 0.08 TOTAL NUMBER OF BALLS: 36 DIMENSIONS NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT Z DETAIL B SUBSTRATE ccc Z Z // bbb Z MOLD CAP 5. PRIMARY DATUM -Z- IS SEATING PLANE
6 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y Please refer to http://www.linear.com/product/LTM2895#packaging for the most recent package drawings.
2895faFor more information www.linear.com/LTM2895 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER A 03/18 Added UL/CSA Certifications Increased tSSFSCK Min Specification Added Pin Function clarifications Added Application Information clarifications Fixed Timing Diagram timing markers 1, 6 5, 17 9, 10 12-15 19-21
2895fa For more information www.linear .com/L TM2895 ANALOG DEVICES, INC. 2017 LT 0318 REV A • PRINTED IN USA www.linear.com/LTM2895 RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LTM2881 Isolated RS485/RS422 μModule T ransceiver with Integrated DC/DC Converter 2500VRMS Isolation in Surface Mount BGA or LGA LTM2882 Dual Isolated RS232 μModule T ransceiver with Integrated DC/DC Converter 2500VRMS Isolation in Surface Mount BGA or LGA LTM2892 SPI/Digital or I2C Isolated μModule T ransceiver 3500VRMS Isolation, 6 Channels LTM2883 SPI/Digital or I2C Isolated μModule with Adjustable 5V, and ±12.5V Nominal Voltage Rails 2500VRMS Isolation in Surface Mount BGA LTM2885 Isolated RS485/RS422 µModule T ransceiver 6500VRMS Isolation in Surface Mount BGA LTM2886 SPI or I2C μModule Isolator with Adjustable 5V and ±5V Regulated Power 2500VRMS Isolation in Surface Mount BGA LTM2887 SPI or I2C μModule Isolator with Dual Adjustable 5V Rails 2500V RMS Isolation in Surface Mount BGA LTM2889 Complete 4Mbps CAN FD μModule Isolator + Power 2500VRMS Isolation in Surface Mount BGA LTM2893 Complete 100MHz SPI ADC μModule Isolator 6000VRMS Isolation in Surface Mount BGA LTM2894 Complete Isolated USB μModule T ransceiver 7500VRMS Isolation in Surface Mount BGA LTM2884 Isolated USB T ransceiver with Isolated Power 2500VRMS Isolation in Surface Mount BGA LTM9100 Isolated Switch Controller with I2C Command and Telemetry 5000V RMS Isolation in Surface Mount BGA DACs LTC2641-16/ LTC2642-16 16-Bit VOUT DAC in 3mm × 3mm DFN LTC2641-16/LTC2642-16, Maximum 16-Bit INL Error: ±1LSB Over Temperature LTC2758-18 Dual Serial 18-Bit SoftSpan™ I OUT DACs LTC2575-18, Maximum 18-Bit INL Error: ±1LSB Over Temperature Dual DAC Circuit 10µF 10k VOUT INV RFB REF VDD CS SCK DIN CLR GND L TC2642-16 VOUT GND VIN L T6654-5 8Vi 5Vi VL2 VCC2 ON2 LOAD2 SS2 SSB2 SCK2 MOSI2 MISO2 SA2 SB2 SC2 GND2 VL VCC ON SSB SCK MOSI MISO SA SB SC GND LOAD BUSY FAUL T SS ISOLATION BARRIER ON CLRA CS2 SCK MOSI SYSINT FL TINT CS MISO VDD GND 5Vi 3.3V L TM2895 /uni03BCP CONFIGURATION REGISTERS: WRITE 0x30H AND 0xA3H SETS SCK2 TO 33MHz, WORDLENGTH TO 16-BIT , AND DUAL DAC MODE VOUT INV RFB REF VDD CS SCK DIN CLR GND L TC2642-16 5Vi VREF VREF CLRB
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–8Vi L T1469 8Vi –8Vi L T1469