LTM2894 (Rev. A)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 18
Technical content
Rev AFor more information www.analog.com TYPICAL APPLICATION FEATURES DESCRIPTION Isolated USB Data Transceiver The LT M®2894 is a complete galvanically-isolated USB 2.0 compatible μModule® (micromodule) transceiver. The LTM2894 is ideal for isolation in host, hub, bus split- ter or peripheral device applications. It is compatible with USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) operation. Automatic speed selection configures integrated pull-up resistors on the upstream port to match those sensed on the downstream device. The isolator µModule technology uses coupled inductors to provide 7500V RMS of isolation and 17.4mm of creepage between the upstream and downstream USB interface. This device is ideal for systems requiring isolated ground returns or large common mode voltage variations. Uninter- rupted communication is guaranteed for common mode transients greater than 50kV/μs. Enhanced ESD protection allows this part to withstand up to ±20kV (human body model) on the USB transceiver interface pins to local supplies and ±20kV through the isolation barrier to supplies without latchup or damage. Isolated V2.0 Full Speed Hub Port Full Speed Data
APPLICATIONS
n Isolated USB T ransceiver: 7500VRMS for 1 Minute n CSA (IEC/UL) Approved, File #255632 n Reinforced Insulation n USB 2.0 Full Speed and Low Speed Compatible n Auto-Configuration of Bus Speed n 4.4V to 36V VBUS and VBUS2 Operating Range n 3.3V LDO Output Supply Signal References VLO and VLO2 n 50kV/μs Common Mode T ransient Immunity n ±20kV HBM ESD on USB Interface Pins n 1414VPEAK Maximum Continuous Working Voltage n 17.4mm Creepage Distance n 22mm × 6.25mm Surface Mount BGA n Isolated USB Interfaces n Host, Hub, or Device Isolation n Industrial/Medical Data Acquisition All registered trademarks and trademarks are the property of their respective owners.
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3.3V VBUS VBUS2 D1+ D1– ON2 VLO2 D2+ USB PORT 120µF D2– GND2GND15k 15k HUB µC ISOLATION BARRIER 500ns/DIV D2+ 0.5V/DIV D2– 0.5V/DIV
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Rev A For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS Supply Voltages 0.3V to (VLO + 0.3) 0.3V to (VLO2 + 0.3) Operating Temperature Range 40 to 125°C 5°C 0°C (Note 1) X W V U T S R P N M L K J H G F E D C B A 1 2 3 4 5 6 TOP VIEW D1– D1+ ON VLO VBUSGND D2– D2+ ON2VLO2 VBUS2 GND GND2 GND2 BGA PACKAGE 24-LEAD (22mm × 6.25mm × 2.06mm) TJMAX = 125°C, θJA = 49.6°C/W , θJB = 33.7°C/W, θJCTOP = 26°CW , θJCBOT = 34°C/W , WEIGHT = 0.5g ORDER INFORMATION PART NUMBER PACKAGE TYPE BALL FINISH PA RT MARKING MSL RATING TEMPERATURE RANGEDEVICE FINISH CODE LTM2894CY#PBF BGA SAC305 (RoHS) LTM2894Y e1 3 0°C to 70°C LTM2894IY#PBF –40°C to 85°C LTM2894HY#PBF –40°C to 125°C
- Device temperature grade is indicated by a label on the shipping container.
- Pad or ball finish code is per IPC/JEDEC J-STD-609.
- BGA Package and Tray Drawings
- This product is not recommended for second side reflow. This product is moisture sensitive. For more information, go to Recommended BGA PCB Assembly and Manufacturing Procedures
Rev AFor more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supply VBUS Operating Supply Range (USB Bus Power Input) l 4.4 5 36 V IBUSPOFF VBUS Supply Current Power Off ON = 0V l 1 20 µA IBUS VBUS Supply Current Power On Figure 1, VBUS = 5V, IVLO = 0mA l 5 9 mA IBUSSPND VBUS Supply Current Suspend Mode VBUS = 5V, USB Suspend Timeout l 1.5 2.0 mA VBUS2 Operating Supply Range (Isolated Power Input) l 4.4 5 36 V IBUS2POFF VBUS2 Supply Current Power Off ON2 = 0V l 1 10 µA IBUS2 VBUS2 Supply Current Power On Figure 1, VBUS2 = 5V, IVLO2 = 0mA l 5 9 mA IBUS2SPND VBUS2 Supply Current Suspend Mode VBUS2 = 5V, USB Suspend Timeout l 5 9 mA VLO VLO Regulated Output Voltage Signal Reference Figure 1, I VLO = 0mA l 3.05 3.3 3.55 V VLO Output Voltage Maximum Current Source Figure 1 l 10 mA VLO2 VLO2 Regulated Output Voltage Signal Reference Figure 1, I VLO2 = 0mA l 3.05 3.3 3.55 V VLO2 Output Voltage Maximum Current Source Figure 1 l 10 mA USB Input Levels (D1+, D1–, D2+, D2–) Single-Ended Input High Voltage l 2.0 V Single-Ended Input Low Voltage l 0.8 V Single-Ended Input Hysteresis l 200 mV Differential Input Sensitivity |(D1+ – D1–)| or |(D2+ – D2–)| l 0.2 V Common Mode Voltage Range (D1+ + D1–)/2 or (D2+ + D2–)/2 l 0.8 2.5 V Logic Input Levels (ON, ON2) Logic Input High Voltage l 2.0 V Logic Input Low Voltage l 0.8 V Logic Input Current l ±1 µA Logic Input Hysteresis 200 mV USB Output Levels (D1+, D1–, D2+, D2–) Output Low Voltage RPU = 1.5kΩ to 3.6V, Figure 2 l 0 0.3 V Output High Voltage RPD = 15kΩ to 0V l 2.8 3.6 V Differential Output Signal Cross-Point Voltage l 1.3 2.0 V Terminations R PU Bus Pull-Up Resistance on Upstream Facing Port D2 + or D2– Pull-Up 1.5kΩ to 3.3V l 1.425 1.575 kΩ RPD Bus Pull-Down Resistance on Downstream Facing Port (D2+ and D2–) D2+ and D2– Pull-Down to GND2 l 14.25 15.75 kΩ ZDRV USB Driver Output Resistance l 28 44 Ω USB T ransceiver Pad Capacitance to GND (Note 2) 10 pF The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, VBUS2 = 5V, GND = GND2 = 0V, ON = 3.3V, ON2 = 3.3V
Rev A For more information www.analog.com SWITCHING CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Low Speed USB tLDR Low Speed Data Rate CL = 50pF to 450pF (Note 4) 1.5 Mbps tLR Rise Time Figure 2, CL = 50pF to 600pF l 75 300 ns tLF Fall Time Figure 2, CL = 50pF to 600pF l 75 300 ns tLPRR,tLPFF Propagation Delay Figure 2, CL = 50pF to 600pF l 200 300 ns Differential Jitter To Next T ransition (Note 8) ±45 ns Differential Jitter To Paired T ransitions (Note 8) ±15 ns Full Speed USB t FDR Full Speed Data Rate CL = 50pF (Note 4) 12 Mbps tFR Rise Time Figure 3, CL = 50pF l 4 20 ns tFF Fall Time Figure 3, CL = 50pF l 4 20 ns tFPRR, tFPFF Propagation Delay Figure 3, CL = 50pF l 60 80 115 ns Differential Jitter To Next T ransition (Note 8) 2 ns Differential Jitter To Paired T ransitions (Note 8) 1 ns Suspend Wake Up from Suspend Mode Resume Signal l 0.25 10 µs ESD HBM (Note 8) Isolation Barrier GND to GND2 ±20 kV D1+, D1–, D2+, D2– D1+/D1– to GND, VBUS, or VLO D2+/D2– to GND2, VBUS2, or VLO2 ±20 ±20 kV kV ON or ON2 ±4 kV The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VBUS = 5V, VBUS2 = 5V, GND = GND2 = 0V, ON = 3.3V, ON2 = 3.3V.
Rev AFor more information www.analog.com ISOLATION CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Guaranteed by design and not subject to test. Note 3: This µModule transceiver includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above specified maximum operating junction temperature may result in device degradation or failure. Note 4: Maximum data rate is guaranteed by other measured parameters and is not directly tested. Note 5: Device considered a 2-terminal device. Measurement between groups of pins A1 through B6 shorted together and pins W1 through X6 shorted together. Note 6: The rated dielectric insulation voltage should not be interpreted as a continuous voltage rating. Note 7: In accordance with UL1577, each device is proof tested at the 7500V RMS rating by applying an acceleration factor of 1.2, 9000VRMS, for one second. Note 8: Evaluated by design, not production tested. Note 9: Ratings are for pollution degree 2, material group 3 and overvoltage category II where applicable. Ratings for other environmental and electrical conditions to be determined from the appropriate safety standard. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Isolation Barrier: GND to GND2 VISO Rated Dielectric Insulation Voltage (Notes 6, 7) 1 Minute (Derived from 1 Second Test) 7500 VRMS
1 Second (Note 5) 9000 VRMS
Common Mode T ransient Immunity (Note 2) 50 75 kV/µs VIORM Maximum Working Insulation Voltage (Note 2) 1414 VPEAK, VDC
1000 VRMS
Partial Discharge VPR = 2650 VPEAK (Note 5) 5 pC CTI Comparative T racking Index IEC 60112 (Note 2) 600 VRMS Depth of Erosion IEC 60112 (Note 2) 0.017 mm DTI Distance Through Insulation (Note 2) 0.2 mm Input to Output Resistance (Notes 2, 5) 1 5 TΩ Input to Output Capacitance (Notes 2, 5) 2 pF Creepage Distance (Notes 2, 5) 18.1 mm Specifications are at TA = 25°C. CSA (Note 9) CSA 60950-1-07+A1+A2 and IEC 60950-1, second edition, +A1 +A2: Basic Insulation at 910VRMS Reinforced Insulation at 455VRMS CSA 62368-1-14 and IEC 62368-1-14:2014, second edition: Basic Insulation at 600VRMS Reinforced Insulation at 455VRMS CSA 60601-1:14 and IEC 60601-1, third edition, +A1: Tw o means of patient protection (2 MOPP) at 287.5VRMS UL 1577-2015: Single Protection, 6000VRMS Isolation Voltage File 255632
Rev A For more information www.analog.com TIME (ns) D+, D– SIGNALS (V) 2.5 1.5 2.0 3.5 3.0 4.0 1.0 0.5 –0.5 20 4010 30 60
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TIME (ns) D+, D– SIGNALS (V) 2.6 1.6 2.1 3.1 3.6 1.1 0.1 0.6 200 400100 300 600
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TYPICAL PERFORMANCE CHARACTERISTICS Low Speed Differential Jitter Full Speed Eye Diagram Low Speed Eye Diagram Thermal Derating for Operating Temperature Range vs V BUS or VBUS2 Low Speed Data Full Speed Propagation Delay vs Temperature Low Speed Propagation Delay vs Temperature Full Speed Differential Jitter TA = 25°C, unless otherwise noted. VBUS = 5V, VBUS2 = 5V, GND = GND2 = 0V, ON = 3.3V, ON2 = 3.3V. TEMPERATURE (°C) –50 PROPAGATION DELAY (ns) 100 500 100
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12525–25 75 CLOAD = 120pF TEMPERATURE (°C) –50 PROPAGATION DELAY (ns) 250 240 230 220 210 200 500 100
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12525–25 75 CLOAD = 120pF 10ns/DIV 1V/DIV
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JITTER 1.4nsP-P D1– D1+ D2– D2+ 50ns/DIV 1V/DIV
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JITTER 7.5nsP-P D1+ D1– D2+ D2– 5µs/DIV D2+ 0.5V/DIV D2– 0.5V/DIV
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TEMPERATURE RISE PER GRADE θ JA = 49.6°C/W H-GRADE I-GRADE C-GRADE AMBIENT TEMPERATURE (°C) –60 –40 –20 100 120 140 VBUS OR VBUS2 (V)
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Rev AFor more information www.analog.com PIN FUNCTIONS Upstream Side D1– ( A1): USB Data Bus Upstream Facing Negative T ransceiver Pin. A 1.5k pull-up resistor is automatically configured to indicate the idle condition of the D1– pin. D1+ ( A2): USB Data Bus Upstream Facing Positive T ransceiver Pin. A 1.5k pull-up resistor is automatically configured to indicate the idle condition of the D1+ pin. ON (A3): Enable. Enables data communication through the isolation barrier. If ON is high, the upstream side is enabled. If ON is low, the upstream side is held in reset. The ON pin is referenced between VLO and GND. VLO (A4): Voltage Supply Output from the Upstream Side 3.3V LDO. The VLO pin is used as a positive reference for the ON pin and can support up to 10mA of surplus current to controlling devices. This pin contains internal ceramic bypass capacitance of 4.4µF. GND (A5, B1 - B6): Upstream Circuit Ground. V BUS ( A6): Voltage Supply Input for Upstream USB T ransceiver. Recommended operating range is 4.4V to 36V. Connect to the USB VBUS supply or an external source. This pin contains internal ceramic bypass capacitance of 0.3µF. Downstream Side GND2 (W1 - W6, X5): Downstream Circuit Ground. – (X1): USB Data Bus Downstream Facing Negative T ransceiver Pin. The pin has a 15k pull-down resistor to GND2. D2+ (X2): USB Data Bus Downstream Facing Positive T ransceiver Pin. The pin has a 15k pull-down resistor to GND2. ON2 (X3): Enable. Enables data communication through the isolation barrier. If ON2 is high, the downstream side is enabled. If ON2 is low, the downstream side is held in reset. The ON2 pin is referenced between VLO2 and GND2. VLO2 (X4): Voltage Supply Output from the Downstream Side 3.3V LDO. The VLO2 pin can support up to 10mA of surplus current for low voltage devices. This pin contains internal ceramic bypass capacitance of 4.4µF. V BUS2 (X6): Voltage Supply Input for the Isolated Down- stream USB T ransceiver. Recommended operating range is 4.4V to 36V referenced to GND2. This pin contains internal ceramic bypass capacitance of 0.3µF. PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y.
Figure 1. Power Supply Loads
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Figure 2. Low Speed Timing Measurements Figure 3. Full Speed Timing Measurements
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Rev A For more information www.analog.com OPERATION The LTM2894 µModule transceiver provides a galvanically isolated robust USB interface, complete with decoupling capacitors. An automatically configured pull up resistor is included to represent the condition of the isolated down- stream USB bus to the upstream USB bus. The LTM2894 is ideal for use in USB connections where grounds between upstream hub/host and downstream devices can take on different voltages. Isolation in the LTM2894 blocks high voltage differences and eliminates ground loops and is extremely tolerant of common mode transients between ground potentials. Error free operation is maintained though common mode events exceeding 50kV/µs provid- ing excellent noise isolation. The integrated USB transceiver on both sides of the isola- tion barrier supports full and low speed modes defined in the USB 2.0 Specification. The communication through the isolation barrier for USB is bidirectional and as such the LTM2894 determines data flow direction based on which side a start of packet (SOP) begins first. The direction of data is maintained until an end of packet (EOP) pattern is observed or a timeout occurs due to a lack of activity. The USB interface maintains a small consistent propagation delay representative of a single connection or hub delay and transfers all bus state and data information. Pull-up resistors integrated in the upstream interface automatically indicate device connections and discon - nections. A downstream device connection automatically selects the proper pull-up resistor at the upstream facing port after sensing the idle state of the downstream de - vice at connection time. Disconnection of a downstream device automatically releases the pull-up resistor on the upstream facing port allowing the upstream 15k pull-down resistors to pull the bus signals to a disconnect condition. This function makes the LTM2894 ideal for host, hub, bus splitter, or peripheral device integration. µModule Technology The LTM2894 utilizes isolator µModule technology to translate signals across an isolation barrier. Signals on either side of the barrier are encoded into pulses and translated across the isolation boundary using coreless transformers formed in the µ Module substrate. This system, complete with data refresh, error checking, safe shutdown on fail, and extremely high common mode im- munity, provides a robust solution for bidirectional signal isolation. The µModule technology provides the means to combine the isolated signaling with our USB transceiver in one small package. USB T ransceiver Pin Protection The LTM2894 USB transceiver pins D1 +, D1–, D2+, and D2– have protection from ESD and short-circuit faults. The transceiver pins withstand ±20KV HBM ESD events. Overcurrent circuitry on the transceiver pins monitor fault conditions from D1+ and D1– to GND, VLO, or VBUS (5.3V MAX) and from D2+ and D2– to GND2, VLO2, or VBUS2 (5.3V MAX). A current detection circuit disables the transceiver pin if the pin sinks about 40mA for greater than 600ns. The VLO and VLO2 output supplies protect the USB trans- ceiver pins from shorts to GND or GND2 respectively with a 40mA current limit. APPLICATIONS INFORMATION USB Connectivity The LTM2894 µModule transceiver connects directly to USB ports on the upstream side and the downstream side without the addition of external components. The trans - ceiver passes through all data and does not act as a hub or intelligent device. The bus lines are monitored for idle conditions, start of packet, and end of packet conditions to properly maintain bus speed and data direction. The series resistance, pull-up, and pull-down resistors are built into the LTM2894. The upstream facing USB port contains automatically configured 1.5k pull-up resistors which are switched in or out based on the downstream side peripheral device configuration. This implementation allows upstream reporting of the downstream bus speed and connection/disconnection conditions. Built-in 15k pull- down resistors are included from the D2 + and D2– signals to GND2 supporting the downstream bus configuration.
K-state to begin a data packet and set the data direction. the LTM2894 isolator with a delay of approximately 80ns. automatic monitoring and reporting of the bus speeds. suspend the VBUS supply current reduces below 2mA. when the LTM2894 is in a hub, host, or peripheral device. ports downstream transceiver disconnects and reconnects. change is detected and may take up to 10µs. the limits set in the USB specification. BUS2 current does not reduce in suspend mode. current and over temperature conditions. Figure 4. Idle State Automatic Resistor Setting
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not support full compliance with the USB 2.0 specification. cross over voltages of the successive data transitions. add additional jitter or pulse width distortion. a detailed discussion of this problem. considerations optimize the performance of the LTM2894.
- Do not place copper between the inner columns of pads on the top or bottom on the PCB. This area must remain open to withstand the rated isolation voltage and maintain the creepage distance.
- Route D1– and D1 + and D2 – and D2 + as differential pairs with 90Ω impedance, matching the USB cable impedance. RF, Magnetic Field Immunity The isolator µModule technology used within the LTM2894 has been independently evaluated, and successfully passed the RF and magnetic field immunity testing requirements per European Standard EN 55024, in accordance with the following test standards: EN 61000-4-3 Radiated, Radio-Frequency, Electromag- netic Field Immunity EN 61000-4-8 Power Frequency Magnetic Field Immunity EN 61000-4-9 Pulsed Magnetic Field Immunity T ests were performed using an unshielded test card de - signed per the data sheet PCB layout recommendations. Specific limits per test are detailed in T able 2.
Table 2. Test Frequency Field Strength
Figure 5. Low Noise, Low EMI, 5kVRMS, Reinforced USB Isolator Demo Circuit in Figure 6. Results are corrected per IEC 61000-4-20.
11 GND
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Figure 6. PC Board Layout Figure 7. EMI Plot Figure 8. Bus Splitter
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Figure 10. Powered Peripheral Device Figure 11. Peripheral Powered with 3.3V Only
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Figure 9. USB Host Integration
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Rev A For more information www.analog.com PACKAGE TOP VIEW PIN “A1” CORNER Y X aaa Z aaa Z 24-Lead (22mm × 6.25mm × 2.06mm) (Reference LTC DWG# 05-08-1991 Rev Ø) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE DETAIL A Øb (24 PLACES) DETAIL B SUBSTRATE A ccc Z DETAIL B PACKAGE SIDE VIEW MOLD CAP Z M X Y Z ddd M Z eee SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 1.81 0.40 1.41 0.55 0.45 0.46 0.95 NOM 2.06 0.50 1.56 0.60 0.50 22.0 6.25 1.0 20.75 5.0 0.56 1.00 MAX 2.31 0.60 1.71 0.65 0.55 0.66 1.05 0.15 0.10 0.15 0.15 0.08 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 24 D E SUGGESTED PCB LAYOUT TOP VIEW 0.00 9.375 10.375 2.50 0.50 1.50 2.50 1.50 0.50 0.00 10.375 9.375 10.075 10.675 // bbb Z Z 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu 0.60 ±0.025 Ø 24x 2.80 2.20 BGA 24 1014 REV Ø TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y PACKAGE BOTTOM VIEW X W V U T S R P N M L K J H G F E D C B A 1 2 3 4 5 6 DETAIL A SEE NOTES PIN 1 e e F G b SEE NOTES b PACKAGE DESCRIPTION
Rev AFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER A 06/18 Added UL/CSA Certifications Increased Typical Creepage Distance 1, 5
Figure 12. V1.1 USB Hub Isolation