Driver IC

LTM2893

Analog Devices

7.5kVRMS SPI/Digital or I2C 關Module Isolator with Transformer Driver Rev. A

Manufacturer: Analog Devices

Document: 30 Pages / 1Mb

Request Quote Download Datasheet Read online HTML view

Read LTM2893 online.

LTM2893/LTM2389-1 (Rev. C)

Document overview

Manufacturer or author: Analog Devices, Inc.
PDF pages: 32

Technical content

Rev CFor more information www.analog.comDocument Feedback TYPICAL APPLICATION FEATURES DESCRIPTION 100MHz Isolated ADC Serial Interface The LT M®2893 is a high speed isolated μModule (micromodule) SPI interface with ADC control signals. The LTM2893 is optimized for isolating 1Msps high resolution 18-bit SAR ADCs, such as the LTC2338 and similar families, and can interface with most general purpose ADCs. The LTM2893-1 is optimized for isolating the LTC2348 and similar families of simultaneous sampling ADCs that require writing configuration settings into the ADC. LTM2893 isolates the conversion start, sampling signal, with very low aperture jitter (30ps) and low latency (20ns). The interface enables fast throughput with no cycle latency, which makes the LTM2893 ideally suited for a wide variety of applications. The LTM2893 has a high speed SPI-compatible serial port that supports 1.71V to 5.5V logic and is configurable for ADCs with 8 to 32 bit SPI word lengths. It also isolates three select signals (SA, SB, SC) for controlling analog multiplexers or gain settings. The isolation barrier tolerates large voltage ground variations between the logic interface and the isolated side of the LTM2893. Uninterrupted communication is maintained during voltage transients greater than 50kV/µs. LTC2328-18 ADC Isolation AIN = ±10.24V, SNR = 95dB

APPLICATIONS

n Isolated Interface: 6000VRMS for 1 Minute n CSA (IEC/UL) Approved, File #255632 n 100MHz SPI-Compatible I/O n Configurable SPI Word Length 8 to 32 Bits n Low Jitter Conversion Start (30psRMS) n Supports Simultaneously Sampled ADCs n Read Only (LTM2893), Read/Write (LTM2893-1) n Three Isolated Multiplexer Select Signals n 1.71V to 5.5V I/O Voltages n 3V to 5.5V Supply Voltages n High Common Mode T ransient Immunity n 15mm × 6.25mm BGA Package n Remote Sensing n High Speed Data Acquisition n Industrial Process Control n Test and Measurement Equipment L TM2893 VL VCC VL2VCC2 CNV BUSY SS SCK MISOA SA SB SC SA2 SB2 SC2 CNV2 BUSY2 SS2 SCK2 MISOA2 CNV BUSY SPI INTERFACE BUFFER SELECT CNV2 BUSY2 SPI INTERFACE CNV BUSY SCK SDO RDL CHAIN VDD 5Vi3.3Vi 5Vi5V 3.3V 3.3Vi REFINOVDD REFBUF VDDLBYP IN+ IN– VIN SHDN VOUT_F VOUT_S 0.1µF 10µF 2.2µF 47µF 3.3nF IN+ IN– OUT 2.2µF L TC2328-18 L TC6655-2.048 L T1468 6.8nF ±10V INPUT INPUT RETURN 500/uni03A9 20/uni03A9 20/uni03A9 MASTER FPGA

28931 TA01a

1µF +15Vi –15Vi ISOLATION BARRIER 1µFSELECT2 All registered trademarks and trademarks are the property of their respective owners.

Rev C For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS Supply Voltages Isolated Supply Voltages Logic Signals ON, CNV, BUSY, SA, SB, SC, SS, CSC, MISOA, MISOB, Isolated Signals MISOA2, M ISO B2, ON2, BUSY2, BUSYS, MOSI2, CNV2, S CK2, SS2, Operating Temperature Range (Note 11) (Note 1) BGA PACKAGE 36-PIN (15mm × 6.25mm × 2.06mm) TJMAX = 125°C, θJA = 36°C/W , θJCTOP = 27.5°C/W , θJCBOTTOM = 17.5°C/W θJB = 19.1°C/W , WEIGHT = 0.36g TOP VIEW R P N M L K J H G F E D C B A 1 2 3 4 5 6 CNV FAUL T SC SCK CSC SA BUSY SB GND MOSI GND MISOB SS GND MISOA ON VCC VL SC2 BUSYS CNV2 SA2 VL2 SCK2 SB2 BUSY2 GND2 GND2 MOSI2 MISOB2 GND2 SS2 MISOA2 VCC2 ON2 VL2 ORDER INFORMATION PART NUMBER PACKAGE TYPE BALL FINISH P ART MARKING MSL RATING TEMPERA TURE RANGEDEVICE FINISH CODE LTM2893CY#PBF BGA SAC305 (RoHS) LTM2893Y e1 3 0°C to 70°C LTM2893IY#PBF –40°C to 85°C LTM2893HY#PBF –40°C to 125°C LTM2893CY-1#PBF BGA SAC305 (RoHS) LTM2893Y-1 e1 3 0°C to 70°C LTM2893IY-1#PBF –40°C to 85°C LTM2893HY-1#PBF –40°C to 125°C Device temperature grade is indicated by a label on the shipping container Pad or ball finish code is per IPC/JEDEC J-STD-609. This product is not recommended for second side reflow This product is moisture sensitive. For more information, go to Recommended BGA PCB Assembly and Manufacturing Procedures

Rev CFor more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full specified operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, GND = 0V, VCC2 = 5V, VL2 = 3.3V, GND2 = 0V unless otherwise noted. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supplies VCC Operating Supply Range l 3.0 5.5 V ICC Operating Supply Current Idle l 9 12 mA Operating Supply Current 1Msps, ADC Conversion Rate 20pF Loads, SCK = 100MHz l 12 15 mA VCC2 Isolated Operating Supply Range l 3.0 5.5 V ICC2 Isolated Operating Supply Current Idle l 9 12 mA Isolated Operating Supply Current, 1Msps ADC Conversion Rate 20pF Loads, SCK2 = 100MHz l 12 15 mA VL Logic Interface Supply Range l 1.71 5.5 V IL Logic Interface Supply Current Inputs and Outputs Static at GND or VL l ±200 µA Logic Interface Supply Current, 1Msps Conversion Rate SCK = 100MHz, 20pF Load l 2 5 mA VL2 Isolated Interface Supply Range l 1.71 5.5 V IL2 Isolated Interface Supply Current Inputs and Outputs Static at GND2 or VL2 l ±200 µA Isolated Interface Supply Current, 1Msps ADC Conversion Rate SCK2 = 100MHz, 20pF Load l 2.5 5 mA Digital Inputs and Digital Outputs (Logic Side) VIH High Level Input Voltage 1.71V ≤ VL ≤ 5.5V l 0.8 • VL V VIL Low Level Input Voltage 1.71V ≤ VL ≤ 5.5V l 0.2 • VL V Digital Input Current (MOSI, SCK, CNV) V IN = 0V to VL l ±1 µA Digital Input Current (SS, CSC, SA, SB, SC, ON) V IN = 0V to VL l ±60 µA Digital Input Capacitance Note 2 5 pF VOH High Level Output Voltage IOUT = –500µA, 1.71V ≤ VL ≤ 5.5V l VL – 0.2 V VOL Low Level Output Voltage IOUT = 500µA, 1.71V ≤ VL ≤ 5.5V l 0.2 V IOZ High-Z Output Leakage Current MISOA, MISOB SS = VL l ±1 µA Output Source Current (Short-Circuit) V OUT = 0V (Note 2) –80 mA Output Sink Current (Short-Circuit) VOUT = VL (Note 2) 80 mA Digital Inputs and Digital Outputs (Isolated Side) V IH High Level Input Voltage 1.71V ≤ VL2 ≤ 5.5V l 0.8 • VL2 V VIL Low Level Input Voltage 1.71V ≤ VL2 ≤ 5.5V l 0.2 • VL2 V Digital Input Current (ON2, BUSY2, BUSYS) V IN = 0V to VL2, ON2 = VL2 l ±60 µA Digital Input Current (MISOA2, MISOB2) V IN = 0V to VL2 l ±10 µA Digital Input Capacitance Note 2 5 pF VOH High Level Output Voltage IOUT = –500µA, 1.71V ≤ VL2 ≤ 5.5V l VL2 – 0.2 V VOL Low Level Output Voltage IOUT = 500µA, 1.71V ≤ VL2 ≤ 5.5V l 0.2 V Output Source Current (Short-Circuit) V OUT = 0V (Note 2) –80 mA Output Sink Current (Short-Circuit) VOUT = VL2 (Note 2) 80 mA ESD Performance (Note 7) Isolation Barrier Logic Side I/O Pins Isolated Side I/O Pins From GND, VL, or VCC to GND2, VL2, or VCC2 With Respect to GND, VL, or VCC With Respect to GND2, VL2, or VCC2 ±15 kV kV kV

Rev C For more information www.analog.com SWITCHING CHARACTERISTICS The l denotes the specifications which apply over the full specified operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, GND = 0V, VCC2 = 5V, VL2 = 3.3V, GND2 = 0V unless otherwise noted. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Conversion Start tCNVH CNV Pulse Width l 20 ns tBUSYLH CNV↑ to BUSY↑ Delay l 40 ns tDCNV CNV↑ to CNV2↑ Delay (Aperture Delay) l 12 21 33 ns tCNV2H CNV2 Pulse Width (Config. SCK2 Frequency ≥ 40MHz) l 20 52 ns (Config. SCK2 Frequency ≤ 33MHz) l 35 80 ns CNV to CNV2 Rising Edge Jitter RMS (Note 7) 30 ps Minimum Low Time for CNV 100 ns SPI Timing t QUIET SCK or SS↑ Space to CNV↑ LTM2893 LTM2893-1, Configuration Register = 0x9F l 20 320 ns ns tSCK SCK Input Period SCK2 Frequency 100MHz LTM2893 (Note 3) SCK2 Frequency 100MHz LTM2893-1 (Note 3) l l 1185 ns ns tSCKH SCK Input High Time (Note 2) l 4 ns tSCKL SCK Input Low Time (Note 2) l 4 ns tSCK2 SCK2 Output Period SCK2 Frequency 100MHz (Notes 3, 8) l 9.5 10 10.8 ns tSCK2H SCK2 Output High Time (Note 2) l 4 ns tSCK2L SCK2 Output Low Time (Note 2) l 4 ns tHDMISO2 MISOA2, MISOB2 Data Hold Time from SCK2↑ (Note 2) l 1 ns tDMISO MISOA, MISOB Data Valid Delay from SCK↑ SCK2 Frequency = 100MHz or 66MHz or from SCK↓ SCK2 Frequency ≤ 50MHz C L = 20pF, VL = 5.5V (Note 2) CL = 20pF, VL = 2.5V (Note 2) CL = 20pF, VL = 1.71V (Note 2) l l l 5 7.5 9.5 ns ns ns tSUMISO2 MISOA2, MISOB2, Setup Time to SCK2↑ (Note 2) l 1.8 ns tHMISO MISOA, MISOB Data Remains Valid Delay from SCK↑ SCK2 Frequency = 100MHz or 66MHz or from SCK ↓ SCK2 Frequency ≤ 50MHz CL = 20pF (Note 2) l 2 ns tDMISOSSF MISOA, MISOB Data Valid Delay from SS↓ CL = 20pF l 10 ns MISOA, MISOB Data Valid Delay from BUSY↓ SS = 0V, LTM2893 l 10 ns tSSFSCK SS↓ Delay to SCK↑ SCK2 Frequency 100MHz (Note 8), LTM2893-1 l 20 1185 ns tBUSYFSCKR BUSY↓ Delay to SCK↑ SS = 0V, SCK2 Frequency 100MHz (Notes 9, 10) l 20 ns tBUSY2FSS2F BUSY2↓ Delay to SS2↓ l 15 35 ns tBUSY2FBUSYF BUSY2↓ to BUSY↓ SCK2 Frequency 100MHz l 100 ns tSS2FSCK2 SS2↓ Delay to SCK2↑ SCK2 Frequency 100MHz l 15 33 ns tDIS Bus Relinquish Time After SS↑ l 35 ns tSCKSSDIS Last SCK↑ to SS↑ SCK2 Frequency 100MHz (Note 8) LTM2893-1 l 20 1185 ns tSCK2SSDIS Last SCK2↑ to SS2↑ SCK2 Frequency 100MHz l 8 ns SS↑ to SS↓ Space CRCENA Bit = 0 60 ns CRCENA Bit = 1 225 ns tSUMOSI MOSI Setup to SCK↑ LTM2893-1 or Configuration Port Write (Note 2) l 1.5 ns tHDMOSI MOSI Hold Time to SCK↑ LTM2893-1 or Configuration Port Write (Note 2) l 1 ns tSS2FMOSI2 SS2↓ to MOSI2 Valid LTM2893-1 l 8 ns

1 Minute, Derived from 1 Second 6000 VRMS

1 Second 7200 VRMS

Common Mode T ransient Immunity (Note 2) V CC = VL = ON = 5V to GND, VCC2 = VL2 = ON2 = 5V to GND2, 1000V in 20ns T ransient Between GND and GND2 50 100 kV/µs VIORM Maximum Working Insulation Voltage (Note 2) 1000 690 VPEAK, VDC VRMS Partial Discharge VPD = 1830VPEAK (Note 4) 5 pC CTI Comparative T racking Index IEC 60112 (Note 2) 600 VRMS Depth of Erosion IEC 60112 (Note 2) 0.017 mm DTI Distance Through Insulation (Note 2) 0.2 mm Input to Output Resistance (Notes 2, 4) 1 5 TΩ Input to Output Capacitance (Notes 2, 4) 3 pF Creepage Distance (Note 2) 9.2 mm CSA (Note 12) CSA 60950-1-07+A1+A2 and IEC 60950-1, second edition, +A1 +A2: Basic Insulation at 910VRMS Reinforced Insulation at 455VRMS CSA 62368-1-14 and IEC 62368-1-14:2014, second edition: Basic Insulation at 600VRMS Reinforced Insulation at 455VRMS CSA 60601-1:14 and IEC 60601-1, third edition, +A1: T wo means of patient protection (2 MOPP) at 287.5V RMS UL 1577-2015: Single Protection, 6000V RMS Isolation Voltage File 255632 ISOLATION CHARACTERISTICS REGULATORY INFORMATION TA = 25°C.

Rev C For more information www.analog.com

ELECTRICAL CHARACTERISTICS

0.8•VL or 0.8•VL2 0.2•VL or 0.2•VL2 tDELAY tWIDTH

2893 F01

0.8•VL or 0.8•VL2 0.2•VL or 0.2•VL2 0.8•VL or 0.8•VL2 0.5•VL or 0.5•VL2 0.2•VL or 0.2•VL2 Figure 1. Voltage Levels for Timing Specifications Specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, GND = 0V, VCC2 = 5V, VL2 = 5.0V, GND2 = 0V, unless otherwise noted.

2893 G01

2893 G02

2893 G03

Note 2: Guaranteed by design, not production tested. Note 3: Guaranteed by other measured parameters and is not directly tested. a continuous voltage rating. factor of 1.2 for one second. Note 7: Evaluated by Design, not production tested. affected by the selection of SCK2 frequencies in the configuration register . and SCK for large word lengths. junction temperature may result in device degradation or failure.

Rev CFor more information www.analog.com SNR and SINAD Performance with LTC2338-18 CNV2 Jitter vs Temperature CNV2 Jitter vs VL and VL2 Select Pins (SA, SB, SC, SA2, SB2, SC2) V OL and VOH vs VL or VL2 Voltage SPI and ADC Control Outputs (MISOA, MISOB, BUSY , CNV2, SCK2, SS2, MOSI2) V OL and VOH vs VL or VL2 Voltage SCK2 Frequency Variation vs Temperature TYPICAL PERFORMANCE CHARACTERISTICS Specifications are at TA = 25°C. VCC = 5V, VL = 3.3V, GND = 0V, VCC2 = 5V, VL2 = 5.0V, GND2 = 0V, unless otherwise noted. Supply Current vs Sampling Rate 18-Bit, SCK2 Frequency = 100MHz Communication During 100kV/µs Common Mode T ransient Events Temperature De-Rating for Operating Temperature Range (Communicating with an LTC2378-18) VOH (4mA) VOH (1mA) VOH (0.5mA) VOL (4mA) VOL (1mA) VOL (0.5mA) VL OR VL2 SUPPL Y (V) 1.5 2.5 3.5 4.5 5.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VOL TAGE OUT (V)

2893 G07

VOH (4mA) VOH (1mA) VOH (0.5mA) VOL (4mA) VOL (1mA) VOL (0.5mA) VL OR VL2 SUPPL Y (V) 1.5 2.5 3.5 4.5 5.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VOL TAGE OUT (V)

2893 G08

TEMPERATURE (°C) –60 –40 –20 100 120 140 100 101 102 103 104 FREQUENCY PERCENTAGE (%)

2893 G09

FREQUENCY (Hz) 10k 100k 100 MAGNITUDE (dB)

2893 G04

TEMPERATURE (°C) –60 –40 –20 100 120 140 CNV2 JITTER RMS (ps)

2893 G05

V L AND V (V) 1.5 2.5 3.5 4.5 5.5 JITTER RMS (ps)

2893 G06

V CC = 5V V CC2 = 5V V = 5V V L = 5V IV CC IV CC2 IV IV L SAMPLES PER SECOND (kSps) 200 400 600 800 1000 CURRENT (mA)

2893 G10

V L = 3.3V V CC = 5.0V V CC2 = V = 5.0V θJA = 36°C/W C–Grade I–Grade H–Grade TEMPERATURE (°C) 100 125 150 0.50 1.00 1.50 SAMPLING RATE (Msps)

2893 G12

2893 G11

Rev C For more information www.analog.com PIN FUNCTIONS Logic Side (All Inputs and Outputs Referenced to VL and GND) ON (A1): Enable Input. A high input enables the logic side. When ON is low and VL is high, MOSI, SCK, CNV , MISOA, and MISOB are high impedance, an external pull-up or pull-down resistor (100k or greater) is required on each pin to minimize possible internal shoot though current if these pins float. SS (A2): Slave Select Input (Low T rue Slave Chip Select). A low on the SS input enables MISOA and MISOB. To clear faults or write the configuration register the SS input must be high. With the LTM2893, the SS input may remain low between ADC reads. With the LTM2893-1, the SS input must frame the SCK transitions and not exceed the defined watchdog timeouts. The SS pin contains a weak pull up to the V L supply. CSC must be high for SS to be enabled. MOSI (A3): Master Out Slave In Input. MOSI is the serial data input for the configuration registers or input for se- rial data to be written to the isolated ADC through MOSI2, (LT M2893-1 option). When MOSI is not used, MOSI should be connected to GND. Connect a weak pull-up to V L or a weak pull-down to GND to maintain a valid logic input when MOSI is not driven. SCK (A4): Serial Port Clock Input. MISOA and MISOB data change after a rising edge of the SCK input. MOSI data is read in on the rising edge of the SCK input. Connect a weak pull-up to V L or a weak pull-down to GND to maintain a valid logic input when SCK is not driven. BUSY (A5): Busy Output. A high output indicates the ADC is currently converting a result. On the falling edge of the BUSY output the data is ready to be read out of the serial digital interface. At startup, a high on the BUSY output indicates the isolated side is not ready. Once the BUSY output goes low the system is ready. CNV (A6): Conversion Start Input. The rising edge of CNV is transferred to CNV2 with minimal delay and minimal jitter . Do not change the CNV input during a read of the serial digital interface. The falling edge of CNV is ignored. V L (B1): Interface Logic Supply. Recommended operating voltage is 1.71V to 5.5V. Interface supply voltage for pins SA, SB, SC, MISOA, MISOB, MOSI, SCLK, SS, CSC, BUSY, and CNV . Internally bypassed to GND with 1µF. MISOA (B2): Master In Slave Out A Output. Serial data output containing the ADC result from MISOA2. Connect a weak pull-up to V L or a weak pull-down to GND to maintain a valid logic level when MISOA is high impedance while SS is high. MISOB (B3): Master In Slave Out B Output. Serial data output containing the ADC results from MISOB2. Con - nect a weak pull-up to V L or a weak pull-down to GND to maintain a valid logic level when MISOB is high impedance while SS is high.. CSC (B4): Chip Select Configuration Input (CSC Chip Select). A low on the CSC input enables access to the configuration register . The Configuration Register section describes configurable options. SS must be high for CSC to be enabled. GND (B5): Connect to GND. FAUL T (B6): Fault Output Open Drain. A low on the FAUL T output indicates a communication or command error . Connect to an external 4.7k pull-up to V L to monitor fault events. VCC (C1): Supply Voltage. Recommended operating volt- age is 3.0V to 5.5V. Internally bypassed to GND with 1µF. GND (C2-C3): Circuit Ground. Return for VL logic supply and VCC supply. SA (C4): Select Enable Input A. Select signal pass through to SA2 to control an external multiplexer or programmable gain amplifier . T ransitions must not occur just before the beginning of a CNV or SS edge. See the Safe Regions of the Select Enable Signals section for timing constraints. Do not use as a general purpose asynchronous signal. SA contains a weak pull down. Connect to GND when not used.

Rev CFor more information www.analog.com SB (C5): Select Enable Input B. Select signal pass through to SB2 to control an external multiplexer or programmable gain amplifier . T ransitions must not occur just before the beginning of a CNV or SS edge. See the Safe Regions of the Select Enable Signals section for timing constraints. Do not use as a general purpose asynchronous signal. SB contains a weak pull down. Connect to GND when not used. SC (C6): Select Enable Input C. Select signal pass through to SC2 to control an external multiplexer or programmable gain amplifier . T ransitions must not occur just before the beginning of a CNV or SS edge. See the Safe Regions of the Select Enable Signals section for timing constraints. Do not use as a general purpose asynchronous signal. SC contains a weak pull down. Connect to GND when not used. Isolated Side (All Inputs and Outputs Referenced to V L2 and GND2) VCC2 (N1): Isolated Voltage Supply. Recommended op - erating voltage is 3.0V to 5.5V. Internally bypassed to GND2 with 1µF. GND2 (N2,N3): Isolated Ground Return. Keep separate from GND. SA2 (N4): Select Output A. Select signal pass through from SA to control an external multiplexer or programmable gain amplifier . See Figure 12 for timing constraints. Do not use as a general purpose asynchronous signal. SA2 contains a weak pull-down. Leave unconnected when not used, or connect to GND2 if unused and configured as an input. SB2 (N5): Select Output B. Select signal pass through from SB to control an external multiplexer or programmable gain amplifier . See Figure 12 for timing constraints. Do not use as a general purpose asynchronous signal. SB2 contains a weak pull-down. Leave unconnected when not used, or connect to GND2 if unused and configured as an input. SC2 (N6): Select Output C. Select signal pass through from SC to control an external multiplexer or programmable gain amplifier . See Figure 12 for timing constraints. Do not use as a general purpose asynchronous signal. SC2 contains a weak pull-down. Leave unconnected when not used, or connect to GND2 if unused and configured as an input. PIN FUNCTIONS VL2 (P1): Interface Supply Voltage. Recommended operat- ing voltage is 1.71V to 5.5V. Interface supply voltage for pins SA2 , SB2, SC2, MISOA2, MISOB2, MOSI2, SCLK2, SS2, BUSYS, BUSY2, and CNV2. Internally bypassed to GND2 with 1µF. Connect to the ADC SPI interface supply. MISOA2 (P2): Master In Slave Out A Input. Serial data input receiving the results from the ADC. MISOA2 has a weak pull-down when ON2 is high. MISOB2 (P3): Master In Slave Out B Input. Serial data input receiving the results from the ADC. MISOB2 has a weak pull-down when ON2 is high. Connect to GND2 when not used. V L2 (P4): Connect to VL2. GND2 (P5): Connect to GND2. BUSYS (P6): Secondary Busy Input. Connect to secondary ADC BUSY output when two or more ADCs are connected in parallel. Connect to CNV2 to avoid ADC sleep functions. Connect to GND2 when unused. ON2 (R1): Isolated Enable Input. A high input enables the isolated side communication interface. Do Not Float. When ON2 is low and V L2 is high, CNV2, MOSI2, SCK2, MISOA2 and MISOB2 are high impedance, an external pull-up or pull-down resistor (100k or greater) is required on each pin to minimize possible internal shoot though current if these pins float. SS2 (R2): Isolated Side Slave Select Output (Slave Chip Select). Output controlled by internal communication func- tions to fetch data from slave ADC. Connect to external ADC as necessar MOSI2 (R3): Isolated Master Out Slave In 2 Output. LTM2893-1 only, serial data output sending command data to the ADC. LTM2893, connect MOSI2 to GND2. SCK2 (R4): Isolated Serial Clock Output. Serial clock output to the ADC. SCK2 is low when SS2 is high. BUSY2 (R5): Isolated Busy Input. Connect to Primary ADC BUSY output. Connect to CNV2 to use fast ADC read mode (ADC sample rate up to 2Msps). CNV2 (R6): Isolated Conversion Start Output. Connect to ADC conversion start input.

Rev C For more information www.analog.com BLOCK DIAGRAM 28931 BD SPI BUFFER SELECT CONTROL SPI SLAVE CONTROLLER TX RX CNV CNTRL ISOLATOR SELECT2 CONTROL SPI MASTER CONTROLLER RX TX CNV2 CNTRL ISOLATOR 1µF 1µF VCC VL ON CNV BUSY SS CSC SCK MOSI MISOA MISOB SA SB SC GND GND GND FAUL T V CC2 VL2 ON2 CNV2 BUSY2 BUSYS SS2 SCK2 MOSI2 MISOA2 MISOB2 SA2 SB2 SC2 GND2 GND2 GND2 1µF 1µF VL2 P4 A1 R1 = LOGIC SIDE COMMON = ISOLATED SIDE COMMON

Rev CFor more information www.analog.com APPLICATIONS INFORMATION OVERVIEW The LTM2893 contains the functions to communicate with analog to digital converters (ADC) using a fast SPI interface. The LTM2893 utilizes state machines and SPI buffers to manage the ADC-specific operations. An inde- pendent configuration chip select (CSC) allows selection of the SCK frequency , word length, device count, and select signal direction to tailor the operation to a specific ADC. See ADC Requirements for a list of compatibility-tested Analog Devices ADCs. The LTM2893 follows the signal flow of a standard SAR ADC interface. The process is initiated by the rising edge of the CNV input signal. A high on the BUSY signal follows and the CNV start edge is transferred to the isolated ADC through the CNV2 output. The isolated side waits for the ADC’s busy signal, connected to BUSY2, to go high then low. At the falling edge of BUSY2, the isolated side will access the ADC’s SPI port and read out the result and transfer it to the logic side, where it is stored in a buffer . When the buffer has data, the logic side BUSY signal will release and the MISOA, MISOB ports are ready to be read. The ADC SPI isolator adds a small delay to the process of an overall ADC cycle. The small delay, approximately 80ns, is observed as a difference in the length of the BUSY and BUSY2 signals. ISOLATOR µMODULE TECHNOLOGY The LTM2893 utilizes isolator μModule technology to trans- late signals across an isolation barrier . Signals on either side of the barrier are encoded into pulses and translated across the isolation boundary using differential signaling through coreless transformers formed in the μModule substrate. This system, complete with error checking, safe shutdown on fail, and extremely high common mode im- munity, provides a robust solution for bidirectional signal isolation. The μModule technology provides the means to combine the isolated signaling with our SPI transceiver in one small package. ADC REQUIREMENTS Ideally Suited ADI ADCs LTM2893 n LT C2380/LTC2379/LTC2378/LTC2377/LTC2376 n LT C2338/LTC2337/LTC2336 n LT C2328/LTC2327/LTC2326 n LT C2370/LTC2369/LTC2368/LTC2367/LTC2364 n LT C2383/LTC2382/LTC2381 LTM2893-1 n LT C2348/LTC2345 The following requirements should be met for other ADCs to be compatible with the LTM2893: n 6.25MHz ≤ SPI shift clock maximum frequency ≤ 100MHz n Operates in SPI mode (0,0) : SCK starts low, data cap- tured on rising edge. n Meets setup and hold timing requirements (t HDMISO2 and tSUMISO2) with the SPI shift clock operating between 6.25MHz and 100MHz. n SPI shift clock (SCK) is static outside of CS (the ADC does not require a constant running SCK as a conver- sion clock) n If used, the conversion start pulse width minimum is ≤ tCNVH The following requirements should be met for other ADCs to be compatible with the LTM2893-1 in addition to the LTM2893 requirements: n The ADC write data is a second transaction. The first transaction reads the ADC result. A second transaction writes the data received into the MOSI pin when the ADC result is read from the LTM2893.

Rev C For more information www.analog.com APPLICATIONS INFORMATION The SPI bus lacks a formal standard, and therefore, various implementations of protocol, bit lengths, and signal polari- ties exist. In the universe of analog-to-digital converters (ADCs) with serial peripheral inter faces (SPI), a nominal set of requirements must be met to operate properly with the LTM2893. First, the LTM2893 operates similar to mode (0, 0). The data is captured and shifted on the rising edge of SCK. All setup and hold timing characteristics are related to the rising edge of the SCK. In a normal mode (0, 0) SPI pattern, the data changes on the falling edge of the SCK. Be aware of the timing delay for the data to be stable before the rising edge SCK capture, if the chosen ADC changes data on the falling edge. At 100MHz and 66MHz, the LTM2893 changes MISOA and MISOB after the rising edge in order to allow for the maximum time for data to change, stabilize, and be ready for the next rising clock edge. Second, the SCK and SS must be dedicated to the opera- tion of reading or writing data. Some ADC interfaces use the SCK as a conversion clock in addition to the shift clock function for the SPI port. Excessive SCK transitions will assert the FAUL T pin as a SPI buffer under-run. The isolated side will transition SCK2 based on the configured count and will not mimic the extra SCK transitions. The slave select (SS) is low true and frames the SPI trans- action. With the LTM2893, if a single ADC is implemented, the logic side SS can be driven low during normal operation and the isolated side SS2 can be left open. Otherwise, the SS must be returned to a high, and then can be driven low to clear the FAUL T pin. The LTM2893-1 requires the SS to frame the SPI transaction. The CNV to CNV2 signal is initiated on a rising edge. The falling edge of CNV is ignored. The falling edge of CNV2 is generated internally and has up to 5ns of jitter . The positive pulse width of CNV2 is dependent on the configured SCK2 frequency. SCK2 frequencies of 40MHz or greater have a pulse width of ~40ns, and SCK2 frequencies of 33MHz or below have a pulse width of ~60ns. ADCs with or without conversion start or busy pins are compatible with the LTM2893. ADCs that offer conversion start signals and busy signals connect directly to the CNV2 and BUSY2 pins on the LTM2893. The anticipated operation of a conversion start signal is to initiate the conversion operation and for the busy signal to be high during the conversion. The busy signal is anticipated to go low when the conversion is complete. ADCs that offer conversion start signals without a busy signal are anticipated to allow reading of the prior SPI result while the current conversion is ongoing. Connect the CNV2 signal to the ADC conversion start and the BUSY2 signal. This will force the LTM2893 to read data from the ADC after the CNV2 signal goes low. ADCs that do not have a conversion start or a busy signal are anticipated to allow reading of the prior SPI result while a conversion is ongoing. Connect the CNV2 signal to the BUSY2 signal. This will force the LTM2893 to read data from the ADC after the CNV2 signal goes low. This may include ADCs that use the CS signal to initiate a conver - sion start. An example of this is shown in Figure 15 with an LTC2314-14. TIMING AND CONTROL A conversion is initiated by CNV . A rising edge on CNV will start a conversion and start the process controlling the BUSY output and the collection of ADC results. Once a conversion has been initiated, do not start a new conver- sion until the current process is completed and the ADC results have been read or else data loss may occur . Once a CNV rising edge is detected, the BUSY output is asserted high and remains high throughout the ADC conversion phase and is de-asserted at the point the most significant bit is ready to be read. Reading data from the serial digital interface before the BUSY output is de-asserted will result in erroneous results and an assertion of the FAUL T flag. To enable the serial digital interface assert the SS input low. The SS input allows the serial digital interface to be shared with other devices. When the device count is 1-2, the SS input may be held low at all times or asserted low at each read of the ADC results after the BUSY output has gone low. Asserting SS low at each ADC result read will allow a FAUL T report to be cleared. At each SCK rising edge, the MISOA and MISOB data is read by the external master controller and the next data bit is registered to the MISOA and MISOB pin. The external master controller must read the result in one transaction prior to the next CNV rising edge.

Rev CFor more information www.analog.com APPLICATIONS INFORMATION DIGITAL INTERFACE The LTM2893 has a serial digital interface. The flexible VL supply allows the LTM2893 to communicate with digital logic operating between 1.71V and 5.5V, including 2.5V and 3.3V systems. The serial digital interface matches the characteristics of a serial peripheral interface bus (SPI) mode (0, 0) with a minor variation that data is captured on the rising edge and changes after the rising edge for SCK2 frequencies of 100MHz and 66MHz, except for MOSI2 on the LTM2893-1, which changes data on the falling edge of SCK2 in all cases. This variation allows for additional propagation and setup time to the next rising clock (SCK) edge, and should be transparent in most ap- plications. For SCK2 frequencies of 50MHz or less, data is captured on the rising edge of SCK and changes on the falling edge of SCK. The serial output data is clocked out on the MISO pin when SS is low and an external clock is applied to the SCK pin. Clocking out the data immediately after the BUSY signal goes low will yield the best performance. When SS is high, the MISOA and MISOB pins are high impedance. The serial digital interface is monitored by the fault detec- tion system watchdog for conditions that are considered a stalled process. Input timing is monitored for delays longer than tWATCHDOG_TIMEOUT between the rising edges of adjacent SCKs. The SCKs are counted and if the expected number is exceeded, the FAUL T output will go low. The rise and fall time of the logic signals into and out of the serial digital interface are approximately 1ns or less. Careful routing between the master device and the LTM2893 are necessary to avoid reflections resulting in incorrect data sampling or double clocking. Short direct routing with ground shielding is necessary. Avoid adding stubs to the signal routing as these may cause reflections. STARTUP The LTM2893 has an internal startup communication rou- tine to verify both sides of the isolation barrier are ready for communication. The startup routine is initiated when voltage is supplied to V CC and VCC2 inputs above 2.75V, VL and VL2 inputs above 1.5V, the logic side ON signal is high, and the Isolated ON2 signal is high. The BUSY signal will go high and then low indicating the two internal isolators have completed the communication startup routine. Once the BUSY output goes low, the system is ready. The isolated ON2 pin can be controlled by an external volt- age supervisor to delay the system ready signal until all i solated supplies and systems are ready. An example of this is demonstrated in Figure 16 with a LTC2917 configurable voltage supervisor . The logic side BUSY signal will stay high until the isolated side super visor has verified the supplies are above the specified voltage. BUSY INDICATOR (LOGIC SIDE) The BUSY output pin goes high under three conditions: at startup, during data conversion, and when a watchdog timeout occurs. During normal operation, after a CNV rising edge, a high on the BUSY output indicates the ADC is currently converting an ADC result and is de-asserted when the data is ready to be read from MISOA and MISOB. Wait for the BUSY output to go low and wait a t SSFSCK delay before initiating the first SCK after SS is set low. This delay allows the most significant bit to be setup properly. During startup the BUSY output is set high to indicate the LTM2893 is powering up and will be de-asserted when isolated communication is verified. If a watchdog time-out occurs the BUSY signal will go high and the FAUL T pin will go low. BUSY2 AND BUSYS INPUTS (ISOLATED SIDE) The isolated side signals BUSY2 and BUSYS control when the LTM2893 reads data from the ADC(s). Multiple con - figurations of the two isolated busy signals exist. Internally, the BUSY2 and the BUSYS input are logically OR-ed into a single busy response for which the falling edge is used to trigger the ready to read isolated SPI port function. If a single ADC is connected to the LTM2893, the ADC BUSY output connects to the BUSY2 signal and BUSYS is connected to GND2, see Figure 14. Once the BUSY2 signal goes high then low, a SPI transaction will begin. ADCs that contain a sleep function when two conversion start events are triggered without a SPI read must be treated differently. The LTM2893 does not wake up ADCs

that use this function, such as the LTC2338 and LTC2328. keep the ADC awake, see Figure 13. this keep-alive function shown in Figure 2. Table 1. Fault Reporting greater than the minimum referenced in Table 5. of SCKs during a read is considered a fault. L2, or VCC2 was removed and returned. Indicates unexpected interface loss. the read of the serial digital interface. device related to the acquisition of an analog input signal. transition times relative to an analog to digital conversion. of the operation of the CNV , BUSY, or SS active duration. signal transitions within 150ns of the CNV or SS signal. Figure 2. ADC Keep-Alive and Sleep Enable

28931 F02

communication error or an erroneous input condition. FAUL T pin goes low a watchdog time out has occurred. The configuration register is cleared and must be rewritten.

Rev CFor more information www.analog.com APPLICATIONS INFORMATION The direction of the SA, SB, or SC signals may be changed independently with the configuration register . The default condition of ‘0’ for each select bit maintains the signal flow from logic-to-isolated. Loading a ‘1’ into the direction bits will change the direction for that pin(s) to isolated-to-logic. Warning: Careful planning is required for the use of SA, SB, and SC signals. Figure 12 shows the regions were transitions are safe and not safe for the logic side interface. The select signals are sampled and transferred as a packet of the current value of the three signals. The select signal sampling will have up to 10ns of sampling jitter . If a signal transitions after another signal was sampled and is in the process of being transferred to the adjacent side, it will be delayed until the next available transmission slot. The delay may cause a perceived jitter or uncertainty of 80ns. CONFIGURATION REGISTER The LTM2893 contains a configuration register to adjust parameters of the speed and features of the ADC write and read process. After power up, write the configura - tion register by setting the CSC chip select input low and clocking in a one-byte configuration word with SCK and MOSI. The configuration register contains two bytes where the most significant bit of the SPI word selects which byte is addressed. Complete each configuration word by reasserting CSC high. The isolated side will be configured through an internal communication. Table 3 shows the configuration register bit map for control- ling the operation and frequency of the logic and isolated inter faces. The configuration register allows adjustment of the default SCK frequency, direction of the SA, SB, SC to SA2, SB2, SC2 signals, the length of the SPI word and number of SPI words to process per SS cycle. Figure 8 demonstrates access to the configuration register . SCK AND SCK2 FREQUENCY The SCK2 frequency selection list is shown in Table 4. Select the SCK2 frequency that is equal or less than the specifications of the ADC’s SPI port. Example: the LTC2338 has a 100MHz SCK maximum, 10ns minimum SCK period; therefore configure SCK2 for 100MHz. The isolated SCK2 frequency is an internal trimmed oscil- lator . Graph SCK2 Frequency Variation versus Temperature shows the minimum and maximum characteristics over temperature and trim variation of the SC K2 frequency. The logic-side SPI SCK frequency may be selected within a range that is dependent on the isolated-side’s SCK2 frequency. The minimum SCK frequency is limited to avoid triggering the watchdog timer and the maximum SCK frequency is limited to prevent a SPI buffer under-run. To prevent a watchdog time out, the logic-side SPI SCK frequency must be at least 0.00795 times SCK2. If a watchdog timeout occurs, the FAUL T flag will assert low. To prevent a SPI buffer under-run, either the logic-side SPI SCK frequency must be less than the SCK2 frequency or there needs to be a sufficient delay after BUSY falls, t BUSYFSCKR, so that the buffer will be full enough to allow its reading at the desired logic-side SPI SCK frequency. If these conditions are not met and a buffer under-run occurs, then the FAUL T flag will assert low. Accounting for temperature and trim variations, the lowest SCK2 frequency will be 0.925 times the nominal SCK2 frequency. The delay t BUSYFSCKR is calculated using Equation 1 and Table 2 lists values of tBUSYFSCKR for common operating conditions. Equation 1: tBUSYFSCKR ≥ WORD COUNT • WORDLENGTH −2 SCK2 • 0.925 + 2ns, tSSFSCK,MIN max WORD COUNT • WORDLENGTH −1 SCKMAX where tBUSYFSCKR is the time between the falling edge of BUSY and the 1st rising edge of SCK, SCK2 is the nominal configured frequency in Hz and SCK_MAX is the maximum frequency in Hz.

K2 if the corresponding tBUSYFSCKR is observed. BUSYFSCKR calculated in Equation 1.

WORDLENGTH) is equal to or less than 32 bits, the delay needed to meet timing at the maximum SCK frequency of 100MHz is equal to the minimum SS to SCK required and therefore no additional delay is required.

Table 2. BUSY Fall to SCK Rising Delay Required for Major new SPI transaction or a new rising edge on CNV . 3-4 with a word-length of 16.

Figure 3. LTM2893-1 Example Word Delay on Isolated Figure 4. LTM2893-1 Example Word Delay on Isolated Figure 5. LTM2893-1 Worst Case Example Word Delay Figure 11 for a timing representation of the transactions.

2893 F03

2893 F04

2893 F05

setup time SCK2 frequency is set to 50MHz. of ADCs are read simultaneously with the SCK2 signal.

28931 F07

Figure 7. DEVICECOUNT , WORDCOUNT in Parallel and Chain Configuration

28931 F06

WORD COUNT = 2, WORDLENGTH = 18 OR 24. Figure 6. Connecting Four ADCs, One Chain Into MISOA2 and One Chain Into MISOB2

Table 3. Configuration Registers

0 OSCDIV2 OSCDIV1 OSCDIV0 CRC enable

1 Reserved

Table 4. SCK2 Frequency Selection Table (Configuration Register 0 Bit 6, 5, 4) configuration register write requires adherence to the minimum SCK frequency specification. Table 5. SCK Frequency Selection Timing Specifications Note: Exceeding Max of tCSFSCK on the LTM2893, or tSCK, tSSFSCK, or tSCKSSDIS on the LTM2893-1 will result in a watchdog timeout setting FAUL T low. Table 6. SPI Word Length Selection Table (Configuration Register 1 Bits 2, 1, 0)

require the word count to be two. signed per the data sheet PCB layout recommendations. Table 8. Immunity Testing the rated isolation voltage. Length is in units of cm and tRISEFALL is in units of ps. Table 7. SPI Device Count or Word Count Selection Table (Configuration Register 1 Bits 4, 3)

characteristic to be calculated to achieve a sampling rate. frequency is 12.5MHz or 6.25MHz. tCRC: 0ns if CRCENA = 0, 225ns if CRCENA=1. CNV rising edge, minimum of 20ns. relationship of these parameters to a conversion cycle. Figure 8. Writing Configuration Registers Timing Diagram

2893 F08

Figure 9. Logic Side Interface of ADC of the ADC result is set on the MISOA and MISOB pins. second SPI data path is not used. cleared on the next transaction. additional conversion request on CNV .

2893 F09

the full logic side SPI word has been received from MOSI. isolated side sees two transactions, a read and then a write. time penalty and requires flexibility on the part of the ADC. Figure 10. Isolated Side Interface for an ADC Conversion

2893 F10

Figure 11. Isolated Side Read and Write to ADC (LTM2893-1) tSCKSSDIS + tCRC + tQUIET + tADDISODELAY. timing loss to important conversion or result information.

2893 F11

Figure 12. Select Signals Safe T ransition Regions

2893 F12

Figure 13. Isolated 1Msps LTC2338-18 Fully Differential ±10V Input Range, with ADC Sleep Disabled (CNV2 = BUSYS) SUPPL Y INDICATES AN ISOLATED SUPPL Y.

28931 F13

Figure 14. Isolated 1Msps LTC2378-18 Single-Ended 0V to 5V Input (BUSYS = GND2)

Figure 15. Isolated 2Msps LTC2314-14 0V to 4.096V Input Range, ADC SETS SCK2 TO 50MHz AND WORDLENGTH TO 16-BIT .

28931 F15

Figure 16. Startup Sequence with a Voltage Supervisor Enabling Isolated Side Including Isolated Power Solution SETS SCK2 TO 50MHz AND WORDLENGTH TO 16-BIT .

28931 F16

Figure 17. LTM2893 with LTC2440 Delta Sigma ADC Figure 18. Use of SA, SB, SC Pins for Multiplexing Analog Inputs to ADC

28931 F17

28931 F18

Figure 19. LTM2893-1 with SoftSpan™ Configurable LTC2348-18 8-Channel Simultaneous Sampling ADC

96 BITS

28931 F19

Rev C For more information www.analog.com PACKAGE DESCRIPTION 36-Lead (15mm × 6.25mm × 2.06mm) (Reference L TC DWG # 05-08-1987 Rev Ø) PACKAGE TOP VIEW PIN “A1” CORNER Y X aaa Z aaa Z 36-Lead (15mm × 6.25mm × 2.06mm) (Reference LTC DWG# 05-08-1987 Rev Ø) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE DETAIL A Øb (36 PLACES) DETAIL B SUBSTRATE A ccc Z DETAIL B PACKAGE SIDE VIEW MOLD CAP Z M X Y Z ddd M Z eee SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 1.86 0.40 1.46 0.45 0.47 0.51 0.95 NOM 2.06 0.50 1.56 0.60 0.50 15.00 6.25 1.00 13.75 5.00 0.56 1.00 MAX 2.26 0.60 1.66 0.75 0.53 0.61 1.05 0.15 0.10 0.15 0.15 0.08 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 36 D E SUGGESTED PCB LAYOUT TOP VIEW 0.00 5.875 6.875 4.875 1.50 1.50 0.50 2.50 2.50 0.50 0.00 6.875 5.875 4.875 6.675 6.125 // bbb Z Z 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu 0.50 ±0.025 Ø 36x 2.75 2.25 BGA 36 0914 REV Ø TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y PACKAGE BOTTOM VIEW R P N M L K J H G F E D C B A 1 2 3 4 5 6 DETAIL A SEE NOTES PIN 1 e e F G b SEE NOTES b

Rev CFor more information www.analog.com

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 03/17 Corrected V CC2 pin number on Block Diagram Corrected SCK and tBUSYFSCKR formulas Correction to Table 2. BUSY Fall to SCK Rising Delay Required for Major Word Boundaries to Operate at Maximum SCK Under Worst Case SCK2 Tolerance Correction to Table 4. SCK2 Frequency Selection Multiple corrections to Table 5. SCK Frequency Selection Timing Specifications Corrections to multiple sampling rate parameters (t BUSY2FBUSYF, tBUSYFSCKR, tDATAREAD) B 05/17 Revised SS pin description Revised SCK2 frequency range calculation for H-grade Revised tADC_CYCLE_TIME_MIN equation C 02/18 Added UL/CSA Certifications 1, 5 Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Figure 20. Simultaneous Sampled Line Current and Voltage Measurements with T wo LTC2338-18 ADCs

28931 F20

Product Information

LTM2893 specifications and overview.

Summary

7.5kVRMS SPI/Digital or I2C 關Module Isolator with Transformer Driver Rev. A

Description

7.5kVRMS SPI/Digital or I2C 關Module Isolator with Transformer Driver Rev. A

Source title LTM2893 Datasheet(PDF) - Analog Devices

Related Parts

More parts from the same family.

Browse manufacturer