LTM2892

LTM2892 - SPI/Digital or I2C µModule Isolator

Document overview

• Manufacturer or author: Linear Technology Corporation
• PDF pages: 38

Technical content

2892faFor more information www.linear .com/L TM2892 Typical applicaTion FeaTures DescripTion SPI/Digital or I2C µModule Isolator The LT M®2892 is a complete galvanic digital µModule ® (micromodule) isolator . No external components are re- quired. Individual 3V to 5.5V supplies power each side of the digital isolator. Separate logic supply pins allow easy interfacing with different logic levels from 1.62V to 5.5V, independent of the main supply. Module options are available with compatibility to SPI (LTM2892-S) and I 2C (LTM2892-I), master mode only, specifications. Coupled inductors provide 3500VRMS of isolation between the input and output logic interface. This device is ideal for systems where the ground loop is broken, allowing uninterrupted communication through large common mode transients faster than 50kV/μs. L, L T , L TC, L TM, Linear Technology, the Linear logo and µModule are registered trademarks and HotSwap is a trademark of of Linear Technology Corporation. All other trademarks are the property of their respective owners. Isolated 4MHz SPI Interface

applicaTions

n 6-Channel Logic Isolator: 3500VRMS for 1 Minute n UL-CSA Recognized File #E151738 n 3V to 5.5V Supply Operation n No External Components Required n SPI/Digital (LTM2892-S) or I2C (LTM2892-I) Options n High Common Mode T ransient Immunity: 50kV/μs n High Speed Operation: n 10MHz Digital Isolation n 4MHz/8MHz SPI Isolation n 400kHz I2C Isolation n Operation Up to 125°C (H-Grade) n 1.62V to 5.5V Logic Supplies for Flexible Digital Inter- facing n ±15kV ESD HBM Across the Isolation Barrier n Maximum Continuous Working Voltage: 850VPEAK n Low Current Shutdown Mode (<10µA) n Small (9mm × 6.25mm × 2.91mm) BGA Package n Isolated SPI or I2C Interfaces n Industrial Systems n Test and Measurement Equipment n Breaking Ground Loops LTM2892 Operating Through 50kV/µs CM T ransients VCC1 VL1 ON1 EOUTD INA INB INC OUTD OUTE OUTF 3V TO 5.5V MISO SCK MOSI SS 3V TO 5.5V MISO SCK MOSI SS VCC2 VL2 ON2 EOUTA OUTA OUTB OUTC IND INE INF L TM2892-S GND2GND1 ISOLATION BARRIER

2892 TA01a

2892 TA01b

2892fa For more information www.linear .com/L TM2892 absoluTe MaxiMuM raTings Logic Inputs INA , INB, INC, SCLIN, SDA1, EOUTD, INB , INC, IND, INE, INF, SDA2, EOUTA, (Note 1) LTM2892-I LTM2892-S BGA PACKAGE 24-PIN (9mm × 6.25mm × 2.91mm) TOP VIEW OUTB SDA1 OUTC SCLIN SDA1 INA ON1 V L1 VCC1 GND1 INB SDA2 SDA2 INC SCLOUT OUTA ON2 V L2 VCC2 GND2 F G H J E A B C D 5 63 42 1 TJMAX = 125°C, θJA = 30°C/W , θJC(bottom) = 15.7°C/ W, θJC(top) = 25°C/W , θJB = 14.5°C/W θ VALUES DETERMINED PER JESD 51-9, WEIGHT = 0.3g BGA PACKAGE 24-PIN (9mm × 6.25mm × 2.91mm) TOP VIEW OUTD OUTE OUTF EOUTD INA INB INC ON1 V L1 VCC1 GND1 IND INE OUTB INF OUTA OUTC EOUTA ON2 V L2 VCC2 GND2 F G H J E A B C D 5 63 42 1 TJMAX = 125°C, θJA = 30°C/W , θJC(bottom) = 15.7°C/ W, θJC(top) = 25°C/W , θJB = 14.5°C/W θ VALUES DETERMINED PER JESD 51-9, WEIGHT = 0.3g pin conFiguraTion Logic Outputs OUTB, OUTC, OUTD, OUTE, OUTA, OUTB, OUTC, Operating Temperature Range (Note 4) 5°C C to 150°C 0°C

2892faFor more information www.linear .com/L TM2892 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC1 = 5V, VCC2 = 5V, VL1 = 3.3V, VL2 = 3.3V, GND1 = GND2 = 0V, ON1 = VL1, and ON2 = VL2 unless otherwise noted. Specifications apply to all options unless otherwise noted. orDer inForMaTion SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supplies VCC1, VCC2 Input Supply Range l 3 5.5 V VL1, VL2 Logic Supply Range LTM2892-S LTM2892-I l l 1.62 5.5 5.5 V V I CC1, ICC2 Input Supply Current ON1 = ON2 = 0V ON1 = VL1, ON2 = VL2 l l 3.2 4.5 µA mA IL1, IL2 Logic Supply Current ON1 = ON2 = 0V LTM2892-S, ON1 = VL1, ON2 = VL2 IL1, LTM2892-I, ON1 = VL1, ON2 = VL2 IL2, LTM2892-I, ON1 = VL1, ON2 = VL2 l l 150 300 µA µA µA µA Logic/SPI V ITH Input Threshold Voltage ON1, INx, EOUTD, 1.62V ≤ V L1 < 2.35V ON1, INx, EOUTD, 2.35V ≤ VL1 ON2, INx, EOUTA, 1.62V ≤ VL2 < 2.35V ON2, INx, EOUTA, 2.35V ≤ VL2 l l l l 0.25•VL1 0.33•VL1 0.25•VL2 0.33•VL2 0.75•VL1 0.67•VL1 0.75•VL2 0.67•VL2 V V V V I INL Input Current l ±1 µA VHYS Input Hysteresis (Note 2) 150 mV VOH Output High Voltage OUTx, I LOAD = –1mA, 1.62V ≤ VL1 < 3V OUTx, ILOAD = –4mA, 3V ≤ VL1 ≤ 5.5V OUTB (LTM2892-I), ILOAD = –2mA, 3V ≤ VL1 ≤ 5.5V l VL1 – 0.4 V OUTx, ILOAD = –1mA, 1.62V ≤ VL2 < 3V OUTx, ILOAD = –4mA, 3V ≤ VL2 ≤ 5.5V l VL2 – 0.4 V LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTM2892CY-I#PBF LTM2892CY-I#PBF LTM2892Y-I 24-Lead (9mm × 6.25mm × 2.91mm) BGA 0°C to 70°C LTM2892IY-I#PBF LTM2892IY-I#PBF LTM2892Y-I 24-Lead (9mm × 6.25mm × 2.91mm) BGA –40°C to 85°C LTM2892HY-I#PBF LTM2892HY-I#PBF LTM2892Y-I 24-Lead (9mm × 6.25mm × 2.91mm) BGA –40°C to 125°C LTM2892CY-S#PBF LTM2892CY-S#PBF LTM2892Y-S 24-Lead (9mm × 6.25mm × 2.91mm) BGA 0°C to 70°C LTM2892IY-S#PBF LTM2892IY-S#PBF LTM2892Y-S 24-Lead (9mm × 6.25mm × 2.91mm) BGA –40°C to 85°C LTM2892HY-S#PBF LTM2892HY-S#PBF LTM2892Y-S 24-Lead (9mm × 6.25mm × 2.91mm) BGA –40°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear .com/packaging/ This product is moisture sensitive. For more information go to: http://www.linear .com/packaging/ http://www.linear .com/product/LTM2892#orderinfo

2892fa For more information www.linear .com/L TM2892 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC1 = 5V, VCC2 = 5V, VL1 = 3.3V, VL2 = 3.3V, GND1 = GND2 = 0V, ON1 = VL1, and ON2 = VL2 unless otherwise noted. Specifications apply to all options unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VOL Output Low Voltage OUTx, I LOAD = 1mA, 1.62V ≤ VL1 < 3V OUTx, ILOAD = 4mA, 3V ≤ VL1 ≤ 5.5V OUTB (LTM2892-I), ILOAD = 2mA, 3V ≤ VL1 ≤ 5.5V l 0.4 V OUTx, ILOAD = 1mA, 1.62V ≤ VL2 < 3V OUTx, ILOAD = 4mA, 3V ≤ VL2 ≤ 5.5V l 0.4 V ISC Short-Circuit Current 0V ≤ OUTx ≤ V L1 0V ≤ OUTB (LTM2892-I) ≤ VL1 0V ≤ OUTx ≤ VL2 l l ±30 ±85 ±85 mA mA mA I VIL Low Level Input Voltage SCLIN, SDA1 SDA2 l l 0.3•VL1 0.3•VL2 V V VIH High Level Input Voltage SCLIN, SDA1 SDA2 l l 0.7•VL1 0.7•VL2 V V IINL Input Current SCLIN, SDA1 = VL1 or 0V SDA2 = VL2, SDA2 = VL2 = 0V l l µA µA V HYS Input Hysteresis SCLIN, SDA1 SDA2 0.05•V 0.05•VL2 mV mV V OH Output High Voltage SCLOUT , I LOAD = –2mA l VL2 – 0.4 V VOL Output Low Voltage SDA1, I LOAD = 3mA, SCLOUT , ILOAD = 2mA SDA2 = No Load, SDA1 = 0V, 4.5V ≤ VL2 < 5.5V SDA2 = No Load, SDA1 = 0V, 3V ≤ VL2 < 4.5V l l l 0.3 0.4 0.45 0.55 V V V C IN Input Pin Capacitance SCLIN, SDA1, SDA2 (Note 2) l 10 pF CB Bus Capacitive Load SCLOUT , Standard Speed (Note 2) SCLOUT , Fast Speed SDA1, SDA2, SR ≥ 1V/μs, Standard Speed (Note 2) SDA1, SDA2, SR ≥ 1V/μs, Fast Speed l l l l 400 200 400 200 pF pF pF pF SDA, SDA2 Slew Rate l 1 V/µs ISC Short-Circuit Current SDA2 = 0, SDA1 = V L1 0V ≤ SCLOUT ≤ VL2 SDA1 = 0, SDA2 = VL2 SDA1 = VL1, SDA2 = 0 l ±30 –1.8 100 mA mA mA mA ESD (HBM) (Note 2) Isolation Boundar y GND2 to GND1 (VCC2, VL2, GND2) to (VCC1, VL1, GND1) ±15 ±10 kV kV

2892faFor more information www.linear .com/L TM2892 swiTching characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC1 = 5V, VCC2 = 5V, VL1 = 3.3V, VL2 = 3.3V, GND1 = GND2 = 0V, ON1 = VL1, and ON2 = VL2 unless otherwise noted. Specifications apply to all options unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Logic/SPI Maximum Data Rate INx → OUTx, CL = 15pF (Note 3) Bidirectional SPI Communication Unidirectional SPI Communication l l l MHz MHz MHz t PHL, tPLH Propagation Delay INx → OUTx, CL = 15pF (Figure 1) l 35 60 100 ns tR, tF Rise and Fall Time OUTx, CL = 15pF (Figure 1) LTM2892-I, OUTB, CL = 15pF (Figure 1) l l 12.5 ns ns tPWU Output Pulse Width Uncertainty OUTB, OUTC, OUTE, OUTF (Note 2) –20 50 ns tPZH, tPZL Output Enable Time EOUTx = ↓ to OUTx, RL = 1k, CL = 15pF (Figure 2) l 50 ns tPHZ, tPLZ Output Disable Time EOUTx = ↑ to OUTx, RL = 1k, CL = 15pF (Figure 2) l 50 ns tPZH, tPZL ONx Enable Time ONx = ↑ to OUTx, RL = 1k, CL = 15pF (Figure 4) l 60 μs tPHZ, tPLZ ONx Disable Time ONx = ↓ to OUTx, RL = 1k, CL = 15pF (Figure 4) l 50 ns I2C Maximum Data Rate (Note 3) l 400 kHz tPHL, tPLH Propagation Delay SCLIN → SCLOUT , CL = 15pF (Figure 1) SDA1 → SDA2, RL = Open, CL = 15pF (Figure 3) SDA2 → SDA1, RL = 1.1k, CL = 15pF (Figure 3) l l l 150 150 300 225 250 500 ns ns ns t R Rise Time SDA2, CL = 200pF (Figure 3) SDA2, CL = 200pF (Figure 3) SDA1, RL = 1.1k, CL = 200pF (Figure 3) SCLOUT , CL = 200pF (Figure 3) l l l 300 250 250 250 ns ns ns ns t F Fall Time SDA2, CL = 200pF (Figure 3) SDA1, RL = 1.1k, CL = 200pF (Figure 3) SCLOUT , CL = 200pF (Figure 3) l l l 250 250 250 ns ns ns t PWU Output Pulse Width Uncertainty SDA1, SDA2 (Note 2) –20 50 ns tPZH, tPZL ONx Enable Time ON1 = ↑ to SDA1, RL = 1k, CL = 15pF (Figure 4) ON2 = ↑ to (SCLOUT , SDA2), CL = 15pF (Figure 4) l l 60 μs tPHZ, tPLZ ONx Disable Time ON1 = ↓ to SDA1, RL = 1k, CL = 15pF (Figure 4) ON2 = ↓ to SCLOUT , RL = 1k, CL = 15pF (Figure 4) ON2 = ↓ to SDA2, RL = Open, CL = 15pF (Figure 4) l l l 225 ns ns ns t SP Pulse Width of Spikes Suppressed by Input Filter l 0 50 ns

2892fa For more information www.linear .com/L TM2892 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VISO Rated Dielectric Insulation Voltage 1 Minute, Derived from 1 Second Test

1 Second (Notes 5, 6)

Common Mode T ransient Immunity V CC1 = VL1 = ON1 = 5V, VCC2 = VL2 = ON2 = 5V VCM = 1kV, ∆t = 20ns (Note 2) 50 kV/µs VIORM Maximum Continuous Working Voltage (Notes 2, 5) 850 600 V PEAK VRMS Partial Discharge VPD = 1590VPEAK (Note 5) 5 pC CTI Comparative T racking Index IEC 60112 (Note 2) 600 VRMS Depth of Erosion IEC 60112 (Note 2) 0.1 mm DTI Distance Through Insulation (Note 2) 0.1 mm Input to Output Resistance (Notes 2, 5) 1012 Ω Input to Output Capacitance (Notes 2, 5) 3 pF Creepage Distance (Note 2) 5 mm isolaTion characTerisTics TA = 25°C Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Guaranteed by design and not subject to production test. Note 3: Maximum data rate is guaranteed by other measured parameters and is not tested directly. Note 4: This µModule isolator includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above specified maximum operating junction temperature may result in device degradation or failure. Note 5: Device is considered a 2-terminal device. Pin group A1 through B6 shorted together and pin group H1 through J6 shorted together . Note 6: The rated dielectric insulation voltage should not be interpreted as a continuous voltage rating.

2892faFor more information www.linear .com/L TM2892 Typical perForMance characTerisTics SDA1 Low Level Output Voltage vs Temperature SDA2 Low Level Output Voltage vs Temperature Supply Current vs INA to OUTA Data Rate Supply Current vs INA to OUTA Data Rate V CCx and VLx Supply Current vs Temperature VCCx Supply Current vs Temperature VLx Supply Current vs Temperature TA = 25°C, VCC1 = 5V, VCC2 = 5V, VL1 = 3.3V, VL2 = 3.3V, GND1 = GND2 = 0V, ON1 = VL1, and ON2 = VL2, unless otherwise noted. Logic Input Threshold vs V Lx Supply Voltage Logic Output Voltage vs Load Current TEMPERATURE (°C) –50 SUPPL Y CURRENT (mA) 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 500 100

2892 G01

12525–25 75 L TM2892-S NO LOAD, REFRESH DATA ONL Y VCC1 = VL1 = 3.3V VCC2 = VL2 = 3.3V VCC1 = VL1 = 5V VCC2 = VL2 = 5V TEMPERATURE (°C) –50 SUPPL Y CURRENT (mA) 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 500 100

2892 G02

12525–25 75 L TM2892-I NO LOAD, REFRESH DATA ONL Y VCC1 = 3.3V VCC2 = 3.3V VCC1 = 5V VCC2 = 5V TEMPERATURE (°C) –50 SUPPL Y CURRENT (µA) 350 300 250 200 150 100 500 100

2892 G03

12525–25 75 L TM2892-I NO LOAD, REFRESH DATA ONL Y VL1 = 3.3V VL2 = 3.3V VL1 = 5V VL2 = 5V VLx SUPPL Y VOL TAGE (V) THRESHOLD VOL TAGE (V) 3.5 2.5 0.5 1.0 2.0 3.0 1.5 4 52

2892 G04

|LOAD CURRENT| (mA) OUTPUT VOL TAGE (V) 2 1 3

2892 G05

VLx = 5.5V VLx = 3.3V VLx = 1.62V TEMPERATURE (°C) –50 OUTPUT VOL TAGE (V) 0.5 0.4 0.3 0.2 0.1 500 100

2892 G06

12525–25 75 L TM2892-I SDA1 RPU = 1.1k VL1 = 3.3V VL1 = 5V TEMPERATURE (°C) –50 OUTPUT VOL TAGE (V) 0.5 0.4 0.3 0.2 0.1 500 100

2892 G07

12525–25 75 L TM2892-I VL2 = 3.3V VL2 = 5V FREQUENCY (kHz) SUPPL Y CURRENT (mA) 100

2892 G08

VCC1 = VL1 = 3.3V VCC2 = VL2 = 3.3V ICC1, OUTA = ANY LOAD ICC2, OUTA = ANY LOAD IL2, OUTA = NO LOAD IL2, OUTA = 100pF LOAD FREQUENCY (kHz) SUPPL Y CURRENT (mA) 100

2892 G09

VCC1 = VL1 = 3.3V VCC2 = VL2 = 5V ICC1, OUTA = ANY LOAD ICC2, OUTA = ANY LOAD IL2, OUTA = NO LOAD IL2, OUTA = 100pF LOAD

2892fa For more information www.linear .com/L TM2892 Typical perForMance characTerisTics Supply Current vs Data Rate, All Channels Supply Current vs Data Rate, All Channels Supply Current vs Data Rate, All Channels Supply Current vs INA to OUTA Data Rate Supply Current vs INA to OUTA Data Rate Supply Current vs Data Rate, All Channels TA = 25°C, VCC1 = 5V, VCC2 = 5V, VL1 = 3.3V, VL2 = 3.3V, GND1 = GND2 = 0V, ON1 = VL1, and ON2 = VL2, unless otherwise noted. FREQUENCY (kHz) SUPPL Y CURRENT (mA) 100

2892 G10

VCC1 = VL1 = 5V VCC2 = VL2 = 3.3V ICC1, OUTA = ANY LOAD ICC2, OUTA = ANY LOAD IL2, OUTA = NO LOAD IL2, OUTA = 100pF LOAD FREQUENCY (kHz) SUPPL Y CURRENT (mA) 100

2892 G11

VCC1 = VL1 = 5V VCC2 = VL2 = 5V ICC1, OUTA = ANY LOAD ICC2, OUTA = ANY LOAD IL2, OUTA = NO LOAD IL2, OUTA = 100pF LOAD FREQUENCY (kHz) SUPPL Y CURRENT (mA) 100

2892 G12

VCC1 = VL1 = 3.3V VCC2 = VL2 = 3.3V ICC1 OR ICC2, ANY LOAD ALL CHANNELS IL1 OR IL2, NO LOAD EACH CHANNEL IL1 OR IL2, 100pF LOAD ALL CHANNELS FREQUENCY (kHz) SUPPL Y CURRENT (mA) 100

2892 G13

VCC1 = VL1 = 3.3V VCC2 = VL2 = 5V ICC1 OR ICC2, ANY LOAD, ALL CHANNELS I L1, NO LOAD, EACH CHANNEL IL2, NO LOAD, EACH CHANNEL IL1, 100pF LOAD, ALL CHANNELS IL2, 100pF LOAD, ALL CHANNELS FREQUENCY (kHz) SUPPL Y CURRENT (mA) 100

2892 G14

VCC1 = VL1 = 5V VCC2 = VL2 = 3.3V ICC1 OR ICC2, ANY LOAD, ALL CHANNELS I L1, NO LOAD, EACH CHANNEL IL2, NO LOAD, EACH CHANNEL IL1, 100pF LOAD, ALL CHANNELS IL2, 100pF LOAD, ALL CHANNELS FREQUENCY (kHz) SUPPL Y CURRENT (mA) 100

2892 G15

VCC1 = VL1 = 5V VCC2 = VL2 = 5V ICC1 OR ICC2, ANY LOAD, ALL CHANNELS I L1 OR IL2, NO LOAD, EACH CHANNEL I L1 OR IL2, 100pF LOAD, ALL CHANNELS

2892faFor more information www.linear .com/L TM2892 pin FuncTions Logic Side SCLIN (A1): Serial I2C Clock Input, Referenced to VL1 and GND1. Logic input connected to isolated side SCLOUT pin through the isolation barrier . Clock is unidirectional from logic to isolated side. Pull up to V L1 if not used. SDA1 (A2, B2): Serial I 2C Data Pins, Referenced to V L1 and GND1. Bidirectional logic pins connected to isolated side SDA2 pins through the isolation barrier . Under the condition of an isolation communication failure pins are in a high impedance state. Pins connected internally. Pull up to V L1 if not used. INA (A3): Digital Input, Referenced to VL1 and GND1. Logic input connected to OUTA through the isolation barrier . The logic state on INA translates to the same logic state on OUTA. Connect to GND1 or V L1 if not used. ON1 (A4): Enable, Referenced to VL1 and GND1. Enables data communication through the isolation barrier . If ON1 is high the part is enabled and communications are func- tional to the isolated side. If ON1 is low the logic side is held in reset, all digital outputs are in a high impedance state. Connect to V L1 if not driven. VL1 (A5): Logic Supply. Interface supply voltage for pins SCLIN, INA, OUTB, OUTC, and ON1. Operating voltage is 3V to 5.5V. Internally bypassed with 0.22μF. V CC1 (A6): Supply Voltage. Operating voltage is 3V to 5.5V. Internally bypassed with 1.0μF. OUTB (B1): Digital Output, Referenced to V L1 and GND1. Logic output connected to INB through the isolation bar- rier . Under the condition of an isolation communication failure this output is in a high impedance state. OUTC (B3): Digital Output, Referenced to VL1 and GND1. Logic output connected to INC through the isolation bar- rier . Under the condition of an isolation communication failure this output is in a high impedance state. GND1 (B4 to B6): Circuit Ground. Isolated Side SCLOUT (H1): Serial I 2C Clock Output, Referenced to VL2 and GND2. Logic output connected to logic side SCLIN pin through the isolation barrier . Clock is unidirectional from logic to isolated side. SCLOUT has a push-pull output stage; do not connect an external pull-up device. Under the condition of an isolation communication failure this output defaults to a high state. SDA2 (H2, J2): Serial I 2C Data Pins, Referenced to V L2 and GND2. Bidirectional logic pins connected to logic side SDA1 pins through the isolation barrier . Output is biased high by a 1.8mA current source. Do not connect an external pull-up device to SDA2. Under the condition of an isolation communication failure outputs default to a high state. Pins connected internally. OUTA (H3): Digital Output, Referenced to V L2 and GND2. Logic output connected to INA through the isolation bar- rier . Under the condition of an isolation communication failure OUTA defaults to a high state. GND2 (H3 to H5): Isolated Ground. INB (J1): Digital Input, Referenced to VL2 and GND2. Logic input connected to OUTB through the isolation barrier . The logic state on INB translates to the same logic state on OUTB. Connect to GND2 or V L2 if not used. INC (J3): Digital Input, Referenced to VL2 and GND2. Logic input connected to OUTC through the isolation barrier . The logic state on INC translates to the same logic state on OUTC. Connect to GND2 or V L2 if not used. ON2 (J4): Enable, Referenced to VL2 and GND2. Enables data communication through the isolation barrier . If ON2 is high the part is enabled and communications are functional to the logic side. If ON2 is low the isolated side is held in reset, all digital outputs are in a high state. Connect to V L2 if not driven. VL2 (J5): Logic Supply, Referred to GND2. Interface sup- ply voltage for pins SCLOUT , SDA2, INB, INC, OUTA, and ON2 . Operating voltage is 3V to 5.5V. Internally bypassed with 0.22μF. VCC2 (J6): Supply Voltage, Referred to GND2. Operating voltage is 3V to 5.5V. Internally bypassed with 1.0μF. (LTM2892-I)

2892fa For more information www.linear .com/L TM2892 pin FuncTions Logic Side INA (A1): Digital Input, Referenced to VL1 and GND1. Logic input connected to OUTA through the isolation barrier . The logic state on INA translates to the same logic state on OUTA. Connect to GND1 or V L1 if not used. INB (A2): Digital Input, Referenced to VL1 and GND1. Logic input connected to OUTB through the isolation barrier . The logic state on INB translates to the same logic state on OUTB. Connect to GND1 or V L1 if not used. INC (A3): Digital Input, Referenced to VL1 and GND1. Logic input connected to OUTC through the isolation barrier . The logic state on INC translates to the same logic state on OUTC. Connect to GND1 or V L1 if not used. ON1 (A4): Enable, Referenced to VL1 and GND1. Enables data communication through the isolation barrier . If ON1 is high the part is enabled and communications are func- tional to the isolated side. If ON1 is low the logic side is held in reset, all digital outputs are in a high impedance state. Connect to V L1 if not driven. VL1 (A5): Logic Supply. Interface supply voltage for pins INA, INB, INC, OUTD, OUTE, OUTF , EOUTD, and ON1. Operating voltage is 1.62V to 5.5V. Internally bypassed with 0.22μF. V CC1 (A6): Supply Voltage. Operating voltage is 3V to 5.5V. Internally bypassed with 1.0μF. OUTD (B1): Digital Output, Referenced to V L1 and GND1. Logic output connected to IND through the isolation bar- rier . Under the condition of an isolation communication failure this output is in a high impedance state. OUTE (B2): Digital Output, Referenced to VL1 and GND1. Logic output connected to INE through the isolation barrier . Under the condition of an isolation communication failure this output is in a high impedance state. OUTF (B3): Digital Output, Referenced to V L1 and GND1. Logic output connected to INF through the isolation barrier . Under the condition of an isolation communication failure this output is in a high impedance state. EOUTD (B4): Digital Output Enable, Referenced to V and GND1. A logic high on EOUTD places the logic side OUTD pin in a high impedance state, a logic low enables the output. Connect to GND1 or V L1 if not used. GND1 (B5, B6): Circuit Ground. (LTM2892-S) Isolated Side OUTA (H1): Digital Output, Referenced to VL2 and GND2. Logic output connected to INA through the isolation bar- rier . Under the condition of an isolation communication failure OUTA defaults to a low state. OUTB ( H2): Digital Output, Referenced to VL2 and GND2. Logic output connected to INB through the isolation bar- rier . Under the condition of an isolation communication failure OUTB defaults to a low state. OUTC (H3): Digital Output, Referenced to V L2 and GND2. Logic output connected to INC through the isolation bar- rier . Under the condition of an isolation communication failure OUTC defaults to a high state. EOUTA (H4): Digital Output Enable, Referenced to V L2 and GND2. A logic high on EOUTA places the logic side OUTA pin in a high impedance state, a logic low enables the output. Connect to GND2 or V L2 if not used. GND2 (H5, H6): Isolated Ground. IND (J1): Digital Input, Referenced to VL2 and GND2. Logic input connected to OUTD through the isolation barrier . The logic state on IND translates to the same logic state on OUTD. Connect to GND2 or V L2 if not used. INE (J2): Digital Input, Referenced to VL2 and GND2. Logic input connected to OUTE through the isolation barrier . The logic state on INE translates to the same logic state on OUTE. Connect to GND2 or V L2 if not used. INF (J3): Digital Input, Referenced to VL2 and GND2. Logic input connected to OUTF through the isolation barrier . The logic state on INF translates to the same logic state on OUTF . Connect to GND2 or V L2 if not used. ON2 (J4): Enable, Referenced to VL2 and GND2. Enables data communication through the isolation barrier . If ON2 is high the part is enabled and communications are functional to the logic side. If ON2 is low the isolated side is held in reset, OUTA and OUTB are in a low state, and OUTC is in a high state. Connect to V L2 if not driven. VL2 (J5): Logic Supply, Referred to GND2. Interface supply voltage for pins OUTA, OUTB, OUTC, IND, INE, INF , EOUTA, and ON2. Operating voltage is 1.62V to 5.5V. Internally bypassed with 0.22μF. V CC2 (J6): Supply Voltage, Referred to GND2. Operating voltage is 3V to 5.5V. Internally bypassed with 1.0μF.

2892faFor more information www.linear .com/L TM2892 block DiagraMs LTM2892-I L TM2892-I

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0.22µF 0.22µF VL1 VCC1 GND1 ON1 SCLIN SDA1 INA 1µF 1µF OUTB SDA1 OUTC VL2 VCC2 GND2 ON2 SCLOUT SDA2 OUTA INB SDA2 INC

2892fa For more information www.linear .com/L TM2892 LTM2892-S block DiagraMs ISOLATED COMMUNICATIONS INTERFACE ISOLATED COMMUNICATIONS INTERFACE 0.22µF 0.22µF VL1 VCC1 GND1 ON1 INA EOUTD INB INC 1µF 1µF OUTD OUTE OUTF VL2 VCC2 GND2 ON2 OUTA EOUTA OUTB OUTC IND INE INF L TM2892-S

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Figure 1. Logic Timing Measurements Figure 2. Logic Enable/Disable Time

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Figure 4. ONx Enable/Disable Time Figure 3. I2C Timing Measurements

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Figure 5. Supplies Are Independent and mitigation of this phenomenon.

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networks where grounds can take on different voltages. as fast as 50kV/μs providing excellent noise isolation.

high priority serial packet. pulse width uncertainty, and data direction requirements. and clock phase (CPHA) summarized in Table 1. Table 1. SPI Mode

• CS to SCK (master sample SDO, 1st SDO valid) t0 → t1 ≈50ns, CS to CS2 propagation delay t1 → t1+ Isolated slave device propagation (response time), asserts SDO2 t1 → t3 ≈50ns, SDO2 to SDO propagation delay t3 → t5 Setup time for master SDO to SCK
• SDI to SCK (master data write to slave) t2 → t4 ≈50ns, SDI to SDI2 propagation delay t5 → t6 ≈50ns, SCK to SCK2 propagation delay t2 → t5 ≥50ns, SDI to SCK, separate packet non-zero setup time t4 → t6 ≥50ns, SDI2 to SCK2, separate packet non-zero setup time
• SDO to SCK (master sample SDO, subsequent SDO valid) t8 Setup data transition SDI and SCK t8 → t10 ≈50ns, SDI to SDI2 and SCK to SCK2 propagation delay t10 SDO2 data transition in response to SCK2 t10 → t11 ≈50ns, SDO2 to SDO propagation delay t11 → t12 Setup time for master SDO to SCK Maximum data rate for single direction communication, master to slave, is 8MHz, limited by the systems encod- ing/decoding scheme or propagation delay. Timing details for both variations of clock phase are shown in Figures 8 and 9 and Table 3. Additional requirements to insure maximum data rate are
• CS is transmitted prior to (asynchronous) or within the same (synchronous) data packet as SDI SDI and SCK setup data transition occur within the same data packet. Referencing Figure 6, SDI can pre- cede SCK by up to 13ns (t 7 → t8) or lag SCK by 3ns (t8 → t9) and not violate this requirement. Similarly in Figure 8, SDI can precede SCK by up to 13ns (t 4 → t5) or lag SCK by 3ns (t5 → t6).

Figure 6. SPI Timing, Bidirectional, CPHA = 0 Figure 7. SPI Timing, Bidirectional, CPHA = 1

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Table 2. Bidirectional SPI Timing Event Description enabled, initial data is not equivalent to slave device data output. t0-t1, t17-t18 0, 1 Propagation delay chip select, logic to isolated side, 50ns typical. t1 0, 1 Slave device chip select output data enable. t2 0 Start of data transmission, data setup. 1 Start of transmission, data and clock setup. Data transition must be within –13ns to 3ns of clock edge. t1-t3 0, 1 Propagation delay of slave data, isolated to logic side, 50ns typical. t3 0, 1 Slave data output valid, logic side. t2-t4 0 Propagation delay of data, logic side to isolated side. 1 Propagation delay of data and clock, logic side to isolated side. 5 0, 1 Logic side data sample time, half clock period delay from data setup transition. t5-t6 0, 1 Propagation delay of clock, logic to isolated side. t6 0, 1 Isolated side data sample time. t8 0, 1 Synchronous data and clock transition, logic side. t7-t8 0, 1 Data to clock delay, must be ≤ 13ns. t8-t9 0, 1 Clock to data delay, must be ≤ 3ns. t8-t10 0, 1 Propagation delay clock and data, logic to isolated side. t10, t14 0, 1 Slave device data transition. t10-t11, t14-t15 0, 1 Propagation delay slave data, isolated to logic side. t11-t12 0, 1 Slave data output to sample clock setup time. t13 0 Last data and clock transition logic side. 1 Last sample clock transition logic side. 13-t14 0 Propagation delay data and clock, logic to isolated side. 1 Propagation delay clock, logic to isolated side. 15 0 Last slave data output transition logic side. 1 Last slave data output and data transition, logic side. 15-t16 1 Propagation delay data, logic to isolated side. t17 0, 1 Asynchronous chip select transition, end of transmission. Disable slave data output logic side. t18 0, 1 Chip select transition isolated side, slave data output disabled.

Figure 8. SPI Timing, Unidirectional, CPHA=0 Figure 9. SPI Timing, Unidirectional, CPHA=1

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Table 3. Unidirectional SPI Timing Event Description t0 0, 1 Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns. t0-t1 0, 1 Propagation delay chip select, logic to isolated side. t2 0 Start of data transmission, data setup. 1 Start of transmission, data and clock setup. Data transition must be within –13ns to 3ns of clock edge. t2-t3 0 Propagation delay of data, logic side to isolated side. 1 Propagation delay of data and clock, logic side to isolated side. 3 0, 1 Logic side data sample time, half clock period delay from data setup transition. t3-t5 0, 1 Clock propagation delay, clock and data transition. t4-t5 0, 1 Data to clock delay, must be ≤ 13ns. t5-t6 0, 1 Clock to data delay, must be ≤ 3ns. t5-t7 0, 1 Data and clock propagation delay. t8 0 Last clock and data transition. 8-t9 0 Clock and data propagation delay. 9-t10 1 Data propagation delay. t11 0, 1 Asynchronous chip select transition, end of transmission. t12 0, 1 Chip select transition isolated side.

mum data rate is 400kHz which supports fast-mode I2C. greater than 400pF in standard mode. be greater than 1V/μs for proper operation. Figure 10. I2C Timing Diagram Figure 11. Isolated SDA2 Pin Schematic

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to the left of the appropriate curve. fall times and minimize noise. at the SCLOUT pin to reduce noise injection onto SDA2. Figure 12. Maximum Standard Speed Pull-Up Figure 13. Maximum Fast Speed Pull-Up Resistance on SDA1

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Figure 14. Operation with Figure 16. T ransient dV/dT , 70kV/µsFigure 15. 70kV/µs T ransient Figure 17. Static Operation with Figure 18. 200kV/µs T ransient Figure 20. Common Mode Figure 21. Common Mode Figure 19. Data Refresh Recovery

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2892faFor more information www.linear .com/L TM2892 applicaTions inForMaTion PCB Layout The high integration of the LTM2892 makes PCB layout very simple. However , to optimize its electrical isolation characteristics and EMI performance, some layout con - siderations are necessary. Input and output supply decoupling is not required, since these components are integrated within the package. An additional polarized bulk capacitor with a value of 3.3µF to 10µF is recommended. The high ESR of this capacitor reduces board resonances and minimizes voltage spikes caused by hot plugging of the supply voltage. For EMI sensitive applications, an additional low ESL ceramic capacitor of 1µF to 4.7µF, placed as close to the power and ground terminals as possible, is recommended. Alternatively, a number of smaller value parallel capacitors may be used to reduce ESL and achieve the same net capacitance. Do not place copper on the PCB between the inner columns of pads. This area must remain open to withstand the rated isolation voltage. The use of solid ground planes for GND1 and GND2 is recommended for non-EMI critical applications to optimize signal fidelity, and minimize RF emissions due to uncoupled PCB trace conduction. The drawback of using ground planes, where EMI is of concern, is the creation of a dipole antenna structure which can radiate differential voltages formed between GND1 and GND2. If ground planes are used it is recommended to minimize their area, and use contiguous planes as any openings or splits can exacerbate RF emissions. For large ground planes a small capacitance (≤ 330pF) from GND1 to GND2, either discrete or embedded within the substrate, provides a low impedance cur - rent return path for the module parasitic capacitance, minimizing any high frequency differential voltages and substantially reducing radiated emissions. Discrete capacitance will not be as effective due to parasitic ESL. In addition, voltage rating, leakage, and clear - ance must be considered for component selection. Embedding the capacitance within the PCB substrate provides a near ideal capacitor and eliminates com - ponent selection issues ; however , the PCB must be 4 layers. Care must be exer cised in applying either technique to ensure the voltage rating of the barrier is not compromised. In applications without an embedded PCB substrate capacitance, a slot may be added between the logic side and isolated side device pins. The slot extends the creepage path between terminals on the PCB side, and may reduce leakage caused by PCB contamination. The slot should be placed in the middle of the device and extend beyond the package perimeter . The PCB layout in Figures 22a and 22b shows the demo boards for the LTM2892. EMI performance is shown in Figure 23, measured using a gigahertz transverse electromagnetic (GTEM) cell and method detailed in IEC 61000-4-20, “Testing and Mea - surement Techniques – Emission and Immunity Testing in Transverse Electromagnetic W aveguides.”

2892fa For more information www.linear .com/L TM2892 Figure 22a. LTM2892-S Demo Board Layout (DC1957A) applicaTions inForMaTion

2892faFor more information www.linear .com/L TM2892 applicaTions inForMaTion Figure 22b. LTM2892-I Demo Board Layout (DC1986A)

Figure 23. LTM2892 Demo Board Emissions

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Figure 24. High Speed Bidirectional 8-Bit Parallel Isolator

Figure 25. Isolated SPI Interface with Multiple Chip Select

• C5 10µF 2.2nF 1N4148W 5V1 COM1 SDA1 SCL1 VCC1 VL1 ON1 OUTC INA SDA1 SDA1 OUTB SCLIN GND1 GND1 GND1 V CC2 VL2 ON2 INC OUTA SDA2 SDA2 INB SCLOUT GND2 GND2 GND2 L TM2892-I ISOLATION BARRIER 10µF 5V2 COM2 SDA2 SCL2 VCC1 VL1 ON1 OUTC INA SDA1 SDA1 OUTB SCLIN GND1 GND1 GND1 V CC2 VL2 ON2 INC OUTA SDA2 SDA2 INB SCLOUT GND2 GND2 GND2 L TM2892-I ISOLATION BARRIER 10µF 5V3 COM3 SDA3 SCL3 VCC1 VL1 ON1 OUTC INA SDA1 SDA1 OUTB SCLIN GND1 GND1 GND1 V CC2 VL2 ON2 INC OUTA SDA2 SDA2 INB SCLOUT GND2 GND2 GND2 L TM2892-I D5 D4 ISOLATION BARRIER 5V5 COM5 SDA5 SCL5 SHDN TC RILIM SS VC RFB RREF SW TEST GND GND GND GND GND GND 5 6 2 3 1 16 17 8 9 VIN BIAS 10µF 200k 90.9k 6.04k 26.1k 56.2k 10k 26.1k 1.5nF 10nF L T3574 10µF VCC1 VL1 ON1 OUTC INA SDA1 SDA1 OUTB SCLIN GND1 GND1 GND1 V CC2 VL2 ON2 INC OUTA SDA2 SDA2 INB SCLOUT GND2 GND2 GND2 L TM2892-I ISOLATION BARRIER 5V4 COM4 SDA4 SCL4 10µF TR1:E TR1:F TR1: WÜRTH ELEKTRONIK 749196111 D2-D6: DIODES, INC. B0520LW TR1:D TR1:C SDA SCL TR1:BTR1:A

Figure 26. Parallel Multi-Zone Isolated I2C Interface

• 50V 50V VCC1 VL1 ON1 OUTF INC OUTE INB OUTD INA EOUTD GND1 GND1 VCC2 VL2 ON2 INF OUTC INE OUTB IND OUTA EOUTA GND2 GND2 L TM2892-S ISOLATION BARRIER SHDN T C RILIM SS VC R FB RREF SW TEST GND GND GND GND GND GND 5 6 Ox CS MOSI SCK MISO Ox 2 3 1 16 17 8 9 VIN BIAS 10µF 4.7nF 6.04k 124k 20k 10k 249k 220pF 50k 2.2nF 10nF L T3574 1:2 150µH C6 1µF VCC µC GND 1µF CS SDO SDI SCK GPIO2 GPIO1 WDT MM TOS VREG VREF VTEMP2 VTEMP1 NC V C12 S12 C11 S11 C10 S10 100k 1M 1M 1µF 1µF 100k 100k 100k L TC6803-2

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Figure 27. Battery Stack Monitor with Isolated SPI Interface

Figure 28. –48V , 200W Hot Swap™ Controller with Isolated I2C Interface

Figure 29. Isolated I2C Voltage, Current and Temperature Power Supply Monitor

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• • FB1 FB2 10nF 75Ω 10nF RJ45 CONNECTOR 75Ω
• • 10nF PHY (NETWORK PHYSICAL LAYER CHIP) 75Ω 10nF75Ω 1nF Q1: FAIRCHILD IRFM120A OR PHILIPS PHT6NQ10T FB1, FB2: TDK MPZ2012S601A T1: PULSE H6096NL OR COILCRAFT ETH1-230LD

Figure 30. One Complete Isolated Power Over Ethernet (PoE) Port

2892fa For more information www.linear .com/L TM2892 24-Lead (9mm × 6.25mm × 2.91mm) (Reference L TC DWG # 05-08-1898 Rev A) package DescripTion NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW BGA 24 0911 REV A L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” DETAIL A PIN 1 0.000 0.5 0.5 1.5 1.5 2.5 2.5 3.875 3.875 2.875 2.875 0.000 DETAIL A Øb (24 PLACES) F G H J E A B C D 2 14 35 6 DETAIL B SUBSTRATE // bbb Z D A ccc Z DETAIL B PACKAGE SIDE VIEW MOLD CAP Z M X Y Z ddd M Z eee 0.5 ±0.025 Ø 24x SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 2.71 0.40 2.31 0.50 0.45 0.36 1.95 NOM 2.91 0.50 2.41 0.60 0.50 9.00 6.25 1.00 7.75 5.00 0.41 2.00 MAX 3.11 0.60 2.51 0.70 0.55 0.46 2.05 0.15 0.10 0.20 0.15 0.08 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 24 E b e e b F G 24-Lead (9mm × 6.25mm × 2.91mm) (Reference LTC DWG # 05-08-1898 Rev A) Please refer to http://www.linear .com/product/LTM2892#packaging for the most recent package drawings.

2892faFor more information www.linear .com/L TM2892 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER A 08/16 Addd UL-CSA File # Revised propagation delay when SDA2 → SDA1, and I2C Data Hold Time 5, 21

Figure 31. Series Multi-Zone Isolated I2C Interface, Working Voltage Multiplier