LTM2887

LTM2887 LINER | Alldatasheet

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Technical content

2887fbFor more information www.linear .com/L TM2887 TYPICAL APPLICATION FEATURES DESCRIPTION SPI/Digital or I2C µModule Isolator with Dual Adjustable 5V Regulators The LT M®2887 is a complete galvanic digital µModule ® (micromodule) isolator. No external components are required. A single 3.3V or 5V supply powers both sides of the interface through an integrated, isolated DC/DC converter. A logic supply pin allows easy interfacing with different logic levels from 1.62V to 5.5V, independent of the main supply. Available options are compliant with SPI and I 2C (master mode only) specifications. The isolated side includes two 5V nominal power supplies, including programmable current limit, each capable of providing more than 100mA of load current. The supplies may be adjusted from their nominal value using a single external resistor. Coupled inductors and an isolation power transformer provide 2500V RMS of isolation between the input and out- put logic interface. This device is ideal for systems where the ground loop is broken, allowing for a large common mode voltage range. Communication is uninterrupted for common mode transients greater than 30kV/μs. L, LT, LT C, LT M, Linear Technology, the Linear logo and µModule are registered trademarks of Analog Devices, Inc. All other trademarks are the property of their respective owners. Isolated 4MHz SPI Interface

APPLICATIONS

n 6-Channel Logic Isolator: 2500VRMS for 1 Minute n UL-CSA Recognized File #E151738 n Isolated DC Power: n 1.8V to 5V Logic Supply at Up to 100mA n 0.6V to 5V Auxiliary Supply at Up to 100mA n No External Components Required n SPI/Digital (L TM2887-S) or I2C (L TM2887-I) Options n High Common Mode T ransient Immunity: 30kV/μs n High Speed Operation: n 10MHz Digital Isolation n 4MHz/8MHz SPI Isolation n 400kHz I2C Isolation n 3.3V (L TM2887-3) or 5V (L TM2887-5) Operation n 1.62V to 5.5V Logic Supply n ±10kV ESD HBM Across the Isolation Barrier n Maximum Continuous Working Voltage: 560VPEAK n Low Current Shutdown Mode (<10µA) n Low Profile 15mm × 11.25mm × 3.42mm BGA Package n Isolated SPI or I2C Interfaces n Industrial Systems n Test and Measurement Equipment n Breaking Ground Loops LTM2887 Operating Through 50kV/µs CM Transients

2887 TA01a

3.3V AT 100mA 1.15k 27.4k 1.15k 6.04k 20ns/DIV 5V/DIV 200V/DIV SCK SD0 SCK2 = SD02

2887 TA01b

2887fb For more information www.linear .com/L TM2887 LTM2887-I LTM2887-S VCCGNDDO1 AVCC2IVL2GND2I1 BGA PACKAGE 32-PIN (15mm × 11.25mm × 3.42mm) TOP VIEW AVL2 F G H L J K E A B C D 2 1 4 3 5 6 7 8 DNC DO2 SDA SCL DI1 GND ON V L DNC I2 SDA2 SCL2 O1 VL2 IVCC2 VCC2 TJMAX = 125°C, θJA = 23.9°C/W, θJCbottom = 8.1°C/W, θJCtop = 18.1°C/W, θJB = 9.3°C/W θ VALUES DETERMINED PER JESD51-9, WEIGHT = 1.2g VCCGNDDO1 AVCC2IVL2GND2I1 BGA PACKAGE 32-PIN (15mm × 11.25mm × 3.42mm) TOP VIEW AVL2 F G H L J K E A B C D 2 1 4 3 5 6 7 8 DO2 SDO SDI SCKCS SDOE ON V L I2 SDO2 SDI2 SCK2CS2 VL2 IVCC2 VCC2 TJMAX = 125°C, θJA = 23.9°C/W, θJCbottom = 8.1°C/W, θJCtop = 18.1°C/W, θJB = 9.3°C/W θ VALUES DETERMINED PER JESD51-9, WEIGHT = 1.2g ABSOLUTE MAXIMUM RATINGS Logic Inputs DI1, SCK, SDI, CS, SCL, SDA, SDOE, I1, I2, SDA 2, (Note 1) PIN CONFIGURATION Logic Outputs O1, SCK2, SDI 2, CS2, Operating Temperature Range (Note 4) 5°C 55°C to 125°C 5°C

2887fbFor more information www.linear .com/L TM2887 LTM2887 C Y -3 I #PBF LEAD FREE DESIGNATOR PBF = Lead Free LOGIC OPTION I = Inter-IC (I2C) Bus S = Serial Peripheral Interface (SPI) Bus INPUT VOL T AGE RANGE 3 = 3V to 3.6V 5 = 4.5V to 5.5V PACKAGE T YPE Y = Ball Grid Array (BGA) TEMPERATURE GRADE C = Commercial Temperature Range (0°C to 70°C) I = Industrial Temperature Range (–40°C to 85°C) H = Automotive T emperature Range (–40°C to 125°C) PRODUCT P ART NUMBER PRODUCT SELECTION GUIDE ORDER INFORMATION PART NUMBER PAD OR BALL FINISH PART MARKING PACKAGE TYPE MSL RATING INPUT VOL T AGE RANGE LOGIC OPTION TEMPERATURE RANGE DEVICE FINISH CODE LTM2887CY-3I#PBF SAC305 (RoHS) LTM2887Y-3I e1 BGA 3 3V to 3.6V I2C 0°C to 70°C LTM2887IY-3I#PBF –40°C to 85°C LTM2887HY-3I#PBF –40°C to 125°C LTM2887CY-3S#PBF LTM2887Y-3S SPI 0°C to 70°C LTM2887IY-3S#PBF –40°C to 85°C LTM2887HY-3S#PBF –40°C to 125°C LTM2887CY-5I#PBF LTM2887Y-5I 4.5V to 5.5V I2C 0°C to 70°C LTM2887IY-5I#PBF –40°C to 85°C LTM2887HY-5I#PBF –40°C to 125°C LTM2887CY-5S#PBF LTM2887Y-5S SPI 0°C to 70°C LTM2887IY-5S#PBF –40°C to 85°C LTM2887HY-5S#PBF –40°C to 125°C

• Device temperature grade is indicated by a label on the shipping container.
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Terminal Finish Part Marking: www.linear.com/leadfree
• This product is not recommended for second side reflow. For more information, go to www.linear.com/BGA-assy
• Recommended BGA PCB Assembly and Manufacturing Procedures: www.linear.com/BGA-assy
• BGA Package and T ray Drawings: www.linear.com/packaging
• This product is moisture sensitive. For more information, go to: www.linear.com/BGA-assy http://www.linear.com/product/LTM2887#orderinfo

2887fb For more information www.linear .com/L TM2887 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at TA = 25°C. LTM2887-3 VCC = 3.3V, LTM2887-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Supplies VCC Input Supply Range LTM2887-3 LTM2887-5 l l 4.5 3.3 3.6 5.5 V V V L Logic Supply Range LTM2887-S LTM2887-I l l 1.62 5.5 5.5 V V I CC Input Supply Current ON = 0V LTM2887-3, ON = V L, No Load LTM2887-5, ON = VL, No Load l l l µA mA mA I L Logic Supply Current ON = 0V LTM2887-S, ON = V L LTM2887-I, ON = VL l 0 150 µA µA µA Output Supplies V CC2 Regulated Output Voltage No Load, AV CC2 Open l 4.75 5 5.25 V Output Voltage Operating Range (Note 2) 0.6 5.5 V Line Regulation ILOAD = 1mA, MIN ≤ VCC ≤ MAX l 1 6 mV Load Regulation ILOAD = 1mA to 100mA l 45 150 mV ADJ Pin Voltage ILOAD = 1mA to 100mA l 540 580 620 mV Voltage Ripple ILOAD = 100mA (Note 2) 1 mVRMS Efficiency LTM2887-5, ILOAD = 100mA (Note 2) 62 % ICC2 Output Short Circuit Current V CC2 = 0V, IVCC2 = 0V 200 mA Internal Current Limit ΔVCC2 = –5%, IVCC2 = 0V l 100 mA External Programmed Current Limit VCC2 = 5V, R(IVCC2 to GND2) = 2.26k VCC2 = 5V, R(IVCC2 to GND2) = 1.5k VCC2 = 5V, R(IVCC2 to GND2) = 1.15k l l l 103 115 mA mA mA V L2 Regulated Output Voltage No Load, AV L2 Open l 4.75 5 5.25 V Output Voltage Operating Range LTM2887-I (Note 2) LTM2887-S (Note 2) 1.8 5.5 5.5 V V Line Regulation I LOAD = 1mA, MIN ≤ VCC ≤ MAX l 0.25 3 mV Load Regulation ILOAD = 1mA to 100mA l 25 100 mV ADJ Pin Voltage ILOAD = 1mA to 100mA l 540 580 620 mV Voltage Ripple ILOAD = 100mA (Note 2) 1 mVRMS Efficiency LTM2887-5, ILOAD = 100mA (Note 2) 62 % IL2 Output Short Circuit Current V L2 = 0V, IVL2 = 0V 200 mA Current Limit ΔVL2 = –5%, IVL2 = 0V l 100 mA External Programmed Current Limit V L2 = 5V, R(IVL2 to GND2) = 2.26k VL2 = 5V, R(IVL2 to GND2) = 1.5k VL2 = 5V, R(IVL2 to GND2) = 1.15k l l l 103 115 mA mA mA Logic/SPI V ITH Input Threshold Voltage ON, DI1, SDOE, SCK, SDI, CS 1.62V ≤ V L < 2.35V ON, DI1, SDOE, SCK, SDI, CS 2.35V ≤ VL I1, I2, SDO2 l l l 0.25 • VL 0.33 • VL 0.33 • VL2 0.75 • VL 0.67 • VL 0.67 • VL2 V V V I INL Input Current l ±1 µA

2887fbFor more information www.linear .com/L TM2887

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VHYS Input Hysteresis 150 mV VOH Output High Voltage DO1, DO2, SDO ILOAD = –1mA, 1.62V ≤ VL < 3V ILOAD = –4mA, 3V ≤ VL ≤ 5.5V l VL – 0.4 V O1, SCK2, SDI2, CS2, ILOAD = –4mA l VL2 – 0.4 V VOL Output Low Voltage DO1, DO2, SDO I LOAD = 1mA, 1.62V ≤ VL < 3V ILOAD = 4mA, 3V ≤ VL ≤ 5.5V l 0.4 V O1, SCK2, SDI2, CS2, ILOAD = 4mA l 0.4 V ISC Short-Circuit Current 0V ≤ (DO1, DO2, SDO) ≤ VL 0V ≤ (O1, SCK2, SDI2, CS2) ≤ VL2 l ±60 ±85 mA mA I2C VIL Low Level Input Voltage SCL, SDA SDA2 l l 0.3 • VL 0.3 • VL2 V V VIH High Level Input Voltage SCL, SDA SDA2 l l 0.7 • VL 0.7 • VL2 V V IINL Input Current SCL, SDA = VL or 0V SDA2 = VL2, SDA2 = VL2 = 0V l l µA µA VHYS Input Hysteresis SCL, SDA SDA2 0.05 • V L 0.05 • VL2 mV mV V OH Output High Voltage SCL2, ILOAD = –2mA DO2, ILOAD = –2mA l VL2 – 0.4 VL – 0.4 V V V OL Output Low Voltage SDA, ILOAD = 3mA DO2, ILOAD = 2mA SCL2, ILOAD = 2mA SDA2, No Load, SDA = 0V, 4.5V ≤ VL2 < 5.5V SDA2, No Load, SDA = 0V, 3V < VL2 < 4.5V l l l l l 0.3 0.4 0.4 0.4 0.45 0.55 V V V V V C IN Input Pin Capacitance SCL, SDA, SDA2 (Note 2) l 10 pF CB Bus Capacitive Load SCL2, Standard Speed (Note 2) SCL2, Fast Speed SDA, SDA2, SR ≥ 1V/µs, Standard Speed (Note 2) SDA, SDA2, SR ≥ 1V/µs, Fast Speed l l l l 400 200 400 200 pF pF pF pF Minimum Bus Slew Rate SDA , SDA2 l 1 V/µs ISC Short-Circuit Current SDA2 = 0, SDA = VL 0V ≤ SCL2 ≤ VL2 0V ≤ DO2 ≤ VL SDA = 0, SDA2 = VL2 SDA = VL, SDA2 = 0 l ±30 ±30 –1.8 100 mA mA mA mA mA ESD (HBM) (Note 2) Isolation Boundar y (VCC2, VL2, GND2) to (VCC, VL, GND) ±10 kV The l denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at TA = 25°C. LTM2887-3 VCC = 3.3V, LTM2887-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.

2887fb For more information www.linear .com/L TM2887 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Logic Maximum Data Rate DI1 → O1, Ix → DOx, CL = 15pF (Note 3) l 10 MHz tPHL, tPLH Propagation Delay CL = 15pF (Figure 1) l 35 60 100 ns tR Rise Time CL = 15pF (Figure 1) LTM2887-I, DO2, CL = 15pF (Figure 1) l l 12.5 ns ns tF Fall Time CL = 15pF (Figure 1) LTM2887-I, DO2, CL = 15pF (Figure 1) l l 12.5 ns ns SPI Maximum Data Rate Bidirectional Communication (Note 3) Unidirectional Communication (Note 3) l l MHz MHz t PHL, tPLH Propagation Delay CL = 15pF (Figure 1) l 35 60 100 ns tPWU Output Pulse Width Uncertainty SDO, SDI2, CS2 (Note 2) ±50 ns tR Rise Time CL = 15pF (Figure 1) l 3 12.5 ns tF Fall Time CL = 15pF (Figure 1) l 3 12.5 ns tPZH, tPZL Output Enable Time SDOE = ↓, RL = 1kΩ, CL = 15pF (Figure 2) l 50 ns tPHZ, tPLZ Output Disable Time SDOE = ↑, RL = 1kΩ, CL = 15pF (Figure 2) l 50 ns I2C Maximum Data Rate (Note 3) l 400 kHz tPHL, tPLH Propagation Delay SCL → SCL2, CL = 15pF (Figure 1) SDA → SDA2, RL = Open, CL = 15pF (Figure 3) SDA2 → SDA, RL = 1.1kΩ, CL = 15pF (Figure 3) l l l 150 150 300 225 250 500 ns ns ns t PWU Output Pulse Width Uncertainty SDA, SDA2 (Note 2) ±50 ns tHD;DAT Data Hold Time (Note 2) 600 ns tR Rise Time SDA2, CL = 200pF (Figure 3) SDA, RL = 1.1kΩ, CL = 200pF (Figure 3) SCL2, CL = 200pF (Figure 1) l l l 300 250 250 ns ns ns t F Fall Time SDA2, CL = 200pF (Figure 3) SDA, RL = 1.1kΩ, CL = 200pF (Figure 3) SCL2, CL = 200pF (Figure 1) l l l 250 250 250 ns ns ns t SP Pulse Width of Spikes Suppressed by Input Filter l 0 50 ns Power Supply Power-Up Time ON = ↑ to VCC2 (Min) ON = ↑ to VL2 (Min) l l ms ms SWITCHING CHARACTERISTICS The l denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at TA = 25°C. LTM2887-3 VCC = 3.3V, LTM2887-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.

2887fbFor more information www.linear .com/L TM2887 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Guaranteed by design and not subject to production test. Note 3: Maximum Data rate is guaranteed by other measured parameters and is not tested directly. Note 4: This Module includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above specified maximum operating junction temperature may result in device degradation or failure. Note 5: Device considered a 2-terminal device. Pin group A1 through B8 shorted together and pin group K1 through L8 shorted together. Note 6: The rated dielectric insulation voltage should not be interpreted as a continuous voltage rating. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VISO Rated Dielectric Insulation Voltage 1 Minute, Derived from 1 Second Test

1 Second (Notes 5, 6)

V RMS VRMS Common Mode T ransient Immunity LTM2887-3 V CC = 3.3V, LTM2887-5 VCC = 5V, VL = ON = 3.3V, VCM = 1kV, Δt = 33ns (Note 2) 30 kV/µs VIORM Maximum Continuous Working Voltage (Notes 2, 5) 560 400 VPEAK, VDC VRMS Partial Discharge VPD = 750VRMS (Note 5) 5 pC Input to Output Resistance (Notes 2, 5) 109 Ω CTI Comparative T racking Index IEC 60112 (Note 2) 600 VRMS Depth of Erosion IEC 60112 (Note 2) 0.017 mm DTI Distance Through Insulation (Note 2) 0.06 mm Input to Output Capacitance (Notes 2, 5) 6 pF Creepage Distance (Note 2) 9.5 mm ISOLATION CHARACTERISTICS TA = 25°C.

2887fb For more information www.linear .com/L TM2887 TYPICAL PERFORMANCE CHARACTERISTICS VCC2 or VL2 Output Voltage vs Input Voltage and Load Current VCC2 or VL2 Output Voltage vs Input Voltage and Load Current VCC Supply Current vs Temperature VCC2 and VL2 Voltage vs Equal Load Current TA = 25°C, LTM2887-3 VCC = 3.3V, LTM2887-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted. VCC2 or VL2 Load Regulation vs Temperature VCC2 or VL2 Efficiency VCC2 or VL2 Voltage and VCC Input Current vs Load Current VCC2 or VL2 Load Regulation vs Temperature TEMPERATURE (°C) –50 SUPPL Y CURRENT (mA) 500 100

2887 G01

12525–25 75 NO LOAD, REFRESH DATA ONL Y L TM2887-3 VCC = 3.3V L TM2887-5 V CC = 5V LOAD CURRENT (mA) OUTPUT VOL TAGE (V) 5.25 4.50 4.25 4.75 5.00 4.00 10050 7525

2887 G02

L TM2887-3, VCC = 3.3V L TM2887-5, VCC = 5V LOAD CURRENT (mA) OUTPUT VOL TAGE (V) 5.25 4.25 4.50 4.75 5.00 4.00 10050

2887 G03

L TM2887-3, VCC = 3V L TM2887-3, VCC = 3.3V L TM2887-3, VCC = 3.6V LOAD CURRENT (mA) OUTPUT VOL TAGE (V) 5.25 4.25 4.50 4.75 5.00 4.00 15010050 200

2887 G04

L TM2887-5, VCC = 4.5V L TM2887-5, VCC = 5V L TM2887-5, VCC = 5.5V TEMPERATURE (°C) –50 OUTPUT VOL TAGE (V) 5.10 4.95 5.00 5.05 4.90 25 0 –2550

2887 G05

VCC = 3.3V ILOAD = 1mA ILOAD = 10mA ILOAD = 100mA 5.10 5.05 5.00 4.95 4.90 TEMERATURE (°C) –50 OUTPUT VOL TAGE (V) 75 50 25 0 –25

2887 G06

ILOAD = 1mA ILOAD = 10mA ILOAD = 100mA L TM2887-5 VCC = 5V LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (W) 1.4 0.2 0.4 0.6 0.8 1.0 1.2 0.0 125 100 75 50 25175 150

2887 G07

L TM2887-3, VCC = 3.3V L TM2887-5, VCC = 5V LOAD CURRENT (mA) OUTPUT VOL TAGE (V) ICC CURRENT (mA) 5.5 2.0 3.0 2.5 3.5 4.0 4.5 5.0 1.5 800 100 200 300 400 500 600 700 0.0 125 100 75 50 25175 150

2887 G08

L TM2887-3, VCC = 3.3V L TM2887-5, VCC = 5V VOL TAGE CURRENT

2887fbFor more information www.linear .com/L TM2887 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, LTM2887-3 VCC = 3.3V, LTM2887-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted. VCC2 or VL2 Transient Response 100mA Load Step VCC2 or VL2 Ripple 200µs/DIV

2887 G09

0.2V/ DIV 50mA/ DIV 400ns/DIV

2887 G10

LOAD = 100mA LOAD = 1mA VCC2 or VL2 Noise 10ms/DIV

2887 G11

LOAD = 100mA LOAD = 1mA VCC Supply Current vs Single Channel Data Rate Logic Input Threshold vs VL Supply Voltage Logic Output Voltage vs Load Current DATA RATE (Hz) VCC CURRENT (mA) 100k10k 1M

2887 G12

L TM2887-5CL = 1nF CL = 330pF CL = 100pF CL = 20pF VL SUPPL Y VOL TAGE (V) THRESHOLD VOL TAGE (V) 3.5 2.5 0.5 1.0 2.0 3.0 1.5 4 52

2887 G13

|LOAD CURRENT| (mA) OUTPUT VOL TAGE (V) 2 1 3

2887 G14

VL = 5.5V VL = 3.3V VL = 1.62V Power On Sequence VCC2 and VL2 Efficiency with Equal Load Current

2887 G15

VL = 5V LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (W) 1.4 0.8 0.4 0.6 0.2 1.0 1.2 0.0 75 50 25100

2887 G16

L TM2887-3, VCC = 3.3V L TM2887-5, VCC = 5V POWER LOSS EFFICIENCY BASED ON THERMAL IMAGING OF DEMO CIRCUIT 1791A V CC2 and V EQUALL Y LOADED L TM2887-3, VCC = 3.3V L TM2887-5, VCC = 5V TEMPERATURE (°C) 100 125 100 200 300 400 500 600 V CC SUPPL Y CURRENT (mA)

2887 G17

Derating for 125°C Maximum Internal Operating Temperature

2887fb For more information www.linear .com/L TM2887 PIN FUNCTIONS LTM2887-I Logic Side DO2 (A1): Digital Output, Referenced to VL and GND. Logic output connected to I2 through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state. DNC (A2): Do Not Connect. Pin connected internally. SCL (A3): Serial I 2C Clock Input, Referenced to V L and GND. Logic input connected to isolated side SCL2 pin through isolation barrier. Clock is unidirectional from logic to isolated side. Do not float. SDA (A4): Serial I 2C Data Pin, Referenced to VL and GND. Bidirectional logic pin connected to isolated side SDA2 pin through isolation barrier. Under the condition of an isola- tion communication failure this pin is in a high impedance state. Do not float. DI1 (A5): Digital Input, Referenced to VL and GND. Logic input connected to O1 through isolation barrier. The logic state on DI1 translates to the same logic state on O1. Do not float. GND (A6, B2 to B6): Circuit Ground. ON (A7): Enable, Referenced to V L and GND. Enables power and data communication through the isolation barrier. If ON is high the part is enabled and power and communications are functional to the isolated side. If ON is low the logic side is held in reset, all digital outputs are in a high impedance state, and the isolated side is unpowered. Do not float. V L (A8): Logic Supply. Interface supply voltage for pins DI1, SCL, SDA, DO1, DO2, and ON. Operating voltage is 1.62V to 5.5V. Internally bypassed with 1µF. DO1 (B1): Digital Output, Referenced to VL and GND. Logic output connected to I1 through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state. V CC (B7 to B8): Supply Voltage. Operating voltage is 3V to 3.6V for LTM2887-3 and 4.5V to 5.5V for LTM2887-5. Internally bypassed with 2.2µF. LTM2887-I Isolated Side I2 (L1): Digital Input, Referenced to VL2 and GND2. Logic input connected to DO2 through isolation barrier. The logic state on I2 translates to the same logic state on DO2. Do not float. DNC (L2): Do Not Connect. Pin connected internally. SCL2 (L3): Serial I 2C Clock Output, Referenced to VL2 and GND2. Logic output connected to logic side SCL pin through isolation barrier. Clock is unidirectional from logic to isolated side. SCL2 has a push-pull output stage, do not connect an external pull-up device. Under the condition of an isolation communication failure this output defaults to a high state. SDA2 (L4): Serial I 2C Data Pin, Referenced to V L2 and GND2. Bidirectional logic pin connected to logic side SDA pin through isolation barrier. Output is biased high by a 1.8mA current source. Do not connect an external pull- up device to SDA2. Under the condition of an isolation communication failure this output defaults to a high state. O1 (L5): Digital Output, Referenced to V L2 and GND2. Logic output connected to DI1 through isolation barrier. Under the condition of an isolation communication failure O1 defaults to a high state. V L2 (L6): 3V to 5.5V Adjustable Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC con- verter and regulated to 5V with no external components. Internally bypassed with 4.7µF IVCC2 (L7): VCC2 precision current limit adjust pin. Current limit threshold is set by connecting a resistor between IV CC2 and GND2. For detailed information on how to set the current limit resistor value, see the Application Infor- mation section. If not used, tie IVCC2 to GND2. Internally bypassed with 10nF. VCC2 (L8): 0.6V to 5.5V Adjustable Isolated Supply Volt- age. Internally generated from VCC by an isolated DC/DC converter and regulated to 5V with no external components. Internally bypassed with 4.7µF . I1 (K1): Digital Input, Referenced to V L2 and GND2. Logic input connected to DO1 through isolation barrier. The logic state on I1 translates to the same logic state on DO1. Do not float. GND2 (K2 to K5): Isolated Ground.

2887fbFor more information www.linear .com/L TM2887 PIN FUNCTIONS LTM2887-I Isolated Side AVL2 (K6): 5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 600mV referenced to GND2. See Applications Information section for details. IVL2 (K7): VL2 precision current limit adjust pin. Current limit threshold is set by connecting a resistor between IVL2 and GND2. For detailed information on how to set the current limit resistor value, see the Application Infor- mation section. If not used, tie IV L2 to GND2. Internally bypassed with 10nF. AVCC2 (K8): 5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 600mV referenced to GND2. See Applications Information section for details. LTM2887-S Logic Side SDO (A1): Serial SPI Digital Output, Referenced to V L and GND. Logic output connected to isolated side SDO2 pin through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state. DO2 (A2): Digital Output, Referenced to V L and GND. Logic output connected to I2 through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state. SCK (A3): Serial SPI Clock Input, Referenced to V L and GND. Logic input connected to isolated side SCK2 pin through isolation barrier. Do not float. SDI (A4): Serial SPI Data Input, Referenced to VL and GND. Logic input connected to isolated side SDI2 pin through isolation barrier. Do not float. CS (A5): Serial SPI Chip Select, Referenced to VL and GND. Logic input connected to isolated side CS2 pin through isolation barrier. Do not float. SDOE (A6): Serial SPI Data Output Enable, Referenced to VL and GND. A logic high on SDOE places the logic side SDO pin in a high impedance state, a logic low enables the output. Do not float. ON (A7): Enable, Referenced to V L and GND. Enables power and data communication through the isolation barrier. If ON is high the part is enabled and power and communications are functional to the isolated side. If ON is low the logic side is held in reset, all digital outputs are in a high impedance state, and the isolated side is unpowered. Do not float. V L (A8): Logic Supply. Interface supply voltage for pins SDI, SCK, SDO, SDOE, DO1, DO2, CS, and ON. Operating voltage is 1.62V to 5.5V. Internally bypassed with 1µF. DO1 (B1): Digital Output, Referenced to V L and GND. Logic output connected to I1 through isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state. GND (B2 to B6): Circuit Ground. V CC (B7 to B8): Supply Voltage. Operating voltage is 3V to 3.6V for LTM2887-3 and 4.5V to 5.5V for LTM2887-5. Internally bypassed with 2.2µF. LTM2887-S Isolated Side SDO2 (L1): Serial SPI Digital Input, Referenced to V L2 and GND2. Logic input connected to logic side SDO pin through isolation barrier. Do not float. I2 (L2): Digital Input, Referenced to VL2 and GND2. Logic input connected to DO2 through isolation barrier. The logic state on I2 translates to the same logic state on DO2. Do not float. SCK2 (L3): Serial SPI Clock Output, Referenced to V L2 and GND2. Logic output connected to logic side SCK pin through isolation barrier. Under the condition of an isolation communication failure this output defaults to a low state. SDI2 (L4): Serial SPI Data Output, Referenced to V L2 and GND2. Logic output connected to logic side SDI pin through isolation barrier. Under the condition of an isolation communication failure this output defaults to a low state. CS2 (L5): Serial SPI Chip Select, Referenced to V L2 and GND2. Logic output connected to logic side CS pin through isolation barrier. Under the condition of an isolation com- munication failure this output defaults to a high state. VL2 (L6): 1.8V to 5.5V Adjustable Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC con- verter and regulated to 5V with no external components. Internally bypassed with 4.7µF.

2887fb For more information www.linear .com/L TM2887 PIN FUNCTIONS LTM2887-S Isolated Side IVCC2 (L7): VCC2 precision current limit adjust pin. Current limit threshold is set by connecting a resistor between IVCC2 and GND2. For detailed information on how to set the current limit resistor value, please see the Applica - tion Information section. If not used, tie IV CC2 to GND2. Internally bypassed with 10nF. VCC2 (L8): 0.6V to 5.5V Adjustable Isolated Supply Volt- age. Internally generated from VCC by an isolated DC/DC converter and regulated to 5V with no external components. Internally bypassed with 4.7µF. I1 (K1): Digital Input, Referenced to V L2 and GND2. Logic input connected to DO1 through isolation barrier. The logic state on I1 translates to the same logic state on DO1. Do not float. GND2 (K2 to K5): Isolated Ground. AVL2 (K6): 5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 600mV Referenced to GND2. See Applications Information section for details.. IVL2 (K7): VL2 precision current limit adjust pin. Current limit threshold is set by connecting a resistor between IVL2 and GND2. For detailed information on how to set the current limit resistor value, please see the Applica - tion Information section. If not used, tie IV L2 to GND2. Internally bypassed with 10nF. AVCC2 (K8): 5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 600mV Referenced to GND2. See Applications Information section for details.

2887fbFor more information www.linear .com/L TM2887 BLOCK DIAGRAMS LTM2887-I

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1µF VCC IVCC2 AVCC2 IVL2 VL2 VCC2 VL 2.2µF GND ON SDA DI1 DO2 DO1 SCL AVL2 SCL2 SDA2 GND2 DC/DC CONVERTER ISOLATED COMMUNI- CATIONS INTERFACE ISOLATED COMMUNI- CATIONS INTERFACE REG REG REG 4.7µF 4.7µF 10nF 10nF

2887fb For more information www.linear .com/L TM2887 BLOCK DIAGRAMS

2887 BDb

1µF VCC IVCC2 AVCC2 IVL2 VL2 VCC2 VL 2.2µF GND ON SDI CS SDO DO2 SDOE DO1 SCK CS2 AVL2 SDO2 SCK2 SDI2 GND2 DC/DC CONVERTER ISOLATED COMMUNI- CATIONS INTERFACE ISOLATED COMMUNI- CATIONS INTERFACE REG REG REG 4.7µF 4.7µF 10nF 10nF LTM2887-S

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Figure 1. Logic Timing Measurements Figure 2. Logic Enable/Disable Time Figure 3. I2C Timing Measurements

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networks where grounds can take on different voltages. greater than 30kV/μs providing excellent noise isolation. translate signals and power across an isolation barrier. a powerful isolated DC/DC converter in one small package. transformer saturation due to driver duty cycle imbalance. Simply connect the desired logic supply to VL. is bypassed internally by a 1µF capacitor. and mitigation of this phenomenon.

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Figure 4. VCC and VL Are Independent

Figure 5. Adjustable Voltage Rails ages represent the maximums for guaranteed performance. The output adjustment range for V CC2 is 0.6V to 5.5V. pin bias currents and internal voltage dividers. shutdown due to low dropout regulator power dissipation. internally decoupled with 10nF capacitors. ary by encoding and decoding of the inputs and outputs.

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no jitter on the associated output channels, only delay. clock phase (CPHA) summarized in Table 1. Table 1. SPI Mode is still dominated by the system propagation delays .

• CS to SCK (master sample SDO, 1st SDO valid) t0 → t1 ≈50ns, CS to CS2 propagation delay t1 → t1+ Isolated slave device propagation (response time), asserts SDO2 t1 → t3 ≈50ns, SDO2 to SDO propagation delay t3 → t5 Set-up time for master SDO to SCK APPLICATIONS INFORMATION
• SDI to SCK (master data write to slave) t2 → t4 ≈50ns, SDI to SDI2 propagation delay t5 → t6 ≈50ns, SCK to SCK2 propagation delay t2 → t5 ≥50ns, SDI to SCK, separate packet non-zero set-up time t4 → t6 ≥50ns, SDI2 to SCK2, separate packet non-zero set-up time
• SDO to SCK (master sample SDO, subsequent SDO valid) t8 set-up data transition SDI and SCK t8 → t10 ≈50ns, SDI to SDI2 and SCK to SCK2 propagation delay t10 SDO2 data transition in response to SCK2 t10 → t11 ≈50ns, SDO2 to SDO propagation delay t11 → t12 Set-up time for master SDO to SCK Maximum data rate for single direction communication, master to slave, is 8MHz, limited by the systems encod- ing/decoding scheme or propagation delay. Timing details for both variations of clock phase are shown in Figures and 9 and T able 3. Additional requirements to insure maximum data rate are:
• CS is transmitted prior to (asynchronous) or within the same (synchronous) data packet as SDI
• SDI and SCK set-up data transition occur within the same data packet. Referencing Figure 6, SDI can pre- cede SCK by up to 13ns ( t7 → t8) or lag SCK by 3ns (t8 → t9) and not violate this requirement. Similarly in Figure 8, SDI can precede SCK by up to 13ns (t4 → t5) or lag SCK by 3ns (t5 → t6).

Figure 6. SPI Timing, Bidirectional, CPHA = 0 Figure 7. SPI Timing, Bidirectional, CPHA = 1

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Figure 8. SPI Timing, Unidirectional, CPHA = 0 Figure 9. SPI Timing, Unidirectional, CPHA = 1

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Table 2. Bidirectional SPI Timing Event Description

1 Propagation delay of data and clock, logic side to isolated side

1 Last sample clock transition logic side

1 Propagation delay clock, logic to isolated side

1 Last slave data output and data transition, logic side

Table 3. Unidirectional SPI Timing Event Description

1 Last clock transition

1 Clock propagation delay

Figure 10. I2C Timing Diagram

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greater than 400pF in STANDARD mode.

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Figure 12. Maximum Standard Speed Pull-Up Resistance on SDA Figure 13. Maximum Fast Speed Pull-Up Resistance on SDA be greater than 1V/µs for proper operation. to the left of the appropriate curve. output driver; do not connect an external pull-up device. filter at the SCL2 pin to reduce noise injection onto SDA2. Figure 11. Isolated SDA2 Pin Schematic

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signed per the data sheet PCB layout recommendations. Specific limits per test are detailed in Table 4. Table 4. EMC Immunity Tests layout considerations are necessary. stress and improve the thermal conductivity. to reduce ESL and achieve the same net capacitance. the rated isolation voltage. of the barrier is not compromised.

Figure 14. LTM2887 Low EMI Demo Board Layout

• In applications without an embedded PCB substrate capacitance a slot may be added between the logic side and isolated side device pins. The slot extends the creepage path between terminals on the PCB side, and may reduce leakage caused by PCB contamination. The slot should be placed in the middle of the device and extend beyond the package perimeter. The PCB layout in Figures 14 and 15 shows the low EMI demo board for the L TM2887. The demo board uses a combination of EMI mitigation techniques, including both embedded PCB bridge capacitance and discrete GND to GND2 capacitors. T wo safety rated type Y2 capacitors are used in series, manufactured by MuRata, part number GA342QR7GF471KW01L. The embedded capacitor ef - fectively suppresses emissions above 400MHz, whereas the discrete capacitors are more effective below 400MHz. EMI performance is shown in Figure 16, measured using a Gigahertz Transverse Electromagnetic (GTEM) cell and method detailed in IEC 61000-4-20, Testing and Measure- ment Techniques – Emission and Immunity Testing in Transverse Electromagnetic W aveguides.

Figure 15. LTM2887 Low EMI Demo Board Layout (DC1791A)

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Figure 17. Isolated I2C 12-Bit, 0V to 4.096V Analog Input and Output Figure 16. LTM2887 Low EMI Demo Board Emissions

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Figure 18. Isolated SPI Device Expansion

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Figure 19. Isolated I2C Buffer with Dual Outputs

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Figure 20. 16-Channel Isolated Temperature to Frequency Converter

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Figure 21. Digitally Switched Dual Power Supply with Undervoltage Monitor

Figure 22. Quad 16-Bit 0 to 4.096V Output Range DAC Figure 23. Parallel Output Supplies for Higher Current

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Figure 24. –48V, 200W Hot Swap Controller with Isolated I2C Interface

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24 ADIN

Figure 25. 12-Cell Battery Stack Monitor with Isolated SPI Interface and Low Power Shutdown

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Figure 26. Isolated I2C Voltage, Current and Temperature Power Supply Monitor

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Figure 27. One Complete Isolated Powered Ethernet Port

2887fb For more information www.linear .com/L TM2887 32-Lead (15mm × 11.25mm × 3.42mm) (Reference L TC DWG # 05-08-1851 Rev D) 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW BGA 32 1112 REV D L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” DETAIL A PIN 1 0.000 0.635 0.635 1.905 1.905 3.175 3.175 4.445 4.445 6.350 6.350 5.080 5.080 0.000 DETAIL A Øb (32 PLACES) F G H L J K E A B C D 2 14 35 6 7 8 DETAIL B SUBSTRATE 0.27 – 0.37 2.45 – 2.55 // bbb Z D A ccc Z DETAIL B PACKAGE SIDE VIEW MOLD CAP Z M X Y Z ddd M Z eee 0.630 ±0.025 Ø 32x SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 3.22 0.50 2.72 0.60 0.60 NOM 3.42 0.60 2.82 0.75 0.63 15.0 11.25 1.27 12.70 8.89 MAX 3.62 0.70 2.92 0.90 0.66 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 32 E b e e b F G 32-Lead (15mm × 11.25mm × 3.42mm) (Reference LTC DWG # 05-08-1851 Rev D) SEE NOTES Please refer to http://www.linear.com/product/LTM2887#packaging for the most recent package drawings.

2887fbFor more information www.linear .com/L TM2887 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 03/17 Added UL-CSA File Number 1 B 07/17 Changed MIN limit for t PWU (SPI and I2C) 6

2887fb For more information www.linear .com/L TM2887  LINEAR TECHNOLOGY CORPORATION 2016 LT 0717 REV B • PRINTED IN USA www.linear.com/LTM2887 RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LTM2881 Isolated RS485/RS422 µModule T ransceiver with Integrated DC/DC Converter 20Mbps 2500VRMS Isolation with Power in LGA/BGA Package LTM2882 Dual Isolated RS232 µModule T ransceiver with Integrated DC/DC Converter 2500V RMS Isolation with Power in LGA/BGA Package LTM2883 SPI/Digital or I2C µModule Isolator with Integrated DC/DC Converter 2500VRMS Isolation with Adjustable ±12.5V and 5V Power in BGA Package LTM2884 Isolated USB T ransceiver with Power 2500VRMS Auto Speed Selection, 1 to 2.5W Isolated Power LTM2886 SPI/Digital or I2C µModule Isolator with Integrated DC/DC Converter 2500VRMS Isolation with Fixed ±5V and Adjustable 5V Power in BGA Package LTM2889 Isolated CAN FD µModule T ransceiver with Power 4Mbps 2500V RMS Isolation with Power in BGA Package LTM2892 SPI/Digital or I2C µModule Isolator 3500VRMS Isolation without Power in 9mm × 6.25mm BGA Package LT C

1535 Isolated RS485 T ransceiver 2500VRMS Isolation with External T ransformer Drive

LTC4310 Hot-Swappable I2C Isolators Bidirectional I2C Communication, Low Voltage Level Shifting, 100kHz or 400kHz Operation LTC6803-1, LTC6803-3, LTC6803-2, LTC6803-4 Multicell Battery Stack Monitor LTC6803-1 Allows for Multiple Devices to be Daisy Chained, the LTC6803-2 Allows for Parallel Communication Batter y Stack Topologies Isolated Dual Channel Simultaneous Sampling Analog to Digital Converter, Input Range 0V to 2.5V L TM2887-3S 1.15k 3.3V 1µF 10µF 19.1k SCK MISO µC Ox VCC GND ON CS CS2 VL VCC GND SDI SDI2 SDOE SCK DO2 SCK2 AVCC2 IVCC2 IVL2 AVL2 VCC2 VL2 SDO SDO2 DO1 I1 GND2

2887 TA02

CH0– VDD CH1+ CH1– CH0+ CH0– CH1+ CH1– 10µF 6.04k