LTM2886

LTM2886 DS (Rev_D)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 38

Technical content

Rev. DFor more information www.analog.com TYPICAL APPLICATION FEATURES DESCRIPTION SPI/Digital or I2C µModule Isolator with Fixed ±5V and Adjustable 5V Regulated Power The LT M®2886 is a complete galvanic digital µModule ® (micromodule) isolator . No external components are required. A single 3.3V or 5V supply powers both sides of the interface through an integrated, isolated DC/DC converter . A logic supply pin allows easy interfacing with different logic levels from 1.62V to 5.5V, independent of the main supply. Available options are compliant with SPI and I2C (master mode only) specifications. The isolated side includes fixed ±5V and 5V adjustable power supplies, each capable of providing more than 100mA of load current. The 5V adjustable supply may be programmed via an external voltage divider . Coupled inductors and an isolation power transformer provide 2500VRMS of isolation between the input and out- put logic interface. This device is ideal for systems where the ground loop is broken, allowing for a large common mode voltage range. Communication is uninterrupted for common mode transients greater than 30kV/μs. All registered trademarks and trademarks are the property of their respective owners. Isolated 4MHz SPI Interface

APPLICATIONS

n 6-Channel Logic Isolator: 2500VRMS for 1 Minute n UL-CSA Recognized File #E151738 n Isolated DC Power: n 3V to 5V Adjustable at Up to 100mA n ±5V Fixed at Up to 100mA n No External Components Required n SPI/Digital (LTM2886-S) or I2C (LTM2886-I) Options n High Common Mode T ransient Immunity: 30kV/μs n High Speed Operation: n 10MHz Digital Isolation n 4MHz/8MHz SPI Isolation n 400kHz I2C Isolation n 3.3V (LTM2886-3) or 5V (LTM2886-5) Operation n 1.62V to 5.5V (LTM2886-S) or 3V to 5.5V (LTM2886-I) Logic Supply n ±10kV ESD HBM Across the Isolation Barrier n Maximum Continuous Working Voltage: 560VPEAK n Low Current Shutdown Mode (<10µA) n Low Profile (15mm × 11.25mm × 3.42mm) BGA Package n Isolated SPI or I2C Interfaces n Industrial Systems n Test and Measurement Equipment n Breaking Ground Loops LTM2886 Operating Through 50kV/µs CM T ransients

2886 TA01a

–5V AT 100mA 20ns/DIV 5V/DIV 200V/DIV SCK SD0 SCK2 = SD02

2886 TA01b

Rev. D For more information www.analog.com LTM2886-I LTM2886-S VCCGNDDO1 GND2 GND2I1 BGA PACKAGE 32-PIN (15mm × 11.25mm × 3.42mm) TOP VIEW AVCC2 F G H L J K E A B C D 21 43 5 6 7 8 DNCDO2 SDASCL DI1 GND ON VL DNCI2 SDA2SCL2 O1 VCC2 V– V+ TJMAX = 125°C, θJA = 25.5°C/W , θJC(BOTTOM) = 9.2°C/W , θJC(TOP) = 16.6°C/W , θJBOARD = 9.9°C/W θ VALUES DETERMINED PER JESD51-9, WEIGHT = 1.2g VCCGNDDO1 GND2 GND2I1 BGA PACKAGE 32-PIN (15mm × 11.25mm × 3.42mm) TOP VIEW AVCC2 F G H L J K E A B C D 21 43 5 6 7 8 DO2SDO SDISCK CS SDOE ON VL I2SDO2 SDI2SCK2 CS2 VCC2 V– V+ TJMAX = 125°C, θJA = 25.5°C/W , θJC(BOTTOM) = 9.2°C/W , θJC(TOP) = 16.6°C/W , θJBOARD = 9.9°C/W θ VALUES DETERMINED PER JESD51-9, WEIGHT = 1.2g ABSOLUTE MAXIMUM RATINGS Logic Inputs DI1, SCK, SDI, CS, SCL, SDA, SDOE, I1, I2, SDA2, (Note 1) PIN CONFIGURATION Logic Outputs O1, SCK2, SDI2, CS2, Operating Temperature Range (Note 4)

Rev. DFor more information www.analog.com LTM2886 C Y -3 I #PBF LEAD FREE DESIGNATOR PBF = Lead Free LOGIC OPTION I = Inter-IC (I2C) Bus S = Serial Peripheral Interface (SPI) Bus INPUT VOL TAGE RANGE 3 = 3V to 3.6V 5 = 4.5V to 5.5V PACKAGE TYPE Y = Ball Grid Array (BGA) TEMPERATURE GRADE C = Commercial Temperature Range (0°C to 70°C) I = Industrial Temperature Range (–40°C to 85°C) H = Automotive Temperature Range (–40°C to 125°C) PRODUCT PART NUMBER ORDER INFORMATION PRODUCT SELECTION GUIDE PART NUMBER PAD OR BALL FINISH PART MARKING PACKAGE TYPE MSL RATING INPUT VOL TAGE RANGE LOGIC OPTION TEMPERATURE RANGE DEVICE FINISH CODE LTM2886CY-3I#PBF SAC305 (RoHS) LTM2886Y-3I e1 BGA 3 3V to 3.6V I2C 0°C to 70°C LTM2886IY-3I#PBF –40°C to 85°C LTM2886HY-3I#PBF –40°C to 125°C LTM2886CY-3S#PBF LTM2886Y-3S SPI 0°C to 70°C LTM2886IY-3S#PBF –40°C to 85°C LTM2886HY-3S#PBF –40°C to 125°C LTM2886CY-5I#PBF LTM2886Y-5I 4.5V to 5.5V I2C 0°C to 70°C LTM2886IY-5I#PBF –40°C to 85°C LTM2886HY-5I#PBF –40°C to 125°C LTM2886CY-5S#PBF LTM2886Y-5S SPI 0°C to 70°C LTM2886IY-5S#PBF –40°C to 85°C LTM2886HY-5S#PBF –40°C to 125°C

• Device temperature grade is indicated by a label on the shipping container .
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Terminal Finish Part Marking: www.linear .com/leadfree
• This product is not recommended for second side reflow. For more information, go to www.linear .com/BGA-assy
• Recommended BGA PCB Assembly and Manufacturing Procedures: www.linear . com/BGA-assy
• BGA Package and T ray Drawings: www.linear .com/packaging
• This product is moisture sensitive. For more information, go to: www.linear .com/BGA-assy http://www.linear .com/product/LTM2886#orderinfo

Rev. D For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at TA = 25°C. LTM2886-3 VCC = 3.3V, LTM2886-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Supplies VCC Input Supply Range LTM2886-3 LTM2886-5 l l 4.5 3.3 3.6 5.5 V V VL Logic Supply Range LTM2886-S LTM2886-I l l 1.62 5.5 5.5 V V ICC Input Supply Current ON = 0V LTM2886-3, No Load LTM2886-5, No Load l l l µA mA mA IL Logic Supply Current ON = 0V LTM2886-S, ON = VL LTM2886-I, ON = VL l 0 150 µA µA µA Output Supplies VCC2 Regulated Output Voltage No Load, AVCC2 OPEN l 4.75 5 5.25 V Output Voltage Operating Range (Note 2) 3 5.5 V Line Regulation ILOAD = 1mA, MIN ≤ VCC ≤ MAX l 2 7.5 mV Load Regulation ILOAD = 1mA to 100mA l 15 100 mV ADJ Pin Voltage ILOAD = 1mA to 100mA l 1.15 1.220 1.27 V Voltage Ripple ILOAD = 100mA (Note 2) 1 mVRMS Efficiency LTM2886-5, ILOAD = 100mA (Note 2) 61 % ICC2 Output Short Circuit Current VCC2 = 0V 150 mA Current Limit ΔVCC2 = –5% l 90 mA V+ Regulated Output Voltage No Load l 4.8 5 5.2 V Line Regulation ILOAD = 1mA, MIN ≤ VCC ≤ MAX l 2 7.5 mV Load Regulation ILOAD = 1mA to 100mA l 35 150 mV Voltage Ripple ILOAD = 100mA (Note 2) 1 mVRMS Efficiency LTM2886-5, ILOAD = 100mA (Note 2) 61 % I+ Output Short Circuit Current V+ = 0V 150 mA Current Limit ΔV+ = –5% l 90 mA V– Regulated Output Voltage No Load l –4.8 –5 –5.2 V Line Regulation ILOAD = –1mA, MIN ≤ VCC ≤ MAX l 5 15 mV Load Regulation ILOAD = 1mA to 100mA l 35 150 mV Voltage Ripple ILOAD = 100mA (Note 2) 1 mVRMS Efficiency LTM2886-5, ILOAD = 100mA (Note 2) 61 % I– Output Short-Circuit Current V– = 0V 150 mA Current Limit ΔV– = 5% l 90 mA

Rev. DFor more information www.analog.com

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Logic/SPI VITH Input Threshold Voltage ON, DI1, SDOE, SCK, SDI, CS: 1.62V ≤ VL < 2.35V ON, DI1, SDOE, SCK, SDI, CS: 2.35V ≤ VL I1, I2, SDO2 l l l 0.25 • VL 0.33 • VL 0.33 • VCC2 0.75 • VL 0.67 • VL 0.67 • VCC2 V V V IINL Input Current l ±1 µA VHYS Input Hysteresis 150 mV VOH Output High Voltage DO1, DO2, SDO, ILOAD = –1mA, 1.62V ≤ VL < 3V, ILOAD = –4mA, 3V ≤ VL ≤ 5.5V l VL – 0.4 V O1, SCK2, SDI2, CS2, ILOAD = –4mA l VCC2 – 0.4 V VOL Output Low Voltage DO1, DO2, SDO, ILOAD = 1mA, 1.62V ≤ VL < 3V, ILOAD = 4mA, 3V ≤ VL ≤ 5.5V l 0.4 V O1, SCK2, SDI2, CS2, ILOAD = 4mA l 0.4 V ISC Short-Circuit Current 0V ≤ (DO1, DO2, SDO) ≤ VL 0V ≤ (O1, SCK2, SDI2, CS2) ≤ VCC2 l ±60 ±85 mA mA I2C VIL Low Level Input Voltage SCL, SDA SDA2 l l 0.3 • VL 0.3 • VCC2 V V VIH High Level Input Voltage SCL, SDA SDA2 l l 0.7 • VL 0.7 • VCC2 V V IINL Input Current SCL, SDA = VL or 0V SDA2 = VCC2, SDA2 = VCC2 = 0V l l µA µA VHYS Input Hysteresis SCL, SDA SDA2 0.05 • VL 0.05 • VCC2 V V VOH Output High Voltage SCL2, ILOAD = –2mA DO2, ILOAD = –2mA l l VCC2 – 0.4 VL – 0.4 V V VOL Output Low Voltage SDA, ILOAD = 3mA DO2, ILOAD = 2mA SCL2, ILOAD = 2mA SDA2, No Load, SDA = 0V, 4.5V ≤ VCC2 < 5.5V SDA2, No Load, SDA = 0V, 3V ≤ VCC2 < 4.5V l l l l l 0.3 0.4 0.4 0.4 0.45 0.55 V V V V V CIN Input Pin Capacitance SCL, SDA, SDA2 (Note 2) l 10 pF CB Bus Capacitive Load SCL2, Standard Speed (Note 2) SCL2, Fast Speed SDA, SDA2, SR ≥ 1V/µs, Standard Speed (Note 2) SDA, SDA2, SR ≥ 1V/µs, Fast Speed l l l l 400 200 400 200 pF pF pF pF Minimum Bus Slew Rate SDA, SDA2 l 1 V/µs ISC Short-Circuit Current SDA2 = 0, SDA = VL 0V ≤ SCL2 ≤ VCC2 0V ≤ DO2 ≤ VL SDA = 0, SDA2 = VCC2 SDA = VL, SDA2 = 0 l ±30 ±30 –1.8 100 mA mA mA mA mA ESD (HBM) (Note 2) Isolation Boundary (VCC2, V+, V–, GND2) to (VCC, VL, GND) ±10 kV The l denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at TA = 25°C. LTM2886-3 VCC = 3.3V, LTM2886-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.

Rev. D For more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Logic Maximum Data Rate DI1 → O1, Ix → DOx, CL = 15pF (Note 3) l 10 MHz tPHL, tPLH Propagation Delay CL = 15pF (Figure 1) l 35 60 100 ns tR Rise Time CL = 15pF (Figure 1) LTM2886-I, DO2, CL = 15pF (Figure 1) l l 12.5 ns ns tF Fall Time CL = 15pF (Figure 1) LTM2886-I, DO2, CL = 15pF (Figure 1) l l 12.5 ns ns SPI Maximum Data Rate Bidirectional Communication (Note 3) Unidirectional Communication (Note 3) l l MHz MHz tPHL, tPLH Propagation Delay CL = 15pF (Figure 1) l 35 60 100 ns tPWU Output Pulse Width Uncertainty SDO, SDI2, CS2 (Note 2) ±50 ns tR Rise Time CL = 15pF (Figure 1) l 3 12.5 ns tF Fall Time CL = 15pF (Figure 1) l 3 12.5 ns tPZH, tPZL Output Enable Time SDOE = ↓, RL = 1kΩ, CL = 15pF (Figure 2) l 50 ns tPHZ, tPLZ Output Disable Time SDOE = ↑, RL = 1kΩ, CL = 15pF (Figure 2) l 50 ns I2C Maximum Data Rate (Note 3) l 400 kHz tPHL, tPLH Propagation Delay SCL → SCL2, CL = 15pF (Figure 1) SDA → SDA2, RL = Open, CL = 15pF (Figure 3) SDA2 → SDA, RL = 1.1kΩ, CL = 15pF (Figure 3) l l l 150 150 300 225 250 500 ns ns ns tPWU Output Pulse Width Uncertainty SDA, SDA2 (Note 2) ±50 ns tHD;DAT Data Hold Time (Note 2) 600 ns tR Rise Time SDA2, CL = 200pF (Figure 3) SDA, RL = 1.1kΩ CL = 200pF (Figure 3) SCL2, CL = 200pF (Figure 1) l l l 300 250 250 ns ns ns tF Fall Time SDA2, CL = 200pF (Figure 3) SDA, RL = 1.1kΩ CL = 200pF (Figure 3) SCL2, CL = 200pF (Figure 1) l l l 250 250 250 ns ns ns tSP Pulse Width of Spikes Suppressed by Input Filter l 0 50 ns Power Supply Power-Up Time ON = ↑ to VCC2 (Min) ON = ↑ to V+ (Min) ON = ↑ to V– (Min) l l l 0.6 0.6 0.6 ms ms ms SWITCHING CHARACTERISTICS The l denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at TA = 25°C. LTM2886-3 VCC = 3.3V, LTM2886-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. Specifications apply to all options unless otherwise noted.

Rev. DFor more information www.analog.com Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Guaranteed by design and not subject to production test. Note 3: Maximum Data rate is guaranteed by other measured parameters and is not tested directly. Note 4: This Module includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above specified maximum operating junction temperature may result in device degradation or failure. Note 5: Device considered a 2-terminal device. Pin group A1 through B8 shorted together and pin group K1 through L8 shorted together . Note 6: The rated dielectric insulation voltage should not be interpreted as a continuous voltage rating. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VISO Rated Dielectric Insulation Voltage 1 Minute, Derived from 1 Second Test

1 Second (Notes 5, 6)

Common Mode T ransient Immunity LTM2886-3 VCC = 3.3V, LTM2885-5 VCC = 5V, VL = ON = 3.3V, VCM = 1kV, Δt = 33ns (Note 2) 30 kV/µs VIORM Maximum Continuous Working Voltage (Notes 2, 5) 560 400 VPEAK, VDC VRMS Partial Discharge VPD = 750VRMS (Note 5) 5 pC CTI Comparative T racking Index IEC 60112 (Note 2) 600 VRMS Depth of Erosion IEC 60112 (Note 2) 0.017 mm DTI Distance Through Insulation (Note 2) 0.06 mm Input to Output Resistance (Notes 2, 5) 109 Ω Input to Output Capacitance (Notes 2, 5) 6 pF Creepage Distance (Note 2) 9.5 mm ISOLATION CHARACTERISTICS T A = 25°C. TYPICAL PERFORMANCE CHARACTERISTICS Isolated Supplies vs Equal Load Current VCC Supply Current vs Temperature Isolated Supplies vs Equal Load Current TA = 25°C, LTM2886-3 VCC = 3.3V, LTM2886-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted. TEMPERATURE (°C) –50 SUPPL Y CURRENT (mA) 500 100

2886 G01

12525–25 75 L TM2886-3 VCC = 3.3V L TM2886-5 VCC = 5V NO LOAD, REFRESH DATA ONL Y LOAD CURRENT (mA) VOL TAGE (V) 5.50 4.25 4.50 4.75 5.00 5.25 4.00 5030 4010 20

2886 G02

|V–| L TM2886-3 VCC = 3.3V LOAD CURRENT (mA) VOL TAGE (V) 5.50 4.50 4.25 4.75 5.00 5.25 4.00 604020

2886 G03

VCC = 5V VCC2 |V–|

Rev. D For more information www.analog.com VCC2 Line Regulation vs Load Current V+ Line Regulation vs Load Current V– Line Regulation vs Load Current VCC2 Line Regulation vs Load Current V+ Line Regulation vs Load Current V– Line Regulation vs Load Current V+ Load Regulation vs Temperature V– Load Regulation vs Temperature VCC2 Load Regulation vs Temperature LOAD CURRENT (mA) VCC2 VOL TAGE (V) 6.0 3.0 3.5 4.0 4.5 5.0 5.5 2.5 5025 75 100 125 150 175

2886 G04

VCC = 3V VCC = 3.3V VCC = 3.6V L TM2886-3 LOAD CURRENT (mA) V+ VOL TAGE (V) 6.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 755025 100

2886 G05

VCC = 3V VCC = 3.3V VCC = 3.6V L TM2886-3 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 LOAD CURRENT (mA) |V–| VOL TAGE (V) 150 17525 50 75 100 125

2886 G06

VCC = 3V VCC = 3.3V VCC = 3.6V L TM2886-3 LOAD CURRENT (mA) VCC2 VOL TAGE (V) 6.0 3.0 3.5 4.0 4.5 5.0 5.5 2.5 10050 150 200 250

2886 G07

VCC = 4.5V VCC = 5V VCC = 5.5V L TM2886-5 LOAD CURRENT (mA) V+ VOL TAGE (V) 6.0 3.0 3.5 4.0 4.5 5.0 5.5 2.5 10050 150

2886 G08

VCC = 4.5V VCC = 5V VCC = 5.5V 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 LOAD CURRENT (mA) |V–| VOL TAGE (V) 20050 100 150 250

2886 G09

VCC = 4.5V VCC = 5V VCC = 5.5V L TM2886-5 TEMPERATURE (°C) –50 VCC2 VOL TAGE (V) 5.15 5.00 5.10 5.05 4.95 4.85 4.90 500 100

2886 G10

12525–25 75 ICC2 = 1mA ICC2 = 100mA L TM2886-3 VCC = 3.3V TEMPERATURE (°C) –50 V+ VOL TAGE (V) 5.15 5.00 5.10 5.05 4.95 4.85 4.90 500 100

2886 G11

12525–25 75 I+ = 1mA I+ = 100mA L TM2886-3 VCC = 3.3V TEMPERATURE (°C) –50 |V–| VOL TAGE (V) 5.15 5.00 5.10 5.05 4.95 4.85 4.90 500 100

2886 G12

12525–25 75 L TM2886-3 VCC = 3.3V I– = 1mA I– = 100mA TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, LTM2886-3 VCC = 3.3V, LTM2886-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted.

Rev. DFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS V– Load Regulation vs Temperature VCC2 Efficiency VCC2 Voltage and ICC Current vs Load Current VCC2 Load Regulation vs Temperature V+ Load Regulation vs Temperature TA = 25°C, LTM2886-3 VCC = 3.3V, LTM2886-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted. V+ Efficiency TEMPERATURE (°C) –50 VCC2 VOL TAGE (V) 5.15 5.05 5.10 5.00 4.85 4.90 4.95 500 100

2886 G13

12525–25 75 L TM2886-5 VCC = 5V ICC2 = 1mA ICC2 = 100mA TEMPERATURE (°C) –50 V+ VOL TAGE (V) 5.15 5.00 5.10 5.05 4.95 4.85 4.90 500 100

2886 G14

12525–25 75 I+ = 1mA I+ = 100mA L TM2886-5 VCC = 5V TEMPERATURE (°C) –50 |V–| VOL TAGE (V) 5.15 4.90 5.10 5.05 5.00 4.95 4.85 500 100

2886 G15

12525–25 75 I– = 1mA I– = 100mA L TM2886-5 VCC = 5V LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (W) 1.4 1.0 0.6 0.8 0.4 0.2 1.2 0.0 15010050 200 250

2886 G16

L TM2886-3, VCC = 3.3V L TM2886-5, VCC = 5V LOAD CURRENT (mA) VCC2 VOL TAGE (V) ICC CURRENT (mA) 600 400 200 300 100 500 15050 100 200 250

2886 G17

L TM2886-3, VCC = 3.3V L TM2886-5, VCC = 5V LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (W) 1.4 1.2 0.8 0.4 0.6 0.2 1.0 0.0 10050 200150

2886 G18

L TM2886-3, VCC = 3.3V L TM2886-5, VCC = 5V V+ Voltage and ICC Current vs Load Current 0 15010050 200 300250 LOAD CURRENT (mA) V+ VOL TAGE (V) ICC CURRENT (mA) 600 400 200 300 100 500

2886 G19

L TM2886-3, VCC = 3.3V L TM2886-5, VCC = 5V

Rev. D For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS V– Efficiency V– Voltage and ICC Current vs Load Current VCC2 T ransient Response 100mA Load Step V+ T ransient Response 100mA Load Step V– T ransient Response 100mA Load Step TA = 25°C, LTM2886-3 VCC = 3.3V, LTM2886-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted. VCC2 Ripple V+ Ripple V– Ripple LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (W) 1.4 1.0 0.8 0.2 0.6 0.4 1.2 0.0 200 25010050 150

2886 G20

L TM2886-3, VCC = 3.3V L TM2886-5, VCC = 5V EFFICIENCY POWER LOSS LOAD CURRENT (mA) |V–| VOL TAGE (V) ICC CURRENT (mA) 600 300 100 200 400 500 25020015010050

2886 G21

L TM2886-3, VCC = 3.3V L TM2886-5, VCC = 5V ICC CURRENT VOL TAGE 100µs/DIV 0.5V/DIV 50mA/DIV

2886 G22

100µs/DIV 0.5V/DIV 50mA/DIV

2886 G23

100µs/DIV 0.5V/DIV 50mA/DIV

2886 G24

2886 G25

LOAD = 1mA LOAD = 100mA 400ns/DIV

2886 G26

LOAD = 1mA LOAD = 100mA 2mV/DIV 400ns/DIV

2886 G27

LOAD = 1mA LOAD = 100mA 2mV/DIV

Rev. DFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS VCC Supply Current vs Single Channel Data Rate Logic Input Threshold vs VL Supply Voltage Logic Output Voltage vs Load Current TA = 25°C, LTM2886-3 VCC = 3.3V, LTM2886-5 VCC = 5V, VL = 3.3V, GND = GND2 = 0V, ON = VL unless otherwise noted. VCC2 Noise V+ Noise V– Noise Isolated Supply Efficiency with Equal Load CurrentPower On Sequence Derating for 125°C Maximum Internal Operating Temperature 1ms/DIV 2mV/DIV

2886 G28

LOAD = 100mA 1ms/DIV

2886 G29

LOAD = 100mA 1ms/DIV 2mV/DIV

2886 G30

LOAD = 100mA DATA RATE (Hz) VCC CURRENT (mA) 100k10k 1M

2886 G31

VCC = 5VCL = 1nF CL = 330pF CL = 100pF CL = 20pF VL SUPPL Y VOL TAGE (V) THRESHOLD VOL TAGE (V) 3.5 2.5 0.5 1.0 2.0 3.0 1.5 4 52

2886 G32

|LOAD CURRENT| (mA) OUTPUT VOL TAGE (V) 21 3

2886 G33

VL = 5.5V VL = 3.3V VL = 1.62V 100µs/DIV 2.5V/DIV 1V/DIV ON VCC2

2886 G34

L TM2886-5, VL = 5V LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (W) 1.4 0.2 0.4 0.6 1.0 0.8 1.2 0.0 50 6010 20 30 40 70 80 90

2886 G35

L TM2886-3, VCC = 3.3V L TM2886-5, VCC = 5V BASED ON THERMAL IMAGING OF DEMO CIRCUIT 1790A V CC2 , V , V EQUALL Y LOADED L TM2886-3, VCC = 3.3V L TM2886-5, VCC = 5V TEMPERATURE (°C) 100 125 100 200 300 400 500 600 V CC SUPPL Y CURRENT (mA)

2886 G36

Rev. D For more information www.analog.com PIN FUNCTIONS Logic Side DO2 (A1): Digital Output, Referenced to VL and GND. Logic output connected to I2 through isolation barrier . Under the condition of an isolation communication failure this output is in a high impedance state. DNC (A2): Do Not Connect. Pin connected internally. SCL (A3): Serial I 2C Clock Input, Referenced to V L and GND. Logic input connected to isolated side SC L2 pin through isolation barrier . Clock is unidirectional from logic to isolated side. Do not float. SDA (A4): Serial I2C Data Pin, Referenced to VL and GND. Bidirectional logic pin connected to isolated side SDA2 pin through isolation barrier . Under the condition of an isola- tion communication failure this pin is in a high impedance state. Do not float. DI1 (A5): Digital Input, Referenced to VL and GND. Logic input connected to O1 through isolation barrier . The logic state on DI1 translates to the same logic state on O1. Do not float. GND (A6, B2 to B6): Circuit Ground. ON ( A7): Enable, Referenced to V L and GND. Enables power and data communication through the isolation barrier . If ON is high the part is enabled and power and communications are functional to the isolated side. If ON is low the logic side is held in reset, all digital outputs are in a high impedance state, and the isolated side is unpowered. Do not float. VL (A8): Logic Supply. Interface supply voltage for pins DI1, SCL, SDA, DO1, DO2, and ON. Operating voltage is 3V to 5.5V. Internally bypassed with 1µF. DO1 (B1): Digital Output, Referenced to VL and GND. Logic output connected to I1 through isolation barrier . Under the condition of an isolation communication failure this output is in a high impedance state. VCC (B7 to B8): Supply Voltage. Operating voltage is 3V to 3.6V for LTM2886-3 and 4.5V to 5.5V for LTM2886-5. Internally bypassed with 2.2µF. Isolated Side I2 ( L1): Digital Input, Referenced to V CC2 and G ND2. Logic input connected to DO2 through isolation barrier . The logic state on I2 translates to the same logic state on DO2. Do not float. DNC (L2): Do Not Connect. Pin connected internally. SCL2 (L3): Serial I2C Clock Output, Referenced to V CC2 and GND2. Logic output connected to logic side SCL pin through isolation barrier . Clock is unidirectional from logic to isolated side. SCL2 has a push-pull output stage, do not connect an external pull-up device. Under the condition of an isolation communication failure this output defaults to a high state. SDA2 (L4): Serial I2C Data Pin, Referenced to V CC2 and GND2. Bidirectional logic pin connected to logic side SDA pin through isolation barrier . Output is biased high by a 1.8mA current source. Do not connect an external pull- up device to S DA2. Under the condition of an isolation communication failure this output defaults to a high state. O1 (L5): Digital Output, Referenced to V CC2 and G ND2. Logic output connected to DI1 through isolation barrier . Under the condition of an isolation communication failure O1 defaults to a high state. VCC2 (L6): 3V to 5.5V Adjustable Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC con- verter and regulated to 5V with no external components. Internally bypassed with 2.2µF. V– (L7): –5V Nominal Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC converter and regulated to –5V with no external components. Internally bypassed with 2.2µF. V+ (L8): 5V Nominal Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC converter and regulated to 5V with no external components. Internally bypassed with 2.2µF. I1 ( K1): Digital Input, Referenced to V CC2 and G ND2. Logic input connected to DO1 through isolation barrier . The logic state on I1 translates to the same logic state on DO1. Do not float. GND2 (K2 to K5, K7, K8): Isolated Ground. AVCC2 (K6): 5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 1.22V referenced to GND2. See Applications Information section for details. (LTM2886-I)

Rev. DFor more information www.analog.com PIN FUNCTIONS Logic Side SDO ( A1): Serial SPI Digital Output, Referenced to V L and GND. Logic output connected to isolated side SDO2 pin through isolation barrier . Under the condition of an isolation communication failure this output is in a high impedance state. DO2 (A2): Digital Output, Referenced to VL and GND. Logic output connected to I2 through isolation barrier . Under the condition of an isolation communication failure this output is in a high impedance state. SCK (A3): Serial SPI Clock Input, Referenced to V L and GND. Logic input connected to isolated side SC K2 pin through isolation barrier . Do not float. SDI (A4): Serial SPI Data Input, Referenced to VL and GND. Logic input connected to isolated side SDI2 pin through isolation barrier . Do not float. CS (A5): Serial SPI Chip Select, Referenced to VL and GND. Logic input connected to isolated side CS2 pin through isolation barrier . Do not float. SDOE (A6): Serial SPI Data Output Enable, Referenced to VL and GND. A logic high on SDOE places the logic side SDO pin in a high impedance state, a logic low enables the output. Do not float. ON (A7): Enable, Referenced to VL and GND. Enables power and data communication through the isolation barrier . If ON is high the part is enabled and power and communications are functional to the isolated side. If ON is low the logic side is held in reset, all digital outputs are in a high impedance state, and the isolated side is unpowered. Do not float. VL (A8): Logic Supply. Interface supply voltage for pins SDI, SCK, SDO, SDOE, DO1, DO2, CS, and ON. Operating voltage is 1.62V to 5.5V. Internally bypassed with 1µF. DO1 (B1): Digital Output, Referenced to VL and GND. Logic output connected to I1 through isolation barrier . Under the condition of an isolation communication failure this output is in a high impedance state. GND (B2 to B6): Circuit Ground. VCC (B7 to B8): Supply Voltage. Operating voltage is 3V to 3.6V for LTM2886-3 and 4.5V to 5.5V for LTM2886-5. Internally bypassed with 2.2µF. Isolated Side SDO2 (L1): Serial SPI Digital Input, Referenced to V CC2 and GND2. Logic input connected to logic side SDO pin through isolation barrier . Do not float. I2 ( L2): Digital Input, Referenced to V CC2 and G ND2. Logic input connected to DO2 through isolation barrier . The logic state on I2 translates to the same logic state on DO2. Do not float. SCK2 (L3): Serial SPI Clock Output, Referenced to V CC2 and GND2. Logic output connected to logic side SCK pin through isolation barrier . Under the condition of an isolation communication failure this output defaults to a low state. SDI2 (L4): Serial SPI Data Output, Referenced to V CC2 and GND2. Logic output connected to logic side SDI pin through isolation barrier . Under the condition of an isolation communication failure this output defaults to a low state. CS2 (L5): Serial SPI Chip Select, Referenced to VCC2 and GND2. Logic output connected to logic side CS pin through isolation barrier . Under the condition of an isolation com- munication failure this output defaults to a high state. VCC2 (L6): 3V to 5.5V Adjustable Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC con- verter and regulated to 5V with no external components. Internally bypassed with 2.2µF. V– (L7): –5V Nominal Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC converter and regulated to –5V with no external components. Internally bypassed with 2.2µF. V+ (L8): 5V Nominal Isolated Supply Voltage. Internally generated from VCC by an isolated DC/DC converter and regulated to 5V with no external components. Internally bypassed with 2.2µF. I1 ( K1): Digital Input, Referenced to V CC2 and G ND2. Logic input connected to DO1 through isolation barrier . The logic state on I1 translates to the same logic state on DO1. Do not float. GND2 (K2 to K5, K7, K8): Isolated Ground. AVCC2 (K6): 5V Nominal Isolated Supply Voltage Adjust. The adjust pin voltage is 1.22V Referenced to GND2. See Applications Information section for details. (LTM2886-S)

Rev. D For more information www.analog.com BLOCK DIAGRAMS (LTM2886-I) 2886 BD 1µF 2.2µF VCC VCC2 AVCC2 VL 2.2µF GND ON SDA DI1 DO2 DO1 SCL SCL2 SDA2 GND2 DC/DC CONVERTER ISOLATED COMMUNI- CATIONS INTERFACE ISOLATED COMMUNI- CATIONS INTERFACE REG 2.2µF 2.2µF REG REG

Rev. DFor more information www.analog.com (LTM2886-S)

2886 BDa

1µF 2.2µF VCC VCC2 AVCC2 VL 2.2µF GND ON SDOE DO2 SDI CS SDO DO1 SCK CS2 SDO2 SCK2 SDI2 GND2 DC/DC CONVERTER ISOLATED COMMUNI- CATIONS INTERFACE ISOLATED COMMUNI- CATIONS INTERFACE REG 2.2µF 2.2µF REG REG

2886 F01

Figure 1. Logic Timing Measurements Figure 2. Logic Enable/Disable Time Figure 3. I2C Timing Measurements

2886 F02

2886 F03

networks where grounds can take on different voltages. greater than 30kV/μs providing excellent noise isolation. translate signals and power across an isolation barrier . coreless transformers formed in the µModule substrate. a powerful isolated DC/DC converter in one small package. transformer saturation caused by secondary imbalances. current, total output power capability is approximately 1W. All voltage rails are bypassed with 2.2µF ceramic capacitors. Figure 4. Simply connect the desired logic supply to VL. is bypassed internally by a 1µF capacitor . and mitigation of this phenomenon.

2886 F04

Figure 4. VCC and VL Are Independent

Figure 5. Adjustable Voltage Rails = 3.3V, V+ and V– are fixed at 5V and –5V respectively. ary by encoding and decoding of the inputs and outputs. no jitter on the associated output channels, only delay. clock phase (CPHA) summarized in Table 1. Table 1. SPI Mode shutdown due to low dropout regulator power dissipation.

2886 F05

Rev. DFor more information www.analog.com

• CS to SCK (master sample SDO, 1st SDO valid) t0 → t1 ≈50ns, CS to CS2 propagation delay t1 → t1+ Isolated slave device propagation (response time), asserts SDO2 t1 → t3 ≈50ns, SDO2 to SDO propagation delay t3 → t5 Set-up time for master SDO to SCK
• SDI to SCK (master data write to slave) t2 → t4 ≈50ns, SDI to SDI2 propagation delay t5 → t6 ≈50ns, SCK to SCK2 propagation delay t2 → t5 ≥50ns, SDI to SCK, separate packet non-zero set-up time t4 → t6 ≥50ns, SDI2 to SCK2, separate packet non-zero set-up time
• SDO to SCK (master sample SDO, subsequent SDO valid) t8 set-up data transition SDI and SCK t8 → t10 ≈50ns, SDI to SDI2 and SCK to SCK2 propagation delay APPLICATIONS INFORMATION t10 SDO2 data transition in response to SCK2 t10 → t11 ≈50ns, SDO2 to SDO propagation delay t11 → t12 Set-up time for master SDO to SCK Maximum data rate for single direction communication, master to slave, is 8MHz, limited by the systems encod- ing/decoding scheme or propagation delay. Timing details for both variations of clock phase are shown in Figures 8 and 9 and Table 3. Additional requirements to insure maximum data rate are:
• CS is transmitted prior to (asynchronous) or within the same (synchronous) data packet as SDI
• SDI and SCK set-up data transition occur within the same data packet. Referencing Figure 6, SDI can pre- cede SCK by up to 13ns (t7 → t8) or lag SCK by 3ns (t8 → t9) and not violate this requirement. Similarly in Figure 8, SDI can precede SCK by up to 13ns (t4 → t5) or lag SCK by 3ns (t5 → t6).

Figure 7. SPI Timing, Bidirectional, CPHA = 1

2886 F07

Figure 6. SPI Timing, Bidirectional, CPHA = 0

2886 F06

Figure 8. SPI Timing, Unidirectional, CPHA = 0

2886 F08

Figure 9. SPI Timing, Unidirectional, CPHA = 1

2886 F09

Table 2. Bidirectional SPI Timing Event Description

1 Propagation delay of data and clock, logic side to isolated side

1 Last sample clock transition logic side

1 Propagation delay clock, logic to isolated side

1 Last slave data output and data transition, logic side

and logic data fall time of 300ns at maximum bus loading. greater than 400pF in STANDARD mode.

Table 3. Unidirectional SPI Timing Event Description

1 Last clock transition

1 Clock propagation delay

Figure 11. Isolated SDA2 Pin Schematic Figure 10. I2C Timing Diagram

2886 F11

2886 F10

be greater than 1V/µs for proper operation. to the left of the appropriate curve.

output driver; do not connect an external pull-up device. a printed circuit board or route with ground between. filter at the SCL2 pin to reduce noise injection onto SDA2. rails may be filtered to improve the noise performance. ment on the V– rail will be nearly equivalent. high frequency filter to lower the noise corner frequency. RMS noise at a bandwidth of 340Hz is approximately 22µV. Figure 12. Maximum Standard Speed Pull-Up Resistance on SDA Figure 13. Maximum Fast Speed Pull-Up Resistance on SDA Figure 14. Filtered Voltage Rails for Low Noise Applications

2886 F12

2886 F13

2886 F15

Figure 15. V+ Output Noise Spectral Density Without Filter Figure 16. V+ Output Noise Spectral Density With Filter signed per the data sheet PCB layout recommendations. Specific limits per test are detailed in Table 5. Table 4. EMC Immunity Tests layout considerations are necessary.

• Under heavily loaded conditions VCC and GND current can exceed 300mA. Sufficient copper must be used on the PCB to insure resistive losses do not cause the supply voltage to drop below the minimum allowed level. Similarly, the VCC2 and GND2 conductors must be sized to support any external load current. These heavy copper traces will also help to reduce thermal stress and improve the thermal conductivity.
• Input and output supply decoupling is not required, since these components are integrated within the package. An additional bulk capacitor with a value of 6.8µF to 22µF is recommended. The high ESR of this capacitor reduces board resonances and minimizes voltage spikes caused by hot plugging of the supply voltage. For EMI sensitive applications, an additional low ESL ceramic capacitor of 1µF to 4.7µF, placed as close to the power and ground terminals as possible, is recommended. Alternatively, a number of smaller value parallel capacitors may be used to reduce ESL and achieve the same net capacitance.
• Do not place copper on the PCB between the inner columns of pads. This area must remain open to withstand the rated isolation voltage.
• The use of solid ground planes for GND and G ND2 is recommended for non-EMI critical applications to optimize signal fidelity, thermal performance, and to minimize RF emissions due to uncoupled PCB trace FREQUENCY (kHz) 0.01 0.1 1 OUTPUT NOISE SPECTRAL DENSITY (µV/√Hz) 0.1 0.01 10 100 1000

2886 F16

Figure 17. LTM2886 Low EMI Demo Board Layout can exacerbate RF emissions.

• For large ground planes a small capacitance (≤330pF) from GND to G ND2, either discrete or embedded within the substrate, provides a low impedance cur - rent return path for the module parasitic capacitance, minimizing any high frequency differential voltages and substantially reducing radiated emissions. Discrete capacitance will not be as effective due to parasitic ESL. In addition, voltage rating, leakage, and clear - ance must be considered for component selection. Embedding the capacitance within the PCB substrate provides a near ideal capacitor and eliminates com - ponent selection issues ; however , the PCB must be four layers. Care must be exercised in applying either technique to ensure the voltage rating of the barrier is not compromised.
• In applications without an embedded PCB substrate capacitance a slot may be added between the logic side and isolated side device pins. The slot extends the creepage path between terminals on the PCB side, and may reduce leakage caused by PCB contamination. The slot should be placed in the middle of the device and extend beyond the package perimeter . The PCB layout in Figures 17 and 18 shows the low EMI demo board for the LTM2886. The demo board uses a combination of EMI mitigation techniques, including both embedded PCB bridge capacitance and discrete GND to GND2 capacitors. T wo safety rated type Y2 capacitors are used in series, manufactured by MuRata, part number GA342QR7GF471KW01L. The embedded capacitor ef - fectively suppresses emissions above 400MHz, whereas the discrete capacitors are more effective below 400MHz. EMI performance is shown in Figure 19, measured using a Gigahertz T ransverse Electromagnetic (GTEM) cell and method detailed in IEC 61000-4-20, Testing and Measure- ment Techniques – Emission and Immunity Testing in T ransverse Electromagnetic Waveguides.

Figure 18. LTM2886 Low EMI Demo Board Layout (DC1790A)

2886 F20

Figure 20. Isolated I2C 12-Bit, ±5V Analog Input and Output Figure 19. LTM2886 Low EMI Demo Board Emissions

2886 F19

Figure 21. Isolated SPI Device Expansion

2886 F21

Figure 22. Isolated I2C Buffer with Dual Outputs

2886 F22

Figure 23. 16-Channel Isolated Temperature to Frequency Converter

2886 F23

2886 F24

Figure 24. Digitally Switched T riple Power Supply with Undervoltage Monitor

Figure 25. Quad 16-Bit ±5V Output Range DAC

2886 F25

Figure 26. –48V, 200W Hot Swap Controller with Isolated I2C Interface

2886 F26

24 ADIN

Figure 27. 12-Cell Battery Stack Monitor with Isolated SPI Interface and Low Power Shutdown

2886 F27

2886 F28

Figure 28. Isolated I2C Voltage, Current and Temperature Power Supply Monitor

2886 F29

Figure 29. One Complete Isolated Powered Ethernet Port

Rev. D For more information www.analog.com 32-Lead (15mm × 11.25mm × 3.42mm) (Reference L TC DWG # 05-08-1851 Rev D) 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu

7 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW BGA 32 1112 REV D L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” DETAIL A PIN 1 0.000 0.635 0.635 1.905 1.905 3.175 3.175 4.445 4.445 6.350 6.350 5.080 5.080 0.000 DETAIL A Øb (32 PLACES) F G H L J K E A B C D 2 14 35678 DETAIL B SUBSTRATE 0.27 – 0.37 2.45 – 2.55 // bbb Z D A ccc Z DETAIL B PACKAGE SIDE VIEW MOLD CAP Z M X YZddd M Zeee 0.630 ±0.025 Ø 32x SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 3.22 0.50 2.72 0.60 0.60 NOM 3.42 0.60 2.82 0.75 0.63 15.0 11.25 1.27 12.70 8.89 MAX 3.62 0.70 2.92 0.90 0.66 0.15 0.10 0.20 0.30 0.15 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 32 E b e e b F G 32-Lead (15mm × 11.25mm × 3.42mm) (Reference LTC DWG # 05-08-1851 Rev D) SEE NOTES Please refer to http://www.linear .com/product/LTM2886#packaging for the most recent package drawings.

Rev. DFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 03/17 Added UL-CSA File Number 1 B 07/17 Changed MIN limits for tPWU (SPI and I2C) Changed MAX limits for Power-Up Time C 11/22 Updated Features Updated Pin Funtions Updated Figure 4 D 9/25 Updated Template. Updated Features and Copyright Information. 1–38

Rev. D For more information www.analog.com ANALOG DEVICES, INC. 2016-2025 www.analog.com RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LTM2881 Isolated RS485/RS422 µModule T ransceiver with Integrated DC/DC Converter 20Mbps 2500VRMS Isolation with Power in LGA/BGA Package LTM2882 Dual Isolated RS232 µModule T ransceiver with Integrated DC/DC Converter 2500VRMS Isolation with Power in LGA/BGA Package LTM2883 SPI/Digital or I2C µModule Isolator with Integrated DC/DC Converter 2500VRMS Isolation with Adjustable ±12.5V and 5V Power in BGA Package LTM2884 Isolated USB T ransceiver with Power 2500VRMS, Auto Speed Selection, 1 to 2.5W Isolated Power LTM2889 Isolated CAN FD µModule T ransceiver with Power 4Mbps 2500VRMS Isolation with Power in BGA Package LTM2892 SPI/Digital or I2C µModule Isolator 3500VRMS Isolation without Power in 9mm × 6.25mm BGA Package LT C

1535 Isolated RS485 T ransceiver 2500VRMS Isolation with External Transformer Drive

LTC4310 Hot-Swappable I2C Isolators Bidirectional I2C Communication, Low Voltage Level Shifting, 100kHz or 400kHz Operation LTC6803-1, LTC6803-3, LTC6803-2, LTC6803-4 Multicell Battery Stack Monitor LTC6803-1 Allows for Multiple Devices to be Daisy Chained, the LTC6803-2 Allows for Parallel Communication Battery Stack Topologies 14-Bit Isolated High Speed Bipolar ADC ON CS CS2 L TM2886-3S VL VCC GND SDI SDI2 SDOE SCK 3.3V DO2 SCK2 AVCC2 VCC2 SDO SDO2 DO1 I1 GND2 10µF 0.1µF 10µF 0.1µF 1µF µC OX MISO IX VCC GND OY SCK

2886 TA03

L TC1417, ADC ±2.048V INPUT RANGE DGND BUSY VREF CONVST RD REFC SHDN ECLK SCLK VDD AIN+ VSS AIN– CLKODOUT + + 10µF 0.1µF 1µF+