LTM2885

LTC2862A_V01 AD | Alldatasheet

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Technical content

Rev. AFor more information www.analog.comDocument Feedback TYPICAL APPLICATION

DESCRIPTION

±60V Fault Protected 3V to 5.5V RS485/RS422 Transceiver with Level 4 IEC ESD RS485 Link With Large Ground Loop Voltage

FEATURES

APPLICATIONS

n Protected from Overvoltage Line Faults to ±60V n 3V to 5.5V Supply Voltage n 20Mbps or Low EMI 250kbps Data Rate n ±40kV HBM ESD Interface Pins, ±15kV Other Pins n Enhanced Receiver and Failsafe Noise Immunity n IEC Level 4 ESD and EFT on Interface Pins n Extended Common Mode Range: ±25V n Guaranteed Failsafe Receiver Operation n High Input Impedance Supports 224 Nodes n MP-Grade Option Available (–55°C to 125°C) n Fully Balanced Differential Receiver Thresholds for Low Duty Cycle Distortion n Current Limited Drivers and Thermal Shutdown n Compliant with TIA/EIA-485-A n Pin Compatible with LTC2862 and LT®1785 n Available in DFN and Leaded Packages n AEC-Q100 Qualified for Automotive Applications (LTC2862A#W) n Supervisory Control and Data Acquisition (SCADA) n Industrial Control and Instrumentation Networks n Automotive and Transportation Electronics n Building Automation, Security Systems and HVAC n Medical Equipment n Lighting and Sound System Control LTC2862A-1 Receiving 10Mbps ±200mV Differential Signal with 1MHz ±25V Common Mode Sweep PART NUMBER DUPLEX ENABLES MAX DATA RATE (bps) LTC2862A-1 HALF YES 20M LTC2862A-2 HALF YES 250k The LT C®2862A is a low power , 20Mbps or 250kbps RS485/ RS422 transceiver operating on 3V to 5.5V supplies with ±60V overvoltage fault protection on the interface pins during all modes of operation, including power-down. Improvements were made to the LTC2862 for greater ro- bustness and signal integrity: ±40kV HBM and Level 4 IEC ESD protection on the interface pins; increased resistance to electrical overstress; increased receiver noise immunity; additional receiver noise filtering on the LTC2862A-2; and an improved failsafe function optimized for high speed in the LTC2862A-1 and noise rejection in the LTC2862A-2. Low EMI slew rate limited data transmission is available in the 250kbps LTC2862A-2 option, while the LTC2862A-1 operates to 20Mbps. Extended ±25V input common mode range and full fail - safe operation improve data communication reliability in electrically noisy environments and in the presence of large ground loop voltages. All registered trademarks and trademarks are the property of their respective owners. PRODUCT SELECTION GUIDE GND1 GND2 2862A TA01a RO1 RE1 DE1 DI1 VCC1 L TC2862A L TC2862A VCC2 RO2 RE2 DE2 DI2D D R R V GROUND LOOP ≤25V PEAK A,B 50V/DIV A– B 0.5V/DIV 100ns/DIV 2862A TA01b RO 5V/DIV RO A,B A– B

Rev. A For more information www.analog.com ABSOLUTE MAXIMUM RATINGS ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2862ACS8-1#PBF LTC2862ACS8-1#TRPBF 2862A1 8-Lead (150mil) Plastic SO 0°C to 70°C LTC2862AIS8-1#PBF LTC2862AIS8-1#TRPBF 2862A1 8-Lead (150mil) Plastic SO –40°C to 85°C LTC2862AHS8-1#PBF LTC2862AHS8-1#TRPBF 2862A1 8-Lead (150mil) Plastic SO –40°C to 125°C LTC2862AMPS8-1#PBF LTC2862AMPS8-1#TRPBF 2862A1 8-Lead (150mm) Plastic SO –55°C to 125°C LTC2862ACS8-2#PBF LTC2862ACS8-2#TRPBF 2862A2 8-Lead (150mil) Plastic SO 0°C to 70°C LTC2862AIS8-2#PBF LTC2862AIS8-2#TRPBF 2862A2 8-Lead (150mil) Plastic SO –40°C to 85°C LTC2862AHS8-2#PBF LTC2862AHS8-2#TRPBF 2862A2 8-Lead (150mil) Plastic SO –40°C to 125°C LTC2862AMPS8-2#PBF LTC2862AMPS8-2#TRPBF 2862A2 8-Lead (150mm) Plastic SO –55°C to 125°C LTC2862ACDD-1#PBF LTC2862ACDD-1#TRPBF LGYK 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C LTC2862AIDD-1#PBF LTC2862AIDD-1#TRPBF LGYK 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC2862AHDD-1#PBF LTC2862AHDD-1#TRPBF LGYK 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LTC2862ACDD-2#PBF LTC2862ACDD-2#TRPBF LGYM 8-Lead (3mm × 3mm) Plastic DFN 0°C to 70°C LTC2862AIDD-2#PBF LTC2862AIDD-2#TRPBF LGYM 8-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C LTC2862AHDD-2#PBF LTC2862AHDD-2#TRPBF LGYM 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C Supply Voltages Operating Ambient Temperature Range (Note 4) PIN CONFIGURATION LTC2862A-1, LTC2862A-2 LTC2862A-1, LTC2862A-2 TOP VIEW VCC B A GND RO RE DE DI S8 PACKAGE 8-LEAD (150mil) PLASTIC SO TJMAX = 150°C, θJA = 120°C/W, θJC = 39°C/W TOP VIEW DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN EXPOSED PAD (PIN 9) CONNECT TO PCB GND TJMAX = 150°C, θJA = 43°C/W, θJC = 5.5°C/W 1RO RE DE DI VCC B A GND (Note 1)

Rev. AFor more information www.analog.com ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE AUTOMOTIVE PRODUCTS** LTC2862AIS8-1#WPBF LTC2862AIS8-1#WTRPBF 2862A1 8-Lead (150mil) Plastic SO –40°C to 85°C LTC2862AIS8-2#WPBF LTC2862AIS8-2#WTRPBF 2862A1 8-Lead (150mil) Plastic SO –40°C to 85°C LTC2862AHS8-1#WPBF LTC2862AHS8-1#WTRPBF 2862A1 8-Lead (150mil) Plastic SO –40°C to 125°C LTC2862AHS8-2#WPBF LTC2862AHS8-2#WTRPBF 2862A1 8-Lead (150mil) Plastic SO –40°C to 125°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. **Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.

ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supplies VCC Primary Power Supply l 3 5.5 V ICCS Supply Current in Shutdown Mode (C-, I-Grade) DE = 0V, RE = VCC l 0 10 µA Supply Current in Shutdown Mode (H-, MP-Grade) DE = 0V, RE = VCC l 0 40 µA ICCTR Supply Current with Both Driver and Receiver Enabled (LTC2862A-1) No Load, DE = VCC, RE = 0V l 1.1 1.6 mA ICCR Supply Current with Receiver Enabled (LTC2862A-1) No Load, DE = RE = 0V l 1.0 1.4 mA ICCTRS Supply Current with Both Driver and Receiver Enabled (LTC2862A-2) No Load, DE = VCC, RE = 0V l 3.5 8 mA ICCRS Supply Current with Receiver Enabled (LTC2862A-2) No Load, DE = RE = 0V l 1.3 1.8 mA Driver |VOD| Differential Driver Output Voltage R = ∞ (Figure 1) l 1.5 3 VCC V R = 27Ω (Figure 1) l 1.5 2 5 V R = 50Ω (Figure 1) l 2 2.3 VCC V Δ|VOD| Change in Magnitude of Driver Differential Output Voltage R = 27Ω or 50Ω (Figure 1) l 0 0.2 V VOC Driver Common-Mode Output Voltage R = 27Ω or 50Ω (Figure 1) l 2 3 V Δ|VOC| Change in Magnitude of Driver Common-Mode Output Voltage R = 27Ω or 50Ω (Figure 1) l 0 0.2 V IOSD Maximum Driver Short-Circuit Current –60V ≤ (A or B) ≤ 60V (Figure 2) l ±150 ±250 mA Receiver IIN Receiver Input Current (A, B) VCC = 0V or 3.3V, VIN = 12V (Figure 3) l 143 µA VCC = 0V or 3.3V, VIN = –7V (Figure 3) l –100 µA The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise noted. (Note 2)

Rev. A For more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS RIN Receiver Input Resistance 0 ≤ VCC ≤ 5.5V, VIN = –25V or 25V (Figure 3) 112 kΩ VCM Receiver Common Mode Input Voltage (A + B)/2 l –25 25 V VTH+ Positive Differential Input Signal Threshold Voltage (A – B) –25V ≤ VCM ≤ 25V l 125 200 mV VTH– Negative Differential Input Signal Threshold Voltage (A – B) –25V ≤ VCM ≤ 25V l –200 –125 mV ΔVTH Differential Input Signal Hysteresis (VTH+ – VTH–) VCM = 0V 250 mV VTFS Differential Input Failsafe Threshold Voltage –25V ≤ VCM ≤ 25V l –200 –75 –10 mV ΔVTFS Differential Input Failsafe Hysteresis (VTFS – VTH–) VCM = 0V 50 mV VOH Receiver Output High Voltage I(RO) = –3mA (Sourcing) l VCC –0.4V VCC –0.2V V VOL Receiver Output Low Voltage I(RO) = 3mA (Sinking) l 0.2 0.4 V IOZR Receiver Three-State (High Impedance) Output Current on RO RE = High, VCC = 5V, RO = 0V or VCC l –32 5 µA IOSR Receiver Short-Circuit Current RE = Low, RO = 0V or VCC l ±20 mA CIN Input Capacitance (A and B) (Note 5) 50 pF Logic VTH Input Threshold Voltage (DE, DI, RE) 3.0 ≤ VCC ≤ 5.5V l 0.33 • VCC 0.67 • VCC V IINL Logic Input Current (DE, DI, RE) 0 ≤ VIN ≤ VCC l 0 ±5 µA ESD (Note 5) ESD Protection Level of Interface Pins (A,B), Powered or Unpowered Human Body Model, A or B to GND, VCC, B or A, 1μF Between VCC and GND ±40kV kV IEC 61000-4-2 ESD Level 4, Contact, 1μF Between VCC and GND ±8kV kV ESD Protection Level of All Other Pins (RO, RE, DE, DI, VCC, GND) Human Body Model ±15kV kV ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise noted. (Note 2)

Rev. AFor more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Driver – High Speed (LTC2862A-1) fMAX Maximum Data Rate (Note 3) l 20 Mbps tPLHD, tPHLD Driver Input to Output RDIFF = 54Ω, CL = 100pF (Figure 4) l 25 50 ns ΔtPD Driver Input to Output Difference |tPLHD – tPHLD| RDIFF = 54Ω, CL = 100pF (Figure 4) l 2 5 ns tSKEWD Driver Output A to Output B RDIFF = 54Ω, CL = 100pF (Figure 4) l ±10 ns tRD, tFD Driver Rise or Fall Time RDIFF = 54Ω, CL = 100pF (Figure 4) l 4 15 ns tZLD, tZHD Driver Enable Time RL = 27Ω, CL = 100pF, RE = 0V (Figure 5) l 25 50 ns tLZD, tHZD Driver Disable Time RL = 27Ω, CL = 100pF, RE = 0V (Figure 5) l 45 75 ns tZHSD, tZLSD Driver Enable from Shutdown RL = 27Ω, CL = 100pF, RE = High (Figure 5) l 5 10 µs tSHDND Time to Shutdown RL = 27Ω, CL = 100pF, RE = High (Figure 5) l 50 90 ns Driver – Slew Rate Limited (LTC2862A-2) fMAXS Maximum Data Rate (Note 3) l 250 kbps tPLHDS, tPHLDS Driver Input to Output RDIFF = 54Ω, CL = 100pF (Figure 4) l 850 1500 ns ΔtPDS Driver Input to Output Difference |tPLHDS – tPHLDS| RDIFF = 54Ω, CL = 100pF (Figure 4) l 10 150 ns tSKEWDS Driver Output A to Output B RDIFF = 54Ω, CL = 100pF (Figure 4) l ±500 ns tRDS, tFDS Driver Rise or Fall Time RDIFF = 54Ω, CL =100pF (Figure 4) l 500 800 1200 ns tZLDS, tZHDS Driver Enable Time RL = 27Ω, CL = 100pF, RE = 0V (Figure 5) l 400 800 ns tLZDS, tHZDS Driver Disable Time RL = 27Ω, CL = 100pF, RE = 0V (Figure 5) l 45 75 ns tZHSDS, tZLSDS Driver Enable from Shutdown RL = 27Ω, CL = 100pF, RE = High (Figure 5) l 6 11 µs tSHDNDS Time to Shutdown RL = 27Ω, CL = 100pF, RE = High (Figure 5) l 50 90 ns Receiver tPLHR, tPHLR Receiver Input to Output (LTC2862A-1) CL = 15pF, V CM = 0V, |VAB| = 1.5V, tR and tF < 4ns (Figure 6) l 50 65 ns tPLHRS, tPHLRS Receiver Input to Output (LTC2862A-2) CL = 15pF, V CM = 0V, |VAB| = 1.5V, tR and tF < 4ns (Figure 6) l 400 700 ns tSKEWR Differential Receiver Skew |tPLHR – tPHLR| (LTC2862A-1) CL = 15pF (Figure 6) l 1 5 ns tSKEWRS Differential Receiver Skew |tPLHRS – tPHLRS| (LTC2862A-2) CL = 15pF (Figure 6) l 5 30 ns tPFSN Failsafe Enter Delay (LTC2862A-1) CL = 15pF, VCM = 0V, |VAB| = 1.5V, tR and tF < 4ns (Figure 8) l 80 110 ns tPFSNS Failsafe Enter Delay (LTC2862A-2) CL = 15pF, VCM = 0V, |VAB| = 1.5V, tR and tF < 4ns (Figure 8) l 1.5 2.3 µs SWITCHING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise noted. (Note 2)

Rev. A For more information www.analog.com Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. Note 3: Maximum data rate is guaranteed by other measured parameters and is not tested directly. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 150ºC when overtemperature protection is active. Continuous operation above the specified maximum operating temperature may result in device degradation or failure. Note 5: Not tested in production. SWITCHING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tPFSX Failsafe Exit Delay (LTC2862A-1) CL = 15pF, VCM = 0V, |VAB| = 1.5V, tR and tF < 4ns (Figure 8) l 45 60 ns tPFSXS Failsafe Exit Delay (LTC2862A-2) CL = 15pF, VCM = 0V, |VAB| = 1.5V, tR and tF < 4ns (Figure 8) l 0.7 1.3 µs tRR, tFR Receiver Output Rise or Fall Time CL = 15pF (Figure 6) l 3 6 ns tZLR, tZHR Receiver Enable Time RL = 500Ω, CL = 15pF, DE = High (Figure 7) l 18 30 ns tLZR, tHZR Receiver Disable Time RL = 500Ω, CL = 15pF, DE = High (Figure 7) l 29 40 ns tZHSR, tZLSR Receiver Enable from Shutdown RL = 500Ω, CL = 15pF, DE = High (Figure 7) l 5 10 µs tSHDNR Time to Shutdown RL = 500Ω, CL = 15pF, DE = High (Figure 7) l 24 40 ns

Rev. AFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Driver Output Short-Circuit Current vs Voltage Driver Output Low/High Voltage vs Output Current Driver Differential Output Voltage vs Temperature Supply Current vs Data Rate Driver Skew vs Temperature Driver Propagation Delay vs Temperature TA = 25°C, VCC = 3.3V, unless otherwise noted. Supply Current vs TemperatureSupply Current vs VCC OUTPUT CURRENT (mA) 0.0 DRIVER OUTPUT VOLTAGE (V) 2.0 1.5 1.0 0.5 2.5 3.0 3.5 10 20 30 40 2862A G07 VOH VOL TEMPERATURE (°C) –50 1.5 VOD (V) 1.9 1.7 2.1 2.3 2.5 0 50 100 2862A G08 150 RDIFF = 100/uni03A9 RDIFF = 54/uni03A9 TEMPERATURE (°C) DRIVER SKEW (SLEW LIMITED) (ns) –50 –1.5DRIVER SKEW (NON SLEW LIMITED) (ns) 0.0 –0.5 –1.0 0.5 1.0 1.5 0 50 100 2862A G04 150 100 120 SLEW LIMITED NON SLEW LIMITED RDIFF = 54/uni03A9 CL = 100pF TEMPERATURE (°C) DRIVER DELAY (SLEW LIMITED) (ns) –50

20 DRIVER DELAY (NON SLEW LIMITED) (ns)

RDIFF = 54/uni03A9 CL = 100pF VCC (V) 3.0 SUPPLY CURRENT (mA) 2.0 1.5 1.0 0.5 2.5 3.0 3.5 4.5 3.5 4.0 4.5 5.0 2862A G01 5.5

4.0 ICCTRS

SUPPLY CURRENT (mA) DATA RATE (SLEW LIMITED) (kbps) 30 35 DATA RATE (NON SLEW LIMITED) (Mbps) 40 45 50 55 2862A G03 100 200 150 250 SLEW LIMITED NON SLEW LIMITED RDIFF = 54/uni03A9 CL = 100pF OUTPUT VOLTAGE (V) –60 –200 OUTPUT CURRENT (mA) –50 –100 –150 150 100 200 –40 0–20 20 40 2862A G06 OUTPUT LOW OUTPUT HIGH TEMPERATURE (°C) –50

0.1 SUPPLY CURRENT (µA)

1000 ICCTR

Receiver Output Voltage vs Output Current (Source and Sink) OUTPUT CURRENT (ABSOLUTE VALUE) (mA) 0.0 0.0 RECEIVER OUTPUT VOLTAGE (V) 3.0 2.0 1.0 4.0 5.0 6.0 2.0 4.0 6.0 2862A G09 8.0 VCC = 5.5V VCC = 3.3V VCC = 3V TO 5.5V

Rev. A For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, VCC = 3.3V, unless otherwise noted. T ransmitter Propagation Delay vs Temperature (LTC2862A-1) T ransmitter Propagation Delay vs Temperature (LTC2862A-2) Failsafe Enter and Exit Delay vs Temperature (LTC2862A-1) Failsafe Enter and Exit Delay vs Temperature (LTC2862A-2) Receiver Propagation Delay vs Temperature (LTC2862A-1) Receiver Propagation Delay vs Temperature (LTC2862A-2) t PHLD t PLHD TEMPERATURE (°C) –50 –25 100 125 TRANSMITTER DELAY (ns) 2862A G10 t PHLDS t PLHDS TEMPERATURE (°C) –50 –25 100 125 600 620 640 660 680 700 720 740 TRANSMITTER DELAY (ns) 2862A G11 t PFSN t PFSX TEMPERATURE (°C) –50 –25 100 125 100 FAILSAFE DELAY (ns) 2862A G12 t PFSNS t PFSXS TEMPERATURE (°C) –50 –25 100 125 0.6 0.8 1.0 1.2 1.4 1.6 FAILSAFE DELAY (µs) 2862A G13 t PLHR t PHLR TEMPERATURE (°C) –50 –25 100 125 RECEIVER DELAY (ns) 2862A G14 t PHLRS t PLHRS TEMPERATURE (°C) –50 –25 100 125 300 325 350 375 400 425 450 475 RECEIVER DELAY (ns) 2862A G15

Rev. AFor more information www.analog.com PIN FUNCTIONS PIN NAME PIN NUMBER DESCRIPTION RO 1 Receiver Output. If the receiver output is enabled (RE low) and A–B > 200mV, then RO will be high. If A–B < –200mV, then RO will be low. If the receiver inputs are open, shorted, or terminated without a signal, RO will be high. Integrated 250kΩ pull-up to VCC. RE 2 Receiver Enable. A low input enables the receiver. A high input forces the receiver output into a high impedance state. If RE is high with DE low, the part will enter a low power shutdown state. DE 3 Driver Enable. A high input on DE enables the driver. A low input will force the driver outputs into a high impedance state. If DE is low with RE high, the part will enter a low power shutdown state. DI 4 Driver Input. If the driver outputs are enabled (DE high), then a low on DI forces the driver noninverting output A low and inverting output B high. A high on DI, with the driver outputs enabled, forces the driver noninverting output A high and inverting output B low. GND 5 Ground. Exposed Pad 9 Connect the exposed pad on the DFN packages to GND. B 7 Inverting Receiver Input and Inverting Driver Output. Impedance is ~112kΩ in receive mode or unpowered. A 6 Noninverting Receiver Input and Noninverting Driver Output. Impedance is ~112kΩ in receive mode or unpowered. VCC 8 Power Supply. 3V < VCC < 5.5V. Bypass with 1µF ceramic capacitor to GND for best ESD performance. LTC2862A LOGIC INPUTS MODE A, B RO DE RE 0 0 Receive RIN Active 0 1 Shutdown RIN High-Z* 1 0 Transceive Active Active 1 1 Transmit Active High-Z* * 250kΩ pull-up to VCC. FUNCTION TABLE

Rev. AFor more information www.analog.com APPLICATIONS INFORMATION ±60V Fault Protection The LTC2862A is an improved overvoltage fault-tolerant RS485/RS422 transceiver that operates from 3V to 5.5V power supplies. Industrial installations may encounter common mode voltages between nodes far greater than the –7V to 12V range specified by the RS485 standards. Standard RS485 transceivers can be damaged by voltages above their typical absolute maximum ratings of –8V to 12.5V. The limited overvoltage tolerance of standard RS485 transceivers makes implementation of effective external protection networks difficult without interfering with proper data network performance within the –7V to 12V region of RS485 operation. Replacing standard RS485 transceivers with the rugged LTC2862A devices may eliminate field failures due to overvoltage faults without using costly external protection devices. The ±60V fault protection of the LTC2862A is achieved by using a high-voltage BiCMOS integrated circuit technology. The naturally high breakdown voltage of this technology provides protection in powered-off and high-impedance conditions. The driver outputs use a progressive foldback current limit design to protect against overvoltage faults while still allowing high current output drive. The LTC2862A is protected from ±60V faults even with the loss of GND or V CC (GND open faults not tested in production). Additional precautions must be taken in the case of VCC present and GND open. The LTC2862A chip will protect itself from damage, but the chip ground current may flow out through the ESD diodes on the logic I/O pins and into associated circuitry. The system designer should examine the susceptibility of the associated circuitry to damage if the condition of a GND open fault with V CC present is anticipated. The high voltage rating of the LTC2862A makes it simple to extend the overvoltage protection to higher levels using external protection components. Compared to lower voltage RS485 transceivers, external protection devices with higher breakdown voltages can be used, so as not to interfere with data transmission in the presence of large common mode voltages. The Typical Applications section shows a protection network against faults up to ±360V peak, while still maintaining the extended ±25V common mode range on the signal lines. ±25V Extended Common Mode Range To further increase the reliability of operation and extend functionality in environments with high common mode voltages due to electrical noise or local ground potential differences due to ground loops, the LTC2862A features an extended common mode operating range of –25V to 25V. This extended common mode range allows the LTC2862A to transmit and receive under conditions that would cause data errors and possible device damage in competing products. ±40kV ESD Protection The LTC2862A features exceptionally robust ESD protection. The transceiver interface pins (A,B) feature protection to ±40kV HBM with respect to GND, VCC (with a 1µF capacitor to GND), A or B without latchup or damage, during all modes of operation or while unpowered. All the other pins are protected to ±15kV HBM to make this a component capable of reliable operation under severe environmental conditions. Level 4 IEC ESD and EFT Protection The improved ESD protection of the LTC2862A provides a high level of protection in the IEC ESD and EFT (Electrical Fast T ransient) tests. The IEC ESD stress exceeds that of the HBM test in peak current, amplitude, and rise time, while the EFT test provides a prolonged repetitive stress. Combined with the HBM test, the IEC tests help ensure that the LTC2862A is robust under a wide range of real world hazards. The LTC2862A passes the following tests on the A, B pins:

IEC 61000-4-2 Edition 2.0 2008-12 ESD Level 4: ±8kV contact (A or B to GND, direct discharge to bus pins with transceiver and protection circuit mounted on a test card with a low impedance ground discharge path from board GND to ESD gun return lead, per Figure 4 of the standard)
IEC 61000-4-4 Second Edition 2004-07 EFT Level 4: ±5kV (line to GND, 5kHz repetition rate, 15ms burst duration, 60 second test duration, discharge coupled to bus pins through 100pF capacitor per paragraph 7.3.2 of the standard)

the LTC2862A package, resulting in a failed chip. 60V. The maximum current in a fault condition is ±250mA. less than ±15mA for fault voltages over ±40V. enabled, the state of RO will reflect the polarity of (A–B). input signal levels and slow input edge rates. is terminated but not driven by an active transmitter. Figure 9. Duty Cycle of Balanced Receiver with ±200mV

Rev. AFor more information www.analog.com The LTC2862A uses fully symmetric positive and negative receiver thresholds VTH– and VTH+ (typically ±125mV) to maintain good duty cycle symmetry at low signal levels. The failsafe operation is performed with a window comparator to determine when the differential input voltage falls above the VTFS failsafe threshold (typically –75mV) but below the V TH+ threshold. If this condition persists for more than about 40ns for the LTC2862A-1 or 1.2µs for the LTC2862A-2 the failsafe condition is asserted and the RO pin is forced to the logic 1 state. This circuit provides full failsafe operation and a large dynamic signal hysteresis of ~250mV between VTH– and VTH+ with no negative impact to receiver duty cycle symmetry, as shown in Figure 9. The input signal in Figure 9 was obtained by driving a 10Mbps RS485 signal through 1000 feet of cable, thereby attenuating it to a ±200mV signal with slow rise and fall times. Good duty cycle symmetry is observed at RO despite the degraded input signal. The failsafe circuit has been enhanced with noise filtering to exit the failsafe state. In the absence of noise filtering, a noise transient that momentarily forces the A-B differential voltage below the VTH– receiver threshold will cause the RO output to go low, which may be interpreted as a false start character by the microcontroller. The LTC2862A receiver reduces these false signals by low pass filtering the signal to exit the failsafe state. The noise filtering in the failsafe circuit of the LTC2862A-2 is much greater than in the LTC2862A-1, commensurate with its lower data rate. For example, the LTC2862A-1 exits the failsafe state when a –1V differential pulse of about 3ns duration is applied, while the LTC2862A-2 requires a –1V pulse of about 400ns duration to exit the failsafe state. (The minimum pulse widths to enter or exit the failsafe state are not tested in production, but the underlying filtering is reflected in the tFSN, tFSX, tFSNS, and tFSXS measurements). Enhanced Receiver Noise Immunity An additional benefit of the fully symmetric receiver thresholds is enhanced receiver noise immunity. The differential input signal must go above the positive threshold to register as a logic 1 and go below the negative threshold to register as a logic 0. This provides a hysteresis of 250mV (typical) at the receiver inputs for any valid data signal. (An invalid data condition such as a DC sweep of the receiver inputs will produce a different observed hysteresis due to the activation of the failsafe circuit.) Competing devices that employ a negative offset of the input threshold voltage generally have a much smaller hysteresis and subsequently have lower receiver noise immunity. The LTC2862A-2 provides additional noise immunity by adding low-pass filtering to the differential signal in its receiver. Commensurate with its maximum data rate of 250kbps, the LTC2862A-2 receiver attenuates high frequency signals above approximately 660kHz. This low- pass filter removes high frequency noise transients that might otherwise be interpreted as data. (High frequency noise filtering is not tested in production, but the underlying filtering is reflected in the tPLHR, tPHLR, tPLHRS, and tPHLRS measurements). RS485 Network Biasing RS485 networks are usually biased with a resistive divider to generate a differential voltage of ≥200mV on the data lines, which establishes a logic 1 state (the idle state) when all the transmitters on the network are disabled. The values of the biasing resistors are not fixed, but depend on the number and type of transceivers on the line and the number and value of terminating resistors. Therefore, the values of the biasing resistors must be customized to each specific network installation, and may change if nodes are added to or removed from the network. The internal failsafe feature of the LTC2862A eliminates the need for external network biasing resistors provided they are used in a network of transceivers with similar internal failsafe features. The LTC2862A transceivers will operate correctly on biased, unbiased, or under-biased networks. Hi-Z State The receiver output is internally driven high (to V CC) or low (to GND) with no external pull-up needed. When the receiver is disabled the RO pin becomes Hi-Z with a 250k pull-up resistor to VCC. APPLICATIONS INFORMATION

Rev. A For more information www.analog.com High Receiver Input Resistance The bus receiver input load from A or B to GND is less than one-seventh unit load, permitting a total of 224 receivers per system without exceeding the RS485 receiver loading specification. The input load of the receiver is unaffected by enabling/disabling the receiver or by powering/unpowering the part. Supply Current The unloaded static supply currents in these devices are low — typically 1.1mA for non slew limited devices and 3.5mA for slew limited devices. In applications with resistively terminated cables, the supply current is dominated by the driver load. For example, when using two 120Ω terminators with a differential driver output voltage of 2V, the DC load current is 33mA, which is sourced by the positive voltage supply. Power supply current increases with toggling data due to capacitive loading and this term can increase significantly at high data rates. A plot of the supply current vs data rate is shown in the Typical Performance Characteristics of this data sheet. During fault conditions with a positive voltage larger than the supply voltage applied to the transmitter pins, or during transmitter operation with a high positive common mode voltage, positive current of up to 80mA may flow from the transmitter pins back to VCC. If the system power supply or loading cannot sink this excess current, a 5.6V 1W 1N4734 Zener diode may be placed between VCC and GND to prevent an overvoltage condition on VCC. The LTC2862A contains a supply undervoltage lockout circuit that enables the transmitter and receiver outputs when VCC exceeds ~2.7V and disables the transmitter and receiver outputs when VCC falls below ~2.5V. When the LTC2862A is unpowered, the logic inputs (DE, DI, RE) are high impedance for voltages > 0V. Each input has a diode clamp to GND that will conduct if a negative voltage sufficient to forward bias the diode (~ –0.6V at 25°C) is applied to the pad. The RO output contains a CMOS driver with parasitic diodes to GND and VCC. The diode to GND will conduct if forward biased by a negative voltage below GND, while the diode to VCC will conduct if forward biased by a positive voltage above VCC. If VCC is low, this APPLICATIONS INFORMATION will result in the RO line being clamped to approximately 0.6V above VCC. The impedance of the logic inputs and the RO output are not tested with the LTC2862A unpowered. Shutdown Mode Delay The LTC2862A features a low power shutdown mode that is entered when both the driver and the receiver are simultaneously disabled (pin DE low and RE high). A shutdown mode delay of approximately 250ns (not tested in production) is imposed after this state is received before the chip enters shutdown. If either DE goes high or RE goes low during this delay, the delay timer is reset and the chip does not enter shutdown. This reduces the chance of accidentally entering shutdown if DE and RE are driven in parallel by a slowly changing signal or if DE and RE are driven by two independent signals with a timing skew between them. This shutdown mode delay does not affect the outputs of the transmitter and receiver, which start to switch to the high impedance state upon the reception of their respec- tive disable signals as defined by the parameters tSHDND and tSHDNR. The shutdown mode delay affects only the time when all the internal circuits that draw DC power from VCC are turned off. High Speed Considerations A ground plane layout with a 0.1µF bypass capacitor placed less than 7mm away from the VCC pin is recommended. The PC board traces connected to signals A/B should be symmetrical and as short as possible to maintain good differential signal integrity. To minimize capacitive effects, the differential signals should be separated by more than the width of a trace and should not be routed on top of each other if they are on different signal planes. Care should be taken to route outputs away from any sensitive inputs to reduce feedback effects that might cause noise, jitter, or even oscillations. The logic inputs have a typical hysteresis of 100mV to provide noise immunity. Fast edges on the outputs can cause glitches in the ground and power supplies which are exacerbated by capacitive loading. If a logic input is held near its threshold (typically VCC/2), a noise glitch from a

Rev. A For more information www.analog.com APPLICATIONS INFORMATION PROFIBUS Compatible Interface PROFIBUS is an RS485-based field bus. In addition to the specifications of TIA/EIA-485-A, the PROFIBUS specification contains additional requirements for cables, interconnects, line termination, and signal levels. The following discussion applies to the PROFIBUS Type A cables with associated connectors and termination. The Type A cable is a twisted pair shielded cable with a characteristic impedance of 135Ω to 165Ω and a loop resistance of < 110Ω/km. The LTC2862A RS485 transceiver may be used in PROFIBUS compatible equipment if the following considerations are implemented. (Please refer to the schematic of the PROFIBUS Compatible Interface in the Typical Applications Section.) 1. The polarity of the PROFIBUS signal is opposite to the polarity convention used in this data sheet. The PRO- FIBUS B wire is driven by a non-inverted signal, while the A wire is driven by an inverted signal. Therefore, it is necessary to swap the output connections from the transceiver . Pin A is connected to the PROFIBUS B wire, and Pin B is connected to the PROFIBUS A wire. 2. Each end of the PROFIBUS line is terminated with a 220Ω resistor between B and A, a 390Ω pull-up resistor between B and V CC, and a 390Ω pull-down resistor between A and GND. This provides suitable termination for the 150Ω twisted pair transmission cable. 3. The peak to peak differential voltage VOD received at the end of a 100m cable with the cable and termina- tions described above must be greater than 4V and less than 7V. The LTC2862A produces signal levels in excess of 7V when driving this network directly. 8.2Ω resistors may be inserted between the A and B pins of the transceiver and the B and A pins of the PROFIBUS cable to attenuate the transmitted signal to meet the PROFIBUS upper limit of 7V while still providing enough drive strength to meet the lower limit of 4V. 4. The LTC2862A transceiver should be powered by a 5% tolerance 5V supply (4.75V to 5.25V) to ensure that the PROFIBUS VOD tolerances are met. Auxiliary Protection for 5kV Surge, 5kV EFT , and 30kV IEC ESD An interface transceiver used in an industrial setting may be exposed to extremely high levels of electrical overstress due to phenomena such as lightning surge, electrical fast transient (EFT) from switching high current inductive loads, and electrostatic discharge (ESD) from the discharge of electrically charged personnel or equipment. Test methods to evaluate immunity of electronic equipment to these phenomena are defined in the IEC standards 61000-4-2, 61000-4-4, and 61000-4-5, which address ESD, EFT, and surge, respectively. The transients produced by the EFT and particularly the surge tests contain much more energy than the ESD transients. The LTC2862A is designed for high robustness against ESD, but the on-chip protection is not able to absorb the energy associated with the 61000-4-5 surge transients. Therefore, a properly designed external protection network is necessary to achieve a high level of surge protection, and can also extend the ESD and EFT performance of the LTC2862A to extremely high levels. In addition to providing surge, EFT and ESD protection, an external network should preserve or extend the ability of the LTC2862A to withstand overvoltage faults, operate over a wide common mode, and communicate at high frequencies. In order to meet the first two requirements, protection components with suitably high conduction voltages must be chosen. A means to limit current must be provided to prevent damage in case a secondary protection device or the ESD cell on the LTC2862A fires and conducts. The capacitance of these components must be kept low in order to permit high frequency communication over a network with multiple nodes. Meeting the requirements for conducting very high energy electrical transients while maintaining high hold-off voltages and low capacitance is a considerable challenge.

Rev. AFor more information www.analog.com A protection network shown in the Typical Applications section (Network for IEC Level 4 Protection Against 5kV Surge, 5kV EFT and 30kV IEC ESD Plus ±360V Overvoltage Protection) meets this challenge. The network provides the following protection:

IEC 61000-4-2 ESD Level 4: ±30kV contact, ±30kV air (line to GND, direct discharge to bus pins with transceiver and protection circuit mounted on a ground referenced test card per Figure 4 of the standard)
IEC 61000-4-4 EFT Level 4: ±5kV (line to GND, 5kHz repetition rate, 15ms burst duration, 60 second test duration, discharge coupled to bus pins through 100pF capacitor per paragraph 7.3.2 of the standard)
IEC 61000-4-5 Surge Level 4: ±5kV (line to GND, line to line, 8/20µs waveform, each line coupled to generator through 80Ω resistor per Figure 14 of the standard) This protection circuit adds only ~8pF of capacitance per line (line to GND), thereby providing an extremely high level of protection without significant impact to the performance of the LTC2862A transceivers at high data rates. APPLICATIONS INFORMATION The gas discharge tubes (GDTs) provide the primary protection against electrical surges. These devices provide a very low impedance and high current carrying capability when they fire, safely discharging the surge current to GND. The transient blocking units (TBUs) are solid state devices that switch from a low impedance pass through state to a high impedance current limiting state when a specified current level is reached. These devices limit the current and power that can pass through to the secondary protection. The secondary protection consists of a bidirectional thyristor, which triggers above 35V to protect the bus pins of the LTC2862A transceiver. The high trigger voltage of the secondary protection maintains the full ±25V common mode range of the receivers. The final component of the network is the metal oxide varistors (MOVs) which are used to clamp the voltage across the TBUs to protect them against fast ESD and EFT transients which exceed the turn-on time of the GDT. The high performance of this network is attributable to the low capacitance of the GDT and thyristor primary and secondary protection devices. The high capacitance MOV floats on the line and is shunted by the TBU, so it contributes no appreciable capacitive load on the signal.

Rev. A For more information www.analog.com Failsafe O Application (Idle State = Logic O) ±60V 20Mbps Level Shifter/Isolator DI GND VCC VCC1 L TC2862A-1 VCC2 ±60V A B R1 = 200k 1%. PLACE R1 RESISTORS NEAR A AND B PINS OF RECEIVER. R2 = 10k C = 47pF , 5%, 50 WVDC. MAY BE OMITTED FOR DATA RATES < 100kbps. DATA IN 1 DATA OUT 1 VCC RO L TC2862A-1 GND C A B 2862A TA03 C D R PROFIBUS Compatible Line Interface TYPICAL APPLICATIONS RO RE DE DI 8.2/uni03A9 2862A TA02 A*R * THE POLARITY OF A AND B IN THIS DATA SHEET IS OPPOSITE THE POLARITY DEFINED BY PROFIBUS. VCC (4.75V TO 5.25V) GND L TC2862A 8.2/uni03A9 390/uni03A9 4VP-P ≤ VOD ≤ 7VP-P UP TO 1500kbps 220/uni03A9 390/uni03A9 B WIRE A WIRE B WIRE A WIRE VCC 390/uni03A9 220/uni03A9 390/uni03A9 VCC 100m 5.5/uni03A9/WIRE VOD D 2862A TA04 RO DE DI RO DE DI BRI1 A “A” “B” GND VCC L TC2862A DI2

Rev. AFor more information www.analog.com PACKAGE DESCRIPTION 3.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 0.40 ±0.10 BOTTOM VIEW—EXPOSED PAD 1.65 ±0.10 (2 SIDES) 0.75 ±0.05 R = 0.125 TYP 2.38 ±0.10 PIN 1 TOP MARK (NOTE 6)

0.200 REF

0.00 – 0.05 (DD8) DFN 0509 REV C 0.25 ±0.05 2.38 ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 1.65 ±0.05 (2 SIDES)2.10 ±0.05 0.50 BSC 0.70 ±0.05 3.5 ±0.05 PACKAGE OUTLINE 0.25 ±0.05

0.50 BSC

8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698 Rev C)

Rev. A For more information www.analog.com PACKAGE DESCRIPTION .016 – .050 (0.406 – 1.270) .010 – .020 0°– 8° TYP .008 – .010 (0.203 – 0.254) SO8 REV G 0212 .053 – .069 (1.346 – 1.752) .014 – .019 (0.355 – 0.483) TYP .004 – .010 (0.101 – 0.254) .050 (1.270) BSC 1 2 3 4 .150 – .157 (3.810 – 3.988) NOTE 3 8 7 6 5 .189 – .197 (4.801 – 5.004) NOTE 3 .228 – .244 (5.791 – 6.197) .245 MIN .160 ±.005 RECOMMENDED SOLDER PAD LAYOUT .045 ±.005 .050 BSC .030 ±.005 TYP INCHES (MILLIMETERS) NOTE: 1. DIMENSIONS IN 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 4. PIN 1 CAN BE BEVEL EDGE OR A DIMPLE 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610 Rev G)

Rev. AFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 06/21 Add automotive grade. 1, 3

Rev. A For more information www.analog.com  ANALOG DEVICES, INC. 2017-2021 www.analog.com RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LT1785, LT1791 ±60V Fault Protected RS485/RS422 Transceivers ±60V Tolerant, ±15kV ESD, 250kbps LTC2863/LTC2864/ LTC2865 ±60V Fault Protected 3V to 5.5V RS485/RS422 T ransceivers ±60V Tolerant, ±15kV ESD, 20Mbps or 250kbps LTC2877 ±60V Rugged PROFIBUS RS485 T ransceivers PROFIBUS IEC 61158-2 Compliant, ±52kV ESD LT M 2885 6500VRMS Isolated RS485/RS422 μModule® T ransceiver + Power 6500VRMS for 1 Minute, Isolated Power: 5V at 150mA LTC2850/LTC2851/ LTC2852 3.3V 20Mbps ±15kV RS485 Transceivers Up to 256 T ransceivers Per Bus LTC2854, LTC2855 3.3V 20Mbps RS485 Transceivers with Integrated Switchable Termination ±25kV ESD (LTC2854), ±15kV ESD (LTC2855) LTC2856-1 Family 5V 20Mbps and Slew Rate Limited RS485 Transceivers ±15kV ESD LTC2859, LTC2861 5V 20Mbps RS485 Transceivers with Integrated Switchable Termination ±15kV ESD LTC1535 Isolated RS485 Transceiver 2500VRMS Isolation, Requires External T ransceiver LTM2881 Complete 3.3V Isolated RS485/RS422 μModule Transceiver + Power 2500VRMS Isolation with Integrated Isolated DC/DC Converter , 1W Power , Low EMI, ±15kV ESD, 30kV/µs Common Mode T ransient Immunity Network for IEC Level 4 Protection Against 5kV Surge, 5kV EFT and 30kV IEC ESD Plus ±360V Overvoltage Protection 2862A TA05 VCC DE SCRGDT SCR A B DI L TC2862A-1 GDT : BOURNS 2031-42T-SM; 420V GAS DISCHARGE TUBE TBU: BOURNS TBU-CA085-300-WH; 850V TRANSIENT BLOCKING UNIT MOV: BOURNS MOV-7D391K; 390V 25J METAL OXIDE VARISTOR SCR: BOURNS TISP4P035L1NR-S; 35V BIDIRECTIONAL THYRISTOR RO D R GND RE MOV MOV TBU TBU GDT GND RS485 A (EXTERNAL) RS485 B (EXTERNAL)

Summary

±60V Fault Protected 3V to 5.5V RS485/RS422 Transceiver with Level 4 IEC ESD Rev. A

Description