LTM2882 Dual Isolated RS232 μModule Transceiver + Power
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 22
Technical content
For more information www.linear .com/L TM2882 All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION
DESCRIPTION
µModule Transceiver + Power The LT M®2882 is a complete galvanically isolated dual RS232 µModule® (micromodule) transceiver. No external components are required. A single 3.3V or 5V supply powers both sides of the interface through an integrated, isolated DC/DC converter. A logic supply pin allows easy interfacing with different logic levels from 1.62V to 5.5V, independent of the main supply. Coupled inductors and an isolation power transformer provide 2500VRMS of isolation between the line transceiver and the logic interface. This device is ideal for systems with different grounds, allowing for large common mode voltages. Uninterrupted communication is guaranteed for common mode transients greater than 30kV/μs. This part is compatible with the TIA/EIA-232-F standard. Driver outputs are protected from overload and can be shorted to ground or up to ±15V without damage. An auxiliary isolated digital channel is available. This channel allows configuration for half-duplex operation by control- ling the DE pin. Enhanced ESD protection allows this part to withstand up to ±10kV (human body model) on the transceiver interface pins to isolated supplies and across the isolation barrier to logic supplies without latchup or damage. Isolated Dual RS232 µModule T ransceiver
FEATURES
APPLICATIONS
n RS 232 T ransceiver: 2500V RMS for 1 Minute n UL -CSA Recognized File #E151738 n CSA Component Acceptance Notice 5A n Isolated DC Power: 5V at Up to 200mA n No External Components Required n 1.62V to 5.5V Logic Supply for Flexible Digital Interfacing n High Speed Operation 1Mbps for 250pF/3kΩ Load 250kbps for 1nF/3kΩ Load 100kbps for 2.5nF/3kΩ TIA/EIA-232-F Load n 3.3V (LTM2882-3) or 5V (LTM2882-5) Operation n No Damage or Latchup to ±10kV HBM ESD on Isolated RS232 Interface or Across Isolation Barrier n High Common Mode T ransient Immunity: 30kV/μs n Maximum Continuous Working Voltage: 560VPEAK n T rue RS232 Compliant Output Levels n 15mm × 11.25mm BGA and LGA Packages n Isolated RS232 Interface n Industrial Communication n Test and Measurement Equipment n Breaking RS232 Ground Loops 1Mbps Operation
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3.3V (L TM2882-3) 5V (L TM2882-5) VL VCC GND GND2 ISOLATION BARRIER ONOFF VCC2 DE AVAILABLE CURRENT: 150mA (L TM2882-5) 100mA (L TM2882-3) 400ns/DIV DRIVER OUTPUTS TIED TO RECEIVER INPUTS TOUT LOAD = 250pF + RIN ROUT LOAD = 150pF 10V/DIV 5V/DIV TIN T1OUT/R1IN T2OUT/R2IN 5V/DIV
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For more information www.linear .com/L TM2882 PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS Logic Inputs Logic Outputs Driver Output Voltage Receiver Input Voltage Operating Temperature Range (Note 4) LT M2882H 0°C ≤ TA ≤ 105°C Maximum Internal Operating Temperature Storage Temperature Range Peak Package Body Reflow Temperature (Note 1) VCC GND GND2 A B C D E F G H I J K L 1 2 3 4 5 6 7 8 LGA PACKAGE 32-PIN (15mm × 11.25mm × 2.8mm) T JMAX = 125°C, θJA = 29°C/W , θJCtop = 27.9°C/W , θJCbottom = 18°C/W , θJB = 22.7°C/W , WEIGHT = 1.1g BGA PACKAGE 32-PIN (15mm × 11.25mm × 3.42mm) TJMAX = 125°C, θJA = 30°C/W , θJCtop = 27.8°C/W , θJCbottom = 19.3°C/W , θJB = 24°C/W , WEIGHT = 1.1g TOP VIEW VCC2 VLON DIN T1INR1OUTT2IN DEDOUTT1OUTR1INT2OUTR2IN R2OUT
For more information www.linear .com/L TM2882 ORDER INFORMATION PART NUMBER INPUT VOL TAGE PAD OR BALL FINISH PART MARKING PACKAGE TYPE MSL RATING TEMPERATURE RANGEDEVICE FINISH CODE LTM2882CY-3#PBF 3V to 3.6V SAC305 (RoHS) LTM2882Y-3 e1 BGA 0°C to 70°C LTM2882IY-3#PBF –40°C to 85°C LTM2882HY-3#PBF –40°C to 105°C LTM2882CY-5#PBF 4.5V to 5.5V LTM2882Y-5 0°C to 70°C LTM2882IY-5#PBF –40°C to 85°C LTM2882HY-5#PBF –40°C to 105°C LTM2882CV-3#PBF 3V to 3.6V Au (RoHS) LTM2882V-3 e4 LGA 0°C to 70°C LTM2882IV-3#PBF –40°C to 85°C LTM2882CV-5#PBF 4.5V to 5.5V LTM2882V-5 0°C to 70°C LTM2882IV-5#PBF –40°C to 85°C Device temperature grade is indicated by a label on the shipping container . Pad or ball finish code is per IPC/JEDEC J-STD-609.
- Terminal Finish Part Marking: www.linear .com/leadfree This product is not recommended for second side reflow. For more information, go to: www.linear .com/BGA-assy
- Recommended BGA and LGA PCB Assembly and Manufacturing Procedures: www.linear .com/umodule/pcbassembly
- LGA and BGA Package and T ray Drawings: www.linear .com/packaging This product is moisture sensitive. For more information, go to: www. linear .com/umodule/pcbassembly ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. LTM2882-3 VCC = 3.3V, LTM2882-5 VCC = 5.0V, VL = VCC, and GND = GND2 = 0V, ON = VL unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supplies VCC Input Supply Range LTM2882-3 l 3.0 3.3 3.6 V LTM2882-5 l 4.5 5.0 5.5 V VL Logic Supply Range l 1.62 5.5 V ICC Input Supply Current ON = 0V l 0 10 µA LTM2882-3, No Load l 24 30 mA LTM2882-5, No Load l 17 25 mA VCC2 Regulated Output Voltage, Loaded LTM2882-3 DE = 0V, I LOAD = 100mA l 4.7 5.0 V LTM2882-5 DE = 0V, ILOAD = 150mA l 4.7 5.0 V VCC2(NOLOAD) Regulated Output Voltage, No Load DE = 0, No Load 4.8 5.0 5.35 V Efficiency ICC2 = 100mA, LTM2882-5 (Note 2) 65 % ICC2 Output Supply Short-Circuit Current 200 mA Driver V OLD Driver Output Voltage Low RL = 3kΩ l –5 –5.7 V VOHD Driver Output Voltage High RL = 3kΩ l 5 6.2 V IOSD Driver Short-Circuit Current VT1OUT, VT2OUT = 0V, VCC2 = 5.5V l ±35 ±70 mA IOZD Driver Three-State (High Impedance) Output Current DE = 0V, VT1OUT, VT2OUT = ±15V l ±0.1 ±10 µA http://www.linear.com/product/LTM2882#orderinfo
For more information www.linear .com/L TM2882 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. LTM2882-3 VCC = 3.3V, LTM2882-5 VCC = 5.0V, VL = VCC, and GND = GND2 = 0V, ON = VL unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Receiver VIR Receiver Input Threshold Input Low l 0.8 1.3 V Input High l 1.7 2.5 V VHYSR Receiver Input Hysteresis l 0.1 0.4 1.0 V RIN Receiver Input Resistance –15V ≤ (VR1IN, VR2IN) ≤ 15V l 3 5 7 kΩ Logic V ITH Logic Input Threshold Voltage ON, T1IN, T2IN, DIN = 1.62V ≤ V L < 2.35V l 0.25•V L 0.75•V L V ON, T1IN, T2IN, DIN = 2.35V ≤ VL ≤ 5.5V l 0.4 0.67•VL V DE l 0.4 0.67•VCC2 V IINL Logic Input Current l ±1 µA VHYS Logic Input Hysteresis T1IN, T2IN, DIN (Note 2) 150 mV VOH Logic Output High Voltage R1OUT, R2OUT ILOAD = –1mA (Sourcing), 1.62V ≤ VL < 3.0V ILOAD = –4mA (Sourcing), 3.0V ≤ VL ≤ 5.5V l l VL – 0.4 VL – 0.4 V V DOUT , ILOAD = –4mA (Sourcing) l VCC2 – 0.4 V VOL Logic Output Low Voltage R1OUT, R2OUT ILOAD = 1mA (Sinking), 1.62V ≤ VL < 3.0V ILOAD = 4mA (Sinking), 3.0V ≤ VL ≤ 5.5V l l 0.4 0.4 V V DOUT , ILOAD = 4mA (Sinking) l 0.4 V ESD (HBM) (Note 2) RS232 Driver and Receiver Protection (T1OUT, T2OUT, R1IN, R2IN) to (V CC2, GND2) ±10 kV (T1OUT, T2OUT, R1IN, R2IN) to (VCC, VL, GND) ±10 kV Isolation Boundary (VCC2, GND2) to (VCC, VL, GND) ±10 kV SWITCHING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. LTM2882-3 VCC = 3.3V, LTM2882-5 VCC = 5.0V, VL = VCC, and GND = GND2 = 0V, ON = VL unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Maximum Data Rate (T1IN to T1OUT, T2IN to T2OUT) RL = 3kΩ, CL = 2.5nF (Note 3) l 100 kbps RL = 3kΩ, CL = 1nF (Note 3) l 250 kbps RL = 3kΩ, CL = 250pF (Note 3) l 1000 kbps Maximum Data Rate (DIN to DOUT) C L = 15pF (Note 3) l 10 Mbps Driver Driver Slew Rate (6V/tTHL or tTLH) R L = 3kΩ, CL = 50pF (Figure 1) l 150 V/µs tPHLD, tPLHD Driver Propagation Delay RL = 3kΩ, CL = 50pF (Figure 1) l 0.2 0.5 µs tSKEWD Driver Skew |tPHLD – tPLHD| RL = 3kΩ, CL = 50pF (Figure 1) 40 ns tPZHD, tPZLD Driver Output Enable Time DE = ↑ , RL = 3kΩ, CL = 50pF (Figure 2) l 0.6 2 µs tPHZD, tPLZD Driver Output Disable Time DE = ↓ , RL = 3kΩ, CL = 50pF (Figure 2) l 0.3 2 µs
For more information www.linear .com/L TM2882 ISOLATION CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. LTM2882-3 VCC = 3.3V, LTM2882-5 VCC = 5.0V, VL = VCC, and GND = GND2 = 0V, ON = VL unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VISO Rated Dielectric Insulation Voltage 1 Minute, Derived from 1 Second Test 2500 VRMS
1 Second (Notes 5, 6) ±4400 V
Common Mode T ransient Immunity V L = ON = 3.3V, VCM = 1kV, ∆t = 33ns (Note 2) 30 kV/µs VIORM Maximum Working Insulation Voltage (Notes 2, 5) 560 400 VPEAK VRMS Partial Discharge VPR = 1050 VPEAK (Notes 2, 5) 5 pC CTI DTI Comparative T racking Index Depth of Erosion Distance Through Insulation IEC 60112 (Note 2) IEC 60112 (Note 2) (Note 2) 600 0.017 0.06 V RMS mm mm Input to Output Resistance (Notes 2, 5) 109 Ω Input to Output Capacitance (Notes 2, 5) 6 pF Creepage Distance (Notes 2, 5) 9.48 mm Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Guaranteed by design and not subject to production test. Note 3: Maximum Data Rate is guaranteed by other measured parameters and is not tested directly. Note 4: This device includes over-temperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above specified maximum operating junction temperature may result in device degradation or failure. Note 5: Tests performed from GND to GND2, all pins shorted each side of isolation barrier. Note 6: The rated dielectric insulation voltage should not be interpreted as a continuous voltage rating. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. LTM2882-3 VCC = 3.3V, LTM2882-5 VCC = 5.0V, VL = VCC, and GND = GND2 = 0V, ON = VL unless otherwise noted. SWITCHING CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Receiver tPHLR, tPLHR Receiver Propagation Delay CL = 150pF (Figure 3) l 0.2 0.4 µs tSKEWR Receiver Skew |tPHLR – tPLHR| CL = 150pF (Figure 3) 40 ns tRR, tFR Receiver Rise or Fall Time CL = 150pF (Figure 3) l 60 200 ns Auxiliary Channel t PHLL, tPLHL Propagation Delay CL = 15pF, tR and tF < 4ns (Figure 4) l 60 100 ns tRL, tFL Rise or Fall Time CL = 150pF (Figure 4) l 60 200 ns Power Supply Power-Up Time ON = ↑ to VCC2(MIN) l 0.2 2 ms
For more information www.linear .com/L TM2882 TYPICAL PERFORMANCE CHARACTERISTICS VCC Supply Current vs Load Capacitance (Dual Transceiver) VCC Supply Current vs Data Rate (Dual Transceiver) Driver Short-Circuit Current vs Temperature Receiver Input Threshold vs Temperature V CC Supply Current vs Temperature VCC Supply Current vs Temperature TA = 25°C, LTM2882-3 VCC = 3.3V, LTM2882-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. LOAD CAPACITANCE (nF) VCC CURRENT (mA) 100 250kbps, L TM2882-3 100kbps, L TM2882-3 19.2kbps, L TM2882-3 19.2kbps, L TM2882-5 250kbps, L TM2882-5 100kbps, L TM2882-5 1 2
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2.50.5 1.5 DATA RATE (kbps) VCC CURRENT (mA) 140 100 120 400 800
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5.0V CL = 1nF 5.0V CL = 250pF 3.3V CL = 1nF 3.3V CL = 250pF LOAD CAPACITANCE (nF) SLEW RATE (V/µs)
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LOAD CURRENT(mA) OUTPUT VOL TAGE (V)
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VL = 5.5V VL = 3.3V VL = 1.62V Driver Disabled Leakage Current vs Temperature at ±15V TEMPERATURE (°C) –50 THRESHOLD VOL TAGE (V) 3.0 2.0 0.5 1.5 2.5 1.0 500 100
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25–25 75 INPUT HIGH TEMPERATURE (°C) –50 VCC CURRENT (mA) 500 100
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12525–25 75 NO LOAD VCC = 3.3V L TM2882-3 VCC = 5.0V L TM2882-5 TEMPERATURE (°C) –50 VCC CURRENT (mA) 500 100
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12525–25 75 T1OUT AND T2OUT BAUD = 100kbps R L = 3k, CL = 2.5nF VCC = 3.3V L TM2882-3 VCC = 5.0V L TM2882-5 TEMPERATURE (°C) –50 SHORT-CIRCUIT CURRENT (mA) 0 50 75 100
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125–25 25 SOURCING SINKING TEMPERATURE (°C) –50 LEAKAGE CURRENT (nA) 1000 0.01 100 0.1 0.001 0 50 75 100
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125–25 25 VTOUT = ±15V
For more information www.linear .com/L TM2882 TYPICAL PERFORMANCE CHARACTERISTICS Driver Outputs Exiting Shutdown Driver Outputs Enable/Disable Logic Input Threshold vs VL Supply Voltage TA = 25°C, LTM2882-3 VCC = 3.3V, LTM2882-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. VL SUPPL Y VOL TAGE (V) THRESHOLD VOL TAGE (V) 3.5 2.5 0.5 1.0 2.0 3.0 1.5 4 52
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100µs/DIV 5V/DIV T1OUT T1OUT ON T2OUT T2OUT
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DE = VCC2 DE = DOUT , DIN = VL 2µs/DIV 5V/DIV 2V/DIV T1OUT T2OUT
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Operating Through 35kV/µs Common Mode Transients 50ns/DIV 500V/DIV 2V/DIV T1IN R1OUT * MUL TIPLE SWEEPS OF COMMON MODE TRANSIENTS 2V/DIV
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T1OUT = R1IN VCC2 Output Voltage vs Load Current LOAD CURRENT (mA) VCC2 VOL TAGE (V) 5.2 5.0 4.6 4.7 4.9 5.1 4.8 4.5 15050 250
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3.0V 100 200 VCC = 3.0V TO 3.6V , L TM2882-3 VCC = 4.5V TO 5.5V , L TM2882-5 5.5V 5.0V 4.5V 3.6V 3.3V
For more information www.linear .com/L TM2882 VCC2 Load Step Response 100µs/DIV 50mA/DIV 200mV/DIV
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10µs/DIV 100mV/DIV
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T1IN = 250kbps T1OUT , T2OUT , RL = 3k LOAD CURRENT (mA) EFFICIENCY (%) POWER LOSS (W) 1.2 1.0 0.2 0.4 0.8 0.6 200 250100
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TA = 25°C TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, LTM2882-3 VCC = 3.3V, LTM2882-5 VCC = 5V, VL = 3.3V, and GND = GND2 = 0V, ON = VL unless otherwise noted. VCC2 Surplus Current vs Temperature TEMPERATURE (°C) –50 VCC2 CURRENT (mA) 300 200 150 250 100 500 100
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12525–25 75 T1OUT AND T2OUT BAUD = 100kbps R L = 3k, CL = 2.5nF VCC2 = 4.8V VCC = 3.3V L TM2882-3 VCC = 5.0V L TM2882-5
Figure 3. Receiver Timing Measurement Figure 4. Auxiliary Channel Timing Measurement
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Figure 1. Driver Slew Rate and Timing Measurement Figure 2. Driver Enable/Disable Times
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0 OR VL
For more information www.linear .com/L TM2882 LOGIC SIDE R2OUT (Pin A1): Channel 2 RS232 Inverting Receiver Output. Controlled through isolation barrier from receiver input R2IN. Under the condition of an isolation communi- cation failure R2OUT is in a high impedance state. T 2IN (Pin A2): Channel 2 RS232 Inverting Driver Input. A logic low on this input generates a high on isolated output T2OUT. A logic high on this input generates a low on isolated output T2OUT. Do not float. R1OUT (Pin A3): Channel 1 RS232 Inverting Receiver Output. Controlled through isolation barrier from receiver input R1IN. Under the condition of an isolation communi- cation failure R1OUT is in a high impedance state. T 1IN (Pin A4): Channel 1 RS232 Inverting Driver Input. A logic low on this input generates a high on isolated output T1OUT. A logic high on this input generates a low on isolated output T1OUT. Do not float. DIN (Pin A5): General Purpose Non-Inverting Logic Input. A logic high on DIN generates a logic high on isolated output DOUT. A logic low on DIN generates a logic low on isolated output DOUT. Do not float. ON (Pin A6): Enable. Enables power and data communica- tion through the isolation barrier. If ON is high the part is enabled and power and communications are functional to the isolated side. If ON is low the logic side is held in reset and the isolated side is unpowered. Do not float. V L (Pin A7): Logic Supply. Interface supply voltage for pins DIN, R2OUT, T2IN, R1OUT, T1IN, and ON. Operating voltage VCC (Pins A8, B7-B8): Supply Voltage. Operating volt- age is 3.0V to 3.6V for LTM2882-3, and 4.5V to 5.5V for LTM2882-5. Internally bypassed to GND with 2.2µF. GND (Pins B1-B6): Circuit Ground. ISOLATED SIDE GND2 (Pins K1-K7): Isolated Side Circuit Ground. These pads should be connected to the isolated ground and/or cable shield. V CC2 (Pins K8, L7-L8): Isolated Supply Voltage Output. In- ternally generated from VCC by an isolated DC/DC converter and regulated to 5V. Supply voltage for pins R1IN, R2IN, DE, and DOUT. Internally bypassed to GND2 with 2.2µF. R2IN (Pin L1): Channel 2 RS232 Inverting Receiver Input. A low on isolated input R2IN generates a logic high on R2OUT. A high on isolated input R2IN generates a logic low on R2OUT. Impedance is nominally 5kΩ in receive mode or unpowered. T2OUT ( Pin L 2): Channel 2 RS232 Inverting Driver Output. Controlled through isolation barrier from driver input T2IN. High impedance when the driver is disabled (DE pin is low). R 1IN (Pin L3): Channel 1 RS232 Inverting Receiver Input. A low on isolated input R1IN generates a logic high on R1OUT. A high on isolated input R1IN generates a logic low on R1OUT. Impedance is nominally 5kΩ in receive mode or unpowered. T1OUT ( Pin L 4): Channel 1 RS232 Inverting Driver Output. Controlled through isolation barrier from driver input T1IN. High impedance when the driver is disabled (DE pin is low). DOUT (Pin L5): General Purpose Non-Inverting Logic Output. Logic output connected through isolation barrier to DIN. DE (Pin L6): Driver Output Enable. A low input forces both RS232 driver outputs, T1OUT and T2OUT, into a high impedance state. A high input enables both RS232 driver outputs. Do not float. PIN FUNCTIONS
For more information www.linear .com/L TM2882 BLOCK DIAGRAM 2882 BD 2.2µF 2.2µF VCC VCC2 GND2 DE DOUT T1OUT R1IN T2OUT R2IN V L 2.2µF GND ON DIN T1IN T2IN R2OUT R1OUT DC/DC CONVERTER ISOLATED COMMUNI- CATIONS INTERFACE ISOLATED COMMUNI- CATIONS INTERFACE REG VDD VEE VDD VDD VEE VEE
Figure 5. VCC and VL Are Independent
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μs providing excellent noise isolation. translate signals and power across an isolation barrier. voltage, and is rectified by a full-wave voltage doubler. (LDO) to provide a regulated low noise 5V output, VCC2. to levels that guarantee greater than ±5V output swing. Figure 5. Simply connect the desired logic supply to VL. is bypassed internally by a 2.2µF capacitor. and mitigation of this phenomenon.
ary by encoding and decoding of the inputs and outputs. typically ±6ns, but may vary up to about 40ns. active. This mode of operation is illustrated in Figure 6. Figure 6. Half-Duplex Configuration Using DOUT to Drive DE
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prevent damaging the LTM2882. voltages of ±25V relative to GND2. logic high on each receiver’s respective output pin. signed per the data sheet PCB layout recommendations. Specific limits per test are detailed in Table 1.
For more information www.linear .com/L TM2882 APPLICATIONS INFORMATION PCB Layout The high integration of the LTM2882 makes PCB layout very simple. However, to optimize its electrical isolation characteristics, EMI, and thermal performance, some layout considerations are necessary. Under heavily loaded conditions VCC and GND current can exceed 300mA. Sufficient copper must be used on the PCB to insure resistive losses do not cause the supply voltage to drop below the minimum allowed level. Similarly, the V CC2 and GND2 conductors must be sized to support any external load current. These heavy copper traces will also help to reduce thermal stress and improve the thermal conductivity. I nput and Output decoupling is not required, since these components are integrated within the package. An ad- ditional bulk capacitor with a value of 6.8µF to 22µF is recommended. The high ESR of this capacitor reduces board resonances and minimizes voltage spikes caused by hot plugging of the supply voltage. For EMI sensitive applications, an additional low ESL ceramic capacitor of 1µF to 4.7µF, placed as close to the power and ground terminals as possible, is recommended. Alternatively, a number of smaller value parallel capacitors may be used to reduce ESL and achieve the same net capacitance. Do not place copper on the PCB between the inner col- umns of pads. This area must remain open to withstand the rated isolation voltage. The use of solid ground planes for GND and GND2 is recommended for non-EMI critical applications to optimize signal fidelity, thermal performance, and to minimize RF emissions due to uncoupled PCB trace conduction. The drawback of using ground planes, where EMI is of concern, is the creation of a dipole antenna structure which can radiate differential voltages formed between GND and GND2. If ground planes are used it is recommended to minimize their area, and use contiguous planes as any openings or splits can exacerbate RF emissions. For large ground planes a small capacitance (≤ 330pF) from GND to GND2, either discrete or embedded within the substrate, provides a low impedance current return path for the module parasitic capacitance, minimizing any high frequency differential voltages and substantially reducing radiated emissions. Discrete capacitance will not be as effective due to parasitic ESL. In addition, volt- age rating , leakage, and clearance must be considered for component selection. Embedding the capacitance within the PCB substrate provides a near ideal capacitor and eliminates component selection issues; however, the PCB must be 4 layers. Care must be exercised in applying either technique to insure the voltage rating of the barrier is not compromised. The PCB layout in Figures 7a to 7e show the low EMI demo board for the LTM2882. The demo board uses a combination of EMI mitigation techniques, including both embedded PCB bridge capacitance and discrete GND to GND2 capacitors. Tw o safety rated type Y2 capacitors are used in series, manufactured by Murata, part number GA342QR7GF471KW01L. The embedded capacitor ef - fectively suppresses emissions above 400MHz, whereas the discrete capacitors are more effective below 400MHz. EMI performance is shown in Figure 8, measured using a Gigahertz T ransverse Electromagnetic (GTEM) cell and method detailed in IEC 61000-4-20, “Testing and Mea - surement T echniques – Emission and Immunity Testing in T ransverse Electromagnetic Waveguides.”
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Figure 8. Low EMI Demo Board Emissions
Figure 9. Single Line Dual Half-Duplex Figure 10. Driving Larger Capacitive Loads
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Figure 13. Isolated Multirail Power Supply Figure 11. 1.8V Microprocessor Interface
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Figure 12. Isolated 5V Power Supply
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For more information www.linear .com/L TM2882 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTM2882#packaging for the most recent package drawings. NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW BGA 32 0517 REV E L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” DETAIL A PIN 1 0.000 0.635 0.635 1.905 1.905 3.175 3.175 4.445 4.445 6.350 6.350 5.080 5.080 0.000 DETAIL A Øb (32 PLACES) F G H L J K E A B C D 2 14 35 6 7 8 D A DETAIL B PACKAGE SIDE VIEW M X Y Z ddd M Z eee 0.630 ±0.025 Ø 32x E b e e b F G 32-Lead (15mm × 11.25mm × 3.42mm) (Reference LTC DWG # 05-08-1851 Rev E) SEE NOTES SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 3.22 0.50 2.72 0.60 0.60 0.27 2.45 NOM 3.42 0.60 2.82 0.75 0.63 15.0 11.25 1.27 12.70 8.89 0.32 2.50 MAX 3.62 0.70 2.92 0.90 0.66 0.37 2.55 0.15 0.10 0.20 0.30 0.15 TOTAL NUMBER OF BALLS: 32 DIMENSIONS NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT Z DETAIL B SUBSTRATE ccc Z Z // bbb Z MOLD CAP 5. PRIMARY DATUM -Z- IS SEATING PLANE
6 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y
For more information www.linear .com/L TM2882 LGA Package 32-Lead (15mm × 11.25mm × 2.82mm) (Reference L TC DWG # 05-08-1773 Rev A) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS LAND DESIGNATION PER JESD MO-222 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. THE TOTAL NUMBER OF PADS: 32 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE DETAIL B DETAIL B SUBSTRATE MOLD CAP 0.290 – 0.350 2.400 – 2.600 bbb Z Z PACKAGE TOP VIEW 11.25 BSC 15.00 BSC PAD “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW PADS SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW LGA 32 0113 REV A L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” 8.89 BSC 1.27 BSC 0.635 0.635 1.905 1.905 3.175 3.175 4.445 4.445 6.350 6.350 5.080 5.080 0.000 SYMBOL aaa bbb eee TOLERANCE 0.10 0.10 0.05 DETAIL A 0.630 ±0.025 Ø 32x S Y X eee DETAIL C 0.630 ±0.025 Ø 32x S Y X eee F G H L J K E A B C D 2 14 35 6 7 2.69 – 2.95 DETAIL A 12.70 BSC DETAIL c PAD 1 SEE NOTES
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTM2882#packaging for the most recent package drawings.
For more information www.linear .com/L TM2882 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER A 3/10 Changes to Features Add BGA Package to Pin Configuration, Order Information and Package Description Sections Changes to LGA Package in Pin Configuration Section Update to Pin Functions Update to RF, Magnetic Field Immunity Section “PCB Layout Isolation Considerations” Section Replaced 2, 15 B 3/11 H-Grade parts added. Reflected throughout the data sheet. 1-20 C 1/12 MP-Grade parts added. Reflected throughout the data sheet. 1-24 D 11/12 Storage temperature range updated. 2 E 5/14 Removed H-grade and MP-grade parts throughout the data sheet. Reduced Maximum Internal Operating Temperature and Storage Temperature Range. Added CTI and DTI parameters. 1-22 F 9/14 Revised Output Supply Short-Circuit Current (I CC2) 3 G 4/16 Added CSA information Revised ICC (LTM2882-5) limit H 2/18 H-Grade parts added. Reflected throughout the data sheet. 1-22
2500 VRMS Isolation with Power in BGA Package
Figure 16. Isolated Gate Drive with Overcurrent Detection Figure 14. Isolated RS232 Interface with Handshaking Figure 15. Isolated Dual Inverting Level T ranslator