Power Management

LTCXX

Linear Technology

1.1A, Low Noise, Low Dropout Linear Regulator

Manufacturer: Linear Technology

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LT1965 LINER | Alldatasheet

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OUTPUT CURRENT (A) DROPOUT VOLTAGE (mV)100 200 300 0.2 0.4 0.6 0.8 1 400 150 250 350 1.2

1965 TA01b

TJ = 25°C TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

1.1A, Low Noise, Low Dropout Linear Regulator The LT®1965 is a low noise, low dropout linear regulator. The device supplies 1.1A of output current with a 290mV typical dropout voltage. Operating quiescent current is 500μA, reducing to <1μA in shutdown. Quiescent current is well controlled; it does not rise in dropout as with many other regulators. The LT1965 regulator has very low out- put noise which makes it ideal for sensitive RF and DSP supply applications. Output voltage ranges from 1.20V to 19.5V. The LT1965 regulator is stable with output capacitors as low as 10μF. Internal protection circuitry includes reverse battery pro- tection, current limiting with foldback, thermal limiting and reverse current protection. The LT1965 is available as an adjustable device with a 1.20V reference voltage. The package offering includes the 5-lead TO-220, 5-lead DD-PAK as well as the thermally enhanced 8-lead MSOP and 8-lead 3mm × 3mm DFN. 3.3V to 2.5V Regulator ■ Output Current: 1.1A ■ Dropout Voltage: 290mV ■ Low Noise: 40μVRMS (10Hz to 100kHz) ■ 500μA Quiescent Current ■ Wide Input Voltage Range: 1.8V to 20V ■ No Protection Diodes Needed ■ Controlled Quiescent Current in Dropout ■ Adjustable Output from 1.20V to 19.5V ■ < 1μA Quiescent Current in Shutdown ■ Stable with 10μF Output Capacitor ■ Stable with Ceramic, Tantalum or Aluminum Electrolytic Capacitors ■ Reverse Battery Protection ■ No Reverse Current ■ Current Limit with Foldback Protection ■ Thermal Limiting ■ 5-Lead TO-220, DD-PAK, Thermally Enhanced 8-Lead MSOP and 8-Lead 3mm × 3mm DFN Packages ■ Logic Power Supplies ■ Post Regulator for Switching Supplies ■ Low Noise Instrumentation , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Dropout Voltage IN SHDN 10μF* *CERAMIC, TANTALUM OR ALUMINUM ELECTROLYTIC1965 TA01 OUT VIN > 3V TO 20V ADJ GND LT1965 2.5V 1.1A 10μF* 5.11k 4.75k

(Note 1) TOP VIEW DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN 1OUT OUT ADJ GND IN IN SHDN GND TJMAX = 125°C, θJA = 65°C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB OUT OUT ADJ GND IN IN SHDN GND TOP VIEW MS8E PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 60°C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB Q PACKAGE 5-LEAD PLASTIC DD-PAK FRONT VIEW ADJ OUT GND IN SHDN TAB IS GND TJMAX = 125°C, θJA = 30°C/W T PACKAGE 5-LEAD PLASTIC TO-220 ADJ OUT GND IN SHDN FRONT VIEW TAB IS GND TJMAX = 125°C, θJA = 50°C/W PIN CONFIGURATION ORDER INFORMATION Operating Junction Temperature Range (E, I Grade) Lead Temperature (Soldering, 10 sec) (Only for MSOP , TO-220, DD-PAK Packages) ... 300°C LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT1965EDD#PBF LT1965EDD#TRPBF LCXW 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT1965EMS8E#PBF LT1965EMS8E#TRPBF LTCXX 8-Lead Plastic MSOP –40°C to 125°C LT1965EQ#PBF LT1965EQ#TRPBF LT1965Q 5-Lead Plastic DD-PAK –40°C to 125°C LT1965ET#PBF LT1965ET#TRPBF LT1965T 5-Lead Plastic TO-220 –40°C to 125°C LT1965IDD#PBF LT1965IDD#TRPBF LCXW 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C LT1965IMS8E#PBF LT1965IMS8E#TRPBF LTCXX 8-Lead Plastic MSOP –40°C to 125°C LT1965IQ#PBF LT1965IQ#TRPBF LT1965Q 5-Lead Plastic DD-PAK –40°C to 125°C LT1965IT#PBF LT1965IT#TRPBF LT1965T 5-Lead Plastic TO-220 –40°C to 125°C Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *Temperature grades are identiﬁ ed by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based ﬁ nish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Absolute maximum input to output differential voltage is not achievable with all combinations of rated IN pin and OUT pin voltages. With the IN pin at 22V, the OUT pin may not be pulled below 0V. The total measured voltage from IN to OUT must not exceed ±22V. Note 3: The LT1965 is tested and speciﬁ ed under pulse load conditions such that T J ≅ TA. The LT1965E is 100% tested at TA = 25°C. Performance at –40°C and 125°C is assured by design, characterization, and correlation with statistical process controls. The LT1965I is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 4: The LT1965 is tested and speciﬁ ed for these conditions with the ADJ connected to the OUT pin. PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Input Voltage (Notes 4, 12) I LOAD = 0.5A ILOAD = 1.1A ● 1.65 1.8 2.3 V V ADJ Pin Voltage (Notes 4, 5) V IN = 2.1V, ILOAD = 1mA 2.3V < VIN < 20V, 1mA < ILOAD < 1.1A ● 1.182 1.164 1.20 1.20 1.218 1.236 V V Line Regulation (Note 4) ΔV IN = 2.1V to 20V, ILOAD = 1mA ● 38 m V Load Regulation V IN = 2.3V, ΔILOAD = 1mA to 1.1A VIN = 2.3V, ΔILOAD = 1mA to 1.1A ● 4.25 8 mV mV Dropout Voltage VIN = VOUT(NOMINAL) (Notes 6, 7, 12) ILOAD = 1mA ILOAD = 1mA ● 0.05 0.08 0.14 V V ILOAD = 100mA ILOAD = 100mA ● 0.10 0.175 0.28 V V ILOAD = 500mA ILOAD = 500mA ● 0.19 0.25 0.36 V V ILOAD = 1.1A ILOAD = 1.1A ● 0.29 0.36 0.49 V V GND Pin Current VIN = VOUT(NOMINAL) + 1V (Notes 6, 8) ILOAD = 0mA ILOAD = 1mA ILOAD = 100mA ILOAD = 500mA ILOAD = 1.1A 0.5 0.6 2.2 8.2 1.1 1.5 5.5 mA mA mA mA mA Output Voltage Noise C OUT = 10μF, ILOAD = 1.1A, BW = 10Hz to 100kHz 40 μV RMS ADJ Pin Bias Current (Notes 4, 9) 1.3 4.5 μA Shutdown Threshold V OUT = Off to On VOUT = On to Off

0.2 0.85 0.45 V ⎯S⎯H⎯D⎯N Pin Current (Note 10) V ⎯S⎯H⎯D⎯N = 0V V⎯S⎯H⎯D⎯N = 20V 0.01 5.5 μA μA Quiescent Current in Shutdown V IN = 6V, V⎯S⎯H⎯D⎯N = 0V 0.01 1 μA Ripple Rejection V IN – VOUT = 1.5V (AVG), VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz, ILOAD = 0.75A 57 75 dB Current Limit V IN = 7V, VOUT = 0 VIN = VOUT(NOMINAL) + 1V, ΔVOUT = -0.1V (Note 6) ● 1.2 A Input Reverse Leakage Current V IN = –20V, VOUT = 0 1 mA Reverse Output Current (Note 11) V OUT = 1.2V, VIN < 1.2V (Note 4) 175 400 μA The ● denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 3) Note 5: Maximum junction temperature limits operating conditions. The regulated output voltage speciﬁ cation does not apply for all possible combinations of input voltage and output current. Limit the output current range if operating at the maximum input voltage. Limit the input-to-output voltage differential if operating at the maximum output current. Note 6: To satisfy minimum input voltage requirements, the LT1965 is tested and speciﬁ ed for these conditions with an external resistor divider (bottom 4.02k, top 4.32k) for an output voltage of 2.5V. The external resistor divider adds 300μA of output DC load current. Note 7: Dropout voltage is the minimum input-to-output voltage differential needed to maintain regulation at a speciﬁ ed output current. In dropout, the output voltage equals: (V IN – VDROPOUT) Note 8: GND pin current is tested with VIN = VOUT(NOMINAL) + 1V and a current source load. GND pin current increases slightly in dropout. See GND pin current curves in the Typical Performance Characteristics section.

OUTPUT CURRENT (A) DROPOUT VOLTAGE (mV)100 200 300 0.2 0.4 0.6 0.8 1 400 500 150 250 350 450 1.2

1965 G01

TJ = 125°C TJ = 25°C OUTPUT CURRENT (A) GUARANTEED DROPOUT VOLTAGE (mV) 100 200 300 0.2 0.4 0.6 0.8 1 400 500 150 250 350 450 1.2

1965 G02

= TEST POINTS TJ = 125°C TJ = 25°C DROPOUT VOLTAGE (mV)100 200 300 400 500 150 250 350 450

1965 G03

IL = 1.1A IL = 500mA IL = 100mA IL = 1mA TEMPERATURE (°C) –50 –25 0 25 50 75 100 125 QUIESCENT CURRENT (mA)0.2 0.4 0.6 0.8 1.0 0.1 0.3 0.5 0.7 0.9

1965 G04

TEMPERATURE (°C) –50 –25 0 25 50 75 100 125 VIN = 6V RL = ∞, IL = 0 VSHDN = VIN

1.182 ADJ PIN VOLTAGE (V)

1.190 1.198 1.206 1.218 1.186 1.194 1.202 1.210 1.214

1965 G05

TEMPERATURE (°C) –50 –25 0 25 50 75 100 125 IL = 1mA QUIESCENT CURRENT (mA)0.2 0.4 0.6 0.8 1.0 0.1 0.3 0.5 0.7 0.9

1965 G06

INPUT VOLTAGE (V) 01 6 4 8 12 20 142 6 10 18 TJ = 25°C RL = 4.02k VSHDN = VIN TYPICAL PERFORMANCE CHARACTERISTICS Typical Dropout Voltage Guaranteed Dropout Voltage Dropout Voltage Quiescent Current ADJ Pin Voltage Quiescent Current Note 9: ADJ pin bias current ﬂ ows into the ADJ pin. Note 10: ⎯S⎯H⎯D⎯N pin current ﬂ ows into the ⎯S⎯H⎯D⎯N pin. Note 11: Reverse output current is tested with the IN pin grounded and the OUT pin forced to the rated output voltage. This current ﬂ ows into the OUT pin and out of the GND pin. Note 12: For the LT1965, the minimum input voltage speciﬁ cation limits the dropout voltage under some output voltage/load conditions. Note 13: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature is active. Continuous operation above the speciﬁ ed maximum operating junction temperature may impair device reliability.

CURRENT LIMIT (A) 0.5 1.0 1.5 2.0 2.5

1965 G14

INPUT/OUTPUT DIFFERENTIAL (V) 01 6 4 8 12 20 142 6 10 18 TJ = 125°C TJ = –50°C TJ = 25°C ΔVOUT = –100mV GND PIN CURRENT (mA) 0.4 0.8 1.2 1.6 2.0 0.2 0.6 1.0 1.4 1.8

1965 G07

INPUT VOLTAGE (V) 08 246 1 0 7135 9 TJ = 25°C VSHDN = VIN *FOR VOUT = 1.2V RL = 24Ω, IL = 50mA* RL = 120Ω, IL = 10mA* RL = 1.2k, IL = 1mA* GND PIN CURRENT (mA)

1965 G08

INPUT VOLTAGE (V) 08 246 1 0 7135 9 TJ = 25°C VSHDN = VIN *FOR VOUT = 1.2V RL = 1.091Ω, IL = 1.1A* RL = 2.4Ω, IL = 500mA* RL = 12Ω, IL = 100mA* LOAD CURRENT (A) GND PIN CURRENT (mA) 5.00 10.0 15.0 20.0 25.0 2.50 7.50 12.5 17.5 22.5 1.2

1965 G09

VIN = VOUT(NOMINAL) + 1V SHDN PIN THRESHOLD (V)0.2 0.4 0.6 0.8 1.0 0.1 0.3 0.5 0.7 0.9

1965 G10

TEMPERATURE (°C) –50 –25 0 25 50 75 100 125 OFF TO ON ON TO OFF SHDN PIN VOLTAGE (V) SHDN PIN INPUT CURRENT (μA) 4 8 12 16 2020 6 10 14 18

1965 G11

5.0 SHDN PIN INPUT CURRENT (μA) 5.2 5.4 5.6 5.8 6.0 5.1 5.3 5.5 5.7 5.9

1965 G12

TEMPERATURE (°C) –50 –25 0 25 50 75 100 125 VSHDN = 20V ADJ PIN BIAS CURRENT (μA) 1.0 2.0 3.0 4.0 4.5 0.5 1.5 2.5 3.5

1965 G13

TEMPERATURE (°C) –50 –25 0 25 50 75 100 125 CURRENT LIMIT (A)1.0 2.0 3.0 0.5 1.5 2.5

1965 G15

TEMPERATURE (°C) –50 –25 0 25 50 75 100 125 VIN = 7V VOUT = 0V GND Pin Current GND Pin Current GND Pin Current vs I LOAD TYPICAL PERFORMANCE CHARACTERISTICS ⎯S⎯H⎯D⎯N Pin Threshold ⎯S⎯H⎯D⎯N Pin Input Current ⎯S⎯H⎯D⎯N Pin Input Current ADJ Pin Bias Current Current Limit vs V IN–VOUT Current Limit vs Temperature

TYPICAL PERFORMANCE CHARACTERISTICS Ripple Rejection vs Temperature Minimum Input Voltage Load Regulation Output Noise Spectral Density RMS Output Noise vs Load Current (10Hz to 100kHz) 1.8V 10Hz to 100kHz Output Noise Reverse Output Current Reverse Output Current Ripple Rejection vs Frequency OUTPUT VOLTAGE (V) REVERSE OUTPUT CURRENT (mA)1 2468 10

1965 G16

TJ = 25°C VIN = 0V CURRENT FLOWS INTO OUTPUT PIN V OUT = VADJ REVERSE OUTPUT CURRENT (mA) 0.10 0.20 0.30 0.40 0.50 0.05 0.15 0.25 0.35 0.45

1965 G17

TEMPERATURE (°C) –50 –25 0 25 50 75 100 125 VIN = 0V VOUT = 1.2V RIPPLE REJECTION (dB) 100

1965 G19

TEMPERATURE (°C) –50 –25 0 25 50 75 100 125 IL = 0.75A VIN = VOUT(NOMINAL) + 1V + 0.5P-P RIPPLE AT f = 120Hz MINIMUM INPUT VOLTAGE (V) 1.0 2.0 2.5 0.5 1.5

1965 G20

TEMPERATURE (°C) –50 –25 0 25 50 75 100 125 IL = 500mA IL = 1.1A IL = 100mA –16 LOAD REGULATION (mV)–12 –14 –10

1965 G21

TEMPERATURE (°C) –50 –25 0 25 50 75 100 125 VIN = 2.3V ΔIL = 1mA TO 1.1A 0.01 0.10 1.00 FREQUENCY (Hz) OUTPUT NOISE SPECTRAL DENSITY (μV Hz) 100 1k 10k 100k

1965 G22

VOUT = 3.3V VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V COUT = 10μF IL = 1.1A LOAD CURRENT (A) OUTPUT NOISE VOLTAGE (μVRMS) 0.0001 0.01 0.1 10 0.001 1

1965 G23

VOUT = 2.5V VOUT = 3.3V VOUT = 1.8V VOUT = 1.2V COUT = 10μF IL = 1.1A VOUT = 1.5V 400μs/DIV VOUT 100μV/DIV

1965 G24

COUT = 10μF IL = 1.1A FREQUENCY (Hz) RIPPLE REJECTION (dB) 10 1k 10k 1M 100 100k

1965 G18

IL = 0.75A COUT = 10μF CERAMIC VIN = VOUT(NOMINAL) + 1V + 50mVRMS RIPPLE

TIME (μs) SHDN AND OUTPUT VOLTAGE (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 8020 40 60 100 7010 30 50 90

1965 G26

VIN = 3.3V COUT = 10μF CERAMIC RL = 2.5k, IL = 1mA FOR VOUT = 2.5V 0.0 –100 OUTPUT VOLTAGE DEVIATION (mV)LOAD CURRENT (A) –50 100 0.5 1.0 1.5 10 20 30 40 50 60 70 80

1965 G25

TIME (μs) VIN = 4.3V CIN = 10μF CERAMIC COUT = 10μF CERAMIC VOUT = 3.3V PIN FUNCTIONS OUT (Pins 1, 2 / 1, 2 / 4 / 4): Output. This pin supplies power to the load. Use a minimum output capacitor of 10μF to prevent oscillations. Large load transient applica- tions require larger output capacitors to limit peak volt- age transients. See the Applications Information section for more information on output capacitance and reverse output characteristics. ADJ (Pins 3 / 3 / 5 / 5): Adjust. This pin is the input to the error ampliﬁ er. It has a typical bias current of 1.3μA that ﬂ ows into the pin. The ADJ pin voltage is 1.20V referenced to ground. GND (Pins 4, 5 / 4, 5 / 3 / 3): Ground. For the adjustable LT1965, connect the bottom of the resistor divider, setting output voltage, directly to GND for optimum regulation. ⎯S⎯H⎯D⎯N (Pin 6 / 6 / 1 / 1): Shutdown. Pulling the ⎯S⎯H⎯D⎯N pin low puts the LT1965 into a low power state and turns the output off. Drive the ⎯S⎯H⎯D⎯N pin with either logic or an open collector/drain with a pull-up resistor. The resistor sup- plies the pull-up current to the open collector/drain logic, normally several microamperes and the ⎯S⎯H⎯D⎯N pin current, typically less than 6μA. If unused, connect the ⎯S⎯H⎯D⎯N pin to VIN. The LT1965 will be in its low power shutdown state if the ⎯S⎯H⎯D⎯N pin is not connected. The ⎯S⎯H⎯D⎯N pin cannot be driven below GND unless it is tied to the IN pin. If the ⎯S⎯H⎯D⎯N pin is driven below GND while IN is powered, the output will turn on. ⎯S⎯H⎯D⎯N pin logic cannot be referenced to a negative supply rail. IN (Pins 7, 8 / 7, 8 / 2 / 2): Input. This pin supplies power to the device. The LT1965 requires a bypass capacitor at IN if located more than six inches from the main input ﬁ lter capacitor. Include a bypass capacitor in battery-powered circuits as a battery’s output impedance generally rises with frequency. A bypass capacitor in the range of 1μF to 10μF sufﬁ ces. The LT1965’s design withstands reverse voltages on the IN pin with respect to ground and the OUT pin. In the case of a reversed input, which occurs if a battery is plugged in backwards, the LT1965 behaves as if a diode is in series with its input. No reverse current ﬂ ows into the LT1965 and no reverse voltage appears at the load. The device protects itself and the load. Exposed Pad (Pin 9 / 9, DFN and MSOP Packages Only): Ground. Tie this pin directly to Pins 4 and 5 and the PCB ground. This pin provides enhanced thermal performance with its connection to the PCB ground. See the Applica- tions Information section for thermal considerations and calculating junction temperature. (DFN/MSOP/DD-PAK/TO-220) Transient Response ⎯S⎯H⎯D⎯N Transient Response TYPICAL PERFORMANCE CHARACTERISTICS

The LT1965 has an output voltage range of 1.20V to 20V. maintain the ADJ pin voltage at 1.20V referenced to ground. current, 1.3μA at 25°C, ﬂ ows through R2 into the ADJ pin. Use the formula in Figure 1 to calculate output voltage. pin tied to the OUT pin for an output voltage of 1.20V. Figure 1. Adjustable Operation

1965 F01

voltages should be veriﬁ ed. induced by vibrations in the system or thermal transients. in Figure 4 in response to light tapping from a pencil. increased output voltage noise. output voltage up to the device breakdown. of an output short will not allow the output to recover. Figure 2. Ceramic Capacitor DC Bias Characteristics Figure 3. Ceramic Capacitor Temperature Characteristics Figure 4. Noise Resulting from Tapping on a Ceramic Capacitor

1965 F02

1210 CASE SIZE, 10μF

1965 F03

1965 F04

Other regulators, such as the LT1083/LT1084/LT1085 family, also exhibit this phenomenon, so it is not unique to the LT1965. The problem occurs with a heavy output load when the input voltage is high and the output voltage is low. Com- mon situations include immediately after the removal of a short-circuit or if the shutdown pin is pulled high after the input voltage has already been turned on. The load line for such a load may intersect the output current curve at two points. If this happens, there are two stable output operating points for the regulator. With this double intersection, the input power supply may need to be cycled down to zero and brought up again to make the output recover. Output Voltage Noise The LT1965 regulator’s design provides low output voltage noise over the 10Hz to 100kHz bandwidth while operating at full load. Output voltage noise is approximately 80nV/√ ⎯H⎯z over this frequency bandwidth for the LT1965. For higher output voltages (generated by using a resistor divider), the output voltage noise gains up accordingly. Higher values of output voltage noise may be measured if care is not exercised with regard to circuit layout and testing. Crosstalk from nearby traces can induce unwanted noise onto the LT1965’s output. Power supply ripple rejec- tion must also be considered; the LT1965 regulator does not have unlimited power supply rejection and will pass a small portion of the input noise through to the output. APPLICATIONS INFORMATION Thermal Considerations The LT1965’s maximum rated junction temperature of 125°C limits its power handling capability. Two compon- ents comprise the power dissipated by the device: 1. Output current multiplied by the input/output voltage differential: I OUT • (VIN – VOUT), and 2. GND pin current multiplied by the input voltage: IGND • VIN GND pin current is determined using the GND Pin Current curves in the Typical Performance Characteristics section. Power dissipation equals the sum of the two components listed. The LT1965 regulator has internal thermal limiting that protects the device during overload conditions. For con- tinuous normal conditions, do not exceed the maximum junction temperature rating of 125°C. Carefully consider all sources of thermal resistance from junction to ambi- ent including other heat sources mounted in proximity to the LT1965. The underside of the LT1965 DFN package has exposed metal (4mm 2) from the lead frame to the die attachment. The underside of the LT1965 MSOP package also has ex- posed metal (2mm 2). Both packages allow heat to directly transfer from the die junction to the printed circuit board metal to control maximum operating junction temperature. The dual-in-line pin arrangement allows metal to extend beyond the ends of the package on the topside (component side) of a PCB. Connect this metal to GND on the PCB. The multiple IN and OUT pins of the LT1965 also assist in spreading heat to the PCB. For surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the PC board and its copper traces. Copper board stiffeners and plated through-holes can also be used to spread the heat gener- ated by power devices.

Table 1. Measured Thermal Resistance for DFN Package Table 2. Measured Thermal Resistance for MSOP Package Table 3. Measured Thermal Resistance for DD-PAK Package

1965 F05

that make it ideal for use in battery-powered circuits. maximum rated junction temperature of 125°C. The input of the device withstands reverse voltages of 22V. batteries that are plugged in backwards. stops the output from sourcing current. with a diode when pulled above ground. pin yields a minimum top resistor value of 2.2k. a backup battery or a second regulator holds up the output. output current if the output is pulled above the input. Figure 5. Reverse Output Current

0.01Ω 0.01Ω 10k 2.2k 4.02k 22μF

1965 TA03

VIN > 3.7V 3.3V 2.2A 0.01μF IN OUT ADJ GND LT1965 SHDN IN SHDN OUT ADJ GND LT1965 SHDN +C1 100μF LT1366 6.65k 2.2k 4.02k 6.98k Paralleling of Regulators for Higher Output Current

MSOP (MS8E) 06030.53 ± 0.152 (.021 ± .006) SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.18 (.007) 0.254 (.010) 1.10 (.043) MAX 0.22 – 0.38 (.009 – .015) TYP 0.127 ± 0.076 (.005 ± .003) 0.86 (.034) REF 0.65 (.0256) BSC 0° – 6° TYP DETAIL “A”DETAIL “A” GAUGE PLANE 12 3 4 4.90 ± 0.152 (.193 ± .006) BOTTOM VIEW OF EXPOSED PAD OPTION 7 6 5 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 0.52 (.0205) REF1.83 ± 0.102 (.072 ± .004) 2.06 ± 0.102 (.081 ± .004) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 2.083 ± 0.102 (.082 ± .004) 2.794 ± 0.102 (.110 ± .004) 0.889 ± 0.127 (.035 ± .005) RECOMMENDED SOLDER PAD LAYOUT 0.42 ± 0.038 (.0165 ± .0015) TYP 0.65 (.0256) BSC 3.00 ±0.10 (4 SIDES) 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 0.38 ± 0.10 BOTTOM VIEW—EXPOSED PAD 1.65 ± 0.10 (2 SIDES) 0.75 ±0.05 R = 0.115 TYP 2.38 ±0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6)

0.200 REF

0.00 – 0.05 (DD) DFN 1203 0.25 ± 0.05 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 1.65 ±0.05 (2 SIDES)2.15 ±0.05

0.50 BSC

0.675 ±0.05 3.5 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1662)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION T5 (TO-220) 0801 .028 – .038 (0.711 – 0.965) .067 (1.70) .135 – .165 (3.429 – 4.191) .700 – .728 (17.78 – 18.491) .045 – .055 (1.143 – 1.397) .095 – .115 (2.413 – 2.921) .013 – .023 (0.330 – 0.584) .620 (15.75) TYP .155 – .195* (3.937 – 4.953) .152 – .202 (6.60 – 8.13) .165 – .180 (4.191 – 4.572) .147 – .155 (3.734 – 3.937) DIA .390 – .415 (9.906 – 10.541) .330 – .370 (8.382 – 9.398) .460 – .500 (11.684 – 12.700) .570 – .620 (14.478 – 15.748) .230 – .270 (5.842 – 6.858) BSC SEATING PLANE * MEASURED AT THE SEATING PLANE Q Package 5-Lead Plastic DD Pak (Reference LTC DWG # 05-08-1461) T Package 5-Lead Plastic TO-220 (Standard) (Reference LTC DWG # 05-08-1420) Q(DD5) 0502 .028 – .038 (0.711 – 0.965) TYP .143 +.012 –.020 ()3.632 +0.305 –0.508 .067 (1.702) BSC .013 – .023 (0.330 – 0.584) .095 – .115 (2.413 – 2.921) .004 +.008 –.004 ()0.102 +0.203 –0.102 .050 ± .012 (1.270 ± 0.305) .059 (1.499) TYP .045 – .055 (1.143 – 1.397) .165 – .180 (4.191 – 4.572) .330 – .370 (8.382 – 9.398) .060 (1.524) TYP .390 – .415 (9.906 – 10.541) 15° TYP .420 .350 .565 .090 .042.067 RECOMMENDED SOLDER PAD LAYOUT .325 .205 .080 .565 .090 RECOMMENDED SOLDER PAD LAYOUT FOR THICKER SOLDER PASTE APPLICATIONS .042.067 .420 .276 .320 NOTE: 1. DIMENSIONS IN INCH/ (MILLIMETER) 2. DRAWING NOT TO SCALE .300 (7.620) .075 (1.905) .183 (4.648) .060 (1.524) .060 (1.524) .256 (6.502) BOTTOM VIEW OF DD PAK HATCHED AREA IS SOLDER PLATED COPPER HEAT SINK

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2007 LT 0807 • PRINTED IN USA RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LT1129 700mA, Micropower, LDO V IN: 4.2V to 30V, VOUT(MIN) = 3.8V, VDO = 0.40V, IQ = 50μA, ISD = 16μA; DD, SOT-223, S8, TO220-5 and TSSOP20 Packages LT1761 100mA, Low Noise Micropower, LDO V IN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 20μA, ISD = < 1μA, Low Noise < 20μVRMS, Stable with 1μF Ceramic Capacitors, ThinSOT™ Package LT1762 150mA, Low Noise Micropower, LDO V IN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 25μA, ISD = < 1μA, Low Noise < 20μVRMS, MS8 Package LT1763 500mA, Low Noise Micropower, LDO V IN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 30μA, ISD = < 1μA, Low Noise < 20μVRMS, S8 Package LT1764/LT1764A 3A, Low Noise, Fast Transient Response, LDO VIN: 2.7V to 20V, VOUT(MIN) = 1.21V, VDO = 0.34V, IQ = 1mA, ISD = < 1μA, Low Noise < 40μVRMS, “A” Version Stable with Ceramic Capacitors, DD and TO220-5 Packages LTC1844 150mA, Very Low Drop-Out LDO V IN: 1.6V to 6.5V, VOUT(MIN) = 1.25V, VDO = 0.08V, IQ = 35μA, ISD = < 1μA, Low Noise < 60μVRMS, ThinSOT™ Package LT1962 300mA, Low Noise Micropower, LDO V IN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.27V, IQ = 30μA, ISD = < 1μA, Low Noise < 20μVRMS, MS8 Package LT1963/LT1963A 1.5A, Low Noise, Fast Transient Response, LDO VIN: 2.1V to 20V, VOUT(MIN) = 1.21V, VDO = 0.34V, IQ = 1mA, ISD = < 1μA, Low Noise < 40μVRMS, “A” Version Stable with Ceramic Capacitors; DD, TO220-5, SOT-223 and S8 Packages LT3020 100mA, Low Voltage V DO, VIN(MIN) = 0.9V, LDO VIN: 0.9V to 10V, VOUT(MIN) = 0.20V, VDO = 0.15V, IQ = 120μA, ISD = 3μA, DFN and MS8 Packages LT3021 500mA, Low Voltage V DO, VIN(MIN) = 0.9V, LDO VIN: 0.9V to 10V, VOUT(MIN) = 0.20V, VDO = 0.16V, IQ = 120μA, ISD = 3μA, DFN and S8 Packages LT3023 Dual, 2x 100mA, Low Noise Micropower, LDO VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 40μA, ISD = < 1μA, DFN and MS10 Packages LT3024 Dual, 100mA/500mA, Low Noise Micropower, LDO VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 60μA, ISD = < 1μA, DFN and TSSOP Packages LT3027 Dual, 2x 100mA, Low Noise Micropower, LDO with Independent Inputs VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 25μA, ISD = < 1μA, Low Noise < 20μVRMS, DFN and MS10 Packages LT3028 Dual, 100mA/500mA, Low Noise Micropower, LDO with Independent Inputs VIN: 1.8V to 20V, VOUT(MIN) = 1.22V, VDO = 0.30V, IQ = 30μA, ISD = < 1μA, Low Noise < 20μVRMS, DFN and TSSOP Packages ThinSOT is a trademark of Linear Technology Corporation Adjustable Current Source LT1004-1.2 VIN > 2.7V C1 10μF + C4 10μF 80.6k 2.2k R5, 0.01Ω 2.2k LT1965 IN SHDN OUT ADJ GND LT1366 100k LOAD 470Ω 1μF 3.3μF

1965 TA04

NOTE: ADJUST R1 FOR 0A TO 1.1A CONSTANT-CURRENT

Product Information

LTCXX specifications and overview.

Summary

1.1A, Low Noise, Low Dropout Linear Regulator

Description

1.1A, Low Noise, Low Dropout Linear Regulator

Source title LTCXX Datasheet(PDF) - Linear Technology

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