LTC9101-1

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Technical content

Rev. 0For more information www.analog.com Document Feedback n PoE PSE Switches/Routers and Midspans

APPLICATIONS

48-Port IEEE 802.3bt PoE PSE Controller The LT C®9101-1/LTC9102/LTC9103 chipset is a 48-port power sourcing equipment (PSE) controller designed for use in IEEE 802.3at Type 2, 802.3bt Type 3 and 4 compliant Power over Ethernet (PoE) systems. The LTC9101-1/LTC9102/ LTC9103 is designed to power compliant 802.3af, 802.3at, and 802.3bt PDs. The LTC9101-1/LTC9102/LTC9103 chip- set delivers lowest-in-industry heat dissipation by utilizing low-RDS(ON) external MOSFETs and 0.1Ω sense resistance per power channel. A transformer-isolated communication protocol replaces expensive opto-couplers and complex iso- lated 3.3V supply , resulting in significant BOM cost savings. Advanced power management features include per-port 14-bit current/power monitoring, programmable current/ power limits, and versatile fast shut-down of preselected ports. An advanced power management host software layer is available. PD detection uses a proprietary multi - point detection mechanism ensuring excellent immunity from false PD identification. Autoclass and 5-event physi- cal classification are supported. The LTC9101-1/LTC9102 / LTC9103 includes an I2C serial interface operable up to 1MHz. The LTC9101-1/LTC9102/LTC9103 is pin or I2C pro- grammable to negotiate PD delivered power up to 71.3W. n Fully Compliant IEEE 802.3bt Type 3 and 4 PSE n Fully Compliant IEEE 802.3at Type 2 PSE n Software-Compatible with LTC4291-1/LTC4292 n Up to 48 PSE Ports with One Power Channel per Port n Up to 24 PSE Ports with T wo Power Channels per Port n ECC-Protected eFlash and Data RAMs n Low Power Path Dissipation per Channel n 100mΩ Sense Resistance n 30mΩ or Lower MOSFET RDS(ON) n Chipset Provides Electrical Isolation n Eliminates Optos and Isolated 3.3V Supply n Very High Reliability Multipoint PD Detection n Connection Check Distinguishes Single- Signature and Dual-Signature PDs n Continuous Per-Port Power and Current Monitoring n 1MHz I2C Compatible Serial Control Interface n Pin or I2C Programmable PD Power n Available in 24-Lead 4mm × 4mm (LTC9101-1) and a 64-Lead 7mm × 11mm (LTC9102/LTC9103) QFN Packages All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION

FEATURES

ID:11b ID:10b ID:01b V EE >47µF 0.1µF 100V S1B 0.1µF 1µF 100V CPA CNA DPA DNA V EE SENSE1 GATE1 AGND L TC9102/L TC9103 1000BASE-T OUT1 SENSE2 VSSK2 GATE2 OUT2 TX1 TX2 TX3 TX4 RJ45 V EE V EE V EE RESET SCL SDAIN CFG2 CFG1 CFG0 DGND DPD CND V DD L TC9101-1 CPD DND ISOLATION AD2 AD3 SDAOUT AUTO 4PVALID MSD INT 3.3V (NO I C ISOLATION REQUIRED) V EE ONE 4-PAIR PORT SHOWN ID:00b 0.1/uni03A9 V EE VSSK1 0.1/uni03A9 FLASH 0.1µF 100V S1B 1000pF 2kV

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9101123 TA01a

DESCRIPTION

Rev. 0 For more information www.analog.com ABSOLUTE MAXIMUM RATINGS LTC9102/LTC9103 Supply Voltages (with respect to VEE) C 3V to 5V Analog Pins E 3V to 30V C to 85°C Operating Junction Temperature (Note 2) ...–40°C to 125°C (Notes 1, 4) LTC9101-1 Su pply Voltages (with respect to DGND) Digital Pins ADn, AUTO, CFGn, MSD, S DAIN, SDAOUT, Analog Pins C to 85°C Operating Junction Temperature (Note 2) .. –40°C to 125°C (Note 1)

Rev. 0For more information www.analog.com PIN CONFIGURATION ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC9101AUF-1#PBF LTC9101AUF-1#TRPBF 91011 24-Lead (4mm × 4mm) Plastic QFN –40°C to 85°C LTC9102AUKJ#PBF LTC9102AUKJ#TRPBF LTC9102 64-Lead (7mm × 11mm) Plastic QFN –40°C to 85°C LTC9103AUKJ#PBF LTC9103AUKJ#TRPBF LTC9103 64-Lead (7mm × 11mm) Plastic QFN –40°C to 85°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. LTC9101-1 24 23 22 21 20 19 7 8 9 TOP VIEW UF PACKAGE 24-LEAD (4mm × 4mm) PLASTIC QFN θJC = 4°C/W , θJA = 47°C/W EXPOSED PAD (PIN 25) IS DGND, MUST BE SOLDERED TO PCB 10 11 12 18CFG0 CFG1 CFG2 DNC AD2 AD3 SCL SDAIN SDAOUT INT RESET 4PVALID VDD CAP1 DGND MSD AUTO V DD CAP2 CPD CND DPD DND V DD DGND LTC9102 LTC9103 TOP VIEW VEE UKJ PACKAGE 64-LEAD (7mm × 11mm) PLASTIC QFN θJC = 1°C/W, θJA = 22°C/W EXPOSED PAD (PIN 65) IS VEE, MUST BE SOLDERED TO PCB CAP3 1 EXT3 2 GATE1 3 OUT1 4 SENSE1 5 VSSK1 6 VSSK2 7 SENSE2 8 OUT2 9 GATE2 10 GATE3 11 OUT3 12 SENSE3 13 VSSK3 14 VSSK4 15 SENSE4 16 OUT4 17 GATE4 18 GATE5 19 OUT5 20

52 ID1

51 ID0

50 GATE12

49 OUT12

48 SENSE12

47 VSSK12

46 VSSK11

45 SENSE11

44 OUT11

43 GATE11

42 GATE10

41 OUT10

40 SENSE10

39 VSSK10

38 VSSK9

37 SENSE9

36 OUT9

35 GATE9

34 GATE8

33 OUT8

64 CPA

63 CNA

62 DPA

61 DNA

59 CAP4

58 PWRMD0

57 PWRMD1

56 AGND

55 PWRIN

64-LEAD (7mm × 11mm) PLASTIC QFN θJC = 1°C/W, θJA = 22°C/W EXPOSED PAD (PIN 65) IS VEE, MUST BE SOLDERED TO PCB CAP3 1 EXT3 2 GATE1 3 OUT1 4 SENSE1 5 VSSK1 6 VSSK2 7 SENSE2 8 OUT2 9 GATE2 10 GATE3 11 OUT3 12 SENSE3 13 VSSK3 14 VSSK4 15 SENSE4 16 OUT4 17 GATE4 18 NC 19 NC 20

50 GATE8

49 OUT8

48 SENSE8

47 VSSK8

46 VSSK7

45 SENSE7

44 OUT7

43 GATE7

42 GATE6

41 OUT6

40 SENSE6

39 VSSK6

38 VSSK5

37 SENSE5

36 OUT5

35 GATE5

Rev. 0 For more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main PoE Supply Voltage AGND – VEE Type 2 or 3 Compliant Output Type 4 Compliant Output l l V V LTC9102/LTC9103 Under voltage Lock-Out AGND – V EE l 8.2 9 V VDD VDD Supply Voltage VDD – DGND l 3 3.3 3.6 V Undervoltage Lock-Out 2.8 V VDD Slew Rate, Falling 2.4 ≤ VDD – DGND ≤ 3.0 (Note 7) 20 mV/μs VCAP1, VCAP2 Internal Regulator Supply Voltage VCAP1 – DGND, VCAP2 – DGND (Note 13) 1.2 V VCAP3 Internal 3.3V Regulator Supply Voltage CAP3 – V EE (Note 13) l 3 3.3 3.6 V tCAP3EXT CAP3 External Supply Rise Time 0.5V < CAP3 < CAP3(Min), EXT3 Tied to CAP3 (Note 7) l 1 ms VCAP4 Internal 4.3V Regulator Supply Voltage CAP4 – V EE (Note 13) l 4.3 V IEE VEE Supply Current PWRIN Pin Connected to AGND, EXT3 LOW , All Gates Fully Enhanced. 7.7 11 14 mA I DD VDD Supply Current (VDD – DGND) = 3.3V l 40 60 mA Detection/Connection Check Forced Current Load Resistance 15.5k to 32k l l 220 143 240 160 260 180 µA µA Forced V oltage Load Resistance 18.5k to 27.5k l l V V Detection/Connection Check Current Compliance AGND – OUTn = 0V l 0.8 0.9 mA VOC Detection/Connection Check Voltage Compliance AGND – OUTn, Open Port l 10.4 12 V Detection/Connection Check Voltage Slew Rate AGND – OUTn, C PORT = 150nF (Note 7) l 0.01 V/µs Min. Valid Signature Resistance l 15.5 17 18.5 kΩ Max. Valid Signature Resistance l 27.5 29.7 32 kΩ Classification VCLASS Classification Voltage AGND – OUTn, SENSEn – VSSKn < 5mV l 16 20.5 V Classification Current Compliance SENSEn – VSSKn, OUTn = AGND (Note 15) l 7 8 9 mV Classification Threshold SENSEn – VSSKn (Note 15) Class Signature 0 – 1 Class Signature 1 – 2 Class Signature 2 – 3 Class Signature 3 – 4 Class Signature 4 – Overcurrent l l l l l 0.5 1.3 2.1 3.1 4.5 0.65 1.45 2.3 3.3 4.8 0.8 1.6 2.5 3.5 5.1 mV mV mV mV mV V MARK Classification Mark State Voltage AGND – OUTn, SENSEn – VSSKn < 5mV l 7.5 9 10 V Mark State Current Compliance OUTn = AGND l 7 8 9 mV Gate Driver GATE Pin Pull-Down Current Port Off, GATEn = VEE + 5V 1 mA GATE Pin Fast Pull-Down Current GATEn = VEE + 5V 65 mA GATE Pin On Voltage GATEn – VEE, IGATEn = 1µA l 11 14 V ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 55V and VDD – DGND = 3.3V unless otherwise noted. (Notes 3 and 4)

Rev. 0For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 55V and VDD – DGND = 3.3V unless otherwise noted. (Notes 3 and 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Output Voltage Sense VPG Power Good Threshold Voltage OUTn – VEE l 2 2.4 2.8 V OUT Pin Pull-Up Resistance to AGND Port On Port Off l 300 2500 500 700 kΩ kΩ Current Sense VLIM-2P Active Current Limit, Single-Signature PD OUTn – VEE < 10V Class 1 – Class 3 Class 4 – Class 6 Class 7 Class 8 l l l l 100 110 42.5 106 117 112 124 mV mV mV mV Active Current Limit, Dual-Signature PD OUTn – V EE < 10V Class 1 – Class 3 Class 4 Class 5 l l l 110 42.5 117 124 mV mV mV V INRUSH-2P Active Current Limit, Inrush OUTn – VEE < 30V (Note 16) Single-Signature, Class 1–4, 4-Pair Power All Others l l 21.3 42.5 22.5 mV mV V HOLD-2P DC Disconnect Sense Voltage SENSEn – VSSKn Single-Signature Class 1–4, 4-Pair Power Single-Signature Class 1–4, 2-Pair Power Single-Signature Class 5–8, 4-Pair Power Dual Signature, 2-Pair or 4-Pair Power l l l l 200 500 200 200 350 700 350 350 500 900 700 700 µV µV µV µV V SC Short-Circuit Sense SENSEn – VSSKn – VLIM-2P 60 mV Port Current Readback (See Typical Performance Characteristics, Note 17) Full-Scale Range (Notes 7, 15) 204.6 mV LSB Weight |SENSEn – VSSKn|, VSSKn = VEE (Note 15) 24.98 μV/LSB Conversion Period 1.967 ms VEE Readback (See Typical Performance Characteristics, Note 17) Full-Scale Range (Note 7) 82 V LSB Weight |AGND – VEE| 10.01 mV/LSB Conversion Period 1.967 ms Digital Interface VILD Digital Input Low Voltage ADn, RESET, MSD, CFGn, AUTO, 4PVALID (Note 6)l 0.8 V I2C Input Low Voltage SCL, SDAIN (Note 6) l 1 V VIHD Digital Input High Voltage (Note 6) l 2.2 V Digital Output Low Voltage ISDAOUT = 3mA, IINT = 3mA ISDAOUT = 5mA, IINT = 5mA l l 0.4 0.7 V V Internal Pull-Up to V DD ADn, RESET, MSD, CFG2 50 kΩ Internal Pull-Down to DGND AUTO, 4PVALID, CFG0 50 kΩ EXT3 Pull-Down to VEE 50 kΩ IDn Internal Pull-Up to CAP4 IDn = 0V 5 μA

Rev. 0 For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 55V and VDD – DGND = 3.3V unless otherwise noted. (Notes 3 and 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS PSE Timing Characteristics (Note 7) tDET Detection Time Beginning to End of Detection l 380 500 ms tCLASS_RESET Classification Reset Duration l 15 ms tCEV Class Event Duration l 6 15 20 ms tCEVON Class Event Turn On Duration CPORT = 0.6µF l 0.1 ms tLCE Long Class Event Duration l 88 105 ms tCLASS Class Event ICLASS Measurement Timing l 6 ms tCLASS_LCE Long Class Event ICLASS Measurement Timing l 6 75 ms tCLASS_ACS Autoclass ICLASS Measurement Timing l 88 105 ms tME1 Mark Event Duration (Except Last Mark Event) (Note 11) l 6 9.6 12 ms tME2 Last Mark Event Duration (Note 11) l 6 20 ms tPON Power On Delay, Auto Mode From End of Valid Detect to End of Valid Inrush (Note 14) l 400 ms tAUTO_PSE1 Autoclass Power Measurement Start From End of Inrush to Beginning of Autoclass Power Measurement l 1.4 1.6 s tAUTO_PSE2 Autoclass Power Measurement End From End of Inrush to End of Autoclass Power Measurement l 3.1 3.5 s tAUTO_WINDOW Autoclass Average Power Sliding Window l 0.15 0.23 0.3 s tED Fault Delay From Power On Fault to Next Detect l 1.0 1.3 1.8 s tSTART Maximum Current Limit Duration During Inrush l 50 60 75 ms tCUT Maximum Overcurrent Duration After Inrush l 50 65 75 ms Maximum Overcurrent Duty Cycle l 5.8 6.3 6.7 % tLIM Maximum Current Limit Duration After Inrush (Note 12) Type 3, t LIMn = 0x8 Type 4, tLIMn = 0x5 l l ms ms t MPS Maintain Power Signature (MPS) Pulse Width Sensitivity Current Pulse Width to Reset Disconnect Timer (Note 8) l 6 ms tDIS Maintain Power Signature (MPS) Dropout Time (Note 5) l 320 370 400 ms tMSD Masked Shut Down Delay 6.5 µs I2C Watchdog Timer Duration l 1.5 2 3 s Minimum Pulse Width for Masked Shut Down l 3 µs Minimum Pulse Width for RESET l 4.5 µs

Rev. 0For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 55V and VDD – DGND = 3.3V unless otherwise noted. (Notes 3 and 4) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifespan. Note 2: This chipset includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 140°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: All currents into device pins are positive; all currents out of device pins are negative. Note 4: The LTC9102/LTC9103 operates with a negative supply voltage (with respect to AGND). To avoid confusion, voltages in this data sheet are referred to in terms of absolute magnitude. Note 5: t DIS is the same as tMPDO defined by IEEE 802.3. Note 6: The LTC9101-1 digital inter face operates with respect to DGND. All logic levels are measured with respect to DGND. Note 7: Guaranteed by design, not subject to test. Note 8: The IEEE 802.3 defines MPS as the set of minimum PSE and PD input current requirements to maintain power . An LTC9101-1/LTC9102/ LTC9103 port resets its MPS timer when V SENSEn – VSSKn ≥ VHOLD-2P for tMPS and removes port power when VSENSEn – VSSKn ≥ VHOLD-2P for a period longer than tDIS. See Disconnect section. Note 9: Values Measured at VIHD. Note 10: If a fault condition occurs during an I2C transaction, the INT pin will not be pulled down until a stop condition is present on the I2C bus. Note 11: Load characteristics of the LTC9102/LTC9103 during Mark: 7V < (AGND – VOUTn) < 10V. Note 12: See the LTC9101-1 Software Programming documentation for information on serial bus usage and device configuration and status registers. Note 13 : Do not source or sink current from CAP1, CAP2, CAP3 and CAP4. Note 14: For single-signature PDs, tPON is measured from end of valid detect on either power channel. For dual-signature PDs, tPON is measured from the end of valid detect on the same power channel. Note 15: Port current and port power measurements depend on sense resistor value (0.1Ω typical). See External Component Selection for details. Note 16: See Inrush Control for details on inrush threshold selection. Note 17: ADC characteristics and typical performance are described in terms of LTC9102/LTC9103 hardware capability. Measurements from LTC9102/LTC9103 are processed and synthesized by LTC9101-1 to maintain backwards compatibility with LTC4291 software interface. See LTC9101-1 Software Interface for register descriptions and LSB weights (port current, port power , V EE voltage, and system temperature). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I2C Timing (Note 7) fSCLK Clock Frequency l 1 MHz t1 Bus Free Time Figure 5 (Note 9) l 480 ns t2 Start Hold Time Figure 5 (Note 9) l 240 ns t3 SCL Low Time Figure 5 (Note 9) l 480 ns t4 SCL High Time Figure 5 (Note 9) l 240 ns t5 SDAIN Data Hold Time Figure 5 (Note 9) l 60 ns Data Clock to SDAOUT Valid Figure 5 (Note 9) l 250 ns t6 Data Set-Up Time Figure 5 (Note 9) l 80 ns t7 Start Set-Up Time Figure 5 (Note 9) l 240 ns t8 Stop Set-Up Time Figure 5 (Note 9) l 240 ns tr SCL, SDAIN Rise Time Figure 5 (Note 9) l 120 ns tf SCL, SDAIN Fall Time Figure 5 (Note 9) l 60 ns Fault Present to INT Pin Low (Notes 9, 10) l 150 ns Stop Condition to INT Pin Low (Notes 9, 10) l 1.5 µs ARA to INT Pin High Time (Note 9) l 1.5 µs SCL Fall to ACK Low (Note 9) l 250 ns

Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS 802.3bt Single-Signature Class Probe and Demotion 802.3bt Dual-Signature Power-On Sequence Open Circuit Detection Inrush Current Limit (Note 16) Power-On Current Limits Single-Signature 802.3bt Single-Signature Power-On Sequence, 4-Pair 802.3bt Single-Signature Classification and Power-On, 4-Pair 802.3bt Single-Signature Power-On Sequence, 2-Pair SENSE = 0.1Ω unless otherwise specified.) DETECTION/ CONNECTION CHECK CLASSIFICATION POWER ON V EE OUT1A OUT1B 200ms/DIV –60 –50 –40 –30 –20 –10 CHANNEL VOL TAGE (V)

9101123 G01

V EE CLASS8 OUT1A OUT1B 50ms/DIV –60 –50 –40 –30 –20 –10 CHANNEL VOL TAGE (V)

9101123 G02

V EE 100ms/DIV –60 –50 –40 –30 –20 –10 CHANNEL VOL TAGE (V)

9101123 G03

V EE CLASS5 DETECTION/ CONNECTION CHECK OUT1A OUT1B 200ms/DIV –60 –50 –40 –30 –20 –10 CHANNEL VOL TAGE (V)

9101123 G04

V EE CLASS8 PROBE CLASS 8 CLASS RESET DEMOTION OUT1A OUT1B 50ms/DIV –60 –50 –40 –30 –20 –10 CHANNEL VOL TAGE (V)

9101123 G05

9101123 G06

LIMn = 80h LIMn = 08h OUTn – V EE (V) 100 120 200 400 600 800 1000 1200 V INRUSH-2P (mV) I INRUSH-2P (mA)

9101123 G07

AGND – V EE = 55V CLASS 1–3 CLASS 4–6 CLASS 7 CLASS 8 OUTn – V EE (V) 100 120 200 400 600 800 1000 1200 V LIM–2P (mV) I LIM–2P (mA)

9101123 G08

AGND – V EE = 55V

Rev. 0For more information www.analog.com Power-On Current Limits Dual-Signature CLASS 1–3 CLASS 4 CLASS 5 OUTn – V EE (V) 100 120 200 400 600 800 1000 1200 V LIM-2P (mV) I LIM-2P (mA)

9101123 G09

AGND – V EE = 55V ILIM-2P vs Temperature LIMn = 80h OUTn = V EE T A (°C) –40 –20 100 400 410 420 430 440 450 V LIM–2P (mV) I LIM–2P (mA)

9101123 G10

TYPICAL PERFORMANCE CHARACTERISTICS(RSENSE = 0.1Ω unless otherwise specified.) Classification Current Compliance Port Current Readback Port Current Readback Offset Port Current Readback LSB Port Current Readback vs Temperature CLASSIFICATION CURRENT (mA) SENSEn – VSSKn (mV) 100(mA) 10(mV) –20 –16 –12 OUTn (V)

9101123 G11

N = 4488 µ = 89.610 σ = 0.252 SENSEn – VSSKn = 89.6mV 24.98µV/LSB READBACK (mV) 88.1 88.6 89.1 89.6 90.1 90.6 91.1 100 200 300 400 500 600 700 NUMBER OF ADCS

9101123 G12

N = 4476 µ = 10.931 σ = 14.363 SENSEn – VSSKn = 0 24.98µV/LSB READBACK (µV) –100 –75 –50 –25 100 500 1000 1500 2000 2500 NUMBER OF ADCS

9101123 G13

N = 4488 µ = 24.980 σ = 0.070 (µV/LSB) 24.6 24.7 24.8 24.9 25.0 25.1 25.2 25.3 25.4 100 200 300 400 500 NUMBER OF ADCS

9101123 G14

SENSEn – VSSKn = 100mV 24.98µV/LSB T A (°C) –40 –20 100 99.6 99.8 100.0 100.2 100.4 100.6 100.8 READBACK (mV)

9101123 G15

Rev. 0 For more information www.analog.com VEE Readback VEE Readback vs Temperature VEE Supply Current vs Voltage and Temperature N = 364 µ = 54.998 σ = 0.058 AGND – V EE = 55V 10.01mV/LSB READBACK (V) 54.7 54.8 54.9 55.0 55.1 55.2 55.3 NUMBER OF ADCS

9101123 G16

AGND – V EE = 55V 10.01mV/LSB T A (°C) –40 –20 100 54.5 54.6 54.7 54.8 54.9 55.0 55.1 55.2 READBACK (V)

9101123 G17

85°C 25°C –40°C AGND – V EE (V) I EE (mA)

9101123 G18

TYPICAL PERFORMANCE CHARACTERISTICS CLOCK and DATA READ EYE DIAGRAM CLOCK and DATA WRITE EYE DIAGRAM LTC9102/LTC9103 CP/CN and DP/DN Common Mode Correction Current Port Power Readback vs Temperature Powering Up into 180μF Short Circuit Recovery SENSE = 0.1Ω unless otherwise specified.) AGND – V EE = 55V SENSEn – VSSKn = 100mV POWERn = 55W T A (°C) –40 –20 100 54.5 54.6 54.7 54.8 54.9 55.0 55.1 55.2 55.3 55.4 55.5 READBACK (W)

9101123 G19

V EE FOLDBACK CURRENT LIMIT LOAD FULL Y CHARGED MOSFET ON 5ms/DIV OUT1A 20V/DIV GATE1A 10V/DIV CHANNEL CURRENT 200mA/DIV

9101123 G20

QUICK CURRENT LIMIT RECOVERY V EE = –55V LIMn = E9h 50µs/DIV GATE 10V/DIV OUT 50V/DIV OUT CURRENT 5A/DIV

9101123 G21

N = 337 CP – CN DP – DN 10ns/DIV 200mV/ DIV

9101123 G22

N = 570 CP – CN DP – DN 10ns/DIV 200mV/ DIV

9101123 G23

V CM (V) 0.5 1.5 2.5 3.5 I CM (mA)

9101123 G24

Figure 1. Detect, Class and Turn-On Timing, 4-Pair Port, Primary Alternative, Auto or Semi-Auto Mode

9101123 F01

9101123 G25

9101123 G26

9101123 G27

Figure 2. Current Timings Figure 3. DC Disconnect Timing, 2-Pair System Figure 4. Shut Down Delay Timing Figure 5. I2C Interface Timing

9101123 F02a

9101123 F02b

9101123 F04

9101123 F05

Figure 6. Writing to a Register Figure 7. Reading from a Register Figure 8. Reading the Interrupt Register (Short Form) Figure 9. Reading from Alert Response Address

9101123 F06

9101123 F07

9101123 F08

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Rev. 0 For more information www.analog.com PIN FUNCTIONS LTC9101-1 CFG[2:0] (Pins 3, 2, 1 Respectively): Device Configuration Inputs. Tie the configuration pins high or low to set num- ber of ports, channels per port, and number of connected LTC9102/LTC9103s. See Device Configuration for details. CFG[0] is ignored when a custom configuration package is present. See Stored Configurations for details. AD[3:2] (Pins 6, 5 Respectively): I2C Address Bits 3 to 2. Tie the address pins high or low to set the base I 2C serial address. The base address will be (010A 3A200)b. Internally pulled up to VDD. See Bus Addressing for details. CAP[2:1] (Pins 7, 23 Respectively): Core Power Supply Bypass Capacitors. Connect each pin to a 1μF capacitance to DGND for the internal 1.2V regulator bypass. Do not use other capacitor values. Do not source or sink current from this pin. CPD (Pin 8): Clock T ransceiver Positive Input Output (Digital). Connect to CPA through a data transformer . CND (Pin 9): Clock T ransceiver Negative Input Output (Digital). Connect to CNA through a data transformer . DPD (Pin 10): Data T ransceiver Positive Input Output (Digital). Connect to DPA through a data transformer . DND (Pin 11): Data T ransceiver Negative Input Output (Digital). Connect to DNA through a data transformer . VDD (Pins 12, 19, 24): VDD IO Power Supply. Connect to a 3.3V power supply relative to DGND. Each V DD pin must be locally bypassed with at least a 0.1µF capacitor . A 10µF bulk capacitor must be connected across VDD for increased surge immunity. 4PVALID (Pin 13): 4-Pair Valid Input, Active Low. When low, the LTC9101 -1/LTC9102 /LTC9103 will not apply power to a port unless both pairsets present a valid signa- ture. When high, the LTC9101 -1/LTC9102/LTC9103 will power any pairset presenting a valid signature, regard - less of the other pairset. Ports in 2-pair or AT mode are unaffected by 4-Pair Valid setting. Internally pulled down to DGND. 4PVALID pin is ignored when a custom con - figuration package is present. See Stored Configurations for details. RESET (Pin 14) : Reset Input, Active Low. When RESET is low, the LTC9101-1/LTC9102/LTC9103 is held inactive with all ports off and all internal registers reset. When RESET is pulled high, the LTC9101-1/LTC9102/LTC9103 begins normal operation. RESET can be connected to an external capacitor or RC network to provide a power turn- on delay. Internal filtering of RESET prevents glitches less than 1µs wide from resetting the LTC9101 -1/LTC9102 / LTC9103. Internally pulled up to VDD. INT (Pin 15): Interrupt Output, Open Drain. INT will pull low when any one of several events occur in the LTC9101-1. It will return to a high impedance state when bits 6 or 7 are set in the Reset PB register (0x 1A). The INT signal can be used to generate an interrupt to the host processor , eliminating the need for continuous soft- ware polling. Individual INT events can be disabled using the Int Mask register (0x01). See LTC9101 -1 Software Programming documentation for more information. INT is only updated between I 2C transactions. SDAOUT (Pin 16): Serial Data Output, Open Drain Data Output for the I 2C Serial Interface Bus. The LTC9101 -1 uses two pins to implement the bidirectional SDA func - tion to simplify opto isolation of the I 2C bus. To imple- ment a standard bidirectional SDA pin, tie SDAOUT and SDAIN together . See Applications Information for more information. SDAIN (Pin 17): Serial Data Input. High impedance data input for the I2C serial interface bus. The LTC9101-1 uses two pins to implement the bidirectional SDA function to simplify opto isolation of the I2C bus. To implement a stan- dard bidirectional SDA pin, tie SDAOUT and SDAIN together . See Applications Information for more information. SCL (Pin 18): Serial Clock Input. High impedance clock input for the I2C serial interface bus. The SCL pin should be connected directly to the I2C SCL bus line. SCL must be tied high if the I2C serial interface bus is not used.

Rev. 0For more information www.analog.com PIN FUNCTIONS AUTO (Pin 20): Auto Mode Input, Active High. Auto mode allows the LTC9101 -1 to detect, classify, and power up valid PDs without host interaction. AUTO determines the state of the internal registers when the LTC9101 -1 is reset or comes out of UVLO (see LTC9101 -1 Software Programming documentation). See Auto Mode Maximum PSE Power for details. The state of these register bits can subsequently be changed via the I2C interface. Internally pulled down to DGND. The AUTO pin is ignored when a custom configuration package is present. See Stored Configurations for details. MSD (Pin 21): Maskable Shutdown Input, Active Low. When pulled low, all ports that have their corresponding mask bit set in the mconf register (0x17) will be reset. Internal filtering of MSD prevents glitches less than 1µs wide from resetting ports. The MSD Pin Mode register can configure MSD polarity. Internally pulled up to VDD. DGND (Pins 22, 25): Digital Ground. DGND should be connected to the return from the VDD supply. LTC9102/LTC9103 COMMON CAP3 (Pin 1): Analog Internal 3.3V Power Supply Bypass Capacitor . Connect a 1μF ceramic cap to VEE. A 3.3V power supply may be connected to this pin to improve power supply efficiency. The EXT3 pin must be pulled to CAP3 to shut off the internal 3.3V regulator if power is supplied externally. Do not source or sink current from this pin. Do not connect to CAP3 except as explicitly instructed in ADI documentation (e.g., strapping LTC9102/ LTC9103 pins and terminating the serial interface). EXT3 (Pin 2): External 3.3V Enable. Connect the EXT3 pin to CAP3 to shut off the internal 3.3V regulator when power is supplied externally. Float or connect to V EE for internal regulator operation. ID[1:0] (Pins 52, 51 respectively): T ransceiver ID. Sets the address of the LTC9102/LTC9103 on the multidrop high-speed data interface. ID numbering must start at 00b. Tie high by connecting to CAP3. Tie low by connect- ing to VEE. See Device Configuration section for details. PWRIN (Pin 55): Startup Regulator Bypass and External Low Voltage Supply Input. Power for the internal 4.3V and 3.3V internal supplies. An internal regulator maintains the voltage of this pin above 6V. An external resistor or supply may be connected to this node to improve the power efficiency of the LTC9102/LTC9103. Connect a 1µF capacitor between this pin and VEE. AGND (Pin 56): Analog Ground. PWRMD[1:0] (Pins 57, 58 Respectively): Maximum Power Mode Input. Connect PWRMD0 of the LTC9102/ LTC9103 with ID[1:0] = 00b to V EE with configuration resistor RPWRMD. When the LTC9101-1 is reset with AUTO pin high, RPWRMD selects initial maximum power alloca- tion values for every port in the chipset; the system power supply must be sized to support all ports outputting up to RPWRMD. When auto mode is enabled, the chipset runs independently as a PoE PSE. The chipset will detect and class all ports and grant power to each port up to RPWRMD setting. The PWRMD0 pin of LTC9102/LTC9103s with ID pins set to 01b, 10b, and 11b must be left floating. The PWRMD1 pin of all LTC9102/LTC9103s must be left float- ing. See Auto Mode Maximum PSE Power for R PWRMD options and details. The PWRMD pins are ignored when a custom configuration package is present. See Stored Configurations for details. CAP4 (Pin 59): Analog Internal 4.3V Power Supply Bypass Capacitor . Connect a 1μF ceramic cap to VEE. Do not source or sink current from this pin. VEE (Pins 60, 65): Main PoE Supply Input. Connect to a –51V to –57V supply, relative to AGND. Voltage depends on PSE Type (Type 3 or 4). DNA (Pin 61): Data T ransceiver Negative Input Output (Analog). Connect to DND through a data transformer . DPA (Pin 62): Data T ransceiver Positive Input Output (Analog). Connect to DPD through a data transformer . CNA (Pin 63): Clock T ransceiver Negative Input Output (Analog). Connect to CND through a data transformer . CPA (Pin 64): Clock T ransceiver Positive Input Output (Analog). Connect to CPD through a data transformer .

Rev. 0 For more information www.analog.com PIN FUNCTIONS GATE[12:1] (Pins 50, 43, 42, 35, 34, 27, 26, 19, 18, 11, 10, 3 Respectively): Gate Drive, channel n. Connect GATEn to the gate of the external MOSFET for channel n. When the MOSFET is turned on, the gate voltage is driven to 12V (typ) above VEE. During a current limit condition, the voltage at GATEn will be reduced to maintain constant current through the external MOSFET . If the fault timer expires, GATEn is pulled down, turning the MOSFET off and raising a port fault event. If the channel is unused, the GATEn pin must float. LTC9103 EXCLUSIVE VSSK[8:1] (Pins 47, 46, 39, 38, 15, 14, 7, 6 Respectively): See LTC9102 VSSK[12:1]. SENSE[8:1] (Pins 48, 45, 40, 37, 16, 13, 8, 5 Respectively): See LTC9102 SENSE[12:1]. OUT[8:1] (Pins 49, 44, 41, 36, 17, 12, 9, 4 Respectively): See LTC9102 OUT[12:1]. GATE[8:1] (Pins 50, 43, 42, 35, 18, 11, 10, 3 Respectively): See LTC9102 GATE[12:1]. COMMON PINS NC, DNC (LTC9101 -1 Pin 4; LTC9102 Pins 53, 54; LTC9103 Pins 19– 34, 53, 54): All pins identified with “NC” or “DNC” must be left unconnected. LTC9102 EXCLUSIVE VSSK[12:1] (Pins 47, 46, 39, 38, 31, 30, 23, 22, 15, 14, 7, 6 Respectively): Kelvin Sense to V EE. Connect to VEE side of sense resistor for channel n through a 0.1Ω resistor . Do not connect directly to VEE plane. See Kelvin Sense layout requirements. SENSE[12:1] (Pins 48, 45, 40, 37, 32, 29, 24, 21, 16, 13, 8, 5 Respectively): Current Sense Input, channel n. SENSEn monitors the external MOSFET current via a 0.1Ω sense resistor between SENSEn and VSSKn. If the voltage across the sense resistor reaches the current limit thresh- old ILIM-2P, the GATEn pin voltage is lowered to maintain constant current in the external MOSFET . See Applications Information for further details. If the channel is unused, tie SENSEn to V EE. 12, 9, 4 Respectively): Output Voltage Monitor , channel n. Connect OUTn to the output channel. A current limit foldback circuit limits the power dissipation in the external MOSFET by reducing the current limit threshold when the drain-to-source voltage exceeds 10V. A port power good event is raised when the voltage from OUTn to V EE drops below 2.4V (typ). A 500k resistor is connected internally from OUTn to AGND when the channel is idle. If the chan- nel is unused, the OUTn pin must float.

Rev. 0For more information www.analog.com OVERVIEW Power over Ethernet, or PoE, is a standard protocol for sending DC power over copper Ethernet data wiring. The IEEE group that administers the 802.3 Ethernet data standards added PoE powering capability in 2003. This original PoE standard, known as 802.3af, allowed for 48V DC power at up to 13W. 802.3af was widely popular , but 13W was not adequate for some applications. In 2009, the IEEE released a new standard, known as 802.3at or PoE+, increasing the voltage and current requirements to provide 25.5W of delivered power . IEEE 802.3af and 802.3at are commonly known as PoE 1. In 2018, the IEEE released the latest PoE standard, known as 802.3bt or PoE 2. 802.3bt maximizes PD delivered power at 71.3W. The IEEE standard also defines PoE terminology. A device that provides power to the network is known as a PSE, or power sourcing equipment, while a device that draws power from the network is known as a PD, or powered device. PSEs come in two types: endpoints (typically net- work switches or routers), which provide data and power; and midspans, which provide power but pass through data. Midspans are typically used to add PoE capabil - ity to existing non-PoE networks. PDs are typically IP phones, wireless access points, security cameras, and similar devices. PoE++ Evolution Even during the development of the IEEE 802.3at (PoE 1) 25.5W standard, it became clear there was a significant and increasing need for more than 25.5W of delivered power . In 2013, the 802.3bt task force was formed to develop a standard capable of increasing delivered PD power . The primary objective of the task force is to use all four pairs of the Ethernet cable as opposed to the two pair power utilized by 802.3at. Using all four pairs allows for at least twice the delivered power over existing Ethernet cables. Further , the amount of current per two pairs (known as a pairset) has been increased while maintain- ing the Ethernet data signal integrity. 802.3bt increases PD delivered power from 25.5W to 71.3W, enabling IEEE- compliant high power PD applications. APPLICATIONS INFORMATION The LTC9101-1/LTC9102/LTC9103 delivers power over one or two power channels when configured in 2-pair or 4-pair mode, respectively. Each pairset is driven by a dedi- cated power channel. In this data sheet, the term “chan- nel” refers to the PSE circuitry assigned to a correspond- ing pairset. For the purposes of this document, the terms channel and pairset may be considered interchangeable. In addition, IEEE 802.3bt enables substantially lower Maintain Power Signature (MPS) currents, resulting in significantly lower standby power consumption. This allows new and emerging government or industry standby regulations to be met using standard PoE components. LTC9101-1/LTC9102/LTC9103 Product Overview The LTC9101-1/LTC9102/LTC9103 is a sixth generation PSE controller that implements up to 24 (71.3W) 4-pair or 48 (25.5W) 2-pair PSE ports in either an endpoint or midspan application. Virtually all necessary circuitry is included to implement an IEEE 802.3bt compliant PSE design, requiring a pair of external power MOSFETs and sense resistors per port; these minimize power loss com- pared to alternative designs with onboard MOSFETs, and increase system reliability. The LTC9101-1/LTC9102/LTC9103 chipset implements a proprietary isolation scheme for inter-chip commu - nication. This architecture substantially reduces BOM cost by replacing expensive opto-isolators and isolated power supplies with a single low-cost transformer . A single LTC9101-1 is capable of controlling a bus of up to 4 LTC9102s/LTC9103s over this transformer-isolated interface. Direct connection of the LTC9101 -1 and the associated LTC9102s/LTC9103s is also possible. The LTC9101-1/LTC9102/ LTC9103 offers configurable interrupt signal triggered by per-port events, per-channel power on control and fault telemetry, per-port current monitoring, VEE monitoring, and one second rolling cur- rent, voltage and port power averaging. The LTC9101-1/LTC9102/LTC9103 also offers advanced sixth-generation PSE features including internal eFlash for storage of firmware updates and custom user configura- tion packages, 2-pair operation in 802.3at-compliant or 802.3b t-compliant mode, I 2C quad virtualization for full

power to 25.5W and supports PD Classes 0 to 4. utilized, also referred to as 4-pair power (see Figure 12). Classes 0 to 8 and dual-signature PD Classes 1 to 5. figuration package. See Stored Configurations for details. pins, and improvements to cable surge ride through. of whether the ports are in 2-pair mode or 4-pair mode.

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Figure 10. 2-Pair , Alternative A (Endpoint), Power over Ethernet Single-Signature PD System Diagram

PD Types (as supported by the PD application). Table 1. PSE Maximum Delivered Power , Per-Port *Indicates PD allocated less power than requested. designed to be interoperable. Table 2. 802.3at vs 802.3bt Features of a current fault or short circuit. power than the PSE has available. receiving power over all four pairs (both pairsets). signatures, one to each pairset (see Figure 12).

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Figure 11. 4-Pair Power over Ethernet Single-Signature PD System Diagram

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Figure 12. 4-Pair Power over Ethernet Dual-Signature PD System Diagram

sum of the requested power on both pairsets. possible power levels: 62W or 71.3W. requested power on both pairsets. identification of existing and new PD Classes. advertise Type 3 and 4 feature support to attached PDs. cation and losses in the Ethernet cabling (Table 3). Programming documentation for details. Table 3. IEEE-Specified Power Allocations, Single-Signature PD status and control for four PoE ports. control and status via channel A control and status. state, channel A state and channel B state. likewise are bifurcated to allow per-channel control.

configured in either 2-pair or 4-pair mode. of 2-pair (25.5W) ports and 4-pair (up to 71.3W) ports. Table 4. Device Configuration Options

shutdown, disables the port (see Table 5). Table 5. Operating Modes to apply or remove power at any time. must enable detection and classification. Auto Mode Maximum PSE Power section. any port or channel, as appropriate, that generates a fault. mand the port to remove power at any time. LTC9101-1/LTC9102/LTC9103 until a reset occurs. Table 6. Typical Auto Mode Power On Thresholds,

signature PD, a dual-signature PD, or an invalid result. device is added or removed during connection check. Connection check only affects operation in 4-pair mode. nection check unless the port is in AT mode. See Figure 1. connected device is a valid PD before applying power . above 33k or below 15k (shaded regions in Figure 13).

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Table 7. Typical Auto Mode Power On Thresholds, PD, a dual-signature PD or an invalid result. Figure 11. A single-signature PD presents the same 25k detection resistor to both the pairsets in parallel. single-signature and dual-signature PDs. ments, at the same forced voltage, on the first channel.

forced current and forced voltage measurements. the OUTn pin) and the resulting voltages are measured. and the resulting currents are measured and subtracted. the possible detection results. Detection is enabled in both 2-pair and 4-pair modes. Detection is always performed on a per-channel basis.

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Table 8. Port Detection Status Table 9. Channel Detection Status and return to idle to wait for another command. the end of each detection/classification cycle.

Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION In semi-auto mode, if a valid signature resistance is detected and classification is enabled, the port will clas - sify the PD and report that result as well. The port will then wait for at least 100ms, and will repeat the detection cycle to refresh the data in the Port Status registers. The port will not turn on in response to a power-on com- mand unless the current detect result is Detect Valid. Any other detect result will generate a tSTART fault if a power-on command is received. Behavior in Auto mode is similar to semi-auto; however , after Detect Valid is reported and the port is classified, it is automatically powered on without host intervention. In auto mode the ICUT-2P, ILIM-2P, and PCUT-4P thresholds are automatically set; see the Reset and the AUTO Pin section for more information. Detection is disabled for a port when the LTC9101-1/ LTC9102/LTC9103 is initially powered up with AUTO low, when the port is in shutdown mode, or when the corre - sponding Detect Enable bit is cleared. Detection of Legacy PDs Proprietary PDs that predate the original IEEE 802. 3af stan- dard are commonly referred to today as legacy PDs. One type of legacy PD uses a large common-mode capacitance (>10μF) as the detection signature. Note that PDs in this range of capacitance are defined as invalid, so a PSE that pow- ers legacy PDs is noncompliant with the IEEE standard. The LTC9101-1/LTC9102/LTC9103 can be configured to detect this type of legacy PD. Legacy detection is disabled by default, but can be manually enabled on a per-port basis. When enabled, the port will report Detect Good when it detects either a valid IEEE PD or a high-capacitance legacy PD. With legacy mode disabled, only valid IEEE PDs will be recognized. If a nonstandard PD presents an invalid detection signa- ture not included by legacy detection, the LTC9101-1/ LTC9102/LTC9103 may be configured to perform classi- fication and/or apply power regardless of detection result. To accomplish this, the LTC9101-1/LTC9102/ LTC9103 introduces per-port Force Power and Class Event over - rides. These overrides intentionally defeat compliance checks. See the LTC9101-1 S oftware Programming docu- mentation for details. CLASSIFICATION 802.3af Classification A PD may optionally present a classification signature to the PSE to indicate the maximum power it will draw while operating. The IEEE specification defines this sig - nature as a constant current draw when the PSE port voltage is in the VCLASS range (between 15.5V and 20.5V) as shown in Figure 16, with the current level indicating one of five possible PD signatures. Figure 15 shows a typical PD load line, starting with the slope of the 25k signature resistor below 10V, then transitioning to the classification signature current (in this case, Class 3) in the V CLASS range. Table 10 shows the possible clas- sification values. Figure 15. VOL TAGE (VCLASS) CURRENT (mA) 5 10 15 20

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14.5mA 6.5mA CLASS 4 CLASS 2 CLASS 1 CLASS 0 CLASS 3 OVER CURRENT ≈ ≈ PD Classification Figure 16.

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Type 1 or 2 PSE, 1-Event Class Sequence

the PSE has allocated 25.5W.

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a single class event as shown in Figure 16. operate in a reduced power mode. Table 10. Type 1 and Type 2 PD Classification Values ILIM-2P, and PCUT-4P thresholds. corresponding Class Enable bit is cleared. extra fields to the Ethernet LLDP data protocol. dynamically, enabling system-level LLDP support. of Type 1 classification: Type 2 (2-event) classification. Type 2 PSEs are required to perform classification.

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Figure 20. Type 3 or 4 PSE, 4-Event Class Sequence

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Figure 21. Type 4 PSE, 5-Event Class Sequence

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Figure 18. Type 3 or 4 PSE, 1-Event Class Sequence

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Figure 19. Type 3 or 4 PSE, 3-Event Class Sequence over both pairsets simultaneously.

• The PD is single-signature configuration.
• The PD is Type 3 or T ype 4.
• The PD presents a valid detection signature on an unpowered pairset when power is applied over the other pairset. Although PD signature configuration is not defined for Type 1 and Type 2 PDs, a Type 3 or Type 4 PSE may identify such a PD as single-signature or dual-signature. Single-signature PDs may receive 4-pair power regardless of PD Type. Certain pre-802.3bt “dual-signature” PDs may be damaged by 4-pair power . Type 3 and Type 4 dual-signature PDs are required to present a unique classification response from pre-802.3bt dual-signature PDs of the same Class. For dual-signature PDs, the LTC9101-1/LTC9102/LTC9103 determines and reports both PD Class and PD Type during classification. Type 3, Type 4, and pre-802.3bt Class 1 through Class 4 dual-signature PDs present class signature 1 through 4, respectively, during the first and second class events. Type 3 and Type 4 dual-signature PDs present class sig- nature 0 for all subsequent class events. Thus, a PSE can conclusively determine PD Type by the third class event for all dual-signature PDs.

be flagged as an invalid classification result. ity and for the system’s power supply capability. When AUTO is low the PWRMD0 pin setting is ignored. Table 12. Auto Mode Maximum Delivered Power Capabilities the two halves of a dual-signature PD.

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signature of 4, 4, 0, and 0, respectively.

Rev. 0For more information www.analog.com APPLICATIONS INFORMATION below IINRUSH-2P, as appropriate per the PD configuration and Class. If inrush is not successful, power is removed and the corresponding tSTART faults are set. Otherwise, the port or channel, as appropriate, advances to power on and the programmed current limiting thresholds are used as described in the Current Cutoff and Limit section. Port Power Policing The power policing threshold (PCUT-4P) is monitored on a per-port basis, up to 128W in 0.5W increments (typical). When the total output power over a one second mov- ing average exceeds the specified threshold, power is removed from the port and the corresponding tCUT faults are set. In particular , the port policing feature may be used to ensure delivery of PD Class power while staying below 100W Limited Power Source (LPS) requirements. Current Cutoff and Limit Each LTC9101-1/LTC9102/ LTC9103 port includes two current limiting thresholds (ICUT-2P and ILIM-2P), each with a corresponding timer (tCUT and tLIM). Setting the ICUT-2P and ILIM-2P thresholds depends on several factors: the PD assigned Class, the main supply voltage (V EE), the PSE Type (Type 3 or 4), and the MOSFET SOA. A single set of programmable port I CUT-2P and I LIM-2P thresholds is shared by both channels. The thresholds should be set based on the classification result as shown in Table 6 and Table 7. For a dual-signature PD assigned unequal Classes, the highest Class is used to set the thresholds. For example, a dual-signature PD assigned Class 1 and Class 5 would enforce I CUT-2P and I LIM-2P based on Class 5. Per the IEEE specification, the LTC9101-1/LTC9102/ LTC9103 will allow the channel current to exceed ICUT-2P for a limited period of time before removing power from the port, or channel, as appropriate whereas it will actively control the MOSFET gate drive to keep the channel cur - rent below ILIM-2P. The channel does not take any action to limit the current when only the I CUT-2P threshold is exceeded, but does start the t CUT timer . If the current POWER CONTROL The primary function of the LTC9101-1/LTC9102/LTC9103 is to control power delivery to the PSE port. With the LTC9101-1/LTC9102/LTC9103, a PSE port is composed of either one or two power channels; each power channel controls power delivery over a pairset. Within this section, operation of 4-pair configured ports is defined per chan- nel. When configured for 2-pair operation, only a single power channel is present per port. The LTC9101-1/LTC9102/ LTC9103 delivers power by controlling the gate drive voltage of an external power MOSFET while monitoring the current (through an exter- nal sense resistor) and the output voltage (across the OUT pin). The LTC9101-1/LTC9102/ LTC9103 connects the V EE power supply to the PSE port in a controlled manner , meeting the power demands of the PD while minimizing power dissipation in the external MOSFET and distur - bances to the VEE backplane. Inrush Control When commanded to apply power to a port, the LTC9101-1/LTC9102/LTC9103 ramps up the GATE pin of one or both channels (as commanded), raising the external MOSFET gate voltage in a controlled manner . During a typical inrush, the MOSFET gate voltage will rise until the external MOSFET is fully enhanced or the channel reaches the inrush current limit (IINRUSH-2P). IINRUSH-2P is set automatically by the PSE. When the PSE is applying 4-pair power to a single-signature PD assigned Class 0 to Class 4, I INRUSH-2P is 212.5mA (typical) per channel. Otherwise, IINRUSH-2P is 425mA (typical) per channel. The GATE pin will be servoed if channel current exceeds I INRUSH-2P, actively limiting current to I INRUSH-2P. When the GATE pin is not being servoed, the final V GS is 12V (typical). During inrush, each powered channel runs a timer (tSTART). Each powered channel stays in inrush until tSTART expires. When tSTART expires, the PSE inspects channel voltage and current. When the PSE is applying power to a PD, inrush is successful if the channel(s) are drawing current

Rev. 0 For more information www.analog.com dissipation at safe levels. Current limit and foldback behavior are programmable on a per-port basis. The LTC9101-1/LTC9102/ LTC9103 supports current levels well beyond the maximum values in the 802. 3bt specification. Large values of I LIM-2P may require larger external MOSFETs, additional heat sinking, and setting the tLIM Timer Configuration field to a lower value. MOSFET Fault Detection LTC9101-1/LTC9102/LTC9103 PSE ports are designed to tolerate significant levels of abuse, but in extreme cases it is possible for an external MOSFET to be damaged. A failed MOSFET may short source to drain, which will make the port appear to be on when it should be off; this condition may also cause the sense resistor to fuse open, turning off the port but causing SENSE to rise to an abnor- mally high voltage. A failed MOSFET may also short from gate to drain, causing GATE to rise to an abnormally high voltage. OUT , SENSE and GATE are designed to tolerate up to 80V faults without damage. If the LTC9101-1/LTC9102/LTC9103 detects any of these conditions for more than 3.8ms, it disables all port func- tionality, reduces the gate drive pull-down current for the port and reports a FET Bad fault. This is typically a permanent fault, but the host can attempt to recover by resetting the port, or by resetting the entire chip if a port reset fails to clear the fault. If the MOSFET is in fact bad, the fault will quickly return, and the port will disable itself again. The remaining ports of the LTC9101-1/LTC9102/ LTC9103 are unaffected. An open or missing MOSFET will not trigger a FET Bad fault, but will cause a t START fault if the LTC9101-1/ LTC9102/LTC9103 attempts to turn on the port. Disconnect The LTC9101-1/LTC9102/ LTC9103 monitors powered channels to ensure the PD continues to draw the mini - mum specified current. The IHOLD-2P threshold, monitored as the VHOLD-2P threshold across the 0.1Ω sense resistor , is used to determine if a PD has been disconnected. drops below the ICUT-2P threshold before its timer expires, the tCUT timer counts back down, but at 1/16 the rate that it counts up. If the t CUT timer reaches 65ms (typical), the port or channel, as appropriate, is turned off and the corresponding tCUT faults are set. This allows the channel to tolerate intermittent overload signals with duty cycles below about 6%; longer duty cycle overloads will remove power from the port or channel, as appropriate. The I LIM-2P current limiting circuit is always enabled and actively limiting channel current. The tLIM timer is enabled only when the t LIM Timer Configuration field is set to a non-zero value. This allows tLIM to be set to a shorter value than tCUT to provide more aggressive MOSFET protection and turn off a port before MOSFET damage can occur . The tLIM timer starts when the ILIM-2P threshold is exceeded. When the t LIM timer reaches 1.9ms (typical) times the value in the t LIM Timer Configuration field, the port or channel, as appropriate, is turned off and the appropriate tLIM faults are set. When the t LIM Timer Configuration field is set to 0, t LIM behaviors are tracked by the t CUT timer , which counts up during both I LIM-2P and I CUT-2P events. To maintain IEEE compliance, the programmed tLIM Timer Configuration field should be set as shown in the LTC9101-1 Software Programming documentation. ICUT-2P is typically set to a lower value than I LIM-2P, allowing the port to tolerate minor faults without current limiting. To maintain IEEE compliance, I LIM-2P should be set as shown in Table 6 and Table 7. The programmed I LIM-2P setting is automatically applied following the completion of inrush. The t CUT and tLIM timers are maintained on a per channel basis. When a tCUT or tLIM fault occurs a determination is made to turn off one or both channels. See the Port Fault vs Channel Fault section for details. ILIM-2P Foldback The LTC9101-1/LTC9102/ LTC9103 ILIM-2P threshold is implemented as a two-stage foldback circuit that reduces the channel current if the channel voltage falls below the normal operating voltage. This keeps MOSFET power APPLICATIONS INFORMATION

manner while minimizing power disruption to the PD. with lower bulk capacitance in high reliability applications. neither channel of the port. PD or cabling is indicative of imminent PD or cable failure. In 2-pair mode fault2Pn has no effect. Table 13. Channel Fault Effect on Port/Channel State

0 Port Port

1 Channel Channel

and is set by the user in semi-auto and manual modes. HOLD-2P threshold to 3.5mA (typ). DIS expires, it will remain powered. device, potentially causing damage. protect the PSE, the MOSFET , and downstream circuitry.

port, only 10W is available and the PD cannot be powered.

9101123 F24

Figure 24. 100W PoE System with 10m Cables allows the host to revise the PSE available power budget.

3 Ports • 26W (Measured) = 78W

IEEE 802.3bt introduces a new optional feature, Autoclass. LTC9102/LTC9103 fully supports Autoclass. the Ethernet cable and minimum PSE output voltage. put power substantially over-allocates power to the PD. An example PoE system is shown in two versions.

9101123 F23

Figure 23. 100W PoE System with 100m Cables

1. The PSE measures the Autoclass response of the PD.
2. The PD continues holding the class signature selected

in step 6 until the end of the first class event. sponding to PD assigned Class. directly since it does not have access to the data path. Autoclass requests, the measurement begins immediately. ments are reported in the Port Parametric registers. tion procedure listed below is shown in Figure 25.

9101123 F25

Figure 25. Autoclass Negotiation, Voltage and Current

1. PSE begins issuing the long first class event. The PD

class signature is allowed to settle during this time.

1. The PD responds with a class signature corresponding

is unrelated to the Autoclass negotiation.

1. The PSE measures the PD class signature during this
2. The PD continues presenting its class signature.
3. The PSE continues the long class event and does not

measure the class signature current at this time.

1. The PD, if requesting Autoclass, transitions to class

continues presenting its class signature.

surement in a user-defined manner . level of MSD is register configurable as active high or low. The default behavior is active low. in the single-signature and dual-signature PD definitions. signature and dual-signature PDs. valid detection signature on both pairsets. See Table 14. Table 14. 4-Pair Valid Enabled at each power channel with per-channel A/D converters. channel of a port is on and reads zero at all other times.

• 1s mode : Samples are taken continuously; a moving 1 second average is updated every 100ms VEE Readback The LTC9101-1/LTC9102/ LTC9103 continuously mea - sures the V EE voltage with a dedicated A/D converter . This global VEE measurement is fully synchronized to all port current measurements and can monitor down to the LTC9102/LTC9103 UVLO threshold. Temperature Readback In addition to the over temperature fault in the supply event register , the LTC9101-1 also reports die temperature of each corresponding LTC9102/LTC9103. Overtemperature Protection Overtemperature protection automatically removes power from affected ports when LTC9102/LTC9103 temperature exceeds a preset threshold (150°C, typ). Ports are pre - vented from resuming operation until the die temperature drops below a preset recovery threshold (125°C, typ). See LTC9101-1 Software Interface guide for details. Port Power Readback The LTC9101-1/LTC9102/ LTC9103 provides fully con - tinuous and synchronized port power measurements. The LTC9101-1/LTC9102/LTC9103 calculates the port power by multiplying the port current and VEE measurements. PPORT = IPORT • VEE The Port Power measurements replace the Port Voltage measurements provided in prior ADI PSEs. Port voltage

download and will be auto-loaded at boot. the quad level (groups of 4 ports). are identified and stored in the appropriate flash partition. LTC9101-1 of the base I2C chip address. SMBus data protocols can be found at www.smbus.org. to be present for the serial interface to function. the other pairset. See Table 15. Table 15. 4-Pair Valid Disabled and executing firmware images. Firmware images are stored in a dedicated flash partition. be overwritten by the user .

Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION ISOLATION REQUIREMENTS IEEE 802.3 Ethernet specifications require that network segments (including PoE circuitry) be electrically isolated from the chassis ground of each network interface device. However , network segments are not required to be iso - lated from each other , provided that the segments are connected to devices residing within a single building on a single power distribution system. If the PSE is part of a larger system, contains additional external non-Ethernet ports, or must be referenced to pro- tective ground for some other reason, the PoE subsystem must be electrically isolated from the rest of the system. The LTC9101-1/LTC9102/LTC9103 chipset simplifies PSE isolation by allowing the LTC9101-1 chip to reside on the non-isolated side. There it can receive power from the main logic supply and connect directly to the I2C/SMBus bus. In this case, the SDAIN and SDAOUT pins can be tied together and will act as a standard I 2C/SMBus SDA pin. Isolation between the LTC9101-1 and LTC9102/LTC9103 is implemented using a proprietary transformer-based communication protocol. Additional details are provided in the High-Speed Data Isolation section of this data sheet. For simple devices, such as unmanaged PoE switches, the isolation requirement can be met by using an isolated main power supply for the entire device. This strategy can be used if the device has no electrically conducting ports other than twisted-pair Ethernet. The LTC9101-1 may directly connect to the LTC9102s/LTC9103s in the above circumstances, or if the system already provides isolation. EXTERNAL COMPONENT SELECTION Power Supplies The LTC9101-1/LTC9102/LTC9103 requires two supply voltages to operate. VDD requires 3.3V (nominally) relative to DGND. VEE requires a negative voltage of between –51V to –57V for Type 2 and 3 PSEs, or –53V to –57V for Type 4 PSEs, relative to AGND. Bus Addressing The LTC9101 -1’s primary 7- bit serial bus address is 010A3A200b, with bits 3:2 set by AD3:AD2 respectively. In Figure 6 through Figure 9, AD3:AD2 are set by LTC9101-1 pins and AD1:AD0 are inferred by device configuration. See Table 4 for device configuration options. Depending on device configuration, up to 12 I2C addresses will be popu- lated from the I2C base address upwards. All LTC9101-1s also respond to the broadcast address 0110000b, allow- ing the host to write the same command (typically con - figuration commands) to multiple LTC9101-1s in a single transaction. If the LTC9101-1 is asserting INT, it will also respond to the alert response address (0001100b) per the SMBus specification. Each LTC9101-1/LTC9102/ LTC9103 is logically com - posed of multiple four port groups, known as quads, each packed into a single I2C address. See Device Configuration section for details. For example, if CFG[2:0] is set to 000, an LTC9101-1 is configured as an 8-port or 12-port device when attached to an LTC9102 or an LTC9103, respectively (see Table 4). This configuration requires two or three consecutive I2C addresses, with quad offset 0 starting at the I2C base address. Note that any individual quad I2C address greater than or equal to 0x30 (the broadcast address) will be automati- cally disabled. Interrupts and SMBAlert Most port events can be configured to trigger an inter - rupt, asserting INT and alerting the host to the event. This removes the need for the host to poll the LTC9101 -1, minimizing serial bus traffic and conserving host CPU cycles. Multiple LTC9101 -1s can share a common INT line, with the host using the SMBAlert protocol (ARA) to determine which LTC9101-1 caused an interrupt. Register Description For information on serial bus usage and device configura- tion and status, refer to the LTC9101-1 Software Interface guide. Contact Analog Devices to request this document.

Rev. 0For more information www.analog.com APPLICATIONS INFORMATION capacitor of at least 47μF, 100V and a bulk TVS are also recommended per system. LTC9102/LTC9103 Low Voltage Power Supplies The LTC9102/LTC9103 includes internal voltage regula - tors that generate low voltage supplies directly from the main PoE power supply. At startup, an internal regula - tor generates 6V at PWRIN, drawing power from AGND. Internal 4.3V and 3.3V rails are sub-regulated from PWRIN. The PWRIN pin requires a local 1μF, 100V bypass capacitor . Pull-up resistors can be connected from PWRIN to AGND to dissipate heat outside the LTC9102/LTC9103 package. Optionally, an external power supply can be connected to PWRIN to override the startup regulator and reduce power dissipation. Figure 26 shows a pull-up resistor configuration with the internal 3.3V regulator . Bypass resistors R1, R2, R3, and R4 draw heat away from the LTC9102s/LTC9103s. Note that the voltage of the PWRIN pin changes based on the LTC9102/LTC9103 operating mode and its correspond - ing current consumption. If more current is consumed than the bypass resistors provide, the startup regulator maintains the voltage at 6V typical. The LTC9102 can operate without the pull-up resistors in space-constrained applications. In applications with an external PWRIN supply, a 6.5V reg- ulator provides an optimum voltage to override the inter- nal 6V start-up regulator , while minimizing the LTC9102 device heating. The external supply may be shared across multiple LTC9102s/LTC9103s. A 3.3V power supply can be connected directly to the CAP3 pin, as shown in Figure 27. This provides the most power efficient sleep mode. When supplying external 3.3V power , tie the EXT3 pin to CA P3. This will disable the internal 3.3V regulator and prevent power back-feed. The 3.3V regulator must power up within tCAP3EXT specified in the electrical characteristics table. Digital Power Supply VDD provides digital power for the LTC9101 -1 proces- sor . A ceramic decoupling cap of at least 0.1μF should be placed from each VDD to DGND, as close as practical to each LTC9101 -1. In addition, each LTC9101-1 must include a bulk cap of 10µF for robust surge immunity. A 1.2V core voltage supply is generated internally and requires a 1µF ceramic decoupling cap between the CAP1 pin and DGND and between CAP2 and DGND. In systems using ADI’s proprietary isolation, VDD should be delivered by the host controller’ s non-isolated 3.3V supply. To maintain required isolation, LTC9102/LTC9103 AGND and LTC9101 -1 DGND must not be connected. If using the direct connection scheme, the LTC9101-1 DGND must be connected to LTC9102/LTC9103 VEE. Main PoE Power Supply V EE is the main isolated PoE supply that provides power to the PDs. Because it supplies a relatively large amount of power and is subject to significant current transients, it requires more design care than a simple logic supply. For minimum IR loss and best system efficiency, set V EE near maximum amplitude (57V), leaving enough margin to account for transient over or undershoot, temperature drift, and the line regulation specifications of the particular power supply used. A bypass capacitor and a transient voltage suppressor(TVS) between each LTC9102/LTC9103 AGND and VEE are very important for reliable operation. If a short circuit occurs at one of the output ports it can take as long as 1μs for the LTC9102/LTC9103 to begin regulating the current. During this time the current is limited only by the small impedances in the circuit; a high current spike typically occurs, causing a voltage transient on the VEE supply and possibly causing the LTC9101-1/LTC9102/ LTC9103 to reset due to a UVLO fault. A 1μF, 100V X7R capacitor and a SMAJ58A near each LTC9102/LTC9103 are recom- mended to minimize spurious resets. An electrolytic bulk

side of the system isolation barrier . using the proprietary isolation scheme. selected transformers do not have common-mode chokes. proper operation, strict layout guidelines must be met.

9101123 F26

Figure 26. Power Supply Configuration with Internal 3.3V Supply

9101123 F27

Figure 27. Power Supply Configuration with External 3.3V Regulators LTC9103 chipset relies on pre-existing system isolation. munication protocol (see Figure 29).

Rev. 0For more information www.analog.com APPLICATIONS INFORMATION Surge Protection Ethernet ports can be subject to significant cable surge events. To keep PoE voltages below a safe level and protect the application against damage, protection components, as shown in Figure 30, are required at the main supply, at the LTC9102/LTC9103 supply pins, and at each port. Bulk transient voltage suppression (TVS BULK) and bulk capacitance (C BULK) are required across the main PoE supply and should be sized to accommodate system level surge requirements. Across each LTC9102/LTC9103 AGND pin and VEE pin is a SMAJ58A 58V TVS (D1) and a 1µF, 100V bypass capaci- tor (C1). These components must be placed close to the LTC9102 /LTC9103 pins. Each port requires an S1B clamp diode from OUTn to supply AGND. This diode steers harmful surges into the supply rails where they are absorbed by the surge sup - pressors and the V EE bypass capacitance. The layout of these paths must be low impedance. Sense Resistors The LTC9101-1/LTC9102/LTC9103 is designed for a low 0.1Ω current sense resistance per channel, laid out as shown in the Layout Requirements section, Figure 31. In order to meet the IHOLD-2P, ICUT-2P, and ILIM-2P accuracy required by the IEEE specification, the sense resistors should have ±1% tolerance or better , and no more than ±200ppm/°C temperature coefficient. Port Output Cap Each port requires a 0.1μF cap across OUTn to AGND (see Figure 30) to keep the LTC9102/LTC9103 stable while in current limit during startup or overload. Common ceramic capacitors often have significant voltage coefficients; this means the capacitance is reduced as the applied voltage increases. To minimize this problem, X7R ceramic capaci- tors rated for at least 100V are recommended and must be located close to the LTC9102/LTC9103.

• • 3.3V VEE 49.9/uni03A9 49.9/uni03A9
• • VEE 49.9/uni03A9 49.9/uni03A9 0.01µF 0.01µF DGND DND NOTES: 1. MUL TIPLE L TC9102/L TC9103 DEVICES ON THE HIGH-SPEED DATA INTERFACE ARE DAISY CHAINED. 2. THE HIGH-SPEED DATA INTERFACE IS TERMINATED AT BOTH ENDS. 3. THE 100k RESISTORS AT THE END OF THE HIGH-SPEED DATA INTERFACE CONNECT TO THE LAST L TC9102/L TC9103 CAP3. 4. THE MAXIMUM LENGTH OF THE HIGH-SPEED DATA INTERFACE IS 16 INCHES. 5. THE HIGH-SPEED DATA INTERFACE DIFFERENTIAL IMPEDANCE IS 100/uni03A9. DPD CND INT SCL SDAIN SDAOUT CPD L TC9101-1 (NO I ISOLATION REQUIRED) VDD 0.01µF 0.01µF 1000pF 2kV VEE CAP3-1 CAP3-2 CAP3-3 CAP3-4

9101123 F28

Figure 28. LTC9101-1/LTC9102/LTC9103 Proprietary Isolation Scheme

1. MUL TIPLE L TC9102/L TC9103 DEVICES ON THE HIGH-SPEED DATA

INTERFACE ARE DAISY CHAINED.

1. THE HIGH-SPEED DATA INTERFACE IS TERMINATED AT BOTH ENDS.
2. THE MAXIMUM LENGTH OF THE HIGH-SPEED DATA INTERFACE IS
3. THE HIGH-SPEED DATA INTERFACE DIFFERENTIAL IMPEDANCE IS 100/uni03A9.

Figure 29. LTC9101-1/LTC9102/LTC9103 Proprietary Direct Connection Scheme

9101123 F30

Figure 30. LTC9102/LTC9103 Surge Protection Table 16. Component Selection for PSE Maximum Class

9101123 F31

Figure 31. RSENSE Kelvin Connections LTC9102s/LTC9103s and the high-speed data interface. for example layout references. LTC9102/LTC9103 to the sense resistor (RSENSEn). up to four LTC9102s/LTC9103s.

• • •

9101123 F32

Figure 32. Alternative A (MDI-X) and B (S), 4-Pair , 1000BASE-T , IEEE 802.3bt, Type 3 or Type 4 PSE, Ports 1 and 6 Shown

• • •

9101123 F33

Figure 33. Alternative A (MDI-X), 2-Pair , 1000BASE-T , IEEE 802.3bt or IEEE 802.3at PSE, Ports 1 and 12 Shown

9101123 F34

Figure 34. Autonomous IEEE 802.3bt 4-Pair PSE, Type 3 or Type 4, Alternative A (MDI-X) and B(S), 1000BASE-T , 1 Port Shown

Rev. 0 For more information www.analog.com PACKAGE DESCRIPTION 4.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ±0.10 24 23 BOTTOM VIEW—EXPOSED PAD 2.45 ±0.10 (4-SIDES) 0.75 ±0.05 R = 0.115 TYP 0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UF24) QFN 0105 REV B RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.70 ±0.05 0.25 ±0.05 2.45 ±0.05 (4 SIDES)3.10 ±0.05 4.50 ±0.05 PACKAGE OUTLINE PIN 1 NOTCH R = 0.20 TYP OR 0.35 × 45° CHAMFER 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697 Rev B)

Rev. 0For more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05

9.50 REF

5.50 REF

6.10 ±0.05 7.50 ±0.05 4.40 ±0.05 8.80 ±0.05 4.80 ±0.05 10.10 ±0.05 11.50 ±0.05 0.25 ±0.05 PACKAGE OUTLINE 7.00 ±0.10 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS PIN 1 TOP MARK (SEE NOTE 6) BOTTOM VIEW—EXPOSED PAD 9.50 REF11.00 ±0.10 0.75 ±0.05 R = 0.125 TYP R = 0.10 TYP 0.25 ±0.05 (UKJ64) QFN 0119 REV Ø 0.00 – 0.05 0.40 ±0.10 8.80 ±0.10 4.40 ±0.10 4.80 ±0.10

0.55 REF

1. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 64-Lead Plastic QFN (7mm × 11mm) (Reference LTC DWG # 05-08-1780 Rev Ø) 64-Lead Plastic QFN (7mm × 11mm) (Reference L TC DWG # 05-08-1780 Rev 0)

Rev. 0 For more information www.analog.com  ANALOG DEVICES, INC. 2021 www.analog.com RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LTC4292/ LTC4291-1 4-Port IEEE 802.3bt PoE PSE Controller T ransformer Isolation, 14-bit Current Monitoring per Port with Programmable Current Limit, Supports Type 1-4 PDs LT4293 L TPoE++/IEEE 802.3bt PD Interface Controller External Switch, L TPoE++ and IEEE 802.3bt Support, Configurable Class and AUX Support LT4294 IEEE 802.3bt PD Controller External Switch, IEEE 802.3bt Support, Configurable Class and AUX Support LT4295 IEEE 802.3bt PD with Forward/Flyback Switching Regulator Controller External Switch, IEEE 802.3bt Support, Configurable Class, Forward or No-Opto Flyback Operation, Frequency, PG/SG Delays, Soft-Start, and Aux Support as Low as 9V, Including Housekeeping Buck, Slope Compensation LTC4290/ LTC4271 8-Port PoE/PoE+/L TPoE++ PSE Controller T ransformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and L TPoE ++ PDs LTC4257-1 IEEE 802.3af PD Interface Controller Internal 100V, 400mA Switch, Dual Current Limit, Programmable Class LTC4263 Single IEEE 802.3af PSE Controller Internal FET Switch LTC4265 IEEE 802.3at PD Interface Controller Internal 100V, 1A Switch, 2-Event Classification Recognition LTC4266 Quad IEEE 802.3at PoE PSE Controller With Programmable I CUT/ILIM, 2-Event Classification, and Port Current and Voltage Monitoring LTC4267 IEEE 802.3af PD Interface with Integrated Switching Regulator Internal 100V, 400mA Switch, Dual Inrush Current, Programmable Class LTC4270/ LTC4271 12-Port PoE/PoE+/L TPoE++ PSE Controller T ransformer Isolation, Supports Type 1, Type 2 and L TPoE++ PDs LTC4278 IEEE 802.3at PD Interface with Integrated Flyback Switching Regulator 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller , 50kHz to 250kHz, 12V Aux Support LTC4279 Single PoE/PoE+/L TPoE++ PSE Controller Supports IEEE 802.3af, IEEE 802.3at, L TPoE ++ and Proprietary PDs IEEE 802.3bt Type 3 or Type 4 PSE, Alternative A (MDI-X) and B (S), 1000BASE-T , 1 Port Shown V EE >47µF 0.1µF 100V S1B 0.1µF 1µF 100V CPA CNA DPA DNA V EE SENSE1 GATE1 AGND L TC9102/L TC9103 1000BASE-T OUT1 SENSE2 VSSK2 GATE2 OUT2 TX1 TX2 TX3 TX4 RJ45 ID0 ID1 V EE MSD SCL SDAIN CFG2 CFG1 CFG0 DGND DPD CND V DD L TC9101-1 CPD DND ISOLATION AD2 AD3 SDAOUT RESET INT 3.3V (NO I C ISOLATION REQUIRED) V EE PORT 1 D1: SMCJ58A D2: SMAJ58A 0.1/uni03A9 PSMN040-100MSE V EE VSSK1 0.1/uni03A9 PSMN040-100MSE 0.1µF 100V S1B 1000pF 2kV HIGH- SPEED DATA INTERFACE

9101123 TA02