Amplifier

LTC7652

Linear Technology

Zero-Drift Operational Amplifier

Manufacturer: Linear Technology

Document: 24 Pages / 850Kb

Request Quote Download Datasheet Read online HTML view

More from Linear Technology Browse L parts

Online Datasheet

Read LTC7652 online.

LTC1052_09 LINER | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 24

Technical content

1052 and LTC7652 are low noise zero-drift op amps manufactured using Linear Technology’s enhanced LTCMOS TM silicon gate process. Chopper-stabilization constantly corrects offset voltage errors. Both initial offset and changes in the offset due to time, temperature and common mode voltage are corrected. This, coupled with picoampere input currents, gives these amplifiers unmatched performance. Low frequency (1/f) noise is also improved by the chopping technique. Instead of increasing continuously at a 3dB/octave rate, the internal chopping causes noise to decrease at low frequencies. The chopper circuitry is entirely internal and completely transparent to the user. Only two external capacitors are required to alternately sample-and-hold the offset correction voltage and the amplified input signal. Control circuitry is brought out on the 14-pin and 16-pin versions to allow the sampling of the LTC1052 to be synchronized with an external frequency source. Zero-Drift Operational Amplifier , LTC and LT are registered trademarks of Linear Technology Corporation. FEATURES DESCRIPTIO U ■ Thermocouple Amplifiers ■ Strain Gauge Amplifiers ■ Low Level Signal Processing ■ Medical Instrumentation ■ Guaranteed Max Offset: 5µV ■ Guaranteed Max Offset Drift: 0.05µV/°C ■ Typ Offset Drift: 0.01µV/°C ■ Excellent Long Term Stability: 100nV/√Month ■ Guaranteed Max Input Bias Current: 30pA ■ Over Operating Temperature Range: Guaranteed Min Gain: 120dB Guaranteed Min CMRR: 120dB Guaranteed Min PSRR: 120dB ■ Single Supply Operation: 4.75V to 16V (Input Voltage Range Extends to Ground) ■ External Capacitors can be Returned to V– with No Noise Degradation Ultralow Noise, Low Drift Amplifier Noise Spectrum APPLICATIO SU FREQUENCY (Hz) VOLTAGE NOISE DENSITY (nV/√Hz) 160 140 120 100 400100 200 300 500 LTC1052/7652 • TA02 LTCMOS is a trademark of Linear Technology Corporation. Teflon is a trademark of DuPont. 100Ω INPUT –5V LT 1007 LTC1052 OUTPUT 1 0.1µF 0.1µF 0.1µF 100k 3K 68k 5V1 –5 V 100k 1.5k VOS = 3µV VOS∆T = 50nV/°C NOISE = 0.06µVP-P 0.1Hz TO 10Hz LTC1052/7652 • TA01 TYPICAL APPLICATIO U

Consult LTC Marketing for parts specified with wider operating temperature ranges. (Notes 1 and 2) PACKAGE/ORDER I FOR ATIOUU W ABSOLUTE AXI U RATI GSW WW U Operating Temperature Range LTC1052CN8 REPLACES ICL7650CPA LTC1052CJ8 LTC1052MJ8 ICL7650IJA ORDER PART NUMBER ORDER PART NUMBER LTC7652CH LTC1052CH LTC1052MH REPLACES ICL7652CTV ICL7652ITV ICL7650CTV-1 ICL7650ITV-1 ICL7650CTV ICL7650ITV ICL7650MTV N8 PACKAGE 8-LEAD PDIP TJMAX = 110°C, θJA = 150°C/W 8CEXTA 2 7– IN 3 6 CEXTB OUTPUT 4 5V– OUTPUT CLAMP TOP VIEW TOP VIEW CEXTB CEXTA –I N +I N OUTPUT METAL CAN H PACKAGE V+/CASE LTC1052 OUTPUT CLAMP LTC7652 CRETURN J8 PACKAGE, 8-LEAD CERDIP LTC1052CSW REPLACES LTC1052CS ORDER PART NUMBER ORDER PART NUMBER LTC1052CN LTC1052CJ LTC1052MJ REPLACES ICL7652CPD ICL7650CPD ICL7652IJD ICL7650IJD ICL7650MJD TJMAX = 110°C, θJA = 150°C/W TOP VIEW SW PACKAGE 16-LEAD PLASTIC (WIDE) SO J PACKAGE, 14-LEAD CERDIP TOP VIEW N PACKAGE, 14-LEAD CERDIP TJMAX = 110°C, θJA = 130°C/W 2 13 3 12 4 11 5 10 6 9 7 8 CEXTB NC (GUARD) CEXTA INT/EXT CLK IN CLK OUT –I N V+ +I N OUTPUT NC (GUARD) OUTPUT CLAMP V– CRETURN CEXTB NC (GUARD) CEXTA INT/EXT CLK IN CLK OUT –I N V+ +I N OUTPUT NC (GUARD) OUTPUT CLAMP V– CRETURN NC NC OBSOLETE PACKAGE Consider the N8 Package for Alternate Source OBSOLETE PACKAGE Consider the N14 Package for Alternate SourceConsider the N8 Package for Alternate Source OBSOLETE PACKAGE

ELECTRICAL CHARACTERISTICS

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: Connecting any terminal to voltages greater than V+, or less than V–, may cause destructive latch-up. It is recommended that no sources operating from external supplies be applied prior to power-up of the LTC1052/LTC7652. Note 3: These parameters are guaranteed by design. Thermocouple effects preclude measurement of the voltage levels in high speed automatic testing. VOS is measured to a limit determined by test equipment capability. Voltages on CEXTA and CEXTB, AVOL, CMRR and PSRR are measured to insure proper operation of the nulling loop to ensure meeting the VOS and VOS drift specifications. See Package-Induced VOS in the Applications Information section. Note 4: Output clamp not connected. Note 5: Current noise is calculated from the formula: in = (2q IB)1/2, where q = 1.6 • 10–19 coulomb. TYPICAL PERFOR A CE CHARACTERISTICS UW The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, test circuit TC1, unless otherwise noted. LTC1052M LTC1052C/LTC7652C SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS VOS Input Offset Voltage (Note 3) ±0.5 ±5 ±0.5 ±5 µV ∆VOS/∆Temp Average Input Offset Drift (Note 3) ● ±0.01 ±0.05 ±0.01 ±0.05 µV/°C ∆VOS/∆Time Long-Term Offset Voltage Stability 100 100 nV/ √Month IOS Input Offset Current ±30 ±90 ±30 ±90 pA

±2000 ±350 pA IB Input Bias Current ±1 ±30 ±1 ±30 pA
±1000 ±175 pA enP-P Input Noise Voltage R S = 100Ω, DC to 10HZ, TC3 1.5 1.5 µVP-P RS = 100Ω, DC to 1HZ, TC3 0.5 0.5 µVP-P In Input Noise Current f = 10Hz (Note 5) 0.6 0.6 fA/ √Hz CMRR Common Mode Rejection Ratio V CM = V– to 2.7V ● 120 140 120 140 dB PSRR Power Supply Rejection Ratio V SUPPLY = ±2.375V to ±8V ● 120 150 120 150 dB AVOL Large-Signal Voltage Gain R L = 10k, VOUT = ±4V ● 120 150 120 150 dB VOUT Maximum Output Voltage Swing R L = 10k ● ±4.7 ±4.85 ±4.7 ±4.85 V (Note 4) R L = 100k ±4.95 ±4.95 V SR Slew Rate R L = 10k, CL = 50pF 4 4 V/ µs GBW Gain Bandwidth Product 1.2 1.2 MHz IS Supply Current No Load 1.7 2.0 1.7 2.0 mA
3.0 3.0 mA fS Internal Sampling Frequency 330 330 Hz Clamp On Current R L = 100k ● 25 100 25 100 µA Clamp Off Current –4V < V OUT < 4V 10 100 10 100 pA
21 n A Input Noise Voltage VS = ±5V, TEST CIRCUIT (TC3) DC TO 1Hz DC TO 10Hz 5µV 5µV 10 SEC.

TYPICAL PERFOR A CE CHARACTERISTICS UW Aliasing Error Common Mode Input Range vs Supply Voltage Overload Recovery (Output Clamp Not Used) OVERDRIVE REMOVED AV = –100 Small-Signal Transient Response* Gain Phase vs Frequency SUPPLY VOLTAGE (±V) COMMON MODE RANGE (V) 2 4 61 3 5 7 LTC1052/7652 • TPC04 VCM = V– FREQUENCY (Hz) VOLTAGE GAIN (dB) 100 120 100 10 4 105 107 LTC1052/LTC7652 • TPC06 –20 103 106 –40 PHASE SHIFT (DEGREES) 180 160 120 200 100 140 220 VS = ± 5V CL= 100pF GAIN PHASE Offset Voltage vs Sampling Frequency 1OHzP-P Noise vs Sampling Frequency Input Bias Current vs Temperature SAMPLING FREQUENCY, fS (Hz) VOS (µV) 500 1000 1500 2000 VSUPPLY= ±5V LTC1052/7652 • TPC01 SAMPLING FREQUENCY, fS (Hz) 100 10Hz PEAK-TO-PEAK NOISE (µV) 1k 10k

5 VSUPPLY= ± 5V

LTC1052/7652 • TPC02 AMBIENT TEMPERATURE, TA(°C) –50 INPUT BIAS CURRENT, IB (pA) 100 300 400 500 1000 700 0 50 75 LTC1052/7652 • TPC03 200 800 900 600 –25 25 100 125 GUARANTEED GUARANTEED OUTPUT SPECTRUM (dB) (3Hz BANDWIDTH) fI–fS 50Hz/DIV fS fI VS = ±5V AV = –1 TEST CIRCUIT TC2 IV/DIV 50ms/DIV VS = ±5V OUTPUT VOLTAGE (20mV/DIV) AV = 1 RL = 10k CL = 100pF VS = ±5V *RESPONSE IS NOT DEPENDENT ON PHASE OF CLOCK 2µs/DIV Large-Signal Transient Response* OUTPUT VOLTAGE (2mV/DIV) AV = 1 RL = 10k CL = 100pF VS = ±5V 2µs/DIV

Broadband Noise, CEXT = 0.1µF Supply Current vs Supply Voltage INPUT REFERRED NOISE (5µV/DIV) AV = –1000 1ms/DIV INPUT REFERRED NOISE (5µV/DIV) AV = –1000 1ms/DIV TYPICAL PERFOR A CE CHARACTERISTICS UW Broadband Noise, CEXT = 1.0µF Broadband Noise Test Circuit (TC2) CEXTBCEXTA 2 7 –5 V LTC1052 LTC1052/7652 • TPC07 Output Short-Circuit Current vs Supply VoltageSupply Current vs Temperature TOTAL SUPPLY VOLTAGE, V+ TO V– (V) SUPPLY CURRENT, IS(mA) 0.5 1.0 1.5 2.0 2.5 658 1 0 12 LTC1052/LTC7652 • TPC08 14 16 AMBIENT TEMPERATURE, TA (°C) –50 SUPPLY CURRENT, IS(mA)2.0 3.0 25 75 1.0 –25 0 50 100 125 SUPPLY VOLTAGE = ± 5V LTC1052/LTC7652 • TPC09 Sampling Frequency vs Voltage Comparator Operation Sampling Frequency vs Temperature TOTAL SUPPLY VOLTAGE, V+ TO V– (V) SAMPLING FREQUENCY, fS (Hz) 100 200 300 400 600 681 0 12 LTC1052/LTC7652 • TPC11 14 16 500 TA = 25°C AMBIENT TEMPERATURE, TA (°C) –50 SAMPLING FREQUENCY, fS (Hz) 400 500 600 25 75 LT1052/LTC7652 • TPC12 300 200 –2 5 0 50 100 125 100 SUPPLY VOLTAGE = ± 5V 0.1µF0.1µF VREF* –5 V LTC1052 LTC1052/7652 • TPC13 VIN * – 5V ≤ VREF ≤ 2.7V TOTAL SUPPLY VOLTAGE, V+ TO V– (V) –1 0 –2 0 –3 0 10 14 LTC1052/LTC7652 • TPC10 68 12 16 SHORT-CIRCUIT OUTPUT CURRENT, IOUT (mA) ISINK VOUT = V+ ISOURCE VOUT = V–

50µV 10µV 5µV Response Time vs Overdrive VREF + OVERDRIVE 20ms/DIV TYPICAL PERFOR A CE CHARACTERISTICS UW OUTPUT –5V VREF – 1mV INPUT THEORY OF OPERATIOU DC OPERATION The shaded portion of the LTC1052 block diagram (Figure 1a) entirely determines the amplifier’s DC characteristics. During the auto zero portion of the cycle, the gm1 inputs are shorted together and a feedback path is closed around the input stage to null its offset. Switch S2 and capacitor CEXTA act as a sample-and-hold to store the nulling voltage during the next step—the sampling cycle. In the sampling cycle, the zeroed amplifier is used to amplify the differential input voltage. Switch S2 connects the amplified input voltage to C EXTB and the output gain stage. CEXTB and S2 act as a sample-and-hold to store the amplified input signal during the auto zero cycle. By switching between these two states at a frequency much higher than the signal frequency, a continuous output results. Notice that during the auto zero cycle the g m1 inputs are not only shorted together, but are also shorted to the inverting input. This forces nulling with the common mode voltage present and accounts for the extremely high CMRR of the LTC1052. In the same fashion, variations in 0.1µF0.1µF 2 7 LTC1052 LTC1052/7652 • TC01 OUTPUT RL TEST CIRCUITS 0.1µF0.1µF 2 7 LTC1052 LTC1052/7652 • TC02 OUTPUT (NOISE x 20,000) 34k LT1001 34k BANDWIDTH 10Hz 1Hz 16.2Ω 16.2Ω 162k 162k 16.2k 162k 16.2k 162k 0.1µF 1.0µF 1.0µF 1.0µF 1.0µF 1.0µF

power supply are also nulled. For nulling to take place, the offset voltage, common mode voltage and power supply must not change at a frequency which is high compared to the frequency response of the nulling loop. AC OPERATION AND ALIASING ERRORS So far, the DC performance of the LTC1052 has been explained. As the input signal frequency increases, the problem of aliasing must be addressed. Aliasing is the spurious formation of low and high frequency signals caused by the mixing of the input signal with the sampling frequency, f S. The frequency of the error signals, fE, is: fE = fS ±fI where fI = input signal frequency. Normally it is the difference frequency (fS – fI ) which is of concern because the high frequency (fS + fI) can be easily filtered. As the input frequency approaches the sampling frequency, the difference frequency approaches zero and will cause DC errors—the exact problem that the zero-drift amplifier is meant to eliminate. The solution is simple; filter the input so the sampling loop never sees any frequency near the sampling frequency. At a frequency well below the sampling frequency, the LTC1052 forces I 1 to equal I2 (see Figure 1b). This makes δ l zero, thus the gain of the sampling loop zero at this and higher frequencies (i.e., a low pass filter). The corner frequency of this low pass filter is set by the output stage pole (1/R L4 gm5 RL5 C2). THEORY OF OPERATIOU For frequencies above this pole, I2 is: I2 = VIN gm6 • and I1 – I2 = VIN gm1 – VIN gm6 • The LTC1052 is very carefully designed so that gm1 = gm6 and C1 = C2. Substituting these values in the above equa- tion shows I1 – I2 = 0. The gm6 input stage, with Cl and C2, not only filters the input to the sampling loop, but also acts as a high frequency path to give the LTC1052 good high frequency response. The unity-gain cross frequencies for both the DC path and high frequency path are identical [f3dB = thereby making the frequency response smooth and con- tinuous while eliminating sampling noise in the output as the loop transitions from the high gain DC loop to the high frequency loop. The typical curves show just how well the amplifier works. The output spectrum shows that the difference frequency I–f S = 100Hz) is down by 80dB and the frequency response curve shows no abnormalities or perturbations. Also note the well-behaved small and large-signal step responses and the absence of the sampling frequency in the output spectrum. If the dynamics of the amplifier (i.e., slew rate and overshoot), depend on the sampling clock, the sampling frequency will appear in the output spectrum.

SC11 SC2 2π (gm1/C1) = 1 2π (gm6/C2)] LTC1052/7652 • TPC13 gm1 gm6 gm2 +I N –I N VREF RL1 gm4+ – – + – RL5 VOUT RL4 CEXT A CEXT B VNULL RL2 gm5 gm3 Figure 1a. LTC1052 Block Diagram Auto Zero Cycle

Figure 1b. LTC1052 Block Diagram Sampling Cycle THEORY OF OPERATIOU LTC1052/7652 • TO02 gm6 +I N –I N VREF RL1 + – – + – RL5 VOUT RL4 CEXT A CEXT BRL2 δl gm1 gm2 gm3 gm4 gm5 APPLICATIO S I FOR ATIOWU UU EXTERNAL CAPACITORS CEXTA and CEXTB are the holding elements of a sample- and-hold circuit. The important capacitor characteristics are leakage current and dielectric absorption. A high quality film-type capacitor such as mylar or polypropylene provides excellent performance. However, low grade capacitors such as ceramic are suitable in many applications. Capacitors with very high dielectric absorption (ceramic) can take several seconds to settle after power is first turned on. This settling appears as clock ripple on the output and, as the capacitor settles, the ripple gradually disappears. If fast settling after power turn-on is important, mylar or polypropylene is recommended. Above 85°C, leakage, both from the holding capacitors and the printed circuit board, becomes important. To maintain the capabilities of the LTC1052 it may be necessary to use Teflon™ capacitors and Teflon standoffs when operating at 125 °C (see Achieving Picoampere/ Microvolt Performance). C EXTA and C EXTB are normally in the range of 0.1 µF to 1.0µF. All specifications are guaranteed with 0.1µF and the broadband noise (refer to Typical Performance Char- acteristics) is only very slightly degraded with 0.1 µF. Output clock ripple is not present for capacitors of 0.1µF or greater at any temperature. On competitive devices, connecting CEXTA and CEXTB to V– causes an increase in amplifier noise. Design changes have eliminated this problem on the LTC1052. On the 14-pin LTC1052 and 8-pin LTC7652, the capacitors can be returned to V – or CRETURN with no change in noise performance. ACHIEVING PICOAMPERE/MICROVOLT PERFORMANCE Picoamperes In order to realize the picoampere level of accuracy of the LTC1052, proper care must be exercised. Leakage currents in circuitry external to the amplifier can significantly degrade performance. High quality insulation should be used (e.g., Teflon, Kel-F); cleaning of all insulating surfaces to remove fluxes and other residues will probably be necessary—particularly for high temperature performance. Surface coating may be necessary to provide a moisture barrier in high humidity environments. Board leakage can be minimized by encircling the input connections with a guard ring operated at a potential close to that of the inputs: in inverting configurations, the guard ring should be tied to ground; in noninverting Teflon is a trademark of Dupont.

amplitude, thus cancellation occurs. 100 seconds the oven, preset to 125°C, was switched on. ±0.05µV/°C drift specification. both with the circuit covered and with no cover in “still” air. Figure 3. Offset Drift Test Circuit Figure 4. Transient Response of Offset Drift Test Circuit with 100°C Temperature Step

0 MIN 25 MIN20 MIN5 MIN

100 SECONDS/IN

1 VOS • 1000

transient temperature conditions. The answer is simple. that cannot be distinguished from legitimate signals. thermal EMF effects are an important source of errors. Figure 4. This can only be attributed to the package since warmed-up drift if offsets of less than ±5µV are required. Figure 5. DC to 1Hz (Test Circuit TC3)

20 SEC

this is the function of the 14-pin device. and sets the sampling frequency. avoid this, keep this capacitance below 5pF.

If the LTC1052 is driven into saturation, the nulling loop, attempting to force the differential input voltage to zero, will drive C EXTA and C EXTB to a supply rail. After the saturating drive is removed, the capacitors take a finite time to recover—this is the overload recovery time. The overload recovery is longest when the capacitors are driven to the negative rail (refer to Overload Recovery in the Typical Performance Characteristics section). The overload recovery time in this case is typically 225ms. In the opposite direction (i.e., C EXTA and CEXTB at positive rail), it is about ten times faster (25ms). The overload recovery time for the LTC1052 is much faster than com- petitive devices; however, if a faster overload recovery time is necessary, the output clamp function can be used. When the output clamp is connected to the negative input it prevents the amplifier from saturating, thus keeping C EXTA and CEXTB at their nominal voltages. The output clamp is a switch that turns on when the output gets to APPLICATIO S I FOR ATIOWU UU within approximately 1V of either supply rail. This switch is in parallel with the amplifier’s feedback resistor. As the output moves closer to the rail, the switch on resistance decreases, reducing the closed loop gain. The output swing is reduced when the clamp function is used. How much current the output clamp leaks when off is important because, when used, it is connected to the amplifier’s negative input. Any current acts like input bias current and will degrade accuracy. At the other extreme, the maximum current the clamp conducts when on deter- mines how much overdrive the clamp will take, and still keep the amplifier from saturating. Both of these numbers are guaranteed in the Electrical Characteristics section. LOW SUPPLY OPERATION The minimum supply voltage for proper operation of the LTC1052 is typically 4.0V ( ±2.0V). In single supply applications, PSRR is guaranteed down to 4.7V (±2.35V). This assures proper operation down to the minimum TTL specified voltage of 4.75V. TYPICAL APPLICATIO SU 5V Powered Ultraprecision Instrumentation Amplifier Fast Precision Inverter LTC1052/7652 • TA04 8pF –5V 1N4148 10k* 1000pF 300pF 0.1µF *1% METAL FILM INPUT 0.1µF 10k –5 V OUTPUT 10k 10k FULL POWER BANDWIDTH = 2MHz SLEW RATE = 40V/µs SETTLING (10V STEP) = 12µs TO 0.01% BIAS CURRENT DC = 30pA OFFSET DRIFT = 50nV/°C OFFSET VOLTAGE = 5µV 10k* LT318A+ LTC1052 LTC1052/7652 • TA03 +I N VOUT 0.1µF LTC1043 43k 0.22µF 100k –I N 1N914 0.0047µF 100 ≈– 0.5V CIRCUITRY WITHIN DASHED LINES MAY BE DELETED IF OUTPUT DOES NOT HAVE TO SWING ALL THE WAY TO GROUND 1µF1µF 1µF 1µF 1617 0.1µF 10k DRIFT = 50nV/°C VOS = 3µV GAIN = CMRR = >120dB DC – 20kHz BANDWIDTH = 10Hz R1 + 1 8 + LTC1052

Offset Stabilized Comparator 1HZ to 1.25MHz Voltage-to-Frequency Converter (5V Supply) LTC1052/7652 • TA05 LTC1043 COMPARATOR INPUTS STATUS OUTPUT OV = ZERO 5V = COMPARE –5V 14 13 GROUND OR INPUT COMMON- MODE VOLTAGE 15 18 LTC1052 ZERO COMMAND 5V = ZERO –5 V= COMPARE LT1011 COMPARATOR OUTPUT (± 5V) 10k –5 V 150Ω330Ω 2k –5 V 1µF 0.1µF 0.1µF VIN OV TO 5V TRW MTR–5/ +1200ppm/°C POLYSTYRENE–WESCO #32–P/ – 120ppm/ °C LINEARITY DYNAMIC RANGE ZERO POINT DRIFT GAIN DRIFT ± 0.05% >120dB 0.01Hz/°C 20ppm/°C 0.22µF LTC1043 LTC1052 2 8 0.1µF 0.1µF 10k 74C04 NC 0.01µF OUTPUT 1H to 1.25MHz 3.3pF 10k 100pF** 1/2 16 14 13 LT1004-1.2V 10k FULL-SCALE TRIM (1.25MHz)30.1k* 3.3k 10k 470Ω 330pF 2N2907 470Ω LTC1052/7652 • TA06 2N3904 0.01µF 0.1µF

No VOS Adjust* CMOS DAC Buffer—Single Supply Air Flow Detector TYPICAL APPLICATIO SU 1Hz to 30MHz Voltage-to-Frequency Converter 5V = NO AIR FLOW 0V = AIR FLOW 0.1µF 240Ω 10k AIR FLOW 43.2Ω ± 1% LTC1052/7652 • TA08 TYPE K 0.1µF AMBIENT TEMPERATURE STILL AIR 100k ± 1% LT1004-1.2 LTC1052 *OFFSET VOLTAGE CAUSES NONLINEARITY ERRORS. SEE: “APPLICATION GUIDE TO CMOS MULTIPLYING D/A CONVERTERS,” ANALOG DEVICES, INC. 10k 15V LTC1043 LTC1052 0.1µF 0.1µF 43k 4 ≈ – 0.5V 1µF NON POLARIZED1N914 VOUT 1pF 15 51k 12–BIT CMOS DAC CF* lOUT1 RFB lOUT2 15V 15V 0.1µF 6 5 FOR HIGHER SPEED, REFER TO “FAST PRECISION INVERTER” UNDER TYPICAL APPLICATIONS LTC1052/7652 • TA07 0.22µF TRIGGER HP5082-2810 1Hz TO 30MHz OUTPUT LT1004–1.2V 11 5 7490 74S741/2 0.3Hz/°C ZERO-DRIFT ±0.08% LINEARITY 20ppm/°C GAIN DRIFT 150dB DYNAMIC RANGE *TRW MTR-5/ + 120ppm/°C †WESCO #32-P/ – 120ppm/ °C 10k 2 8 –5 V 10k 1000M 1Hz TRIM CHARGE PUMP LTC1052/7652 • TA09 0.22µF 0.1µF 1/2 LTC1043 30MHz TRIM IN OV TO 3V –5 V 100k STABILIZING AMP 16.2k* 100pF † 0.1µF 0.0.1µF OUT LTC1052 CURRENT SOURCE 12k 120Ω 7.5k 2N3906 120Ω 0.1µF FET BUFFER 2N5486 100pF 50Ω RESET DIODE 2N3904 50Ω NC –5 V 74S132 100k 2N5486

VOS =5 µV VOS/∆T=5 0µV/°C GAIN = 10 FULL POWER BANDWIDTH = 1kHz LTC1052/7652 • TA10 0.1µF –5 V 0.1µF 5V5V –5 V LTC1052 LTC1010 VOUT VIN RL 100k ±100mA 100pF 100k LOAD 2.5k 220Ω 2000pF 100Ω LTC1052/7652 • TA11 OUTPUT INPUT 10k LTC1052 OUTPUT SWING ± 4.92V ± 4.84V ± 4.65V ± 3.65V 220pF 74C04 10k 0.1µF 0.1µF TYPICAL APPLICATIO SU ±100mA Output Drive Increasing Output Current Single 5V Thermocouple Amplifier with Cold Junction Compensation 5k AT 25°C† 232k 301k 301k 2.1M V T CF* LTC1052/7652 • TA12 100k ≈ – 0.5V THERMOCOUPLE TYPE J K T S RF IN914 43k LT1004-1.2 2187Ω 1µF 1µF 1µF 1690Ω 1k– 1820Ω VOUT = VT 1+ Rl RF Rl 10k NONPOLARIZED 1µF † YELLOW SPRINGS INST. CO. PART #44007 *CHOOSE CF TO FILTER NOISE LTC1043 0.0047µF LTC1052 0.1µF 0.1µF

LTC1052/7652 • TA14 OUTPUT INPUT 8 2 INPUT CAPACITANCE BOOTSTRAP 0.1µF LTC1052 10M FAST SOURCE FOLLOWER BANDWIDTH: 20MHz †RISE: 100ns DELAY: 5ns 1N4148 2N5486 100Ω 2000pF DC STABILIZATION 6Q2 2N2222 –5 V –5 V 10M 0.1µF 0.01µF 0.1µF DRAIN CURRENT SINK 10k LT1010 0.1µF TYPICAL APPLICATIO SU Increasing Output Current and Voltage (VSUPPLY = ±15V) DC Stabilized FET Probe Precision Multiplexed Differential Thermocouple Amplifier –5 V 232k 301k 301k 2.1M 0.1µF LTC1052/7652 • TA15 THERMOCOUPLE TYPE J K T S LT1004–1.2V 187Ω 1µF 0.1µF 1µF 1690Ω COLD JUNCTION COMPENSATOR 100k VOUT = 1001 • VTHERMOCOUPLE 5k AT 25°C† † YELLOW SPRINGS INST. CO. PART #44007 0.1µF 1µF LTC1052 1820Ω 516 1µF –5 V LTC1043 ADDRESS –5 V CD4052B 0.0047µF 13 2 LTC1052/7652 • TA13 –15V2N3904 STABLE FOR ALL GAINS, INVERTING AND NONINVERTING, OBSERVE LTC1052 COMMON MODE INPUT LIMITS LTC1052 OUTPUT ±12V AT 20mA | LIMIT INPUT 3k 2 0.1µF –7 V 0.1µF0.1µF 0.1µF NC 3 7 2N3904 15V NC LT318A 30k 33pF

Direct Thermocouple-to-Frequency Converter Direct 10-Bit Strain Gauge Digitizer LT1004–1.2V 0.01% FILM-TRW MAR-6 TRW/MTR/5/ + 120 R T = YELLOW SPRINGS INST. #44007 100pF = POLYSTYRENE FOR GENERAL PURPOSE (1mV FULL-SCALE) 10-BIT A-TO-D, REMOVE THERMOCOUPLE— COLD JUNCTION NETWORK, GROUND POINT A, AND DRIVE LTC1052 POSITIVE INPUT LTC1052/7652 • TA16 0.1µF OUTPUT 0Hz TO 600Hz 0°C TO 60°C F 74C04 1µF 16 –5 V 74C903 1N4148 RT 820pF EDC10k BA 74C04 0.68µF 3300pF –5 V 470Ω 0.1µF 33k 1.8k* 1k* 100pF LTC1043A† 4.75k* 0.1µF 33k COLD JUNCTION TEMPERATURE TRACKING 150k STABILIZING AMPTYPE K THERMOCOUPLE 41.4µV/°C 100k 1N914 1µF 50k 60°C TRIM OPTIONAL INPUT FILTER-AND-OVERLOAD CLAMP LTC1052 187Ω* 487Ω* 301k* COLD JUNCTION BIAS –5 V LTC1052/7652 • TA17 SW2 1/2 LTC1043 CONNECT TO BRIDGE END OF 470k RESISTOR 33µF22.3k* 3.3M BRIDGE DRIVE 1k* 1N4148 SW1 –5 V 1N4148 10k 4 6 –5 V *0.1% METAL FILM TRW MAR-5 FREQUENCY OUT A FREQUENCY OUT B CONNECT DIRECTLY ACROSS BRIDGE DRIVE POINTS (OPTIONAL) TRANSDUCER ZERO NETWORK 10k 100k SW1 = MAIN CURRENT SWITCH SW2 = CURRENT LOADING COMPENSATION SWITCH –5 V LM301A 20Ω 1k68 3 1 14k CLOCK20Ω 74C00 28kSTRAIN GAUGE TRANSDUCER Z IN = 350Ω ZOUT = 350Ω 1000pF –5 V 1000pF 470k* 0.003µF LTC1052 –5 V 13.3MΩ* 0.01µF OUTPUT GATING 5V5V 0.01µF 4114 1/2 74C903 1/2 74C74 INTEGRATOR DATA OUTPUT = OUT A OUT B = 1000 COUNTS FULL-SCALE 2N2905

–5 V LTC1052/7652 • TA18 1µF3 9 p F LINEARITY TRIM LTC1043 CURRENT SWITCH INTEGRATOR 10k –5 V LT1009 75k* –5 V –5 V –5 V 10k FULL-SCALE TRIM 14k CLOCK 0.1µF 0.01µF 0.1µF 74C00 28k 10pF EIN OV TO 5V 1/3 74C903 820pF 95k* 0.01µF0.1µF0.1µF DATA OUTPUT = AOUT BOUT CURRENT SINK 100,000 COUNTS FULL-SCALE NO ZERO TRIM 20ppm/°C GAIN DRIFT *VISHAY S-102 RESISTOR 1/2 74C74 BOUT AOUT LTC1052 LTC1052 24114 7 8 18 15 20k 2N4338

Precision Isolation Amplifier LTC1052/7652 • TA19 1k* 100k* 14 14 0.1µF0.1µF13 74C90 74C90 10k OUTPUT SIDEINPUT SIDE 22M STANCOR PCT-39 10k 10k 10k 10k* 2N5434 IN4148 2N54342N5434 2N5434 – 15V – 15V – 15V 15V 15V 25mA – 15V 25mA 15V 15V 15V 30pF 10M (SELECT) 15V 13.3k* 1k GAIN TRIM OUT1000pF 1000pF 1N4148 1N4148 1.8k 68pF 68pF 20k 20k 4.3k 11k DALE TC–10–11 1.8k POWER DRIVER 2N2222 2N2222 74C04 74C04 74C04 330Ω 100pF 100k ZERO TRIM 20k 1010 1212 NC NC 2N3904 250V ISOLATION 0.03% ACCURACY *1% FILM RESISTOR FLOATING SUPPLY OUTPUTS 2.2µF 2.2µF FLOATING COMMON 1N4148 ÷10÷10 11 11 100k INPUT LTC1052 LTC1052 14–PIN 2N3904

.050 (1.270) MAX .016 – .021** (0.406 – 0.533) .010 – .045* (0.254 – 1.143) SEATING PLANE .040 (1.016) MAX .165 – .185 (4.191 – 4.699) GAUGE PLANE REFERENCE PLANE .500 – .750 (12.700 – 19.050) .305 – .335 (7.747 – 8.509) .335 – .370 (8.509 – 9.398) DIA .200 (5.080) TYP .027 – .045 (0.686 – 1.143) .028 – .034 (0.711 – 0.864) .110 – .160 (2.794 – 4.064) INSULATING STANDOFF 45°TYP H8(TO-5) 0.200 PCD 0801 LEAD DIAMETER IS UNCONTROLLED BETWEEN THE REFERENCE PLANE AND THE SEATING PLANE FOR SOLDER DIP LEAD FINISH, LEAD DIAMETER IS .016 – .024 (0.406 – 0.610) PIN 1 H Package 8-Lead TO-5 Metal Can (.200 Inch PCD) (Reference LTC DWG # 05-08-1320) OBSOLETE PACKAGE

14-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) OBSOLETE PACKAGE J14 0801 .045 – .065 (1.143 – 1.651) .100 (2.54) BSC.014 – .026 (0.360 – 0.660) .200 (5.080) MAX .015 – .060 (0.381 – 1.524) .125 (3.175) MIN .300 BSC (7.62 BSC) .008 – .018 1 234 56 7 .220 – .310 (5.588 – 7.874) .785 (19.939) MAX.005 (0.127) MIN 14 11 8 91013 12 .025 (0.635) RAD TYP NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS

.014 – .026 (0.360 – 0.660) .200 (5.080) MAX .015 – .060 (0.381 – 1.524) .125 3.175 MIN.100 (2.54) BSC .300 BSC (7.62 BSC) .008 – .018 .005 (0.127) MIN .405 (10.287) MAX .220 – .310 (5.588 – 7.874) 12 3 4 87 65 .025 (0.635) RAD TYP .045 – .068 (1.143 – 1.650) FULL LEAD OPTION .023 – .045 (0.584 – 1.143) HALF LEAD OPTION CORNER LEADS OPTION (4 PLCS) .045 – .065 (1.143 – 1.651)NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS 8-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) OBSOLETE PACKAGE N8 1002 .065 (1.651) TYP .045 – .065 (1.143 – 1.651) .130 ± .005 (3.302 ± 0.127) .020 (0.508) MIN.018 ± .003 (0.457 ± 0.076) .120 (3.048) MIN 12 3 4 87 6 5 .255 ± .015* (6.477 ± 0.381) .400* (10.160) MAX .008 – .015 (0.203 – 0.381) .300 – .325 (7.620 – 8.255) .325 +.035 –.015 +0.889 – 0.3818.255() NOTE: 1. DIMENSIONS ARE INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) .100 (2.54) BSC 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. UPACKAGE DESCRIPTIO N Package 14-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) N14 1002 .020 (0.508) MIN .120 (3.048) MIN .130 ± .005 (3.302 ± 0.127) .045 – .065 (1.143 – 1.651) .065 (1.651) TYP .018 ± .003 (0.457 ± 0.076) .005 (0.125) MIN .255 ± .015* (6.477 ± 0.381) .770* (19.558) MAX 31 2 4 5 6 7 891011121314 .008 – .015 (0.203 – 0.381) .300 – .325 (7.620 – 8.255) .325 +.035 –.015 +0.889 – 0.3818.255() NOTE: 1. DIMENSIONS ARE INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) .100 (2.54) BSC

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LW/TP 1202 1K REV A • PRINTED IN USA  LINEAR TECHNOLOGY CORPORATION 1985 UPACKAGE DESCRIPTIO S16 (WIDE) 0502 NOTE 3 .398 – .413 (10.109 – 10.490) NOTE 4 16 15 14 13 12 11 10 9 N 23 4 5 6 78 N/2 .394 – .419 (10.007 – 10.643) .037 – .045 (0.940 – 1.143) .004 – .012 (0.102 – 0.305) .093 – .104 (2.362 – 2.642) .050 (1.270) BSC .014 – .019 (0.356 – 0.482) TYP 0° – 8° TYP NOTE 3 .009 – .013 (0.229 – 0.330) .005 (0.127) RAD MIN .016 – .050 (0.406 – 1.270) .291 – .299 (7.391 – 7.595) NOTE 4 × 45°.010 – .029 (0.254 – 0.737) INCHES (MILLIMETERS) NOTE: 1. DIMENSIONS IN 2. DRAWING NOT TO SCALE 3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS 4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) .420 MIN .325 ±.005 RECOMMENDED SOLDER PAD LAYOUT .045 ±.005 N

123 N/2

.050 BSC.030 ±.005 TYP 16-Lead Plastic Small Outline (Wide .300 Inch) (Reference LTC DWG # 05-08-1620)

Product Information

LTC7652 specifications and overview.

Summary

Zero-Drift Operational Amplifier

Description

Zero-Drift Operational Amplifier

Source title LTC7652 Datasheet(PDF) - Linear Technology

Related Parts

More parts from the same family.

Browse manufacturer