LTC7130 LINER | Alldatasheet
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Technical content
7130fbFor more information www.linear .com/L TC7130 TYPICAL APPLICATION FEATURES DESCRIPTION The LT C®7130 is a current mode synchronous step-down monolithic converter that can deliver up to 20A continuous load current. It employs a unique architecture which enhances the signal-to-noise ratio of the current sense signal, allow- ing the use of a very low DC resistance power inductor to maximize efficiency in high current applications. This feature also reduces the switching jitter commonly found in low DCR applications. The LTC7130 also includes a high speed differential remote sense amplifier and a programmable cur- rent sense limit that can be selected from 10mV to 30mV to set the output current limit up to 20A. In addition, the DCR temperature compensation feature limits the maximum output current precisely over temperature. The LTC7130 also features a precise 0.6V reference with a guaranteed limit of ±0.5% that provides an accurate output voltage. A 5V to 20V input voltage range supports a wide variety of bus voltages and various types of batteries. The LTC7130 is offered in a compact and low profile BGA pack- age available with SnPb/RoHS compliant terminal finishes.
APPLICATIONS
n Wide VIN Range: 4.5V to 20V n Optimized for Low Duty Cycle Applications n High Efficiency: Up to 95% n L TC Proprietary Current Mode Architecture n High Current Parallel Operation n Ultralow DCR Current Sensing with Temperature Compensation n Programmable Output Current Limit n High Speed Differential Remote Sense Amplifier n ±0.5% Output Voltage Regulation Accuracy n Output Short-Circuit Protection with Soft Recovery n Programmable Soft-Start, T racking n Programmable Fixed Frequency: 250kHz to 770kHz n EXTVCC for Reduced Power Dissipation n Fault Indicator for Output UV/OV Conditions n 6.25mm × 7.5mm × 2.22mm BGA Package n DSP , FPGA, ASIC Reference Designs n Telecom/Datacom Systems n Distributed High Power Density Systems L, LT, LT C, LT M, Burst Mode, OPTI-LOOP, μModule, Linear Technology and the Linear logo are registered trademarks and No RSENSE is a trademark of Analog Devices, Inc. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5705919, 5929620, 6177787, 6580258, 6498466, 6611131, patent pending. High Efficiency, 1.5V/20A Step-Down Converter with Very Low DCR Sensing Efficiency vs Load Current 20V 20A Monolithic Buck Converter with Ultralow DCR Sensing EFFICIENCY POWER LOSS V IN = 12V V OUT = 1.5V L = 0.25/uni03BCH (DCR = 0.37mΩ) EXTVCC = 5V CCM LOAD CURRENT (A) 100 EFFICIENCY (%) POWER LOSS (W)
7130 TA01b
0.1µF 0.25µH (0.37m/uni03A9 DCR) 3.09k 220nF 619Ω 4.7µF 1µF 2.2Ω 121k 470µF 220pF 470µF 20k 30.1k 1nF INTVCC TK/SS ITH GND SVIN FREQ SNS– SNSA+ SNSD+ SW BOOST ILIM L TC7130 DIFFN DIFFP MODE/PLLIN DIFFOUT VFB VOUT 1.5V 20A ITEMP SGND RUN VIN VIN = 5V TO 20V PINS NOT USED IN THIS CIRCUIT : PGOOD CLKOUT EXTVCC 220nF 0.1µF INTVCC 3.01k 2.2Ω
7130 TA01a
7130fb For more information www.linear .com/L TC7130 ABSOLUTE MAXIMUM RATINGS Operating Junction Temperature Range 40°C to 125°C 65°C to 150°C (Note 1) ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN = 5V unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loops VIN Input Voltage Range (Note 3) 4.5 20 V VOUT Output Voltage Range with Diffamp Low DCR Sensing without Diffamp and No Low DCR Sensing 0.6 0.6 3.5 5.5 V V V FB Regulated Feedback Voltage Current ITH Voltage = 1.2V (Note 4) –40°C to 85°C –40°C to 125°C l l 0.597 0.5955 0.6 0.6 0.603 0.6045 V V A B C D E F G H J 2 3 4 TOP VIEW BGA PACKAGE 63-PIN (6.25mm × 7.5mm × 2.22mm) 5 6 7 VIN SW INTVCC GND GND BOOST SGND NC1 NC2DIFFN DIFFP DIFFOUT ITH VFB SNSD+ FREQSNS– TK/SS RUN SNSA+ ITEMP ILIM CLKOUT MODE/ PLLIN SVIN EXTVCC PGOOD TJMAX = 125°C, θJA = 21°C/W, θJC = 10°C/W θJA DERIVED FROM LTC7130 DEMO BOARD, Weight = 0.24g PIN CONFIGURATION PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE TYPE MSL RA TING TEMPERATURE RANGE (SEE NOTE 2)DEVICE FINISH CODE LTC7130EY#PBF SAC305 (RoHS) LTC7130 e1 BGA 3 –40°C to 125°C LTC7130IY#PBF SAC305 (RoHS) LTC7130 e1 BGA 3 –40°C to 125°C
- Device temperature grade is indicated by a label on the shipping container.
- Pad or ball finish code is per IPC/JEDEC J-STD-609.
- Terminal Finish Part Marking: www.linear.com/leadfree
- This product is not recommended for second side reflow. For more information, go to www.linear.com/BGA-assy
- Recommended BGA PCB Assembly and Manufacturing Procedures: www.linear.com/BGA-assy ray Drawings: www.linear.com/packaging
- This product is moisture sensitive. For more information, go to: www.linear.com/BGA-assy ORDER INFORMATION (http://www.linear.com/product/LTC7130#orderinfo)
7130fbFor more information www.linear .com/L TC7130 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN = 5V unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IFB Feedback Current (Note 4) –15 –50 nA VREFLNREG Reference Voltage Line Regulation VIN = 4.5V to 20V (Note 4) 0.002 0.02 % VLOADREG Output Voltage Load Regulation (Note 4) Measured in Servo Loop; ∆ITH Voltage = 1.2V to 0.7V Measured in Servo Loop; ∆ITH Voltage = 1.2V to 1.6V l l 0.01 0.01 0.1 0.1 g m Error Amplifier (EA) T ransconductance ITH =1.2V, Sink/Source 5µA (Note 4) 2 mmho I Q Input DC Supply Current Normal Mode Shutdown (Note 5) V RUN = 0V 3.8 mA µA UVLO Undervoltage Lockout VINTVCC Ramping Down 3.4 3.75 4.1 V UVLOHYS UVLO Hysteresis Voltage 0.5 V VFBOVL Feedback Overvoltage Lockout Measured at V FB l 0.64 0.66 0.68 V ISNSD+ SNSD + Pin Bias Current V SNSD+ = 3.3V 30 100 nA ISNSA+ SNSA + Pin Bias Current V SNSA+ = 3.3V 1 2 µA AVT_SNS Total Sense Signal Gain to Current Comparator
5 V/V
V SENSE(MAX) Maximum Current Sense Threshold –40°C to 125°C VSNS– = 1.8V, ILIM = 0V ILIM = 1/4VINTVCC ILIM = 1/2VINTVCC or Float ILIM = 3/4VINTVCC ILIM = VINTVCC l l l l l 8.8 23.5 28.3 11.2 26.5 31.7 mV mV mV mV mV I TEMP DCR Temperature Compensation Current V ITEMP = 0.3V l 9 10 11 µA ITK/SS Soft-Start Charge Current V TK/SS = 0V l 1.0 1.25 1.5 µA VRUN RUN Pin on Threshold Voltage V RUN Rising l 1.1 1.22 1.35 V VRUN(HYS) RUN Pin on Hysteresis Voltage 80 mV t ON(MIN) Minimum On-Time (Note 6) 90 ns INTVCC Linear Regulator VINTVCC Internal VCC Voltage 6V < V IN < 20V 5.25 5.5 5.75 V Load Regulation IINTVCC = 0mA to 20mA 0.5 2 % VEXTVCC External VCC Switchover Voltage EXTVCC Ramping Positive 4.5 4.7 V EXTVCC Voltage Drop I EXTVCC = 20mA, VEXTVCC = 5.5V 40 100 mV EXTVCC Hysteresis 250 mV Oscillator and Phase-Locked Loop fNOM Nominal Frequency VFREQ = 1.2V 450 500 550 kHz fLOW Lowest Frequency VFREQ = 0.4V 225 250 275 kHz fHIGH Highest Frequency VFREQ > 2.4V 700 770 850 kHz RMODE/PLLIN MODE/PLLIN Input Resistance 250 kΩ IFREQ Frequency Setting Current 9 10 11 µA
7130fb For more information www.linear .com/L TC7130 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VRUN = 5V unless otherwise specified. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC7130 is tested under pulsed load conditions such that T J ≈ TA. The LTC7130E is guaranteed to meet performance specifications from 0°C to 85°C operating junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC7130I is guaranteed to meet performance specifications over the full –40°C to 125°C operating junction temperature range. The maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the package thermal impedance and other environmental factors. The thermal derating curves are based on the LTC7130 demo board. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CLKOUT Phase Relative to the Oscillator Clock
180 Deg
CLKOUTHI Clock Output High Voltage V INTVCC = 5.5V 4.5 5.5 V CLKOUTLO Clock Output Low Voltage 0 0.2 V PGOOD Output VPGDLO PGOOD Voltage Low I PGOOD = 2mA 0.1 0.3 V IPGD PGOOD Leakage Current V PGOOD = 5.5V 2 µA VPGD PGOOD T rip VFB with Respect to Set Output Voltage VFB Going Negative VFB Going Positive –10 Differential Amplifier AV Gain –40°C to 125°C l 0.997 1 1.003 V/V RIN Input Resistance Measured at DIFFP Input 80 kΩ VOS Input Offset Voltage V DIFFP = 1.5V, VDIFFOUT = 100µA 2 mV PSRR Power Supply Rejection Ratio 5V < V IN < 20V (Note 7) 90 dB IOUT Maximum Sourcing Output Current 1.5 2 mA V OUT Maximum Output Voltage V INTVCC = 5.5V, IDIFFOUT = 300µA VINTVCC – 1.4 VINTVCC – 1.1 V GBW Gain-Bandwidth Product (Note 7) 3 MHz SR Slew Rate (Note 7) 2 V/µs RDS(ON) RTOP Top Power NMOS On- Resistance 7.3 mΩ RBOTTOM Bottom Power NMOS On- Resistance 2.1 mΩ Note 3: When 4.5V ≤ V IN ≤ 5.5V, INTVCC must be tied to VIN. Guaranteed by design. Note 4: The LTC7130 is tested in a feedback loop that servos VITH to a specified voltage and measures the resultant VFB. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. Note 6: The minimum on-time condition corresponds to the on inductor peak-to-peak ripple current ≥40% of IMAX (see Minimum On-Time Considerations in the Applications Information section). Note 7: Guaranteed by design.
7130fbFor more information www.linear .com/L TC7130 Load Step (Burst Mode® Operation) Inductor Current at Light Load Load Step (Continuous Conduction Mode) Prebiased Output at 1V Load Step (Pulse-Skipping Mode) TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. Efficiency vs Load Current and Mode Efficiency vs Load Current and Mode Efficiency vs Load Current and Mode Efficiency and Power Loss vs Load Current V IN = 20V EFFICIENCY POWER LOSS V OUT = 1.5V LOAD CURRENT (A) 100 EFFICIENCY (%) POWER LOSS (W) vs Load Current
7130 G04
(Burst Mode Operation) V IN = 12V V OUT = 1.5V FRONT PAGE CIRCUIT 20µs/DIV I LOAD 5A/DIV 1A to 15A V OUT AC–COUPLED 100mV/DIV
7130 G05
V IN = 12V V OUT = 1.5V FRONT PAGE CIRCUIT 20µs/DIV VOUT AC–COUPLED 100mV/DIV ILOAD 5A/DIV 1A to 15A
7130 G06
V IN = 12V V OUT = 1.5V FRONT PAGE CIRCUIT 20µs/DIV I LOAD 5A/DIV 1A TO 15A V OUT AC–COUPLED 100mV/DIV
7130 G07
V IN = 12V V OUT = 1.5V LOAD = 300mA 10µs/DIV PULSE–SKIP MODE 10A/DIV Burst Mode OPERATION 10A/DIV CONTINUOUS CONDUCTION MODE 10A/DIV
7130 G08
V IN = 12V V OUT = 1.5V TRACK/SS 500mV/DIV 20ms/DIV V FB 500mV/DIV V OUT 500mV/DIV
7130 G09
0.1 100 100 EFFICIENCY (%) f SW = 500kHz OUT L = 0.25/uni03BCH (DCR = 0.37mΩ) FRONT PAGE CIRCUIT CCM Burst Mode OPERATION PULSE–SKIPPING MODE V = 1.5V
3681 G01
V IN = 5V LOAD CURRENT (A) 0.1 100 100 EFFICIENCY (%) f SW = 500kHz OUT L = 0.25/uni03BCH (DCR = 0.37mΩ) FRONT PAGE CIRCUIT CCM Burst Mode OPERATION PULSE–SKIPPING MODE V = 1.5V
3681 G02
V IN = 12V LOAD CURRENT (A) 0.1 100 100 EFFICIENCY (%) f SW = 400kHz OUT L = 0.25/uni03BCH (DCR = 0.37mΩ) FRONT PAGE CIRCUIT EXTVCC = 5V CCM Burst Mode OPERATION PULSE–SKIPPING MODE V = 1V
3681 G03
V IN = 12V LOAD CURRENT (A)
7130fb For more information www.linear .com/L TC7130 INTVCC Line Regulation Current Sense Threshold vs ITH Voltage Maximum Current Sense Threshold vs Common Mode Voltage VITH (V) –10 CURRENT SENSE THRESHOLD (mV)–5 0.5 1.0 1.25
7130 G12
ILIM = 0V ILIM = 1/4 INTVCC ILIM = 1/2 INTVCC ILIM = 3/4 INTVCC ILIM = INTVCC VSENSE COMMON MODE VOLTAGE (V) CURRENT SENSE THRESHOLD (mV) 4.0
7130 G13
ILIM = INTVCC ILIM = 0V ILIM = 3/4 INTVCC ILIM = 1/4 INTVCC ILIM = 1/2 INTVCC TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. Shutdown (RUN) Threshold vs Temperature Regulated Feedback Voltage vs Temperature Oscillator Frequency vs Temperature TK/SS Pull-Up Current vs Temperature Maximum Current Sense Threshold Voltage vs Feedback Voltage (Current Foldback) FEEDBACK VOLTAGE (V) MAXIMUM CURRENT SENSE THRESHOLD (mV) 0.3 0.5
7130 G14
0.1 0.2 0.4 0.6 ILIM = INTVCC ILIM = 3/4 INTVCC ILIM = 1/2 INTVCC ILIM = 1/4 INTVCC ILIM = 0V TEMPERATURE (°C) TK/SS (µA)
7130 G15
–50 –25 100 125 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 TEMPERATURE (°C) RUN THRESHOLD (V)
7130 G16
1.00 1.20 1.30 1.10 1.40 1.15 1.25 1.05 1.35 –50 –25 100 125 ON OFF –50 –25 100 125 TEMPERATURE (°C) 598.5REGULATED FEEDBACK VOLTAGE (mV) 599.0 599.5 600.0 600.5
7130 G17
601.0 601.5 –50 –25 100 125 TEMPERATURE (°C) FREQUENCY (kHz)
7130 G18
VFREQ = 1.2V INPUT VOL TAGE (V) INTV CC VOL TAGE (V) CC
7130 G11
0.2V/DIV VOUT 0.5V/DIV 20ms/DIV
7130 G10
VIN = 12V VOUT = 1.5V 1/uni03A9 LOAD VTK/SS VOUT
7130fbFor more information www.linear .com/L TC7130 Oscillator Frequency vs Input Voltage VFREQ = 2.5V VFREQ = 1.2V VFREQ = 0V FREQUENCY (kHz) 500 600 700 400 300 200 100 900 800
7130 G19
INPUT VOLTAGE (V) TYPICAL PERFORMANCE CHARACTERISTICS Undervoltage Lockout Threshold (INTVCC) vs Temperature Shutdown Current vs Input Voltage T A = 25°C, unless otherwise noted. –50 –25 100 125 TEMPERATURE (°C) 2.5 UVLO THRESHOLD (V) 2.7 3.1 3.3 3.5 4.5 3.9
7130 G20
2.9 4.1 4.3 3.7 RISE FALL INPUT VOLTAGE (V) SHUTDOWN CURRENT (µA) 100
7130 G21
Shutdown Current vs Temperature Input Quiescent Current vs Input Voltage without EXTVCC Quiescent Current vs Temperature without EXTV CC –50 –25 100 125 TEMPERATURE (°C) SHUTDOWN CURRENT (µA)
7130 G22
INPUT VOLTAGE (V)
7130 G23
QUIESCENT CURRENT (mA) 3.50 3.75 4.00 3.25 3.00 2.75 2.50 –50 –25 100 125 TEMPERATURE (°C)
7130 G24
QUIESCENT CURRENT (mA) 3.2 3.6 2.8 2.4 4.0 3.0 3.4 2.6 3.8 Thermal Derating VIN = 5V Thermal Derating VIN = 12V Thermal Derating VIN = 20V V OUT = 1.5V f SW = 500kHz DC2341A DEMO BOARD NO HEAT SINK 0LFM 200LFM 400LFM AMBIENT TEMPERATURE (°C) 100 125 MAXIMUM LOAD CURRENT (A) Thermal Derating VIN = 5V
7130 G25
V OUT = 1.5V f SW = 500kHz DC2341A DEMO BOARD NO HEAT SINK 0LFM 200LFM 400LFM AMBIENT TEMPERATURE (°C) 100 125 MAXIMUM LOAD CURRENT (A) Thermal Derating VIN = 12V
7130 G26
V OUT = 1.5V f SW = 500kHz DC2341A DEMO BOARD NO HEAT SINK 0LFM 200LFM 400LFM AMBIENT TEMPERATURE (°C) 100 125 MAXIMUM LOAD CURRENT (A) Thermal Derating VIN = 20V
7130 G27
7130fb For more information www.linear .com/L TC7130 PIN FUNCTIONS FREQ (B7): Oscillator Frequency Control Input. A 10µA current source flows out of this pin. Connecting a resistor between this pin and ground sets a DC voltage which in turn programs the oscillator frequency. Alternatively, this pin can be driven with a DC voltage to vary the frequency of the internal oscillator. RUN (B6): Run Control Input. A voltage above 1.22V turns on the IC. Pulling this pin below 1.1V causes the IC to shut down. There is a 1μA pull-up current for the pin. Once the RUN pin rises above 1.22V, an additional 4.5μA pull-up current is added to the pin. TK/SS (B5): Output Voltage T racking and Soft-Start Input. An internal soft-start current of 1.25μA charges the external soft-start capacitor connected to this pin. ITH (A5): Current Control Threshold and Error Ampli - fier Compensation Pin. The current comparator tripping threshold is proportional with this voltage. V FB (A6): Error Amplifier Feedback Input. This pin receives the remotely sensed feedback voltage to set the output voltage through an external resistive divider connected to the DIFFOUT pin or the output. DIFFOUT (A4): Output of Remote Sensing Differential Amplifier. Connect this pin to V FB through a resistive divider to set the desired output voltage. DIFFN (A2): Negative Input of Remote Sensing Differen- tial Amplifier. Connect this pin close to the ground of the output load. DIFFP (A3): Positive Input of Remote Sensing Differential Amplifier. Connect this pin close to the output load. SNSD + (B1): DC Current Sense Comparator Input. The (+) output to the DC current. Comparator is normally connected to a DC current sensing network with a time constant that matches the bandwidth, L/DCR, of the inductor. SNS– (B2): Negative Current Sense Input. This negative input of the current comparator is to be connected to the output. SNSA + (C1): AC Current Sense Comparator Input. The (+) output to the AC current comparator is normally connected to a DCR sensing network. When combined with the SNSD+ pin, the DCR sensing network can be skewed to increase the AC ripple voltage by a factor of 5. ILIM (C2): Current Comparator Sense Voltage Limit. Apply a DC voltage to set the maximum current sense threshold for the current comparator. CLKOUT (C3): Clock Output Pin. The CLKOUT signal is 180° out of phase to the rising edge of the IC internal clock. GND ( D2, D3, D4, E1, E2, E3, F2, F3, G4, G5, G6, H4, H5, H6, H7, J4, J5, J6, J7): Power Ground. Connect this pin closely to the (–) terminal of CV CC and the (–) terminal of CIN. SW (G1, G2, G3, H1, H2, H3, J1, J2, J3): Switch Node Connection. Connect this pin to the output filter induc - tor, bottom N-channel MOSFET drain and top N-channel MOSFET source. Voltage swing at these pins is from a Schottky diode (external) voltage drop below ground to VIN. BOOST (F1): Boosted Top Gate Driver Supply. The (+) terminal of the bootstrap capacitor connects to this pin. This pin swings from a diode voltage drop below INTVCC up to VIN + INTVCC. INTVCC (D1): Internal 5.5V Regulator Output. The internal control circuits are powered from this voltage. Decouple this pin to PGND with a 4.7μF low ESR tantalum or ce - ramic capacitor.
7130fbFor more information www.linear .com/L TC7130 PIN FUNCTIONS SVIN (D5): Main Input Supply. Decouple this pin to PGND with a capacitor (0.1μF to 1μF). For applications where the main input power is 5V, tie the SVIN and INTVCC pins together. VIN (E4, E5, E6, E7, F4, F5, F6, F7, G7): Main Input Supply. These pins connect to the drain of the internal power MOSFETs. Decouple this pin to GND with the input capacitance CIN. EXTVCC (D7): External Supply Voltage Input. Whenever an external voltage supply greater than 4.7V is connected to this pin, an internal switch will close and bypass the internal low dropout regulator, and the external supply will power the IC. Do not exceed 6V on this pin and ensure VIN > VEXTVCC at all times. ITEMP (D6): Temperature DCR Compensation Input. Con- nect to a NTC (negative tempco) resistor placed near the output inductor to compensate for its DCR change over temperature. Floating this pin or tying it to INTVCC disables the DCR temperature compensation function. PGOOD (C7): Power Good Indicator Output. Open-drain logic out that is pulled to ground when the output exceeds the 10% regulation window, after the internal 20μs power bad mask timer expires. MODE/PLLIN (C6): Mode Operation or External Clock Synchronization. Connect this pin to SGND to set the continuous mode of operation. Connect to INTVCC to en- able pulse-skipping mode of operation. Leaving the pin floating will enable Burst Mode operation. A clock signal applied to the pin will force the controller into continuous mode of operation and synchronizes the internal oscillator. SGND (B3, B4, C4, C5): Signal Ground. This is the ground of the controller. Connect compensation components and output setting resistors to this ground. NC (A1, A7): Do not connect. These pins are not connected to anything internally.
7130fb For more information www.linear .com/L TC7130 FUNCTIONAL BLOCK DIAGRAM – + –+ + SLEEP INTVCC 0.55V – + – + 0.5V SS – + 1.22V RUN 1.25µA VIN EA ITH RUN TK/SS 0.6V REF S R Q 5.5V REG ACTIVE CLAMP OSC MODE/SYNC DETECT SLOPE COMPENSATION UVLO R ITHB 1µA/5.5µA FREQ CLKOUT MODE/PLLIN ITEMP 0.6V BURST EN EXTVCC ILIM + – ICOMP IREV F – + 4.7V F OV UV DIFFAMP AMP 0.54V VFB PGOOD GND CB VOUT VIN COUT DB SNS– SNSA+ SW BOOST INTVCC DIFFN DIFFP SNSD+ 7130 BD SGND 0.66V 40k 40k 40k 40k SWITCH LOGIC AND ANTISHOOT- THROUGH OV RUN ON FCNT PLL-SYNC TEMPSNS CIN SVIN VSNS– CVCC INTVCC RC CC1 CSS DIFFOUT RA RB
7130fbFor more information www.linear .com/L TC7130 OPERATION Main Control Loop The LTC7130 uses a LT C proprietary current sensing, current mode step-down architecture. During normal operation, the top MOSFET is turned on every cycle when the oscillator sets the RS latch, and turned off when the main current comparator, ICMP , resets the RS latch. The peak inductor current at which I CMP resets the RS latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier, EA. The remote sense ampli- fier (diffamp) produces a signal equal to the differential voltage sensed across the output capacitor divided down by the feedback divider and re-references it to the local IC ground reference. The V FB pin receives this feedback signal and compares it to the internal 0.6V reference. When the load current increases, it causes a slight decrease in the VFB pin voltage relative to the 0.6V reference, which in turn causes the ITH voltage to increase until the inductor’s average current equals the new load current. After the top MOSFET has turned off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator, I REV , or the beginning of the next cycle. The main control loop is shut down by pulling the RUN pin low. Releasing RUN allows an internal 1.0µA current source to pull up the RUN pin. When the RUN pin reaches 1.22V, the main control loop is enabled and the IC is powered up. When the RUN pin is low, all functions are kept in a controlled state. Sensing Signal of Very Low DCR The LTC7130 employs a unique architecture to enhance the signal-to-noise ratio that enables it to operate with a small sense signal of a very low value inductor DCR, 1mΩ or less, to improve power efficiency, and reduce jitter due to the switching noise which could corrupt the signal. The LTC7130 comprises two positive sense pins, SNSD+ and SNSA+, to acquire signals and processes them internally to provide the response as with a DCR sense signal that has a 14dB signal-to-noise ratio improvement. In the meantime, the current limit threshold is still a function of the inductor peak current and its DCR value, and can be accurately set from 10mV to 30mV in a 5mV steps with the ILIM pin. The filter time constant, R1 • C1, of the SNSD+ should match the L/DCR of the output inductor, while the filter at SNSA+ should have a bandwidth of five times larger than SNSD+, R2 • C2 equals R1 • C1/5 (see Figure 3). INTVCC/EXTVCC Power Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTV CC pin. When the EXTVCC pin is tied to a voltage less than 4.7V, an internal 5.5V linear regulator supplies INTV CC power from VIN. Ground EXTVCC if it is not used. If EXTV CC is taken above 4.7V, the 5.5V regulator is turned off and an internal switch is turned on connecting EXTVCC to INTVCC. Using the EXTVCC pin allows the INTVCC power to be derived from a high efficiency external source such as a switch- ing regulator output. The top MOSFET driver is biased from the floating bootstrap capacitor, CB, which normally recharges during the off cycle through an external diode when the top MOSFET turns off. If the input voltage, VIN, decreases to a voltage close to VOUT , the loop may enter dropout and attempt to turn on the top MOSFET continu- ously. The dropout detector detects this and forces the top MOSFET off for about one-twelfth of the clock period plus 100ns every third cycle to allow CB to recharge (note 7). However, it is recommended that a load be present or the IC operates at low frequency during the dropout transition to ensure CB is recharged. Internal Soft-Start By default, the start-up of the output voltage is normally controlled by an internal soft-start ramp. The internal soft-start ramp connects to the noninverting input of the error amplifier. The V FB pin is regulated to the lower of the error amplifier’s three noninverting inputs (the inter- nal soft-start ramp, the TK/SS pin or the internal 600mV reference). As the ramp voltage rises from 0V to 0.6V over approximately 600µs, the output voltage rises smoothly from its prebiased value to its final set value. Certain applications can result in the start-up of the con- verter into a non-zero load voltage, where residual charge is stored on the output capacitor at the onset of converter switching. In order to prevent the output from discharging under these conditions, the bottom MOSFET is disabled until soft-start is greater than VFB.
7130fb For more information www.linear .com/L TC7130 Shutdown and Start-Up (RUN and TK/SS Pins) The LTC7130 can be shut down using the RUN pin. Pulling the RUN pin below 1.1V shuts down the main control loop for the controller and most internal circuits, including the INTVCC regulator. Releasing the RUN pin allows an internal 1.0µA current to pull up the pin and enable the controller. Alternatively, the RUN pin may be externally pulled up or driven directly by logic. Be careful not to exceed the absolute maximum rating of 6V on this pin. The start-up of the controller’s output voltage, V OUT , is controlled by the voltage on the TK/SS pin, if the internal soft-start has expired. When the voltage on the TK/SS pin is less than the 0.6V internal reference, the LTC7130 regulates the V FB voltage to the TK/SS pin voltage instead of the 0.6V reference. This allows the TK/SS pin to be used to program a soft-start by connecting an external capacitor from the TK/SS pin to SGND. An internal 1.25µA pull-up current charges this capacitor, creating a voltage ramp on the TK/SS pin. As the TK/SS voltage rises linearly from 0V to 0.6V (and beyond), the output voltage, VOUT , rises smoothly from zero to its final value. Alternatively, the TK/SS pin can be used to cause the start-up of VOUT to track that of another supply. Typically, this requires connect- ing to the TK/SS pin an external resistor divider from the other supply to ground (see the Applications Information section). When the RUN pin is pulled low to disable the controller, or when INTVCC drops below its undervoltage lockout threshold of 3.75V, the TK/SS pin is pulled low by an internal MOSFET. When in undervoltage lockout, the controller is disabled and the MOSFETs are held off. Light Load Current Operation (Burst Mode Operation, Pulse-Skipping or Continuous Conduction) The LTC7130 can be enabled to enter high efficiency Burst Mode operation, constant-frequency pulse-skipping mode or forced continuous conduction mode. To select forced continuous operation, tie the MODE/PLLIN pin to SGND. To select pulse-skipping mode of operation, tie the MODE/ PLLIN pin to INTVCC. To select Burst Mode operation, float the MODE/PLLIN pin. When the controller is enabled for Burst Mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the ITH pin indicates a lower value. If the average inductor current is higher than the load current, the error amplifier, EA, will decrease the voltage on the ITH pin. When the ITH voltage drops below 0.5V, the internal sleep signal goes high (enabling “sleep” mode) and both MOSFETs are turned off. In sleep mode, the load current is supplied by the output capacitor. As the output voltage decreases, the EA’s output begins to rise. When the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top MOSFET on the next cycle of the internal oscillator. When the controller is enabled for Burst Mode operation, the inductor current is not allowed to reverse. The reverse current comparator (I REV) turns off the bottom MOSFET just before the inductor current reaches zero, preventing it from reversing and going negative. Thus, the controller operates in discontinuous operation. In forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. The peak inductor current is determined by the voltage on the ITH pin, just as in normal operation. In this mode, the efficiency at light loads is lower than in Burst Mode operation. However, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. When the MODE/PLLIN pin is connected to INTV CC, the LTC7130 operates in PWM pulse skipping mode at light loads. At very light loads, the current comparator, ICMP , may remain tripped for several cycles and force the top MOSFET to stay off for the same number of cycles (i.e., skipping pulses). The inductor current is not allowed to reverse (discontinuous operation). This mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced RF interference as compared to Burst Mode operation. It provides higher low current efficiency than forced continuous mode, but not nearly as high as Burst Mode operation. OPERATION
to maintain low output ripple voltage. controller’s operating frequency from 250kHz to 770kHz. pin and switching frequency. and DIFFN to the load ground. See Figure 1. translated to DIFFOUT, relative to SGND. Figure 1. Differential Amplifier Connection
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when the LTC7130 is in the soft-start or tracking up phase.
7130fb For more information www.linear .com/L TC7130 OPERATION has a positive temperature coefficient. As the temperature of the inductor rises, its DCR value increases. The current limit of the controller is therefore reduced. The LTC7130 offers a method to counter this inaccuracy by allowing the user to place an NTC temperature sensing resistor near the inductor. A constant and precise 10μA current flows out of the ITEMP pin. By connecting a linear- ized NTC resistor network from the ITEMP pin to SGND, the maximum current sense threshold can be varied over temperature according to the following equation: VSENSEMAX(ADJ) = VSENSE(MAX) 2.2– VITEMP 1.5 Where: VSENSEMAX(ADJ) is the maximum adjusted current sense threshold. VSENSE(MAX) is the maximum current sense threshold specified in the Electrical Characteristics table. It is typi- cally 10mV, 15mV, 20mV, 25mV or 30mV, depending on the ILIM pin’s voltage. VITEMP is the voltage of the ITEMP pin. The valid voltage range for DCR temperature compensation on the ITEMP pin is between 0.7V to SGND with 0.7V or above being no DCR temperature correction. An NTC resistor has a negative temperature coefficient, meaning that its resistance decreases as its temperature rises. The V ITEMP voltage, therefore, decreases as the induc- tor’s temperature i ncreases, and in turn the VSENSEMAX(ADJ) will increase to compensate for the inductor’s DCR temperature coefficient. The NTC resistor, however, is non-linear and the user can linearize its value by building a resistor network with regular resistors. Output Overvoltage Protection An overvoltage comparator, OV, guards against transient overshoots (>10%) as well as other more serious condi- tions that may overvoltage the output. In such cases, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. Undervoltage Lockout The LTC7130 has two functions that help protect the controller in case of undervoltage conditions. A precision UVLO comparator constantly monitors the INTVCC voltage to ensure that an adequate gate-drive voltage is present. It locks out the switching action when INTV CC is below 3.75V. To prevent oscillation when there is a disturbance on the INTVCC, the UVLO comparator has 500mV of preci- sion hysteresis. Another way to detect an undervoltage condition is to monitor the VIN supply. Because the RUN pin has a preci- sion turn-on reference of 1.22V, one can use a resistor divider to VIN to turn on the IC when VIN is high enough. An extra 4.5µA of current flows out of the RUN pin once the RUN pin voltage passes 1.22V. The RUN comparator itself has about 80mV of hysteresis. One can program additional hysteresis for the RUN comparator by adjust - ing the values of the resistive divider. For accurate V IN undervoltage detection, VIN needs to be higher than 4.75V.
and output capacitors are selected. sense thresholds of 15mV and 25mV. nection underneath the current sense element (Figure 2). to prevent noise coupling to the sense signal. shown in the Typical Application section. Figure 2. Sense Lines Placement with Inductor DCR
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Temperature Compensation section for details. and it causes some small error to the sense signal. Figure 3. Inductor DCR Current Sensing
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7130fbFor more information www.linear .com/L TC7130 APPLICATIONS INFORMATION Ensure that R1 and R2 have a power rating higher than this value. However, DCR sensing eliminates the conduction loss of a sense resistor; it will provide a better efficiency at heavy loads. The actual ripple voltage will be determined by the following equation: ∆VSENSE = VOUT VIN
- VIN – VOUT R1• C1• fOSC Inductor DCR Sensing Temperature Compensation with NTC Thermistor For DCR sensing applications, the temperature coefficient of the inductor winding resistance should be taken into account when the accuracy of the current limit is critical over a wide range of temperature. The main element used in inductors is Copper; that has a positive tempco of ap- proximately 4000ppm/°C. The LTC7130 provides a feature to correct for this variation through the use of the ITEMP pin. There is a 10µA precision current source flowing out of the ITEMP pin. A thermistor with a NTC (negative tem- perature coefficient) resistance can be used in a network, RITEMP (Figure 3) connected to maintain the current limit threshold constant over a wide operating temperature. The ITEMP voltage range that activates the correction is from 0.7V or less. If floating this pin, its voltage will be at INTVCC potential, about 5.5V. When the ITEMP voltage is higher than 0.7V, the temperature compensation is inactive. The following guidelines will help to choose components for temperature correction. The initial compensation is for 25°C ambient temperature: 1. Set the ITEMP pin resistance to 70k at 25°C. With 10µA flowing out of the ITEMP pin, the voltage on the ITEMP pin will be 0.7V at room temperature. Current limit correction will occur for inductor temperatures greater than 25°C. 2. Calculate the ITEMP pin resistance at the maximum inductor temperature, which is typically 100°C. Use the following equations: VITEMP100C = 0.7 –1.5 IMAX DCR (Max) 100°C– 25°C( ) 0.4 100 VSENSE(MAX) = 0.25V Since VSENSE(MAX) = IMAX • DCR (Max): RITEMP100C = VITEMP100C 10µA =25k where: RITEMP100C = ITEMP pin resistance at 100°C; VITEMP100C = ITEMP pin voltage at 100°C; VSENSE(MAX) = Maximum current sense threshold at room temperature; IMAX = Maximum load current; and DCR (Max) = Maximum DCR value. Calculate the values for the NTC network’s parallel and series resistors, RP and RS. A simple method is to graph the following RS versus RP equations with RS on the y-axis and RP on the x-axis. RS = RITEMP25C – RNTC25C||RP RS = RITEMP100C – RNTC100C||RP Next, find the value of R P that satisfies both equations, which will be the point where the curves intersect. Once RP is known, solve for RS. The resistance of the NTC thermistor can be obtained from the vendor’s data sheet in the form of graphs, tabulated data, or formulas. The approximate value for the NTC thermistor for a given temperature can be calculated from the following equation: R =RO •exp B• 1 T +273 – 1 TO +273
R = Resistance at temperature T, which is in degrees C. RO = Resistance at temperature TO, typically 25°C. B = B-constant of the thermistor. thermistor and the ITEMP pin network over temperature. TL is the inductor temperature. to IMAX for inductor temperatures between 25°C and 100°C. compensation network. (Figure 5). Figure 5. Worst-Case IMAX Versus Inductor Temperature Curve Figure 6. Thermistor Location. Place the Thermistor Next to
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Figure 4. Resistance Versus Temperature for the ITEMP Pin
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- NTC RO = 100k
- RS = 20k
- RP =100k But, the final values should be calculated using the above equations and checked at 25°C and 100°C. After determin- ing the components for the temperature compensation network, check the results by plotting IMAX versus inductor temperature using the following equations: IDC(MAX) = VSENSEMAX(ADJ) – ΔVSENSE DCR(MAX) at 25°C 1 + TL(MAX) – 25°C( ) 0.4 100 ⎝⎜ ⎞ where: VSENSEMAX(ADJ) = VSENSE(MAX) 2.2– VITEMP 1.5 ; DCR = 0.53mΩ L = 0.33/uni03BCH RITEMP: RS = 20k RP = 100k THERMISTOR: RO = 100k TO = 25°C B = 4334 FOR 25°C TO 125°C NOMINAL IMAX UNCORRECTED IMAX CORRECTED IMAX INDUCTOR TEMPERATURE (°C) –50 –25 100 125 150 I MAX (A)
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thermistor next to the output inductor as shown in Figure 6 . pre-biased output without discharging it. the pre-biased output voltage from being discharged. exceed the maximum junction temperature of the part. Current in the Typical Performance Characteristics. temperature derating with both heatsink and airflow. Figure 7. Temperature Derating Curve Based on the
Table 1. Heat Sink Manufacturer (Thermally Conductive Table 2. Thermally Conductive Adhesive Tape Vendor however, requires a large inductor.
- VOUT VIN Inductor Core Selection Once the inductance value is determined, the type of in- ductor must be selected. Core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con - centrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that induc- tance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle (V OUT)/(VIN). To prevent large voltage transients, a low ESR capacitor sized for the APPLICATIONS INFORMATION
Figure 8. Temperature Derating Curve Based on the Figure 9. Temperature Derating Curve Based on the
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7130fbFor more information www.linear .com/L TC7130 maximum RMS current of one channel must be used. The maximum RMS capacitor current is given by: CIN Required IRMS ≈ IMAX VIN VOUT( ) VIN – VOUT( )⎡⎣ ⎤ This formula has a maximum at V IN = 2V OUT, where IRMS = IOUT/2. This simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capaci- tor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be paralleled to meet size or height requirements in the design. Due to the high operating frequency of the LTC7130, ceramic capacitors can also be used for CIN. Always consult the manufacturer if there is any question. Ceramic capacitors are becoming very popular for small designs but several cautions should be observed. X7R, X5R and Y5V are examples of a few of the ceramic materials used as the dielectric layer, and these different dielectrics have very different effect on the capacitance value due to the voltage and temperature conditions applied. Physically, if the capacitance value changes due to applied voltage change, there is a concomitant piezo effect which results in radiating sound! A load that draws varying current at an audible rate may cause an attendant varying input volt- age on a ceramic capacitor, resulting in an audible signal. A secondary issue relates to the energy flowing back into a ceramic capacitor whose capacitance value is being reduced by the increasing charge. The voltage can increase at a considerably higher rate than the constant current being supplied because the capacitance value is decreasing as the voltage is increasing! Nevertheless, ceramic capacitors, when properly selected and used, can provide the lowest overall loss due to their extremely low ESR. A small (0.1µF to 1µF) bypass capacitor, CIN, between the chip VIN pin and ground, placed close to the LTC7130, is also suggested. A 2.2Ω to 10Ω resistor placed between CIN and VIN pin provides further isolation. The selection of COUT is driven by the required effective series resistance (ESR). Typically once the ESR require- ment is satisfied the capacitance is adequate for filtering. The steady-state output ripple (∆VOUT) is determined by: ∆VOUT ≈ ∆IRIPPLE ESR+ 1 8fCOUT where f = operating frequency, COUT = output capacitance and ∆IRIPPLE = ripple current in the inductor. The output ripple is highest at maximum input voltage since ∆IRIPPLE increases with input voltage. The output ripple will be less than 50mV at maximum VIN with ∆IRIPPLE = 0.4IOUT(MAX) assuming: COUT required ESR < N • RSENSE and COUT > 1 8f( ) RSENSE( ) The emergence of very low ESR capacitors in small, surface mount packages makes very small physical implementa- tions possible. The ability to externally compensate the switching regulator loop using the ITH pin allows a much wider selection of output capacitor types. The impedance characteristic of each capacitor type is significantly differ- ent than an ideal capacitor and therefore requires accurate modeling or bench evaluation during design. Manufacturers such as Nichicon, Nippon Chemi-Con and Sanyo should be considered for high performance through-hole capacitors. The OS-CON semiconductor dielectric capacitors available from Sanyo and the Panasonic SP surface mount types have a good (ESR)(size) product. Once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) require- ment. Ceramic capacitors from AVX, Taiyo Yuden, Murata and TDK offer high capacitance value and very low ESR, especially applicable for low output voltage applications. In surface mount applications, multiple capacitors may have to be paralleled to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. New special polymer surface mount capacitors offer very low ESR also but have much lower capacitive density per unit volume. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. Several APPLICATIONS INFORMATION
7130fb For more information www.linear .com/L TC7130 APPLICATIONS INFORMATION excellent choices are the AVX TPS, AVX TPSV, the KEMET T510 series of surface mount tantalums or the Panasonic SP series of surface mount special polymer capacitors available in case heights ranging from 2mm to 4mm. Other capacitor types include Sanyo POSCAP, Sanyo OS-CON, Nichicon PL series and Sprague 595D series. Consult the manufacturers for other specific recommendations. Differential Amplifier The LTC7130 has true remote voltage sense capability. The sense connections should be returned from the load, back to the differential amplifier’s inputs through a com- mon, tightly coupled pair of PC traces. The differential amplifier rejects common mode signals capacitively or inductively radiated into the feedback PC traces as well as ground loop disturbances. The LTC7130 diffamp has 80kΩ input impedance on DIFFP. It is designed to be con- nected directly to the output. The output of the diffamp connects to the VFB pin through a voltage divider, setting the output voltage. External Soft-Start and T racking The LTC7130 has the ability to either soft-start by itself or track the output of another channel or external supply. When the controller is configured to soft-start by itself, a capacitor may be connected to its TK/SS pin or the internal soft-start may be used. The controller is in the shutdown state if its RUN pin voltage is below 1.1V and its TK/SS pin is actively pulled to ground in this shutdown state. If the RUN pin voltage is above 1.22V, the controller powers up. A soft-start current of 1.25µA then starts to charge the TK/SS soft-start capacitor. Note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp volt- age according to the ramp rate on the TK/SS pin. Current foldback is disabled during this phase to ensure smooth soft-start or tracking. The soft-start or tracking range is defined to be the voltage range from 0V to 0.6V on the TK/SS pin. The total soft-start time can be calculated as: tSOFTSTART = 0.6 • CSS 1.25µA Regardless of the mode selected by the MODE/PLLIN pin, the controller always starts in discontinuous mode up to TK/SS = 0.5V. Between TK/SS = 0.5V and 0.54V, it will operate in forced continuous mode and revert to the selected mode once TK/SS > 0.54V. The output ripple is minimized during the 40mV forced continuous mode window, ensuring a clean PGOOD signal. When the chan- nel is configured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the TK/SS pin. Therefore, the volt- age ramp rate on this pin is determined by the ramp rate of the other supply’s voltage. It is only possible to track another supply that is slower than the internal soft-start ramp. Note that the small soft-start capacitor charging current is always flowing, producing a small offset error. To minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. In order to track down another channel or supply after the soft-start phase expires, the LTC7130 is forced into continuous mode of operation as soon as VFB is below the undervoltage threshold of 0.54 V regardless of the setting on the MODE/PLLIN pin. However, the LTC7130 should always be set in forced continuous mode tracking down when there is no load. After TK/SS drops below 0.1V, the controller operates in discontinuous mode. The LTC7130 allows the user to program how its output ramps up and down by means of the TK/SS pin. Through these pins, the output can be set up to either coinciden - tally or ratiometrically track another supply’s output, as shown in Figure 10. In the following discussions, V OUT2 refers to the LTC7130’s output as a slave and VOUT1 refers to another supply output as a master. To implement the coincident tracking in Figure 10a, connect an additional resistive divider to VOUT1 and connect its mid-point to the TK/SS pin of the slave controller. The ratio of this divider should be the same as that of the slave controller’s feed- back divider shown in Figure 11a. In this tracking mode, VOUT1 must be set higher than V OUT2. To implement the ratiometric tracking in Figure 10b, the ratio of the V OUT2 divider should be exactly the same as the master control- ler’s feedback divider shown in Figure 11b . By selecting different resistors, the LTC7130 can achieve different modes of tracking including the two in Figure 10.
Figure 10. Tw o Different Modes of Output Voltage T racking Figure 11. Setup and Coincident and Ratiometric T racking the coincident tracking mode instead of ratiometric. gate drivers and much of the LTC7130’s internal circuitry.
pin and make sure that EXTVCC < VIN. required to derive INTVCC power from the output.
- EXTVCC grounded. This will cause INTVCC to be pow-
penalty of up to 10% at high input voltages.
- EXTVCC connected to an external supply. If a 5V external
- EXTVCC connected to an output-derived boost network.
which is typically 4.5V for logic-level devices. Figure 12. Setup for a 5V Input
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external Schottky diode must be greater than V IN(MAX).
Figure 14. Setting Output Voltage
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skipping in order to limit the short-circuit current. phase shift between the external and internal oscillators. harmonics of the external clock. Figure 13. Using Boost Resistor
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the filter capacitor CLP holds the voltage. high threshold is 1.6V, while the input low threshold is 1V. that the LTC7130 is capable of turning on the top MOSFET. ripple and at least 2mV ripple on the current sense signal. the output power divided by the input power times 100%. Figure 15. Relationship Between Oscillator Frequency Figure 16. Phase-Locked Loop Block Diagram
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7130fbFor more information www.linear .com/L TC7130 what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: % Efficiency = 100%–(L1 + L2 + L3 +…) where L1, L2, etc. are the individual losses as a per cent- age of input power. Although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in LTC7130 circuits: 1) I2R losses, 2) switching and biasing losses, 3) other losses. 1. I 2R losses are calculated from the DC resistances of the internal switches, RSW, and external inductor, RL. In continuous mode, the average output current flows through inductor L but is “ chopped” between the internal top and bottom power MOSFETs. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1-DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus to obtain I2R losses: I2R losses = IOUT2(RSW + RL) 2. The INTVCC current is the sum of the power MOSFET driver and control currents. The power MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a power MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from INTVCC to ground. The resulting dQ/dt is a current out of INTVCC that is typically much larger than the DC control bias current. In continuous mode, IGATECHG = f(Q T + QB), where Q T and Q B are the gate charges of the internal top and bottom power MOSFETs and f is the switching frequency. Since INTVCC is a low dropout regulator output powered by V IN, its power loss equals: PLDO = VIN • IINTVCC 3. Other “hidden” losses such as transition loss and cop- per trace and internal load resistances can account for additional efficiency degradations in the overall power system. It is very important to include these “system” level losses in the design of a system. T ransi- tion loss arises from the brief amount of time the top power MOSFET spends in the saturated region during switch node transitions. Other losses including diode conduction losses during dead-time and inductor core losses which generally account for less than 2% total additional loss. Checking T ransient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ∆ILOAD • ESR, where ESR is the effective series resistance of COUT . ∆ILOAD also begins to charge or discharge COUT, generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time VOUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. The availability of the ITH pin not only allows optimization of control loop behavior but also provides a DC-coupled and AC-filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examin- ing the rise time at the pin. The ITH external components shown in the Typical Application circuit will provide an adequate starting point for most applications. The ITH series RC-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a APPLICATIONS INFORMATION
will demonstrate the actual overall supply performance. PC trace spacing from the IC to the feedback divider. should be as close as possible to the pins of the IC. Figure 17. Branch Current Waveforms
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7130fbFor more information www.linear .com/L TC7130 4. Do the (+) plates of C IN connect to the drain of the topside MOSFET as closely as possible? This capacitor provides the pulsed current to the MOSFET. 5. Keep the switching nodes, SW, BOOST away from sensi- tive small-signal nodes (SNSD+, SNSA+, SNS–, DIFFP, DIFFN, VFB). Ideally the SW, and BOOST printed circuit traces should be routed away and separated from the IC and especially the quiet side of the IC. Separate the high dv/dt traces from sensitive small-signal nodes with ground traces or ground planes. 6. Use a low impedance source such as a logic gate to drive the MODE/PLLIN pin and keep the lead as short as possible. 7. The 47 pF to 330pF ceramic capacitor between the ITH pin and signal ground should be placed as close as possible to the IC. Figure 17 illustrates all branch cur- rents in a switching regulator. It becomes very clear after studying the current waveforms why it is critical to keep the high switching current paths to a small physical size. High electric and magnetic fields will radiate from these loops just as radio stations transmit signals. The output capacitor ground should return to the negative terminal of the input capacitor and not share a com- mon ground path with any switched current paths. The left half of the circuit gives rise to the noise generated by a switching regulator. The GND terminations and Schottky diode should return to the bottom plate(s) of the input capacitor(s) with a short isolated PC trace since very high switched currents are present. External OPTI-LOOP® compensation allows overcompensation for PC layouts which are not optimized but this is not the recommended design procedure. 8. Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of CINTVCC must return to the combined COUT (–) terminals. The VFB and ITH traces should be as short as possible. The output capacitor (–) terminals should be connected as close as possible to the (–) terminals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described above. APPLICATIONS INFORMATION 9. Use a modified “star ground” technique: a low imped- ance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTVCC decoupling capacitor, the bottom of the voltage feedback resistive divider and the SGND pin of the IC. Design Example As a design example of the front page circuit for a single channel high current regulator, assume VIN = 12V(nominal), VIN = 20V(maximum), V OUT = 1.5V, I MAX = 20A, and f = 500kHz (see front page schematic). The regulated output voltage is determined by: VOUT = 0.6V • 1 + RB RA Using a 20k 1% resistor from the V FB node to ground, the top feedback resistor is (to the nearest 1% standard value) 30.1k. The frequency is set by biasing the FREQ pin to 1.2V (see Figure 15). The inductance value is based on a 50% maximum ripple current assumption (10A). The highest value of ripple current occurs at the maximum input voltage: L = VOUT f • ∆IL(MAX) 1− VOUT VIN(MAX) This design will require 0.25µH. The Würth 744308025, 0.25µH inductor is chosen. At the nominal input voltage (12V), the ripple current will be: ∆IL(NOM) = VOUT f • L 1− VOUT VIN(NOM) It will have 10.5A (52.5%) ripple. The peak inductor cur- rent will be the maximum DC value plus one-half the ripple current, or around 25A.
7130fb For more information www.linear .com/L TC7130 TYPICAL APPLICATIONS The minimum on-time occurs at the maximum V IN, and should not be less than 90ns: tON(MIN) = VOUT VIN(MAX) f = 1.5V 20V(500kHz) = 150ns DCR sensing is used in this circuit. If C1 and C2 are chosen to be 220nF, based on the chosen 0.25µH inductor with 0.37mΩ DCR, R1 and R2 can be calculated as: R1= L DCR • C1= 3.07k R2 = L DCR • C2 • 5= 614Ω Choose R1 = 3.09k and R2 = 619Ω. The maximum DCR of the inductor is 0.4m Ω. The VSENSE(MAX) is calculated as: VSENSE(MAX) = 25A • DCRMAX = 10mV The current limit is chosen to be 15mV. If temperature variation is considered, please refer to Inductor DCR Sensing Temperature Compensation with NTC Thermistor. For a 0.37mΩ DCR, a short-circuit to ground will result in a folded back current of: ISC = 1/ 3( ) 15mV 0.37mΩ – 1 90ns(20V) 0.25µH ⎜⎜⎜ ⎟⎟⎟ ≈ 10A COUT is chosen with an equivalent ESR of 4.5mΩ for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately: VORIPPLE = RESR (∆IL) ≈ 0.0045Ω • 10A = 45mVP-P Further reductions in output voltage ripple can be made by placing a 100µF ceramic capacitor across COUT. Very Low Output Ripple Converter Although the LTC7130 recommends 50% inductor ripple for most it’s applications, for applications that need very small output ripple, the inductance can be increased to achieve smaller output ripple. The schematic as shown Figure 18 is similar to that of the front page circuit, except that three times the inductance and double the output capacitance are used. The com - pensation components are changed to maintain the same crossover frequency and phase margin. Figure 19 shows the transient response of 10A load step, and Figure 20 demonstrates that the output voltage ripple is a factor of six smaller than that of typical current mode converters.
Figure 18. High Efficiency, 1.5V/15A Step-Down Converter with Very Low Output Ripple
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Figure 19. Load Step T ransient Response Figure 20. Very Low Output Voltage Ripple
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7130fb For more information www.linear .com/L TC7130 TYPICAL APPLICATIONS High Efficiency, Dual Phase Very Low DCR Sensing 1.2V/40A Step-Down Supply VOUT 1.2V 40A COUT 330µF V IN 7V TO 14V 0.25µH, DCR = 0.37m/uni03A9, WURTH 744308025
7130 TA03
10µF 180µF 100µF C OUT 330µF 0.25µH, DCR = 0.37m/uni03A9, WURTH 744308025 10µF ×2220µF 100µF CMDSH3 4.7µF 1µF 120pF 0.1µF 3.3nF EXTVCC PGOOD U1 PINS NOT USED IN THIS CIRCUIT : 20k 137k 20k 2.49k ITEMP 3.09k 220nF 619/uni03A9 220nF 0.22µF 2.2/uni03A9 INTVCC TK/SS ITH RUN GND SVIN FREQ SNS– SNSA+ SNSD+ SW BOOST DIFFN DIFFP MODE/PLLIN DIFFOUT VFB PGOOD CLKOUT SGND ILIM VIN L TC7130 120k PGOOD ITH TK/SS VFB RUN 1/4 VINTVCC CMDSH3 4.7µF 1µF 120pF EXTVCC CLKOUT U2 PINS NOT USED IN THIS CIRCUIT : 137k DIFFOUT ITEMP 3.09k 220nF 619/uni03A9 220nF 0.22µF 2.2/uni03A9 INTVCC TK/SS ITH ILIM GND SVIN MODE/PLLIN FREQ SNS– SNSA+ SNSD+ SW BOOST DIFFN DIFFP VFB PGOOD SGND RUN VIN L TC7130 PGOOD ITH TK/SS VFB 1/4 VINTVCC RUN 1.8/uni03A9 1.8/uni03A9
7130fbFor more information www.linear .com/L TC7130 PACKAGE PHOTOGRAPHS
7130fb For more information www.linear .com/L TC7130 PACKAGE DESCRIPTION Please refer to http://www.linear.com/product/LTC7130#packaging for the most recent package drawings. NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 5. PRIMARY DATUM -Z- IS SEATING PLANE 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW BGA 63 0914 REV Ø L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” PIN 1 0.000 0.80 0.80 1.60 1.60 2.40 2.40 3.20 0.80 2.40 1.60 0.80 1.60 2.40 3.20 0.000 DETAIL A Øb (63 PLACES) F H J E G A B C D 2 14 35 6 7 DETAIL B SUBSTRATE // bbb Z D AA1 ccc Z DETAIL B PACKAGE SIDE VIEW MOLD CAP Z M X Y Z ddd M Z eee 0.4 ±0.025 Ø 63x SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 2.07 0.35 1.72 0.45 0.37 0.27 1.45 NOM 2.22 0.40 1.82 0.50 0.40 7.50 6.25 0.80 6.40 4.80 0.32 1.50 MAX 2.37 0.45 1.92 0.55 0.43 0.37 1.55 0.15 0.10 0.12 0.15 0.08 NOTES DIMENSIONS TOTAL NUMBER OF BALLS: 63 E b e e b F G 63-Lead (7.5mm × 6.25mm × 2.22mm) (Reference LTC DWG # 05-08-1988 Rev Ø)
7 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y SEE NOTESDETAIL A
7130fbFor more information www.linear .com/L TC7130 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER A 07/16 Modified I Q conditions Changed RUN threshold value Modified INTVCC/EXTVCC section, added Note 7 8, 12, 13, 22 B 05/17 Corrected pin number of Boost pin 8
7130fb For more information www.linear .com/L TC7130 LINEAR TECHNOLOGY CORPORATION 2016 LT 0517 REV B • PRINTED IN USA www.linear .com/L TC7130 RELATED PARTS TYPICAL APPLICATION 5V/5A Step-Down Converter PART NUMBER DESCRIPTION COMMENTS LTC3605/ LTC3605A 20V, 5A Synchronous Step-Down Regulator 4V < VIN < 20V, 0.6V < VOUT < 20V, 96% Max Efficiency, 4mm × 4mm LTC3633A LTC3633A-1 Dual Channel 3A, 20V Monolithic Synchronous Step -Down Regulator 3.6V < VIN < 20V, 0.6V < VOUT < VIN, 95% Max Efficiency, 4mm × 5mm QFN-28 and TSSOP-28 Package LTC3622 17V, Dual 1A Synchronous Step-Down Regulator with Ultralow Quiescent Current 2.7V < V IN < 17V, 0.6V < VOUT < VIN, 95% Max Efficiency, 3mm × 4mm DFN-14 and MSOP-16 Package LTC3613 24V, 15A Monolithic Step-Down Regulator with Differential Output Sensing 4.5V < V IN < 24V, 0.6V < VOUT < 5.5V, 0.67% Output Voltage Accuracy, Valley Current Mode, Programmable from 200kHz to 1MHz, Current Sensing, 7mm × 9mm QFN-56 Package LTC3624 17V, 2A Synchronous Step-Down Regulator with 3.5μA Quiescent Current 2.7V < V IN < 17V, 0.6V < VOUT < VIN, 95% Max Efficiency, 3.5μA IQ, Zero-Current Shutdown, 3mm × 3mm DFN-8 Package LT M
4639 Low VIN 20A DC/DC μModule
Step-Down Regulator Complete 20A Switch Mode Power Supply, 2.375V < V IN < 7V, 0.6V < VOUT < 5.5V, 1.5% Max Total DC Output Voltage Error, Differential Remote Sense Amp, 15mm × 15mm BGA Package LTM4637 20A DC/DC μModule Step-Down Regulator Complete 20A Switch Mode Power Supply, 4.5V < V IN < 20V, 0.6V < VOUT < 5.5V, 1.5% Max Total DC Output Voltage Error, Differential Remote Sense Amp, 15mm × 15mm BGA or LGA Package
7130 TA02
1.8µH DCR = 4.05m/uni03A9, COILCRAFT XAL7070-182ME COUT 470µF 100µF 4.7µF 1µF 180µF 10µF 100pF 0.1µF 2.2nF PINS NOT USED IN THIS CIRCUIT : 100k 28.7k ITEMP CLKOUT DIFFOUT 1.82k 220nF 2.2/uni03A9 INTVCC TK/SS ITH GND SVIN FREQ SNS– EXTVCC SNSA+ SW BOOST DIFFN DIFFP MODE/PLLIN SNSD+ RUN SGND ILIM VIN L TC7130 PGOOD 120k 20k 147k VFB CMDSH3 0.22µF 2.2/uni03A9