LTC7130

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Rev. 0For more information www.analog.com Document Feedback TYPICAL APPLICATION FEATURES DESCRIPTION 25A Monolithic Synchronous DC/DC Step-Down Converter with PMBus Interface The LT C®7131-1 is a high efficiency, 25A monolithic synchronous buck regulator using a phase lockable con- trolled on-time, current mode architecture. The output voltage is programmable with a single external resistor or an external voltage reference through the reference input (REF) pin. The output voltage can be margined up or down up to ±25% with 0.1% resolution via a PMBus-compliant serial interface. The serial interface can also be used to read back fault status and both time-averaged (~ 4ms) and peak input/output current, input/output voltage and temperature. System configuration and monitoring is supported by the LTpowerPlay® development system. The architecture provides extremely fast response and allows operation at the very low on-times required to reg- ulate low output voltages at high switching frequencies. The operating frequency is programmable from 250kHz to 2MHz with an external resistor or for noise sensitive applications, it can be synchronized to an external clock over the same range.

APPLICATIONS

n 4.5V to 20V VIN Range n 1% Total VOUT Accuracy Over Temperature n Single Resistor-Programmable Reference Voltage: 0.4V to 3.5V n PMBus Compliant Serial Interface: n Programmable Output Voltage Margining: Up to ±25% VOUT Range with 0.1% Resolution n Read Back of Average and Peak Temperature, Current, and Voltage (25Hz Refresh Rate) n Fault Status n Phase-Lockable Fixed Frequency Up to 2MHz n Less Than 1ms Power-Up Time n Optional External Reference Input n Pin Selectable Fast-Margining of the Output Voltage n Power Good Flag with Pin Programmable Thresholds and Filter Delay n Differential Remote Output Voltage Sensing n Master Shutdown Mode: 125μA Supply Current n Clock Out for 2-Phase Operation (50A Load) n Available in a Thermally-Enhanced 6.25mm × 7.5mm × 2.22mm BGA Package n Intelligent Energy Efficient Power Conversion n ASIC/FPGA/Processor Power n Point of Load Conversion All registered trademarks and trademarks are the property of their respective owners. INTVCC L TC7131-1 BOOST 1µF VOUT 0.4V TO 3.5V 25A VIN 5V TO 20V 7131-1 TA01a VIN SGND PGND SW VSENSE+ VSENSE− DAOUT PGFD ASEL PMBus INTERFACE RT CSLEW ILIM MODE/SYNC WP MARGIN ITH CIN FB REF PGLIM TRACK/SS 0.1µF L1 RUN_STBY RUN_MSTR SCL, SDA, ALERT PGOOD CLKOUT V IN = 12V f SW = 500kHz V OUT = 3.3V V OUT = 1.8V V OUT = 1.2V V OUT = 1.0V V OUT = 0.8V V OUT = 0.65V LOAD CURRENT (A) 100 EFFICIENCY (%) 7131-1 TA01b Efficiency and Power Loss vs Load Current

Rev. 0 For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS VSENSE+, VSENSE–, CSLEW, RT, ITH, MODE/SYNC, REF, TRACK/SS, PGFD, PGLIM, ASEL, DAOUT, MARGIN, RUN_STBY, RUN_MSTR, PGOOD, ALERT, Operating Junction Temperature Range (Notes 1,7) TOP VIEW BGA PACKAGE 63-LEAD (7.5Amm × 6.25mm × 2.22mm) TJMAX = 150°C, θJA = 18.5°C/W θJCtop= 25.5°C/W , θJCbottom = 5.8°C/W F H J E G A B C D 6 74 5321 NOTE: 1) θ VALUES ARE DETERMINED BY SIMULATION PER JESD51 CONDITIONS. 2) θJA VALUE IS OBTAINED WITH ADI DEMO BOARD. 3) REFER TO PAGE 24 FOR LAB MEASUREMENT AND DE-RATING INFORMATION. VIN SW GNDPGFDPGOODPGLIMRT GND BOOST SGND ASEL VSENSE+ VSENSE– RUN_STBYREFFB ILIMCSLEWTRACK/SSDAOUTITH CLKOUTSDA ALERT SCLWPMARGIN MODE/SYNC RUN_MSTR SVIN INTVCC ORDER INFORMATION PART NUMBER PACKAGE TYPE BALL FINISH PART MARKING MSL RATING TEMPERATURE RANGEDEVICE FINISH CODE LTC7131RY-1#PBF BGA SAC305(RoHS) LTC7131-1 e1 3 –40°C to 150°C

• Device temperature grade is indicated by a label on the shipping container .
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
• BGA Package and Tray Drawings
• This product is not recommended for second side reflow. This product is moisture sensitive. For more information, go to Recommended BGA PCB Assembly and Manufacturing Procedures. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input Supply Range l 4.5 20 V VREF REF Pin Programming Range l 0.4 3.5 V The l denotes the specifications which apply over the specified operating junction temperature range, VIN = 12V unless otherwise noted. (Note 2)

ELECTRICAL CHARACTERISTICS

Rev. 0For more information www.analog.com The l denotes the specifications which apply over the specified operating junction temperature range, VIN = 12V unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IQ VIN Supply Current Normal Mode Standby Shutdown VRUN_MSTR > 1V (Note 4) VRUN_STBY = 0V, VRUN_MSTR > 1V VRUN_MSTR = 0V 500 125 200 mA µA µA VUVLO INTVCC Undervoltage Reset Hysteresis INTVCC Rising INTVCC Falling l 3.6 3.9 0.32 4.25 V V IREF Reference Current LTC7131R-1 (Note 10) l 99 100 101 µA ΔIREF,LINE Reference Current Line Regulation VIN = 5V to 20V (Note 10) l 0.02 %/V ΔVOUT,OFFSET Regulation Accuracy ΔVOUT,OFFSET = (VSENSE+ – VSENSE–) – VREF VREF = 1.5V (Notes 5, 10) l –0.5 0.5 % ΔVOUT,MARGIN Maximum Margining Range Set Point Accuracy Resolution LSD Step Size MFR_VOUT_COMMAND = –25% to 25%, VREF = 1.5V (Note 5) l –25 –0.5 0.1 0.5 Bits NL_VOUT DAC Nonlinearity ±1 LSB AEA Error Amplifier Open Loop Gain ITH = 1V (Note 5) 80 dB fBW Error Amp Gain Bandwidth Product (Note 6) 20 MHz RIN Differential Amplier Input Resistance Measured at VSENSE+ Pin 160 kΩ tSS Internal Soft-Start Time/VREF External CSS = Float 1 ms/V ICSLEW CSLEW Pull-Up Current VCSLEW = 0V 10 µA ILIM SW Valley Current Limit Sourcing (Note 8), ILIM = INTVCC Sinking l 25 –20 A A IRUN_MSTR RUN_MSTR Pull-Up Current VRUN_MSTR = 0V 1.5 µA IRUN_STBY RUN_STBY Pull-Up Current VRUN_STBY = 0V 2.5 µA VRUN_MSTR Regulator On Threshold (Master Shutdown) Regulator On Hysteresis Regulator Power-Down Threshold Rising Edge Falling Edge IQ < 200μA 0.8 0.9 0.1 0.6 1.0 V V V VRUN_STBY Regulator On Threshold (Standby Mode) Hysteresis Rising Edge Falling Edge 0.7 1 0.05 1.2 V V IASEL ASEL Programming Current 10 µA IPGFD PGFD Programming Current 10 µA ISS SS Current VSS = 0V 4 5 6 µA VIH,MARGIN VIL,MARGIN MARGIN High Voltage MARGIN Low Voltage 1.3 0.4 V V IWP WP Pin Pull-Up Current WP = 0V 10 µA SRMARGIN Reference Slew Rate During Margin Change CSLEW = 1nF CSLEW = OPEN CSLEW = INTVCC 0.1 %/ms %/ms %/µs tINIT Initialization Time Delay from Power Applied Until VOUT Ramp Up (Note 6) 1 ms Oscillator and Power Switch fOSC Oscillator Frequency RT = 25.5k RT = INTVCC l 450 435 500 480 550 525 kHz kHz VIH,SYNC VIL,SYNC SYNC Level High SYNC Level Low 1.2 0.3 V V

Rev. 0 For more information www.analog.com The l denotes the specifications which apply over the specified operating junction temperature range, VIN = 12V unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VMODE Discontinuous Mode Threshold 0.7 1 1.3 V tON(MIN) Minimum On-Time 35 ns tOFF(MIN) Minimum Off-Time 100 ns RTOP Top Power NMOS On Resistance 7.3 mΩ RBOTTOM Bottom Power NMOS On Resistance 2.1 mΩ θCLKOUT Relative Phase of CLKOUT MODE/SYNC = 0V (Note 6) 180 Deg PGOOD VPGOOD,DEFAUL T Default PGOOD Threshold VPGLIM = INTVCC, VOUT >1V ±8 ±10 ±12 % VPGOOD,PROGRAM Program PGOOD Threshold VPGLIM/VREF = 0.19, VOUT ≥ 1V VPGLIM/VREF = 0.38 ±13 7.5 ±17 ILEAK PGOOD Leakage Current ±5 µA VOL PGOOD Output Low Voltage IOUT = 3mA 0.1 0.3 V tPGFD PGOOD Filter Delay PGFD = 0V PGFD = 0.65V PGFD = Open 150 1.0 190 1.6 250 2.2 32.5 µs ms ms INTVCC Linear Regulator VINTVCC Internal VCC Voltage 6 < VIN < 20V 4.8 5 5.2 V VLDO_INT VINTVCC Load Regulation ICC = 0mA to 100mA 0.5 % Output Voltage Readback N Resolution LSB Step Size 0.5 Bits mV VF/S Full Scale Output Voltage (Note 9) 16.4 V VOUT_TUE Total Unadjusted Error LTC7131R-1 l ±1 ±0.5 tCONVERT Conversion Time 40 ms Input Voltage Readback N Resolution LSB Step Size Bits mV VF/S Full Scale Input Voltage (Note 9) 131 V VIN_TUE Total Unadjusted Error l ±1.5 % tCONVERT Conversion Time 40 ms Output Current Readback N Resolution LSB Step Size Bits mA VF/S Full Scale Output Current ±82 A IOUT_TUE Total Unadjusted Error ±10 % tCONVERT Conversion Time 40 ms Input Current Readback N Resolution LSB Step Size Bits mA VF/S Full Scale Input Current ±82 A IIN_TUE Total Unadjusted Error ±10 % tCONVERT Conversion Time 40 ms

Rev. 0For more information www.analog.com Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC7131-1R is specified over the –40°C to 150°C operating junction temperature range. High Junction temperatures degrade operating lifetimes. Note the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: The junction temperature (TJ, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD • θJA) where θJA (in °C/W) is the package thermal impedance. Note 4 : The dynamic input supply current is higher due to power MOSFET gate charging (QG × fOSC). See applications Information for more information. Note 5: The LTC7131-1 is tested in a feedback loop that servos FB to a referenced voltage with the ITH pin forced to a voltage between 0.6V and 1V. Note 6: Guaranteed by design, not subject to test. Note 7: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 150°C when overtemperature protection is active. Continuous operation above the specified maximum junction temperature may impair device reliability or permanently damage the device. Note 8: The LTC7131-1 uses valley current mode control so the current limits specified correspond to the valley of the inductor current waveform. Maximum load current is higher and equals the valley current limit ILIM plus one half of the inductor ripple current. Note 9: The maximum input voltage is 20V and output voltage is 5V. Note 10: Total output accuracy is the sum of the tolerances of IREF, RREF(EXTERNAL), ΔVOUT ,OFFSET, and ΔIREF ,LINE • ΔVIN. The l denotes the specifications which apply over the specified operating junction temperature range, VIN = 12V unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Temperature Readback N Resolution LSB Step Size Bits VF/S Full Scale Temperature ±256 °C TTUE Total Unadjusted Error ±3 °C tCONVERT Conversion Time 40 ms PMBus Interface Parameters VIH, SDA, SCL Input High Voltage 1.35 V VIL, SDA, SCL Input Low Voltage 0.8 V IIH, SDA, SCL Input Leakage Current 0V ≤ VPIN ≤ 5.5V –5 5 µA VOL, SDA Output Low Voltage (SDA) ISDA = 3mA 0.4 V VOL, ALERT Output Low Voltage (ALERT) IALERT = 1mA 0.4 V fSCL Serial Bus Operating Frequency 10 400 kHz tBUF Bus Free Time Between Stop and Start Condition 1.3 µs tHD_SDA Hold Time After (Repeated) Start Condition 0.6 µs tSU_SDA Repeated Start Condition Setup Time 0.6 µs tSU_STO Stop Condition Setup Time 0.6 µs tHD_DAT(OUT) Data Hold Time 150 900 ns tHD_DAT(IN) Input Data Hold Time 0 ns tSU_DAT Data Set-Up Time 100 ns tLOW Clock Low Period 1.3 10000 µs tHIGH Clock High Period 0.6 µs tTIMEOUT_SMB Stuck PMBus Timer Measured from Last PMBus Start Event 30 ms

Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Output Margining VOUT Short Circuit and Recovery Hiccup Mode Enabled VOUT Short Circuit and Recovery Hiccup Mode Disabled Load Regulation Line Regulation IREF vs Temperature IREF vs Input Voltage Die Temperature vs Load Oscillator Frequency vs RT MARGIN REGISTERS PRE–LOADED TO –10% and 10% C SLEW = 56pF 1ms/DIV VOUT 2V/DIV 200mV/DIV C SLEW MARGIN 1V/DIV 7131-1 G10 25mΩ SHORT 10ms/DIV TRACK/SS 2V/DIV V OUT 1V/DIV I L 20A/DIV 7131-1 G11 25mΩ SHORT 10ms/DIV TRACK/SS 2V/DIV V OUT 1V/DIV I L 20A/DIV 7131-1 G12 V IN = 12V V OUT = 1.0V f SW = 500kHz LOAD CURRENT (A) –0.15 –0.10 –0.05 0.00 0.05 V OUT ERROR (%) 7131-1 G13 V IN = 12V V OUT = 1.0V f SW = 500kHz INPUT VOL TAGE (V) –0.10 –0.05 0.05 0.10 V OUT ERROR (%) 7131-1 G14 TEMPERATURE (°C) –50 100 150 99.8 99.9 100.0 100.1 100.2 I REF (µA) 7131-1 G15 INPUT VOL TAGE (V) –0.10 –0.05 0.05 0.10 REF (%) 7131-1 G16 DC2824A DEMOBOARD NO HEATSINK, STILL AIR V OUT = 1V , T A = 25°C V IN = 12V , f SW = 1MHz V IN = 12V , f SW = 500kHz V IN = 18V , f SW = 500kHz V IN = 12V , DCM LOAD CURRENT (A) DIE TEMPERATURE (°C) 7131-1 G17 R T (kΩ) 100 0.1 OSCILLATOR FREQUENCY (MHz) 7131-1 G18

Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS VOUT Error vs VOUT VOUT Command INL VOUT Command DNL VIN Measurement Error vs VIN IOUT Measurement Error vs IOUT IIN Measurement Error vs IIN IOUT Measurement Error vs Inductor Ripple Current Valley Current Threshold vs ITH Voltage Current Limit vs Temperature OUTPUT VOL TAGE (V) –1.0 –0.5 0.5 1.0 MEASUREMENT ERROR (%) 7131-1 G19 MFR_VOUT_COMMAND VALUE (%) –25 –12.5 12.5 –1.0 –0.5 0.5 1.0 INL (LSB) 7131-1 G20 MFR_VOUT_COMMAND VALUE (%) –25 –12.5 12.5 –1.0 –0.5 0.5 1.0 DNL (LSB) 7131-1 G21 INPUT VOL TAGE (V) –1.0 –0.5 0.5 1.0 MEASUREMENT ERROR (%) 7131-1 G22 V IN = 12V , V OUT = 1.5V CCM MODE FRONT PAGE CIRCUIT OUTPUT CURRENT (A) MEASUREMENT ERROR (A) 7131-1 G23 V IN = 12V , V OUT = 1.5V CCM MODE FRONT PAGE CIRCUIT I OUT = 0 to 25A INPUT CURRENT (A) –0.50 –0.25 0.25 0.50 MEASUREMENT ERROR (A) 7131-1 G24 INDUCTOR RIPPLE RANGE FOR BEST ACCURACY DUTY CYCLE < 50% INDUCTOR RIPPLE (% of MAX LOAD) 100 MEASUREMENT ERROR (A) 7131-1 G25 ILIM = 0 ILIM = 1V ILIM = INTV CC ITH VOL TAGE (V) 0.3 0.6 0.9 1.2 –30 –20 –10 CURRENT THRESHOLD (A) 7131-1 G26 I LIM = INTV CC TEMPERATURE (°C) –50 100 150 VALLEY CURRENT LIMIT (A) 7131-1 G27

Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Quiescent Current vs Input Voltage Shutdown Current vs Temperature Standby Current vs Input Voltage Shutdown (RUN_MSTR) Threshold vs Temperature Oscillator Frequency vs Input Voltage Oscillator Frequency vs Temperature Undervoltage Lockout Threshold (INTVCC) vs Temperature INTVCC Line Regulation Dynamic Supply Current vs Input Voltage INPUT VOL TAGE (V) QUIESCENT CURRENT (mA) 7131-1 G28 RUN_MSTR = GND RUN_STBY = GND TEMPERATURE (°C) –50 100 150 100 200 300 400 500 600 SHUTDOWN CURRENT (µA) 7131-1 G29 RUN_STBY = GND RUN_MSTR = GND INPUT VOL TAGE (V) 200 400 600 800 1000 SHUTDOWN CURRENT (µA) 7131-1 G30 RUN_MSTR RISING RUN_MSTR FALLING TEMPERATURE (°C) –50 100 150 0.5 0.6 0.7 0.8 0.9 1.0 SHUTDOWN THRESHOLD (V) 7131-1 G31 INPUT VOL TAGE (V) 450 475 500 525 550 FREQUENCY (kHz) 7131-1 G32 R T = 25.5 kΩ TEMPERATURE (°C) –50 100 150 450 475 500 525 550 OSCILLATOR FREQUENCY (kHz) 7131-1 G33 INTV CC Rising INTV CC Falling TEMPERATURE (°C) –50 100 150 3.00 3.25 3.50 3.75 4.00 4.25 4.50 INTV CC VOL TAGE (V) 7131-1 G34 f = 500kHz f = 1MHz INPUT VOL TAGE (V) 4.0 4.5 5.0 5.5 6.0 INTV CC VOL TAGE (V) 7131-1 G35 f = 250kHz f = 500kHz f = 1MHz INPUT VOL TAGE (V) 120 160 200 SUPPL Y CURRENT (mA) 7131-1 G36

Rev. 0 For more information www.analog.com PIN FUNCTIONS ITH (Pin A1) : Error Amplifier Output and Switching Regulator Compensation Point. The current compara - tor’s trip threshold is linearly proportional to this voltage. Use an RC network between the ITH pin and the FB pin to compensate the feedback loop for optimum transient response. DAOUT (Pin A2): Differential Amplifier Output. TRACK/SS (Pin A3): T racking/Soft-Start Input. For soft- start, a capacitor to ground at this pin sets the ramp rate of the output voltage (approximately 5V/sec/μF). For coincident tracking, connect this pin to a resistive divider between the voltage to be tracked and ground. CSLEW (Pin A4) : Slew Rate Control. Add a capacitor to program the V OUT transition slew rate during margin - ing. The slew rate is equal to 0.1% per ms per nF slew rate capacitance. With a 1nF capacitor , the slew rate is 0.1%/ms. T wo default slew rates are also available when this pin is open or shorted to INTVCC. ILIM (Pin A5): Current Limit Programming Pin. 3-state pin (INTVCC, float or SGND) provides 3 choices of current limit: 25A, 15A or user defined. RUN_MSTR (Pin A6): Enable Run Control Input. When forced below 0.8V, the voltage regulator is shut off. When forced below 0.6V, all circuitry is shut off and the IC is put into a low current shutdown mode (IQ = 125μA). MODE/SYNC (Pin A7): Mode Selection and External Clock Input. If this pin is tied to INTVCC, discontinuous mode is enabled at light loads. If this pin is connected to ground, forced continuous mode is selected. Driving the MODE/ SYNC pin with an external clock signal will synchronize the switching frequency to the applied frequency and dis- able discontinuous mode operation. FB (Pin B1): Error Amplifier Input. FB will be servoed to the REF pin voltage plus or minus any margining offset set through the serial interface. REF (Pin B2): Reference Input and Programming Pin. The voltage at this pin is the default reference that the output is regulated to. The PMBus interface allows margining around this default voltage by up to ±25%. This pin can be driven by an external voltage or can be programmed with a resistor to ground. An internal accurate low drift 100μA current source times the external resistor sets the reference voltage. VSENSE+ (Pin B3): VOUT Positive Terminal Voltage Sense. The internal unity gain differential gain amplifier connects to the VOUT positive terminal through this pin. VSENSE– (Pin B4): VOUT Negative Terminal Voltage Sense. The internal unity gain differential gain amplifier connects to the VOUT negative terminal through this pin. Tying this pin to the INTVCC pin forces the IC to operate as a slave in a two-phase configuration. RUN_STBY (Pin B5): Standby Mode Control Input. When forced below 0.7V, only the voltage regulator is shut off while the ADC and PMBus interface are still active. When shutoff, the ADC refresh rate is reduced to 1Hz and the IC quiescent current is reduced to 500μA. This pin sources 2.5μA. Do not pull up with a low impedance (<10kΩ). SVIN (Pin B6): Signal Input Supply. Decouple this pin to SGND with a capacitor . This pin powers the internal control circuitry. This pin is independent of VIN and may be con- nected to the same voltage or to a higher supply voltage. INTVCC (Pin B7): Internal Regulator 5V Output. The con- trol circuits are powered from this voltage. Decouple this pin to PGND with a minimum of 4.7μF low ESR tantalum or ceramic capacitor . This regulator is mainly designed for internal circuits, not to be used as supply for the other ICs. RT (Pin C1) : Oscillator Frequency. This pin provides two modes of setting the constant switching frequency. Connect a resistor from RT pin to ground to program the switching frequency from 200kHz to 2MHz. Tying this pin to INTVCC enables the internal 500kHz oscillator frequency.

Rev. 0For more information www.analog.com PIN FUNCTIONS PGLIM (Pin C2 ): PGOOD Threshold Programming Pin. The voltage difference ΔV between this pin and SGND sets the VOUT overvoltage threshold to VREF + 0.4 • ΔV and the undervoltage threshold to VREF – 0.4 • ΔV . Tying this pin to INTVCC sets the threshold to its default value of ±10%. SGND (Pins C3, C4): Signal Ground. Reference setting resistor , slew rate control capacitor , and frequency setting resistor connections should return to SGND. For optimum load regulation, the SGND pin should be kelvin-connected to the PCB location between the negative terminals of the output capacitors and should not be connected through the PGND plane. PGOOD (Pin C5): Power Good. This open-drain output is pulled down to SGND on start-up and while the output volt- age is outside the power good window set by the PGLIM pin. If the output voltage increases and stays inside the power good window for more than the delay programmed at the PGFD pin, the PGOOD pin is released. If the output voltage leaves the power good window for more than 16 switching cycles the PGOOD pin is pulled down. PGFD (Pin C6): PGOOD Deglitch Filter Delay Select. The voltage at this pin sets the delay that the output must be in regulation before the PGOOD flag is asserted. The delay can be programmed to one of eight discrete values where tDELAY = 200μs • 2N (N = 0 to 7). ASEL (Pin D1): Serial Bus Address Configuration Input. Connect a ±1% resistor from this pin to ground in order to select the 4 LSBs of the serial bus interface address. (See Table 5). MARGIN (Pin D2): Fast Margining Select. In the default mode when this pin is floating, the reference voltage margin offset is changed with MFR_VOUT_COMMAND through the serial interface. If this pin is pulled high, the reference voltage margin offset is immediately ramped to the value pre-stored in the MFR_VOUT_MARGIN_HIGH register . If this pin is pulled low, the reference voltage mar- gin offset is immediately ramped to the value pre-stored in MFR_VOUT_MARGIN_LOW register . WP (Pin D3): Write Protect Pin. An internal 10µA current source pulls the pin to 3.3V. If WP is high, the PMBus writes are restricted. SCL (Pin D4): Serial Bus Clock Input. A pull-up resistor is required in the application. SDA (Pin D5): Serial Bus Data Input and Output. A pull-up resistor is required in the application. CLKOUT (Pin D6): Clock Out Signal for 2-Phase Operation. The phase of this clock is 180° with respect to the internal clock. Signal swing is from INTVCC to GND. BOOST (Pin D7): Boosted Floating Driver Supplies. The (+) terminal of the booststrap capacitors connect to these pins. These pins swing from a diode voltage drop below INTVCC up to VIN + INTVCC. GND (Pins E1, E2, E3, E4, F1, F2, F3, F4, G1, G2, G3, G4): Power Ground. Must be soldered to PCB for electrical connection and rated thermal performance. ALERT (Pin E5): Open Drain Digital Output. Connect the system SMBALERT interrupt signal to this pin. A pull-up resistor is required in the application. SW (Pins E6, E7, F5, F6, F7, G5, G6, G7, H5, H6, H7, J5, J6, J7): Switching Node. This pin connects to the drains of the internal main and synchronous power MOSFET switches. VIN (Pins H1, H2, H3, H4, J1, J2, J3, J4): Power Input Supply. VIN connects to the drain of the internal N-channel power MOSFET . This pin is independent of SVIN and may be connected to the same voltage or to a lower voltage supply.

Rev. 0 For more information www.analog.com BLOCK DIAGRAM 25A –20A REF REF 10µA PGFD PGOOD VPULLUP REF+∆V/2.5 REF–∆V/2.5 ±25% TO EA FAUL T STATUS ON/OFF 10µA VIN VOUT TEMP IOUT IIN 100µA RREF VIN VIN SVIN L SVIN SW PGNDTG ON FORCED CONTINUOUS ICMP MODE/SYNC RUN_STBY TRACK/SS PWM ON/OFF 0.9V 80k 80k 80k80k REF SGND TEMP2.5µA 100k 5µA 1.0V 0.4V VOUT COUT CIN RUV/OV PGLIM IREV PGOOD FIL TER REG LOGIC CHIP ON/OFF DAMP SDA SCL ALERT WP ASEL MARGIN CLKOUT RT CSLEW CIN QT QB 1.5µA CURRENT SENSE S R Q IIN, IOUT VON OST VIN VSENSE– VSENSE+ RUN_MSTR FB DAOUT DAOUT RC1 RC2 CC2 CC1 ITH CSS ITON DAC A/D RAM/ COUNTER PMBus INTERFACE MUX TEMPERATURE SENSE OSC PLL SYNC POWER DOWN OR HICCUP MODE 7131-1 BD ++– + – INTVCC INTVCC BOOST EA OVP NPG PPG 0.4 tON = VON ITON (0.64pF)

Table 1. LTC7131-1 Supported PMBus Commands

Rev. 0 For more information www.analog.com OPERATION Main Control Loop The LTC7131-1 is a 25A current mode monolithic step-down regulator with PMBus Interface. The accurate 100µA current source on the REF pin allows the user to use just one external resistor to program the output voltage. In normal opera- tion, the internal top power MOSFET is turned on for a fixed interval determined by a one-shot timer , OST . When the top power MOSFET turns off, the bottom power MOSFET turns on until the current comparator , ICMP , trips, restarting the one-shot timer and initiating the next cycle. Inductor current is determined by sensing the voltage drop across the bottom power MOSFET’s VDS. The voltage on the ITH pin sets the comparator threshold corresponding to the inductor valley current. The error amplifier , EA, adjusts this ITH voltage by comparing the feedback signal, FB, from the output volt- age with that of voltage on the REF pin. If the load current increases, it causes a drop in the feedback voltage relative to the internal reference. The ITH voltage then rises until the average inductor current matches that of the load current. At low load current, the inductor current can drop to zero and become negative. This is detected by current reversal comparator , IREV , which then shuts off the bottom power MOSFET , resulting in discontinuous operation. Both power MOSFETs will remain off with the output capacitor sup - plying the load current until the I TH voltage rises above the zero current level ( ~0.6V) to initiate another cycle. Discontinuous mode operation is enabled by tying the MODE pin to INTVCC, which forces continuous synchro- nous operation regardless of output load. The operating frequency is determined by the value of the RT resistor , which programs the current for the internal oscillator . The internal phase-lock loop servos the switch- ing regulator on-time to track the internal oscillator to force constant switching frequency. If an external clock signal is detected on the MODE/SYNC pin, the phase-lock loop will servo the on-time to track the external clock signal instead. VOUT Margining The LTC7131-1 has an internal 9-bit DAC that provides up to ±25% adjustment at 0.1%/bit resolution around the reference voltage set at the REF pin. The digital offset value is changed with the MFR_VOUT_COMMAND command through the PMBus interface. When a change in the ref - erence is detected, the reference is ramped (0.1%/step) from its current value to the new value at a rate set by the capacitor value connected to the CSLEW pin, thus providing programmable slew rate of the V OUT transition. To elim- inate the latency of the PMBus transaction when faster changes are required, the LTC7131-1 can be pre-loaded with two additional offsets with the MFR_VOUT_MARGIN_ HIGH and MFR_VOUT_MARGIN_LOW commands. The reference offset can then be switched between any of these three register values with the 3-state MARGIN pin. When using the MARGIN pin, the latency of the VOUT transition is limited only by the chosen CSLEW capacitor and the loop bandwidth of the power supply. Changes to these registers are prevented by pulling the write protect (WP) pin high. Telemetry Readback The LTC7131-1 has an integrated 13-bit ADC that mon - itors and performs conversions on the input and output voltage, input and output current, and die temperature. The values are refreshed at a 25Hz rate and are readable through the PMBus interface. A peak monitor is also available for each of these teleme- try measurements to provide that highest value measured since the start of the monitor . The monitor is reset by the MFR_CLEAR_PEAKS command, writing to the individual peak register , or de-asserting RUN_MSTR. INTVCC Regulator Power for the top and bottom MOSFET and most other internal circuitry is derived from the INTV CC pin. The regulated 5.0V on this pin is generated from an internal low dropout regulator . The top MOSFET driver is biased from the floating bootstrap capacitor , CB, which normally recharges during the off cycle through an external diode when the top MOSFET turns off. Output Voltage T racking and Soft-Start The LTC7131-1 allows the user to program its output volt- age ramp rate by means of the TRACK/SS pin. An inter - nal 5µA pulls up the TRACK/SS pin to INTVCC. Putting an external capacitor on TRACK/SS enables soft starting the output to prevent current surge on the input supply. If no

TRACK/SS pin as described in the applications section. the PGOOD window defaults to ±10%. delay of approximately 16 switching cycles. ramping up to the internal reference voltage. er-on state. Supply current in this mode is typically 125μA. back up to the last value written prior . trols and puts the LTC7131-1 in master shutdown. Table 2. Shutdown Modes Note: Only VIN, VOUT and temperature telemetry are refreshed.

slowly at a rate determined by the soft-start capacitor value. The SS/VOUT ramp-down rate is calculated by Equation 1. capacitor value and the load. not exceed IMAX ±10% where IMAX is set by the ILIM pin. and remains set until the host clears it. Figure 1. Differential Amplifier Connection

the phases, such as overtemperature condition. details regarding 2-phase operation. by minimizing gate charge losses. to allow the switcher to sink current. programmed for each type of fault. time the output goes out of regulation. Figure 2. Fault Response Timing to Overcurrent Event

Rev. 0 For more information www.analog.com OPERATION UVLO comparator constantly monitors the INTVCC voltage to ensure that an adequate gate-drive voltage is present. It locks out the switching action when INTV CC is below 3.9V. To prevent oscillation when there is a disturbance on the INTVCC, the UVLO comparator has 0.32V of precision hysteresis. Another way to detect an undervoltage condition is to monitor the VIN supply. Because the RUN pin has a pre- cision turn-on reference of 0.9V, one can use a resistor divider to VIN to turn on the IC when VIN is high enough. The RUN comparator itself has about 80mV of hysteresis. For accurate VIN undervoltage detection, VIN needs to be higher than 4.75V. SERIAL INTERFACE The LTC7131-1 serial interface is a PMBus compliant slave device and can operate at any frequency between 10kHz and 400kHz . The address is configurable using an external resistor . In addition the LTC7131-1 always responds to the global broadcast address of 0x5A or 0x5B (7 bit). The serial interface supports the following protocols defined in the PMBus specifications: 1) send command, 2) write byte, 3) write word, 4) group, 5) read byte and 6) read word. The PMBus write operations are not acted upon until a complete valid message is received by the LTC7131-1 including the STOP bit. Communication Failure Attempts to access unsupported commands or writing invalid data to supported commands will result in a CML fault. The CML bit is set in the STATUS_WORD command and the ALERT pin is pulled low. Device Addressing The LTC7131-1 offers four different types of addressing over the PMBus interface, specifically: 1) global, 2) device, 3) rail addressing and 4) alert response address (ARA). Global addressing provides a means of the PMBus mas- ter to address all LTC7131-1 devices on the bus. The LTC7131-1 global address is fixed 0x5A or 0x5B (7 bit) or 0xB4 or 0xB6 (8 bit) and cannot be disabled. Device addressing provides the standard means of the PMBus master communicating with a single instance of an LTC7131-1. The value of the device address is set by the ASEL configuration pin. Rail addressing provides a means of the PMBus master addressing a set of channels connected to the same output rail, simultaneously. This is similar to global addressing, however , the PMBus address can be dynamically assigned by using the MFR_RAIL_ ADDRESS command. It is recommended that rail address- ing should be limited to command write operations. All four means of PMBus addressing require the user to employ disciplined planning to avoid addressing conflicts. Fault Status The STATUS_WORD and ALERT pin provide fault status information of the LTC7131-1 to the host. Bus Timeout Failure The LTC7131-1 implements a timeout feature to avoid hanging the serial interface. The data packet timer begins at the first START event before the device address write byte. Data packet information must be completed within 25ms or the LTC7131-1 will tri-state the bus and ignore the given data packet. Data packet information includes the device address byte write, command byte, repeat start event (if a read operation), device address byte read (if a read operation), and all data bytes. The user is encouraged to use as high a clock rate as pos- sible to maintain efficient data packet transfer between all devices sharing the serial bus interface. The LTC7131-1 supports the full PMBus frequency range from 10kHz to 400kHz. Similarity Between PMBus, SMBus and I2C 2-Wire Interface The PMBus 2-wire interface is an incremental extension of the SMBus. SMBus is built upon I2C with some minor differences in timing, DC parameters and protocol. The PMBus/SMBus protocols are more robust than simple I2C byte commands because PMBus/SMBus provide time-outs to prevent bus hangs and optional packet error

Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION Minimum Off-Time and Minimum On-Time Considerations The minimum off-time, tOFF(MIN), is the smallest amount of time that the LTC7131-1 is capable of turning on the bottom power MOSFET , tripping the current comparator and turning the power MOSFET back off. This time is generally about 100ns. The minimum off-time limit imposes a maximum duty cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached, due to a dropping input voltage for exam- ple, then the output will drop out of regulation. The mini- mum input voltage to avoid dropout is given by Equation 4. VIN(MIN) = VOUT • tON + tOFF(MIN) tON (4) Conversely, the minimum on-time is the smallest dura - tion of time in which the top power MOSFET can be in its “on” state. This time is typically 75ns. In continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of Equation 5. DC MIN = f • tON(MIN) (5) where tON(MIN) is the minimum on-time. As the Equation 5 shows, reducing the operating frequency will alleviate the minimum duty cycle constraint. In the cases where the minimum duty cycle is surpassed, the output voltage will still remain in regulation, but the switching frequency will decrease from its programmed value. This is an acceptable result in many applications, so this constraint may not be of critical importance in most cases. High switching frequencies may be used in the design without any fear of severe consequences. As the sections on inductor and capacitor selection show, high switching frequencies allow the use of smaller board com- ponents, thus reducing the size of the application circuit. Inductor Selection Given the desired input and output voltages, the inductor value and operating frequency determine the ripple cur - rent given by Equation 6. ΔIL = VOUT f •L • 1−VOUT VIN (6) Lower ripple current reduces core losses in the inductor , ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low fre- quency with small ripple current. However , achieving this requires a large inductor . There is a trade-off between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 30-40% of I OUT(MAX). This is especially important at low V OUT operation where V OUT is 1.8V or below. Care must be given to choose an inductance value that will generate a big enough current ripple so that the chip’s valley current comparator has enough sig- nal-to-noise ratio to force constant switching frequency. Meanwhile, also note that the largest ripple current occurs at the highest VIN. To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to Equation 7. L = VOUT f •ΔIL(MAX)

• 1− VOUT VIN(MAX) (7) Once the value for L is known, the type of inductor must be selected. Actual core loss is independent of core size for a fixed inductor value, but is very dependent on the inductance selected. As the inductance increases, core losses decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core losses and are pre - ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard”, which means that LTC7131-1 inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor . Toroid or shielded pot cores in ferrite or permalloy materi- als are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price versus size requirements

NEC/Tokin, Cooper , TDK, Wurth Elektronik and Coilcraft. Refer to Table 3 for more details. Table 3. Representative Surface Mount Inductors be used. The maximum RMS current is given by Equation 8. to minimize transient effects during output load changes. is given to ripple current ratings and long-term reliability. capacitance may require multiples in parallel. a voltage spike at VIN large enough to damage the part. acteristics of all the ceramics for a given value and size.

take several cycles to respond to a step in load current. of overshoot seen at this pin. without breaking the feedback loop. circuits or if a Type 3 compensation network is required. components RC3 and CC3 shown in Figure 13.

1. Choose the crossover frequency. For best perfor -
2. Plot Gain and Phase of the modulator and output

Figure 13. PSPICE Model of a LTC7131-1 Current Mode Regulator

VSENSE+ pin (this is R7 on the DC2824 demo board). LTC7131-1 power supply model shown in Figure 13. gain/phase plot should look similar to Figure 14.

1. Add the calculated components to the LTC7131-1 cir-

until the desired response is obtained. RC1 = A convenient resistor value ~1kΩ. Figure 14. T ransfer Function of Buck Modulator

1. Calculate the component values. Once the gain and

Table 7. ASEL Resistor Selection pin or the OPERATION command as specified in Table 8. Table 8. VOUT Margining with the MARGIN Pin and OPERATION width and the slew rate capacitor (CSLEW). ately stepped from old value to new value in <100ns. The LTC7131-1 has true remote voltage sense capability. feedback PC traces as well as ground loop disturbances.

1. Floating the TRACK/SS selects the internal soft-start
2. If a longer soft-start period is desired, it can be set

externally with a capacitor on the TRACK/SS pin.

Figure 17. Slave IC Circuits the MODE/SYNC pin is set to forced continuous mode.

• (INTVCC current). For example, the LTC7131-1 INTV CC current is about 27.5mA from a 20V supply at 500kHz in the BGA package given by Equation 19. P D = 20V • 27.5mA = 0.55W (19) For applications where the main input power is 5V, tie the SVIN, VIN and INTVCC pins together and tie the combined pins to the 5V input with a 1Ω or 2.2Ω resistor as shown in Figure 18 to minimize the voltage drop caused by the gate charge current. This will override the INTV CC linear regulator and will prevent INTVCC from dropping too low due to the dropout voltage. Make sure the INTVCC voltage is at or exceeds 4.5V to prevent excessive dissipation in the internal Power MOSFETs due to high RDS(ON).

1. Other “hidden” losses such as transition loss and cop-
2. The INTV CC decoupling capacitor should be placed
3. Connect the remote sense pins, VSENSE+ and VSENSE–,
4. Do the (+) plates of C IN connect to the drain of the

itor provides the pulsed current to the MOSFET .

1. Keep the switching nodes, SW , BOOST away from

with ground traces or ground planes.

1. Use a low impedance source such as a logic gate to
2. Figure 20 illustrates all branch currents in a switch -

Figure 20. Branch Current Waveforms

Rev. 0For more information www.analog.com APPLICATIONS INFORMATION loops just as radio stations transmit signals. The out- put capacitor ground should return to the negative terminal of the input capacitor and not share a com - mon ground path with any switched current paths. The left half of the circuit gives rise to the noise generated by a switching regulator . The GND terminations and Schottky diode should return to the bottom plate(s) of the input capacitor(s) with a short isolated PC trace since very high switched currents are present. External OPTI-LOOP® compensation allows overcompensation for PC layouts which are not optimized but this is not the recommended design procedure. 7. Are the signal and power grounds kept separate? The combined IC signal ground pin and the ground return of CINTVCC must return to the combined C OUT (–) ter- minals. The FB and ITH traces should be as short as possible. The output capacitor (– ) terminals should be connected as close as possible to the (– ) termi- nals of the input capacitor by placing the capacitors next to each other and away from the Schottky loop described above. 8. Use a modified “star ground” technique: a low imped- ance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the INTV CC decoupling capacitor , the bottom of the voltage feed- back resistive divider and the SGND pin of the IC. Design Example As a design example of the front page circuit for a single channel high current regulator , assume VIN = 12V(nominal), VIN = 20V(maximum), V OUT = 1.5V, I MAX = 25A, and f = 500kHz (see front page schematic). The value of RREF can be determined by solving Equation 25. RREF = 1.5V 100µA = 15k (25) A value of 15k, 0.5% will be selected for R REF. Calculate the timing resistor using Equation 26. RT = 1.235•1010 500000 – 950 = 23.8k (26) Connect the ILIM pin to INTVCC to choose the 25A current limit setting. The inductance value is based on a 40% maximum rip - ple current assumption (10A). The highest value of ripple current occurs at the maximum input voltage calculated by Equation 27. L = VOUT f •ΔIL(MAX) 1− VOUT VIN(MAX) (27) This design will require 0.25µH. The Würth 744308025, 0.25µH inductor is chosen. At the nominal input voltage (12V), the ripple current is given by Equation 28. ΔIL(NOM) = VOUT f •L 1− VOUT VIN(NOM) (28) It will have 10.5A (42%) ripple. The peak inductor current will be the maximum DC value plus one-half the ripple current, or around 30A. The minimum on-time occurs at the maximum V IN, and should not be less than 90ns (Equation 29). tON(MIN) = VOUT VIN(MAX)f = 1.5V 20V(500kHz) = 150ns (29) COUT is chosen with an equivalent ESR of 4.5mΩ for low output ripple. The output ripple in continuous mode will be highest at the maximum input voltage. The output voltage ripple due to ESR is approximately given by Equation 30. V ORIPPLE = RESR (ΔIL) ≈ 0.0045Ω • 10A = 45mVP-P (30) Further reductions in output voltage ripple can be made by placing a 100µF ceramic capacitor across COUT.

Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION Assuming worst-case conditions of VIN = 12V, CIN should be selected for a maximum current rating of Equation 31. IRMS = 25A •1.5V 12V • 20V 1.5V – 1⎛ ⎝⎜ ⎞ ⎠⎟= 8.25ARMS (31) Finally, define the soft start-up time choosing the proper value for the capacitor and the resistor connected to TRACK/SS. If we set minimum t SS = 5ms, Equation 32 can be solved. CSS = 5µA •5ms 1.5V = 16.7nF (32) The standard value of 18nF guarantees the minimum soft- start up time of 5ms. 2-Phase Operation Using two LTC7131-1’s as a 2-phase regulator to supply 50A loads was discussed in the Operation section. A few more details need to be brought to the user’s attention to ensure correct operation: 1. PMBus connection and READ_IIN/IOUT: Although the 2-phase regulator will operate fine with the PMBus interface connected to the master only, the READ_ IOUT and READ_IIN measured values will only be available for the phase(s) that are connected. Since each phase’s LTC7131-1 supplies half the load in a 2-phase converter , the value read (if from the master only) needs to be doubled to obtain the total I OUT or IIN value. Because of slight differences in tracking between phases due to IC and inductor tolerances, a more accurate reading will be obtained by connect - ing to both phases so that total I OUT and IIN can be computed by summing each phase’s contribution. 2. Slave PGOOD/ALERT status and margining: When the master and slave are monitoring the same output, it is sufficient to monitor the master’ s PGOOD and ALERT pins only. The PGOOD/ALERT pins from both master and slave can also be wire OR’ed if desired. However , if the output voltage is margined with the PMBus interface, the PGOOD/ALERT status of the slave will only be valid if the slave knows what the new margined reference is, i.e. the margin change needs to be sent to both the master and the slave. This can be done easily by using the MFR_RAIL_ADDRESS to assign the same rail address to both the master and slave so that the margin change can be done with a single write. Be aware that PMBus reads from a common address need to be done separately to avoid bus contentions. 3. Using the Master’s CLKOUT: The CLKOUT pin provides an 180° out-of-phase clock that can be connected to the slaves MODE/SYNC pin as a simple way to run the phases out-of-phase with each other . However , be aware that the master’ s CLKOUT pin only provides this out-of-phase clock when the master is using its internal oscillator programmed from the RT pin. If the master is externally clocked, the slave’ s anti-phase clock will need to be obtained from another source. High Duty Cycle Applications The internal power MOSFETs of the LTC7131-1 have a top-to-bottom RDS(ON) ratio of 3.5 to optimize power dis- sipation for low duty-cycle applications. For some appli- cations, such as using a 5V supply (Figure 19) or using a separate low voltage supply connected to V IN pin (see Using Separate SVIN/VIN Supplies section), the duty cycle may be high enough that the top MOSFET power dissipa- tion becomes significant at higher loads. It is important in these types of applications to estimate power loss and die temperature rise to make sure the maximum die tempera- ture is not exceeded. Once a prototype is built, this can be easily verified using the READ_TEMPERATURE command. Another consideration for high duty cycles is the upper limit of how high the duty cycle can go. The bottom MOSFET has a minimum on-time of 150ns (worst case) to sense inductor current and refresh the BOOST capacitor . These means that the maximum achievable duty cycle is given by Equation 33. Max % Duty Cycle = (1 – fSW • 150 • 10-9) • 100% (33) The maximum duty cycle will limit the maximum allowable output voltage at the minimum supply voltage.

Figure 22. L TpowerPlay PGFD config resistors are re-measured. value is written to the 7 bits of the data byte. this bit disables this address.

Table 9. Supported OPERATION Command Register Values to VOUT_MODE will set a CML fault. This read-only command has one data byte. and in a steady-state condition. 9-bit 2’s complement number with 0.1%/bit scaling. are inhibited when the WP pin is high. 9-bit 2’s complement number with 0.1%/bit scaling. and for margining the output voltage. 0V), power cycle, or MFR_RESET command. the soft-start capacitor (Equation 34). the state it was in prior to the shutdown. operations are not supported by the LTC7131-1. Figure 23. MFR_RAIL_ADDRESS Data Byte

VOUT_COMMAND and MFR_VOUT_MARGIN_HIGH, i.e. the value is not required to be lower . are inhibited when the WP pin is high. 9-bit 2’s complement number with 0.1%/bit scaling. LOW, i.e. the value is not required to be higher . are inhibited when the WP pin is high. This read-only command has one data byte. The 16-bit word representing the part name and revision. LSB is adjustable by the manufacturer . This read-only command has 2 data bytes. PEAK data values and restarts the peak monitor routine. accept (and ignore) up to two. mation with a summary of the unit’s fault condition. immediately be set again if the fault remains. This command has two data bytes. MFR_RESET, and master shutdown (RUN_MSTR). Table 10. MFR_FAULT_RESPONSE Data Byte

0 Overcurrent Fault Hiccup Mode Enable 0: Disable

1 Overvoltage Fault Hiccup Mode Enable 0: Disable

typically within 50ms of the initialization event. voltage, in volts, at the VIN pin. matted as a 16-bit 2’s complement value scaled 4mV/bit. voltage, in volts as specified by the VOUT_MODE command. matted as a 16-bit 2’s complement value scaled 0.5mV/bit. added to account for quiescent current and driver current. in continuous conduction mode. matted as a 16-bit 2’s complement value scaled 10mA/bit. Table 11. Status Word Bit Descriptions and Conditions

1 Communication Failure (See Note 1) Yes Yes

2 Temperature Fault Temp > 150°C Yes Yes

3 VIN Undervoltage Fault Not Implemented

4 Output Overcurrent Fault Not Implemented

5 Output Overvoltage Fault VOUT > PGOOD High Threshold Yes Yes

6 OFF No Power to the Output (Note 2) No No

7 Busy Not Implemented

8 Unknown Not Implemented

9 Other Not Implemented

10 Fans Not Implemented

11 PGOOD Inverted state of PGOOD pin No No

12 Manufacturer Specific Not Implemented

13 Input Voltage/ Current/Power Fault Not Implemented Yes Yes

14 Output Current/Power Fault Not Implemented

Sections 10.8 and 10.9 for more information.

Rev. 0 For more information www.analog.com READ_IOUT The READ_IOUT command returns the average output current in amperes. The LTC7131-1 senses and measures the currents through its bottom power switches to derive IOUT current. For accurate values at light load currents the part must be in continuous conduction mode. This register is reset to 0x8000 is standby mode when the drivers are off. This read-only command has two data bytes and is for - matted as a 16-bit 2’s complement value scaled 10mA/bit. READ_TEMPERATURE_1 The READ_TEMPERATURE_1 command returns the inter- nal die temperature, in degrees Celsius, of the LTC7131-1. This read-only command has two data bytes and is for - matted as a 16-bit 2’s complement value scaled 1°C/bit. MFR_VOUT_PEAK The MFR_VOUT_PEAK command reports the highest volt- age, in volts, reported by the READ_VOUT measurement. To clear the peak value and restart the peak monitor , use the MFR_CLEAR_PEAKS command or write to the MFR_ VOUT_PEAK. When writing to MFR_VOUT_PEAK, zero, one or two data bytes are accepted but the data is ignored. This command has two data bytes and is formatted as a 16-bit 2’s complement value scaled 0.5mV/bit. MFR_VIN_PEAK The MFR_VIN_PEAK command reports the highest volt- age, in volts, reported by the READ_VIN measurement. To clear the peak value and restart the peak monitor , use the MFR_CLEAR_PEAKS command or write to the MFR_ VIN_PEAK. When writing to MFR_VIN_PEAK zero, one or two data bytes are accepted but the data is ignored. This command has two data bytes and is formatted as a 16-bit 2’s complement value scaled 4mV/bit. PMBus COMMAND DETAILS MFR_TEMPERATURE_1_PEAK The MFR_TEMPERATURE_1_PEAK command reports the highest temperature, in degrees Celsius, reported by the READ_TEMPERATURE_1 measurement. To clear the peak value and restart the peak monitor , use the MFR_CLEAR_PEAKS command or write to the MFR_TEMPERATURE_1_PEAK. When writing to MFR_ TEMPERATURE_1__PEAK zero, one or two data bytes are accepted but the data is ignored. This command has two data bytes and is formatted as a 16-bit 2’s complement value scaled 1°C/bit. MFR_IOUT_PEAK The MFR_IOUT_PEAK command reports the high - est current, in amperes, reported by the READ_IOUT measurement. To clear the peak value and restart the peak monitor , use the MFR_CLEAR_PEAKS command or write to the MFR_ IOUT_PEAK. When writing to MFR_IOUT_PEAK, zero, one or two data bytes are accepted but the data is ignored. This command has two data bytes and is formatted as a 16-bit 2’s complement value scaled 10mA/bit. MFR_IIN_PEAK The MFR_IIN_PEAK command reports the highest cur - rent, in amperes, reported by the READ_IIN measurement. To clear the peak value and restart the peak monitor , use the MFR_CLEAR_PEAKS command or write to the MFR_ IIN_PEAK. When writing to MFR_IIN_PEAK, zero, one or two data bytes are accepted but the data is ignored. This command has two data bytes and is formatted as a 16-bit 2’s complement value scaled 10mA/bit.

Rev. 0For more information www.analog.com TYPICAL APPLICATIONS 1.2V/25A 500kHz Buck Regulator with Minimum External Components VIN 5V TO 20V PGOOD PMBus VOUT 1.2V 25A L TC7131-1 100k SGND 12k 0.5% PGND WP PGOOD SCL SDA ALERT PGFD ASEL TRACK/SS CSLEW RT PGLIM REF ILIM MODE/SYNC RUN_MSTR RUN_STBY CLKOUT MARGIN BOOST SW VSENSE+ VSENSE– DAOUT FB ITH SVIN VIN 7131-1 TA02 0.18µH 6.04k 4700pF 47pF COUT1 330µF COUT2 100µF CIN 22µF CMDSH3 INTVCC10k 10k 10k PGOOD DELAY: 190µs PGOOD THRESHOLD ±10% FREQUENCY: 500kHz SOFT-START DELAY: 1ms MARGIN SLEW RATE: 23%/ms DCM MODE PMBus ADDRESS: 0x20 CIN: TAIYO YUDEN LMK316BJ226ML-T COUT1: PANASONIC EEF-SX0G331XE COUT2: MURATA GRM32ER60J107ME20L L: COILCRAFT XAL6030-331MEB

Rev. 0 For more information www.analog.com TYPICAL APPLICATIONS 1.2V/25A 1MHz Buck Regulator VIN 5.5V TO 20V PGOOD PMBus VOUT 1.2V 25A L TC7131-1 100k SGND6.04k 0.5% 100pF PGND WP PGOOD SCL SDA ALERT PGFD ASEL TRACK/SS CSLEW RT PGLIM REF SVIN VIN 7131-1 TA03 6.04k 0.18µH 4700pF 47pF CIN 22µF ×2INTVCC 5.97k 0.5% 11.8k, 1% 46.4k 64.9k 10k 10k 10k 22nF PGOOD DELAY: 1.6ms PGOOD THRESHOLD ±20% FREQUENCY: 1MHz SOFT-START DELAY: 5ms MARGIN SLEW RATE: 1%/ms DCM MODE PMBus ADDRESS: 0x22 COUT1 330µF COUT2 100µF CIN: TAIYO YUDEN LMK316BJ226ML-T COUT1: PANASONIC EEF-SX0G331XE COUT2: MURATA GRM32ER60J107ME20L L: COILCRAFT XAL6030-181MEB ILIM MODE/SYNC RUN_MSTR RUN_STBY CLKOUT MARGIN BOOST SW VSENSE+ VSENSE– DAOUT FB ITH CMDSH3

Rev. 0For more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE PACKAGE TOP VIEW PIN “A1” CORNER X Y aaa Z aaa Z PACKAGE BOTTOM VIEW SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW BGA 63 0517 REV A L TMXXXXXX µModule TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” PIN 1 0.000 0.80 0.80 1.60 1.60 2.40 2.40 3.20 0.80 2.40 1.60 0.80 1.60 2.40 3.20 0.000 DETAIL A Øb (63 PLACES) F H J E G A B C D 2 14 3567 D A DETAIL B PACKAGE SIDE VIEW M X YZddd M Zeee 0.4 ±0.025 Ø 63x E b e e b F G 63-Lead (7.5mm × 6.25mm × 2.22mm) (Reference LTC DWG # 05-08-1988 Rev A) SEE NOTESDETAIL A SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 2.07 0.35 1.72 0.45 0.37 0.27 1.45 NOM 2.22 0.40 1.82 0.50 0.40 7.50 6.25 0.80 6.40 4.80 0.32 1.50 MAX 2.37 0.45 1.92 0.55 0.43 0.37 1.55 0.15 0.10 0.12 0.15 0.08 TOTAL NUMBER OF BALLS: 63 DIMENSIONS NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT Z DETAIL B SUBSTRATE ccc Z Z // bbb Z MOLD CAP 5. PRIMARY DATUM -Z- IS SEATING PLANE

6 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y

Rev. 0 For more information www.analog.com  ANALOG DEVICES, INC. 2022 www.analog.com RELATED PARTS TYPICAL APPLICATION 1.2V/50A 2-Phase Buck Regulator PGOOD VOUT 1.2V , 50AL TC7131-1 SGND 1nF24.9k PGND WP MARGIN MODE/SYNC PGFD ASEL CSLEW RT PGLIM PGOOD SCL, SDA, ALERT DAOUT FB ITH REF TRACK/SS BOOST SW VSENSE+ VSENSE– SVIN VIN 7131-1 TA04 0.18µH 4700pF 0.1µF CIN 100µF VIN 5V TO 20V SGND PGND WP MARGIN PGOOD PGFD ASEL CSLEW RT CLKOUT RUN_MSTR RUN_MSTRRUN_STBY MODE/SYNC RUN_STBY CLKOUT PGLIM VSENSE– SCL, SDA, ALERT DAOUT FB ITH REF TRACK/SS BOOST SW VSENSE+ SVIN VIN ILIMINTVCCINTVCC 0.18µH 100k 1nF24.9k PMBUS ADDRESS = 0x20 PMBUS ADDRESS = 0x27 6.04k 0.5% 22nF L TC7131-1 MASTER SLAVE CIN: TAIYO YUDEN LMK316BJ226ML-T COUT1: PANASONIC EEF-SX0G331XE COUT2: MURATA GRM32ER60J107ME20L L1, L2: COILCRAFT XAL6030-331MEB 0.1µF 4.7µF 4.7µF ILIM COUT1 330µF COUT2 100µF 47pF PART NUMBER DESCRIPTION COMMENTS LTC3605/ LTC3605A 20V, 5A Synchronous Step-Down Regulator 4V < VIN < 20V, 0.6V < VOUT < 20V, 96% Max Efficiency, 4mm × 4mm LTC3633A LTC3633A-1 Dual Channel 3A, 20V Monolithic Synchronous Step-Down Regulator 3.6V < VIN < 20V, 0.6V < VOUT < VIN, 95% Max Efficiency, 4mm × 5mm QFN-28 and TSSOP-28 Package LTC3622 17V, Dual 1A Synchronous Step-Down Regulator with Ultralow Quiescent Current 2.7V < VIN < 17V, 0.6V < VOUT < VIN, 95% Max Efficiency, 3mm × 4mm DFN-14 and MSOP-16 Package LTC3613 24V, 15A Monolithic Step-Down Regulator with Differential Output Sensing 4.5V < VIN < 24V, 0.6V < VOUT < 5.5V, 0.67% Output Voltage Accuracy, Valley Current Mode, Programmable from 200kHz to 1MHz, Current Sensing, 7mm × 9mm QFN-56 Package LTC3624 17V, 2A Synchronous Step-Down Regulator with 3.5μA Quiescent Current 2.7V < VIN < 17V, 0.6V < VOUT < VIN, 95% Max Efficiency, 3.5μA IQ, Zero-Current Shutdown, 3mm × 3mm DFN-8 Package LT M

4639 Low VIN 20A DC/DC μModule

Step-Down Regulator Complete 20A Switch Mode Power Supply, 2.375V < VIN < 7V, 0.6V < VOUT < 5.5V, 1.5% Max Total DC Output Voltage Error , Differential Remote Sense Amp, 15mm × 15mm BGA Package LTM4637 20A DC/DC μModule Step-Down Regulator Complete 20A Switch Mode Power Supply, 4.5V < VIN < 20V, 0.6V < VOUT < 5.5V, 1.5% Max Total DC Output Voltage Error , Differential Remote Sense Amp, 15mm × 15mm BGA or LGA Package