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Rev. 0For more information www.analog.com TYPICAL APPLICATION FEATURES DESCRIPTION Quad 17V, 1.25A Parallelable Synchronous Step- Down Regulator with Ultralow Quiescent Current The LT C®3644/LTC3644-2 is a quad 1.25A output, high efficiency synchronous monolithic step-down regulator capable of operating from input supplies up to 17V. The switching frequency is internally fixed to 1MHz or 2.25MHz with a ±50% synchronization range. The regulator features ultralow quiescent current and high efficiency over a wide V IN and VOUT range. The step-down regulator operates from an input voltage range of 2.7V to 17V and provides an adjustable output range from 0.6V to V IN while delivering up to 1.25A of output current per channel. LTC3644/LTC3644-2 can be configured for quad 1.25A outputs, triple 2.5A/1.25A/1.25A outputs, dual 2.5A outputs, or dual 3.75A/1.25A outputs. A user selectable mode input is provided to allow the user to trade off ripple noise for light load efficiency; Burst Mode operation provides the highest efficiency at light loads, while forced-continuous mode provides the lowest ripple noise. The regulators can be synchronized to an external clock. LTC3644 Options PART NAME FREQUENCY VOUT LTC3644 1.00MHz Adjustable LTC3644-2 2.25MHz Adjustable 4-Channel 1.25A Quad-Output 1MHz Step-Down Regulator
APPLICATIONS
n Quad Step-down Outputs: 1.25A per Channel n Wide VIN Range: 2.7V to 17V n Wide VOUT Range: 0.6V to VIN n 1.25A/2.5A/3.75A/5A IOUT Configurable with One Inductor n Integrated 300mΩ P-Channel/80mΩ N-Channel MOSFETs Provide Up to 93% Efficiency n No-Load Burst Mode Operation IQ < 10µA with All Channels Enabled n Constant Frequency (1MHz/2.25MHz) with ±50% Frequency Synchronization Range n ±1% Output Voltage Accuracy n Current Mode Operation for Excellent Line and Load T ransient Response n Full Dropout Operation (100% Duty Cycle) n Phase Shift Programmable with External Clock n 5mm × 5mm × 1.72mm BGA Package n Battery Powered Systems n Point-of-Load Supplies n Portable – Handheld Scanners and Cameras All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 5481178, 6580258, 6498466, 6611131, 5705919. Efficiency and Power Loss vs Load at 1MHz in Burst Mode Operation EFFICIENCY POWER LOSS V IN = 12V V OUT = 5.0V , L = 6.8µH V OUT = 3.3V , L = 4.7µH V OUT = 2.5V , L = 3.3µH LOAD CURRENT (A) 0.00 0.25 0.50 0.75 1.00 1.25 100 0.1 0.2 0.3 0.4 0.5 0.6 0.7 EFFICIENCY (%) POWER LOSS (W)
3644 TA01b
3.3µH COUT1 47µF COUT2 47µF CVCC 4.7µF CFF3 22pF CFF4 22pF 619k 309k 3.3µH COUT3 47µF 619k 137k 4.7µH 619k 84.5k 6.8µH COUT4 47µF CIN 22µF V IN1 V IN2 V IN3 V IN4 RUN1 RUN2 RUN3 RUN4 PGOOD1 PGOOD2 PGOOD3 PGOOD4 INTVCC MODE/SYNC PHASE SW1 FB1 SW3 FB3 VOUT1 2.5V AT 1.25A VOUT3 1.8V AT 1.25A VOUT4 5V AT 1.25A VOUT2 3.3V AT 1.25A SW2 FB2 SW4 FB4 GND SV IN V IN 5V TO 17V L TC3644
3644 TA01a
Rev. 0 For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS PGOOD1, PGOOD2, PGOOD3, PGOOD4, PHASE .. –0.3V to 6V Operating Junction Temperature Range C to 125°C C to 150°C C (Note 1) F E A B C D 2 1 4 3 5 6 BGA PACKAGE 36-BALL (5mm × 5mm × 1.72mm) θJA = 25°C/W θJA DERIVED FROM L TC3644 DEMO BOARD θJCtop = 28.9°C/W , θJCbottom = 6.1°C/W θJCtop AND θJCbottom ARE DETERMINED BY SIMULATION PER JESD51 CONDITION TOP VIEW FB2 FB4 VIN4 SW4 SW3 VIN3 FB3 FB1 VIN1 SW1 SW2 VIN2 SVIN GND GND INTVCC PGOOD1 GND GND PGOOD4 RUN1 GND GND RUN4 PHASE GND GND MODE/SYNC PGOOD2 GND GND PGOOD3 RUN2 GND GND RUN3 ORDER INFORMATION PART NUMBER TERMINAL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE (SEE NOTE 2)DEVICE FINISH CODE LTC3644EY#PBF SAC305(RoHS) 3644Y e1 BGA 3 –40°C to 125°C LTC3644IY#PBF SAC305(RoHS) 3644Y e1 BGA 3 –40°C to 125°C LTC3644EY-2#PBF SAC305(RoHS) 3644Y2 e1 BGA 3 –40°C to 125°C LTC3644IY-2#PBF SAC305(RoHS) 3644Y2 e1 BGA 3 –40°C to 125°C
- Device temperature grade is indicated by a label on the shipping container .
- Pad or ball finish code is per IPC/JEDEC J-STD-609.
- BGA Package and Tray Drawings
- This product is moisture sensitive. For more information, go to Recommended BGA PCB Assembly and Manufacturing Procedures SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VINX, SVIN Operating Voltage 2.7 17 V VOUT Output Voltage 0.6 VIN V IQ Input Quiescent Current Forced Continuous Mode (Note 3) Burst Mode, No Load Shutdown Mode; V RUN1 = VRUN2 = VRUN3 = VRUN4 = 0V 0.1 mA µA µA V FB Regulated Feedback Voltage l 0.594 0.6 0.606 V IFB FB Input Current 10 nA Reference Voltage Line Regulation SV IN = 2.7V to 17V (Note 4) 0.01 0.025 %/V Output Voltage Load Regulation (Note 4) 0.1 0.3 % ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). SVIN = VIN1 = VIN2 = VIN3 = VIN4 = 12V, unless otherwise noted.
Rev. 0For more information www.analog.com
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3644/LTC3644-2 is tested under pulsed load conditions such that TJ ≈ TA. The LTC3644E is guaranteed to meet specified performance from 0°C to 85°C. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3644I is guaranteed over the –40°C to 125°C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance, and other environmental factors. The junction temperature The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). SVIN = VIN1 = VIN2 = VIN3 = VIN4 = 12V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NMOS Switch Leakage PMOS Switch Leakage 0.1 0.1 µA µA R DS(ON) NMOS On Resistance PMOS On Resistance 300 mΩ mΩ t ON(MIN) Minimum On Time (Note 6) 60 ns VRUN RUN Input High RUN Input Low 0.35 1.0 V RUN Input Current V RUN = 12V 0.1 10 nA VMODE/SYNC Pulse-Skipping Mode Forced Continuous Mode Burst Mode Operation 1.0 V INTVCC – 0.4 0.3 VINTVCC – 1.2 VINTVCC + 0.3V V V V MODE/SYNC Input Current 0.1 100 nA PHASE Input Threshold Input Low Input High V INTVCC – 0.4 0.4 V V PHASE Input Current V PHASE = 6V 0.1 100 nA tSS Internal Soft Start Time 1.1 ms ILIM Peak Current Limit 1.25A Regulator 2.5A Regulator (2-Channel Combined) 3.75A Regulator (3-Channel Combined) 1.8 2.2 4.4 6.6 2.6 A A A V INTVCC Undervoltage Lockout SV IN Ramping Up 2.35 2.5 2.65 V VINTVCC Undervoltage Lockout Hysteresis 250 mV VIN Overvoltage Lockout Rising l 18 19 20 V VIN Overvoltage Lockout Hysteresis 400 mV fOSC Oscillator Frequency LTC3644-2 LTC3644 l l 1.8 0.82 2.25 1.00 2.60 1.16 MHz MHz SYNC Capture Range % of Programmed Frequency 50 150 % V INTVCC VINTVCC Voltage SVIN > 5.5V 5 V Power Good Range ±7.5 % RPGOOD Power Good Resistance 275 350 Ω tPGOOD PGOOD Delay PGOOD Low to High PGOOD High to Low Cycles Cycles Phase Shift Between Channel 1/2 and Channel 3/4 V PHASE = 0V VPHASE = INTVCC, VMODE/SYNC = 0V 180 Deg Deg J, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal impedance. Note 3: The quiescent current in active mode does not include switching loss of the power FETs. Note 4: The LTC3644 is tested in a proprietary test mode that connects VFB to the output of error amplifier . Note 5: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 6: The minimum on-time is determined by the speed of the top switch driver and peak current comparator . The typical value listed here is guaranteed by design.
Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Phase Shift with External Clock Frequency Sync 180° Phase Operation IQ vs Temperature SW Leakage Current vs Temperature R DS(ON) vs Temperature Efficiency vs Load Current in Burst Mode Operation T A = 25°C, unless otherwise noted. V IN = 12V V OUT = 5V f SW = 1MHz 1.25A OUTPUT , L = 4.7µH 2.50A OUTPUT , L = 2.2µH 3.75A OUTPUT , L = 1.8µH LOAD CURRENT (A) 0.001 0.01 0.1 100 EFFICIENCY (%)
3644 G01
V IN = 12V V OUT1 = 3.3V , V OUT4 = 1.8V L = 4.7µH, L = 3.3µH PHASE = INTVCC MODE/SYNC = EXT CLK 500ns/DIV SW4 10V/DIV SW1 10V/DIV EXT CLK 5V/DIV
3644 G04
V IN = 12V V OUT1 = 3.3V , V OUT4 = 1.8V L = 4.7µH, L = 3.3µH PHASE = INTVCC MODE/SYNC = 2.5V 500ns/DIV SW4 10V/DIV SW1 10V/DIV
3644 G05
SVIN = 17V I Q, SHUTDOWN I Q, SLEEP TEMPERATURE (°C) –50 –25 100 125 QUIESCENT CURRENT (µA)
3644 G06
TEMPERATURE (°C) –50 –25 100 125 SW LEAKAGE (µA)
3644 G07
VDS = 17V PMOS NMOS TEMPERATURE (°C) –50 –25 100 125 100 200 300 400 500 R DS,ON (mΩ)
3644 G08
Efficiency vs Load Current in Burst Mode Operation Efficiency vs Load Current in Burst Mode Operation V IN = 12V f SW = 2.25MHz V OUT = 5.0V , L = 2.2µH V OUT = 3.3V , L = 1.8µH V OUT = 2.5V , L = 1.2µH LOAD CURRENT (A) 0.001 0.01 0.1 100 EFFICIENCY (%)
3644 G02
V IN = 12V V OUT = 5V f SW = 2.25MHz 1.25A OUTPUT , L = 2.2µH 2.50A OUTPUT , L = 1.2µH 3.75A OUTPUT , L = 0.86µH LOAD CURRENT (A) 0.001 0.01 0.1 100 EFFICIENCY (%)
3644 G03
Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Line Regulation, No Load Load Regulation Oscillator Frequency vs Temperature Peak Current Limit vs Temperature Reference Voltage vs Temperature R DS(ON) vs Input Voltage TA = 25°C, unless otherwise noted. PMOS NMOS INPUT VOL TAGE (V) 100 200 300 400 500 R DS,ON (mΩ)
3644 G09
TEMPERATURE (°C) –50 –25 100 125 0.8 0.9 1.0 1.1 1.2 OSCILLATOR FREQUENCY (MHz)
3644 G10
TEMPERATURE (°C) –50 –25 100 125 1.6 1.8 2.0 2.2 2.4 PEAK CURRENT LIMIT (A)
3644 G11
TEMPERATURE (°C) –50 –25 100 125 597.0 597.5 598.0 598.5 599.0 599.5 600.0 600.5 601.0 601.5 602.0 REFERENCE VOL TAGE (mV)
3644 G12
V OUT = 2.5V f SW = 1MHz L = 3.3µH FORCED CONTINUOUS MODE INPUT VOL TAGE (V) –0.5 –0.3 –0.1 0.1 0.3 0.5 OUT ERROR (%)
3644 G13
V IN = 12V V OUT = 2.5V f SW = 1MHz L = 3.3µH FORCED CONTINUOUS MODE LOAD CURRENT (A) 0.25 0.50 0.75 1.25 –0.50 –0.25 0.25 0.50 OUT (%) Load Regulation
3644 G14
Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Load Step at 1MHz Start-Up Operation Burst Mode Operation Pulse-Skipping Operation TA = 25°C, unless otherwise noted. V IN = 12V V OUT = 2.5V I LOAD = 100mA to 1.1A L = 3.3µH C OUT = 47µF 25µs/DIV I L 1A/DIV V OUT AC–COUPLED 200mA/DIV I LOAD 1A/DIV
3644 G15
V IN = 12V V OUT = 5V f SW = 1MHz L = 4.7µH C OUT = 47µF 500µs/DIV RUN 5V/DIV V OUT 2V/DIV PGOOD 2V/DIV I L 200mA/DIV
3644 G17
V IN = 12V V OUT = 3.3V I LOAD = 25mA f SW = 1MHz L = 4.7µH 4µs/DIV V OUT AC–COUPLED 50mV/DIV SW 10V/DIV I L 500mA/DIV
3644 G18
V IN = 12V V OUT = 3.3V I LOAD = 10mA f SW = 1MHz L = 4.7µH 4µs/DIV V OUT AC–COUPLED 50mV/DIV SW 10V/DIV I L 200mA/DIV
3644 G19
Load Step at 2.25MHz V IN = 12V V OUT = 2.5V I LOAD = 100mA to 1.1A L = 1.8µH C OUT = 47µF 20µs/DIV I L 1A/DIV V OUT AC–COUPLED 200mV/DIV I STEP 1A/DIV
3644 G16
FB1 (A6): Feedback Input to the Error Amplifier of Channel 1 Step-Down Regulator . Connect resistor divider tap to this pin. The output voltage can be adjusted from 0.6V to V IN by: VOUT = 0.6V • [1 + (R2/R1)]. FB2 (F6): Feedback Input to the Error Amplifier of Channel 2 Step-Down Regulator . Connect resistor divider tap to this pin. The output voltage can be adjusted from 0.6V to V IN by: VOUT = 0.6V • [1 + (R2/R1)]. Connecting this pin to INTVCC turns this channel into a slave channel to channel 1. PIN FUNCTIONS FB3 (F1): Feedback Input to the Error Amplifier of Channel 3 Step-Down Regulator . Connect resistor divider tap to this pin. The output voltage can be adjusted from 0.6V to V IN by: VOUT = 0.6V • [1 + (R2/R1)]. Connecting this pin to INTVCC turns this channel into a slave channel to channel 4. FB4 (A1): Feedback Input to the Error Amplifier of Channel 4 Step-Down Regulator . Connect resistor divider tap to this pin. The output voltage can be adjusted from 0.6V to V IN by: VOUT = 0.6V • [1 + (R2/R1)]. Connecting this pin to INTVCC turns this channel into a slave channel to channel 1.
Rev. 0For more information www.analog.com PIN FUNCTIONS RUN1 (C5): Logic Controlled RUN Input to Channel 1. Do not leave this pin floating. Logic High activates the step-down regulator . RUN2 (F5): Logic Controlled RUN Input to Channel 2. Do not leave this pin floating. Logic High activates the step-down regulator . RUN3 (F2): Logic Controlled RUN Input to Channel 3. Do not leave this pin floating. Logic High activates the step-down regulator . RUN4 (C2): Logic Controlled RUN Input to Channel 4. Do not leave this pin floating. Logic High activates the step-down regulator . SV IN (A5): Signal VIN Pin. This input powers the INTVCC LDO. May be a different voltage than V IN1, V IN2, V IN3 or VIN4. Connect SVIN to whichever V INX is highest; for applications where it is not known which V IN is highest, connect external diode between SVIN to all VINX to ensure that SVIN is less than a diode drop from the highest VIN. SW1 (C6): Switch Node Connection to the Inductor of Channel 1 Step-Down Regulator . SW2 (D6): Switch Node Connection to the Inductor of Channel 2 Step-Down Regulator . SW3 (D1): Switch Node Connection to the Inductor of Channel 3 Step-Down Regulator . SW4 (C1): Switch Node Connection to the Inductor of Channel 4 Step-Down Regulator . VIN1 (B6): Input Voltage of Channel 1 Step-Down Regulator . May be a different voltage than other channels’ VIN. VIN2 (E6): Input Voltage of Channel 2 Step-Down Regulator . May be a different voltage than other channels’ VIN. VIN3 (E1): Input Voltage of Channel 3 Step-Down Regulator . May be a different voltage than other channels’ VIN. VIN4 (B1): Input Voltage of Channel 4 Step-Down Regulator . May be a different voltage than other channels’ VIN. INTVCC (A2): Low Dropout Regulator . Bypass with a low ESR ceramic cap of at least 4.7µF to ground. MODE/SYNC (D2): Burst Mode Select and External Clock Synchronization of the Step-Down Regulator . Tie MODE/ SYNC to INTV CC for Burst Mode operation with a 550mA peak current clamp. Tie MODE/SYNC to GND for pulse skipping operation, and tie MODE/SYNC to a voltage between 1V and INTV CC – 1.2V for forced continuous mode. Furthermore, connecting this pin to an external clock will synchronize the switch clock to the external clock and put the part in forced continuous mode. GND (A3, A4, B3, B4, C3, C4, D3, D4, E3, E4, F3, F4): Ground backplane for power and signal ground. These pins must be soldered to PCB ground for electrical contact and rated thermal performance. Connect all GND pins together with solid ground plane. PHASE (D5): Phase Select Pin. Do not leave this pin floating. Tie this pin to GND to run the regulators in phase (0 degrees phase shift) between the SW rising edge of channel 1/2 and channel 3/4. Tie this pin to INTV CC to set 180 degrees phase shift between channel 1/2 and channel 3/4. When this pin is high, the phase shift may also be set by modulating the duty cycle of external clock on the MODE/SYNC pin (channel 1/2 edge synced to rising edge of clock, channel 3/4 edge synced to falling edge of clock). For 5A output configuration, this pin must be tied to ground. See the Applications Information section for more details. PGOOD1 (B5): Open Drain Power Good Indicator for Channel 1. PGOOD2 (E5): Open Drain Power Good Indicator for Channel 2. PGOOD3 (E2): Open Drain Power Good Indicator for Channel 3. PGOOD4 (B2): Open Drain Power Good Indicator for Channel 4.
Figure 1. Block Diagram
Rev. 0For more information www.analog.com OPERATION The LTC3644 /LTC3644 -2 is a quad high efficiency monolithic step-down regulator , which uses a constant frequency, peak current mode architecture. It operates through a wide V IN range and regulates with ultralow quiescent current. The operation frequency is set at either 1MHz or 2.25MHz and can be synchronized to an external oscillator ±50% of the inherent frequency. To suit a variety of applications, the selectable MODE/SYNC pin allows the user to trade off output ripple for efficiency. For each channel, the output voltage is set by an external divider returned to the FB pin. An error amplifier compares the divided output voltage with a reference voltage of 0.6V and adjusts the peak inductor current accordingly. Overvoltage and undervoltage comparators pull the PGOOD output low if the output voltage is not within 7.5% of the programmed value. The PGOOD output goes high immediately after achieving regulation and goes low 32 clock cycles after falling out of regulation. Main Control Loop During normal operation, the top power switch (P-channel MOSFET) is turned on at the beginning of a clock cycle. The inductor current is allowed to ramp up to a peak level. Once the level is reached, the top power switch is turned off and the bottom switch (N-channel MOSFET) is turned on until the next clock cycle. The peak current level is controlled by the internally compensated ITH voltage, which is the output of the error amplifier . This amplifier compares the FB voltage to the 0.6V internal reference. When the load current increases, the FB voltage decreases slightly below the reference, which causes the error amplifier to increase the ITH voltage until the average inductor current matches the new load current. The main control loop is shut down by pulling the RUN pin to ground. Low Current Operation T wo discontinuous conduction modes (DCM) are available to control the operation of the LTC3644 at low currents. Both modes, Burst Mode operation and pulse-skipping mode, automatically switch from continuous operation to the selected mode when the load current is low. To optimize efficiency, Burst Mode operation can be selected by tying the MODE/SYNC pin to INTV CC. In Burst Mode operation, the peak inductor current is set to be at least 550mA, even if the output of the error amplifier demands less. Thus, when the switcher is on at relatively light output loads, FB voltage will rise and cause the ITH voltage to drop. Once the ITH voltage goes below 0.2V, the switcher goes into sleep mode with both power switches off. The switchers remain in this sleep state until the external load pulls the output voltage below its regulation point. When all channels are in sleep mode, the part draws an ultralow 10µA of quiescent current from SV IN. To minimize V OUT ripple, pulse-skipping mode can be selected by grounding the MODE/SYNC pin. In LTC3644, pulse-skipping mode is implemented similarly to Burst Mode operation with the peak inductor current set to be at least 90mA. This results in lower ripple than in Burst Mode operation with the trade-off of slightly lower efficiency. Forced Continuous Mode Operation The LTC3644 also has the ability to operate in the forced continuous mode by setting the MODE/SYNC voltage between 1V and V INTVCC – 1.2V. In forced continuous mode, the switcher switches cycle by cycle regardless of what the output load current is. If forced continuous mode is selected, the minimum peak current is set to be –250mA in order to ensure that the part can operate continuously at zero output load. High Duty Cycle/Dropout Operation When the input supply voltage decreases towards the output voltage, the duty cycle increases and slope compensation is required to maintain the fixed switching frequency. The LTC3644 has internal circuitry to accurately maintain the peak current limit (I LIM) of 2.2A even at high duty cycles. As the duty cycle approaches 100%, the LTC3644 enters dropout operation. During dropout, the top PMOS switch is turned on continuously, and all active circuitry is kept alive.
INX pins for an overvoltage condition. suspends operation by shutting off both power MOSFETs. start function when exiting an overvoltage condition. normal operation if their respective RUN pins are enabled. DS(ON) versus VIN for more details. phase generally reduces input voltage and current ripple. input and output voltage ripple. the phase shift such that the SW edges do not coincide. Table 1. Phase Selection only one inductor per output, or dual 3.75A/1.25A outputs.
3644 F02
of the output voltage as shown in Figure 3. capacitance will also decrease the output voltage ripple. in this data sheet for suggested capacitor values. higher voltage rating may be required. capacitor at audio frequencies, generating audible noise. ceramic capacitors are also available. and the PGOOD pins are pulled high with external resistors. of approximately 32 switching cycles. Figure 3. Setting the Output Voltage capacitance of a capacitor deteriorates at higher DC bias. capacitors offer good overall performance.
3644 F03
Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION Frequency Sync Capability The LTC3644 has the capability to sync to a ±50% range of the internal programmed frequency. Once engaged in sync, the LTC3644 immediately runs at the external clock frequency in forced continuous mode. Inductor Selection Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: ΔIL = VOUT f •L 1− VOUT VIN(MAX) Lower ripple current reduces power losses in the inductor , ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However , achieving this requires a large inductor . There is a trade-off between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current this is about 40% of I OUT(MAX). When calculating the ripple current, I OUT(MAX) refers to the maximum output current of the regulator , not the maximum load current of the intended application. To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: L = VOUT f •ΔIL(MAX) 1− VOUT VIN(MAX) Once the value for L is known, the type of inductor must be selected. Actual core loss is independent of core size for a fixed inductor value, but is very dependent on the inductance selected. As the inductance or frequency in-creases, core loss decrease. Unfortunately, increased inductance requires more turns of wire and therefore copper losses increase. Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that the inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequently output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor . Toroid or shielded pot cores in ferrite or permalloy materials are small and don’ t radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price versus size requirements and any radiated field/EMI requirements. New designs for surface mount inductors are available from Coilcraft, Murata, Vishay, TDK and Würth Elektronik. Refer to Table 2 to Table 4 for more details. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Percent efficiency can be expressed as: % Efficiency = 100% - (L1 + L2 + L3 + …) where L1, L2 etc. are the individual losses as a percentage of input power . Although all dissipative elements in the circuit produce losses, three main sources in the LTC3644 circuit are: 1) I 2R losses, 2) switching and biasing losses, 3) other losses. 1. I2R losses are calculated from the DC resistances of the internal switches, R SW, and external inductor , RL. In continuous mode, the average output current flows through inductor L but is “chopped” between the internal top and bottom power MOSFETs. Thus, the series resistance looking into the SW pin is a function of both the top and bottom MOSFET R DS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC)+(RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus to obtain I2R losses: I2R losses = IOUT2(RSW + RL)
Table 2. Recommended Inductors for 1.25A Buck Regulators Table 3. Recommended Inductors for 2.5A Buck Regulators Table 4. Recommended Inductors for 3.75A Buck Regulators
- The switching current is the sum of the MOSFET
higher supply voltages and higher frequencies.
Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION during dead-time and inductor core losses, generally account for less than 2% total additional loss. Thermal Conditions In a majority of applications, the LTC3644 does not dissipate much heat due to its high efficiency. However , in applications where the LTC3644 is running at high ambient temperature, high V IN, high switching frequency, and maximum output current load, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 160°C, all power switches will be turned off until the temperature drops about 15°C cooler . To avoid the LTC3644 from exceeding the maximum junction temperature, the user need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TRISE = PD • θJA As an example, consider the case when the LTC3644 is used in applications where V IN = 12V, IOUT1 = IOUT2 = IOUT3 = IOUT4 = 0.8A, f = 1MHz, V OUT = 1.8V. The equivalent power MOSFET resistance RSW is: RSW =RDS(ON)TOP •VOUT VIN +RDS(ON)BOT• 1− VOUT VIN = 300mΩ•1.8V 12V +80mΩ• 1−1.8V 12V = 113mΩ The active current through V IN at 1MHz without load is about 5mA, which includes switching and internal biasing current loss, and transition loss. Therefore, the total power dissipated by the part is: P D = 4 • IOUT2 • RSW + VIN • IIN(Q) = 4 • 0.8A2 • 113mΩ + 12V • 5mA = 349mW For the BGA package, the θ JA is 25°C/W as measured on the LTC3644 demo board. Therefore, the junction temperature of the regulator operating at 25°C ambient temperature is approximately: Remembering that the above junction temperature is obtained from an R DS(ON) at 25°C, we might recalculate the junction temperature based on a higher RDS(ON) since it increases with temperature. Redoing the calculation assuming that R SW increased 5% at 33.7°C yields a new junction temperature of 34.1°C. If the application calls for a higher ambient temperature and/or higher switching frequency, care should be taken to reduce the temperature rise of the part by using a heat sink or airflow. Board Layout Considerations When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3644 (refer to Figure 4). Check the following in the layout: Do the capacitors CIN connect to the VIN and GND as close as possible? These capacitors provide the AC current to the internal power MOSFETs and their drivers. Does C VCC connect to INTVCC as close as possible? 2. Are COUT and L closely connected? The (–) plate of COUT returns current to GND and the (–) plate of CIN. 3. The resistive divider , R1 and R2, must be connected between the (+) plate of C OUT and a ground line terminated near GND. The feedback signal VFB should be routed away from noisy components and traces, such as the SW line, and its trace length should be minimized. Keep R1 and R2 close to the IC. Keep sensitive components away from the SW pin. The input capacitor , CIN, feedback resistors, and INTV CC bypass capacitors should be routed away from the SW trace and the inductor . A ground plane is preferred. Use several vias connected to ground on the component side. Flood all unused areas on all layers with copper , which reduces the temperature rise of power components. These copper areas should be connected to GND.
Rev. 0For more information www.analog.com APPLICATIONS INFORMATION Design Example As a design example, consider using the LTC3644 in an application with the following specifications: SVIN = VIN1 = VIN2 = VIN3 = VIN4 = 10.8V to 13.2V VOUT1 = 5V, VOUT2 = 3.3V, VOUT3 = 2.5V, VOUT4 = 1.8V ILOAD1(MAX) = ILOAD2(MAX) = 400mA, ILOAD3(MAX) =1 A, ILOAD4(MAX) = 1.25A IOUT(MAX) = 1.25A IOUT(MIN) = 0 fSW = 1MHz Because efficiency is important at both high and low load current, Burst Mode operation will be utilized. To reduce input voltage and current ripple on the common input supply, the PHASE pin is tied to INTVCC for anti-phase operation between channels 1,2 and channels 3,4. Given the internal oscillator of 1MHz, we can calculate the inductors value for about 40% ripple current at maximum VIN: L1= 5V 1 MHz •0.5A ⎟ 1− 13.2V ⎟ = 6.21 µH L2 = 3.3V 1 MHz •0.5A ⎠⎟ 1− 3.3V 13.2V ⎠⎟ = 4.95µH L3 = 2.5V 1 MHz •0.5A ⎠⎟ 1− 2.5V 13.2V ⎠⎟ = 4.05µH L4 = 1.8V 1 MHz •0.5A ⎠⎟ 1− 1.8V 13.2V ⎠⎟ = 3.11 µH Using standard values of L1 = 6.8µH, L2 = 4.7µH, L3 = 3.3µH and L4 = 3.3µH for inductors results in maximum ripple currents of: ΔIL1 = 5V 1 MHz •6.8µH ⎠⎟ 1− 5V 13.2V ⎠⎟ = 0.46A ΔIL2 = 3.3V 1 MHz • 4.7µH ⎠⎟ 1− 3.3V 13.2V ⎠⎟ = 0.53A ΔIL3 = 2.5V 1 MHz •3.3µH ⎠⎟ 1− 2.5V 13.2V ⎠⎟ = 0.61A ΔIL4 = 1.8V 1 MHz •3.3µH ⎠⎟ 1− 1.8V 13.2V ⎠⎟ = 0.47A COUT will be selected based on the ESR that is required to satisfy the output voltage ripple requirement and the bulk capacitance needed for loop stability. For this design, 47µF ceramic capacitors will be used. To prevent large voltage transients, C IN should be sized based on the maximum RMS current: IRMS ≅IOUT(MAX) VOUT VIN VIN VOUT IRMS1= 1.25A 5V 13.2V 13.2V 5V −1= 0.606A IRMS2 = 1.25A 3.3V 13.2V 13.2 3.3V −1= 0.541A IRMS3 = 1.25A 2.5V 13.2V 13.2 2.5V −1= 0.490A IRMS4 = 1.25A 1.8V 13.2V 13.2 1.8V −1= 0.429A IRMS =IRMS1+IRMS2 +IRMS3 +IRMS4 = 2.07A Decoupling the VINX pins each with 22µF ceramic capacitors is adequate for most applications.
3644 F04
Figure 4. Recommended Layout
3644 F05
Figure 5. Dual 3.75A/1.25A 1MHz Step-Down Regulator with Common Input Supply
36442 F06
3644 F07
Figure 7. 2.5A/1.25A/1.25A 1MHz Step-Down Regulator with Common Input Supply
Rev. 0For more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION PACKAGE TOP VIEW PIN “A1” CORNER X Y PACKAGE BOTTOM VIEW SEE NOTES SUGGESTED PCB LAYOUT TOP VIEW DETAIL A PIN 1 0.000 0.4 0.4 1.2 1.2 2.0 2.0 2.0 1.2 0.4 0.4 2.0 1.2 0.000 DETAIL A Øb (36 PLACES) F E A B C D 2 14 35 6 D M X Y Z ddd M Z eee 0.40 ±0.025 Ø 36x E b e e b F G 36-Lead (5mm × 5mm × 1.72mm) (Reference LTC DWG # 05-08-1671 Rev B) SEE NOTES BGA 36 0317 REV B L TCXXXXX TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” A DETAIL B PACKAGE SIDE VIEW DETAIL B SUBSTRATE ccc Z MOLD CAP // bbb Z SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 1.53 0.30 1.23 0.45 0.37 NOM 1.72 0.40 1.32 0.50 0.40 5.00 5.00 0.80 4.00 4.00 0.32 1.00 MAX 1.91 0.50 1.41 0.55 0.43 0.15 0.20 0.20 0.15 0.08 TOTAL NUMBER OF BALLS: 36 DIMENSIONS NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT Z aaa Z2× aaa Z 2× 5. PRIMARY DATUM -Z- IS SEATING PLANE
6 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE
Rev. 0 For more information www.analog.com ANALOG DEVICES, INC. 2021 www.analog.com RELATED PARTS TYPICAL APPLICATION 0.85A/2.5A Series Output 1MHz Step-Down Regulator PART NUMBER DESCRIPTION COMMENTS LTC3621/ LTC3621-2 1A, 17V, 1MHz/2.25MHz, Synchronous Step-Down Regulator 95% Efficiency, V IN: 2.7V to 17V, VOUT(MIN) = 0.6V, IQ = 3.5µA, ISD < 1µA, 2mm × 3mm DFN-6, MSOP-8E Packages LTC3600 1.5A, 15V, 4MHz Synchronous Rail-to-Rail Single Resistor Step-Down Regulator 95% Efficiency, V IN: 4V to 15V, VOUT(MIN) = 0V, IQ = 700µA, ISD < 1µA, 3mm × 3mm DFN-12, MSOP-12E Packages LTC3601 15V, 1.5A (IOUT) 4MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 300µA, ISD < 1µA, 4mm × 4mm QFN-20, MSOP-16E Packages LTC3603 15V, 2.5A (IOUT) 3MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 4.5V to 15V, VOUT(MIN) = 0.6V, IQ = 75µA, ISD < 1µA, 4mm × 4mm QFN-20, MSOP-16E Packages LTC3633A 20V, Dual 3A (IOUT) 4MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 3.6V to 20V, VOUT(MIN) = 0.6V, IQ = 500µA, ISD < 15µA, 4mm × 5mm QFN-28, TSSOP-28E Packages. A Version Up to 20VIN LTC3605A 20V, 5A (IOUT) 4MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 4V to 20V, VOUT(MIN) = 0.6V, IQ = 2mA, ISD < 15µA, 4mm × 4mm QFN-24 Package. A Version Up to 20VIN LTC3604 15V, 2.5A (IOUT) 4MHz Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 3.6V to 15V, VOUT(MIN) = 0.6V, IQ = 300µA, ISD < 14µA, 3mm × 3mm QFN-16, MSOP-16E Packages LTC3624/ LTC3624-2 2A, 17V, 1MHz/2.25MHz Synchronous Step-Down Regulator 95% Efficiency , VIN: 2.7V to 17V, VOUT(MIN) = 0.6V, IQ = 3.5µA, ISD < 1µA, 3mm × 3mm DFN-8, MSOP-12E Packages LTC3622/ LTC3622-2/ LTC3622-23/5 Dual 1A, 17V 1MHz/2.25MHz Synchronous Step-Down Regulator 95% Efficiency, V IN: 2.7V to 17V, VOUT(MIN) = 0.6V, IQ = 5µA, ISD ≤ 1µA, 3mm × 4mm DFN-14, MSOP-16E Packages LTC7124 Dual Channel 3.5A, 17V Monolithic Synchronous Step -Down Regulator 95% Efficiency , VIN: 3.1V to 17V, VOUT(MIN) = 0.6V, IQ < 8μA, ISD < 1μA, 3mm × 5mm QFN-24 C IN 22µF C VCC 4.7µF C FF1 22pF C OUT1 47µF C FF2 22pF C OUT2 47µF 619k 84.5k 619k 137k 3.3µH 2.2µH 10k MODE/SYNC GND V IN 12V L TC3644 V IN1 V IN2 SV IN RUN3 RUN4 RUN1 RUN2 PGOOD2 PGOOD3 PGOOD4 PGOOD1 INTV CC PHASE FB3 SW1 SW2 SW3 SW4 V OUT4 3.3V AT 2.5A V OUT1 5V AT 0.85A +IVIN3-4 FB1 FB2 FB4 VIN3 VIN4