LTC7106 AD | Alldatasheet
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Rev AFor more information www.analog.comDocument Feedback TYPICAL APPLICATION FEATURES DESCRIPTION A 7-Bit Current DAC with PMBus Interface The LT C®7106 is a precision, PMBus controlled, bidi - rectional current digital-to-analog converter that adjusts the output voltage of any conventional V FB referenced regulator . The LTC7106 can work with the vast majority of power management controllers or regulators to enable digital control of the output voltage. Internal power-on reset circuitry keeps the DAC output current at zero (high impedance IDAC) until a valid write takes place. Features include a range bit for easy interfacing to almost any impedance resistor divider , and an open-drain GPO output for controlling the Run or Enable pin of the DC/ DC regulator . For most applications, the current DAC error is significantly attenuated with proper design. See more detail about VOUT accuracy in the Applications Information section of this data sheet. The LTC7106 is supported by the ADI L TpowerPlay® development tool with graphical user interface (GUI).
APPLICATIONS
n ±0.8% IDAC Positive Output Current Accuracy (Over Temp) n ±1.5% IDAC Negative Output Current Accuracy (Over Temp) n PMBus/I2C Compliant Serial Interface n Input Voltage Range: 2.5V to 5.5V n High Impedance at IDAC Output When Disabled n Wide IDAC Operation Voltage (0.4V to 2.0V) n 7-Bit Programmable DAC Output Current for DC/DC VOUT Control n Wide Range IDAC Output Current: ±16μA to ±256μA n Programmable Slew Rate: 500ns ~ 3ms per Bit n Available in a 10-Lead (3mm × 2mm) DFN Package n General Purpose Power Systems n Telecom Systems n Industrial Applications All registered trademarks and trademarks are the property of their respective owners. Margin High and Margin Low CIRCUIT OF FIGURE 11 V OUT = 24V IDAC = –40/uni03BCA IDAC = 40/uni03BCA IDAC = 0/uni03BCA 100ms/DIV EN 2V/DIV V OUT 5V/DIV
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1µF 10k 10k RFB1 RFB2 330µF 10k L TC7106 V DD GND IDAC SDA SCL ALERT GPO ASEL0 ASEL1 VDD 2.5V TO 5.5V SDA ALERT SCL V DD V IN DC/DC SW V FB V OUT RUN EN (0.4V to 2V) V IN VREF 10k PMBus INTERFACE –64/uni03BCA TO 0/uni03BCA 0/uni03BCA TO 63/uni03BCA
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Rev A For more information www.analog.com ABSOLUTE MAXIMUM RATINGS Operating Junction Temperature Range ...–40°C to 125°C (Note 1) TOP VIEW DDB PACKAGE 10-LEAD (3mm × 2mm) PLASTIC DFN θJA = 55°C/W, θJC = 16.8°C/W SDA SCL VDD ALERT GND ASEL1 ASEL0 GPO EN IDAC6 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC7106EDDB#PBF LTC7106EDDB#TRPBF LHCG 10-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C LTC7106IDDB#PBF LTC7106IDDB#TRPBF LHCG 10-Lead (3mm × 2mm) Plastic DFN –40°C to 125°C Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. http://www.linear .com/product/LTC7106#orderinfo PIN CONFIGURATION
Rev AFor more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VDD = 3.3V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Power Supply 2.5 5.5 V IQ Supply Quiescent Current EN High 700 1400 μA ISHUTDOWN Supply Quiescent Current EN = 0V 800 μA VUVLO_R Undervoltage Rising Threshold VDD Rising 2.35 V VUVLO_F Undervoltage Falling Threshold VDD Falling 2.15 V VEN_R Enable Rising Threshold VEN Rising 1.35 V VEN_F Enable Falling Threshold VEN Falling 0.8 V IDAC_OUT IDAC Accuracy Full Scale Positive 0.4 ≤ VIDAC ≤ 2V (Note 3) Range = Normal l 62.5 63 63.5 μA Range = Low l 15.5 15.75 16.0 μA Range = High l 246.7 252.00 255.3 μA Full Scale Negative 0.4 ≤ VIDAC ≤ 2V (Note 3) Range = Normal (0°C to 85°C) –64.64 –64 –63.36 μA Range = Normal l –64.96 –64 –63.04 μA Range = Low l –16.36 –16 –15.64 μA Range = High l –262.50 –256 –249.50 μA LSB 0.4 ≤ VIDAC ≤ 2V Range = Normal 1 μA Range = Low 0.25 μA Range = High 4 μA INL 0.4 ≤ VIDAC ≤ 2V Range = Normal –1 1 LSB Range = Low –1.5 1.5 LSB Range = High –1.6 1.6 LSB DNL 0.4 ≤ VIDAC ≤ 2V Range = Normal –0.3 0.3 LSB Range = Low –0.5 0.5 LSB Range = High –0.8 0.8 LSB IHZ High-Z Current 0.4 ≤ VIDAC ≤ 2V VEN = 0 l 20 nA Digital Input: SDA, SCL VIH 1.4 V VIL 0.8 V CPIN Input Capacitance 10 pF Open-Drain Outputs: ALERTB, GPO, SDA VOL Output Low Voltage ISINK = 3mA 0.4 V
Rev A For more information www.analog.com PMBus INTERFACE TIMING CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VDD = 3.3V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fSCL Serial Bus Operating Frequency 10 400 kHz tBUF Bus Free Time Between Stop and Start Condition 1.3 µs tHD_SDA Hold Time After (Repeated) Start Condition 0.6 µs tSU_SDA Repeated Start Condition Setup Time 0.6 µs tSU_STO Stop Condition Setup Time 0.6 µs tHD_DAT(OUT) Data Hold Time 300 900 ns tHD_DAT(IN) Input Data Hold Time 0 ns tSU_DAT Data Setup Time 100 ns tLOW Clock Low Period 1.3 10000 µs tHIGH Clock High Period 0.6 µs tTIMEOUT_SMB Stuck PMBus Timer 30 ms Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC7106 is tested under pulsed load conditions such that TJ ≈ TA. The LTC7106E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC7106I is guaranteed over the –40°C to 125°C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125°C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • 55°C/W). Note 3: IDAC is a bidirectional current DAC, controlled by 2’s complementary logic. Under the setting of Range = Normal, IDAC = 63µA for Code = 0111111 provides the maximum source current and IDAC = –64µA for Code = 1000000 provides the maximum sink current. Max sink current generates the Highest VOUT, while Max source current generates the lowest VOUT. See the Operation section for more details. TYPICAL PERFORMANCE CHARACTERISTICS Quiescent Current vs Temperature IDAC Leakage Current vs Temperature PIDAC Full-Scale vs Temperature TA = 25°C, VDD = 3.3V, VIDAC = 1.0V, Range = Normal unless otherwise noted. VEN = 0, OR VID[6:0] = 0 TEMPERATURE (°C) –50 130 IDAC LEAKAGE (nA) IDAC Leakage Current vs. Temp
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TEMPERATURE (°C) –50 –10 110 150 62.500 62.600 62.700 62.800 62.900 63.000 63.100 63.200 63.300 63.400 63.500 IDAC PIDAC Full Scale VS. Temperature
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VID[6:0] = 0111111 IRANGE = NOMINAL TEMP (°C) –50 –10 110 150 500 550 600 650 700 750 800 850 900 950 1000 IQ (/uni03BCA)
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Rev AFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS NIDAC vs Temperature Differential Nonlinearity Integral Nonlinearity Buck Start-Up with IDAC Margin High and Margin Low Boost Start-Up with IDAC Margin High and Margin Low TA = 25°C, VDD = 3.3V, Range = Normal unless otherwise noted. TEMPERATURE (°C) –50 100 150 –64.50 –64.40 –64.30 –64.20 –64.10 –64.00 –63.90 –63.80 –63.70 –63.60 –63.50 IDAC (µA)
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VID[6:0] = 1000000 CODE –0.30 –0.26 –0.22 –0.18 –0.14 –0.10 –0.06 –0.02 0.02 0.06 0.10 DNL (LSB)
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–0.15 –0.12 –0.09 –0.06 –0.03 0.03 0.06 0.09 0.12 0.15 INL (LSB) Integral Non–Linearity
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IDAC = –60µA IDAC = 60µA 10mV/DIV GPO 5V/DIV VOUT 0.3V/DIV
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VOUT = 1V IDAC = 0µA L TC7106 + L TM4636 IDAC = –60/uni03BCA IDAC = 60/uni03BCA 100ms/DIV EN 2V/DIV V OUT 200mV/DIV
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IDAC = 0/uni03BCA VOUT = 1V L TC7106 + L TC3784 V OUT = 24V IDAC = –40/uni03BCA IDAC = 40/uni03BCA IDAC = 0/uni03BCA 100ms/DIV EN 2V/DIV V OUT 5V/DIV
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V OUT = 24V V IN = 12V IDAC = 0/uni03BCA 2ms/DIV GPO 5V/DIV V OUT 10V/DIV
7106 G09
IDAC = –40/uni03BCA IDAC = 0/uni03BCA IDAC = 40/uni03BCA
Rev A For more information www.analog.com PIN FUNCTIONS VDD (Pin 3): Input Supply. Bypass this pin to GND with a capacitor (0.1µF to 1µF). IDAC (Pin 6): Bidirectional Current DAC Output. EN (Pin 7) : Chip Enable Pin. Current DAC output is in Hi-Z state when EN is Grounded. Do not leave EN floating. SDA (Pin 1): Serial Bus Data Input and Open-Drain Output. A pull-up resistor to VDD is required in the application. SCL (Pin 2): Serial Bus Clock Input. GPO (Pin 8): Open-Drain Digital Output. A pull-up resistor to VDD is required. ALERT (Pin 4) : Open-Drain Digital Output. A pull-up resistor to V DD is required. ASEL1/ASEL0 (Pins 10, 9) : Serial Bus Address Select Inputs. Each pin has three states (V DD, FLOATING and GND); these two pins provide 9 addresses. GND (Pin 5): Ground.
Rev AFor more information www.analog.com BLOCK DIAGRAM EN VDD GPO IDAC SDA SCL ALERT ASEL0 ASEL1 VREF GND PMBus INTERFACE ADDRESS ADC 7-BIT IDAC VID[6:0] SLEW RATE RANGE 7106 BD
bidirectional analog output current through the pin IDAC. A typical application diagram is shown on the front page. PWM controller can be controlled by a PMBus interface. PMBus interface to conventional analog DC/DC converters. IDAC is in high impedance (Hi-Z). default value of 3.58ms/step. resistor values to meet the output specification target. Table 1. Output Current Range
Table 2. IDAC Current and Corresponding DAC Codes
Table 2. IDAC Current and Corresponding DAC Codes (Continued)
pins. Each pin has three states : high, low and floating. The possible PMBus addresses are shown in Table 3. Table 3. Address Selection message is received by the LTC7106 including the STOP bit. and the ALERT pin is pulled low. rail addressing and 4) alert response address (ARA). or 0xB6 (8 bit) and cannot be disabled. employ disciplined planning to avoid addressing conflicts. information of the LTC7106 to the host. first START event before the device address write byte. operation), and all data bytes.
Figure 1. Timing Diagram
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Figure 2. PMBus Packet Protocol Diagram Element Key Figure 3. Write Byte Protocol Figure 4. Send Byte Protocol Figure 5. Read Word Protocol Figure 6. Read Byte Protocol
Table 4. LTC7106 Supported PMBus Commands is 0x00. The valid range of values are from 0x40 to 0x3 F. is set to margin high, 0xA8. 2’s complement value than what is stored in this register . to a negative number , bit [7] = 1. the maximum current with no clamping.
refer to Table 7 for each bit description. timer count for the slew rate control. Default value = 0x40. will not reset this register . Table 5. Programmable Delay Per Current Step
Figure 7. MFR_RAIL_ADDRESS Data Byte
7106 F07
value is written to the 7 bits of the data byte. disables this address. The default for this register is 0x80. and for margining the output voltage. shutdown (EN), power cycle, or MFR_RESET command. MARGIN_HIGH or MFR_IOUT_MARGIN_LOW. but ignores the second byte. Table 6. Supported OPERATION Command Register Values is PMBus Version 1.2 compliant in both Part I and Part II. command with no CML or ALERTB set.
tion with a summary of the unit’s fault condition. and the fault bit in the status byte will be cleared. immediately be set again if the fault remains. Table 7. Status Byte Bit Descriptions and Conditions
1 Communication Failure (See Note 1) Yes Yes
2 Temperature Fault Not Implemented
3 VIN Undervoltage Fault Not Implemented
4 Output Overcurrent Fault Not Implemented
5 Output Overvoltage Fault Not Implemented
6 OFF Not Implemented
7 Busy Not Implemented
The LTC7106 provides three ranges of IDAC output current. for the nominal IDAC setting. be larger than the IDAC error . lator , an μModule® and a boost controller .
7106 F08
Figure 8. Setting the Output Voltage Using the LTC7106
the IDAC = +50μA, which will margin VOUT from 1.5V to 1.0V. Figure 9. Using the LTC7106 to Margin Low Monolithic Buck Regulator LTC7150S Providing 1.5V to 1.0V at 20A
7106 F09
Figure 10. Using the LTC7106 to Margin High μModule LTM4636 Providing 1.2V to 2.0V at 40A (Range = High) to set IDAC LSB = 4μA. IDAC = –160µA, which will margin VOUT from 1.2V to 2.0V.
7106 F10
Figure 11. Using the LTC7106 with a Boost Controller to Vary VOUT from 28V to 18V IDAC = +50μA, which will margin VOUT from 28V to 18V.
7106 F11
Rev A For more information www.analog.com PACKAGE DESCRIPTION Please refer to http://www.linear .com/product/LTC7106#packaging for the most recent package drawings. 2.00 ±0.10 (2 SIDES) NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.40 ±0.10 BOTTOM VIEW—EXPOSED PAD 0.64 ±0.05 (2 SIDES) 0.75 ±0.05 R = 0.115 TYPR = 0.05 TYP 2.39 ±0.05 (2 SIDES) 3.00 ±0.10 (2 SIDES) 106 PIN 1 BAR TOP MARK (SEE NOTE 6)
0.200 REF
0 – 0.05 (DDB10) DFN 0905 REV Ø 0.25 ±0.05
0.50 BSC
R = 0.20 OR 0.25 × 45° CHAMFER 0.25 ±0.05 2.39 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.64 ±0.05 (2 SIDES) 1.15 ±0.05 0.70 ±0.05 2.55 ±0.05 PACKAGE OUTLINE 10-Lead Plastic DFN (3mm × 2mm) (Reference LTC DWG # 05-08-1722 Rev Ø)
Rev AFor more information www.analog.com
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER A 04/18 Clarified MFG_RAIL_ADDRESS and MFG_SPECIAL_ID paragraphs Changed from “Status Word” to “Status Byte” Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Figure 12. Margining a LT8640S from 1.8V to 1.5V at 6A