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Rev 0For more information www.analog.comDocument Feedback TYPICAL APPLICATION FEATURES DESCRIPTION 140V High Efficiency Switching Surge Stopper The LT C®7862 high efficiency switching surge stopper pro- tects loads from high voltage transients. High efficiency switching allows high output currents, small solution sizes, and high reliability. During an input overvoltage event, the LTC7862 controls the gates of two external N-channel MOSFETs to act as a switching DC/DC step-down regu - lator . This maintains the output voltage at a safe value, allowing the loads to continue to operate through the input overvoltage event. During normal operation, the LTC7862 turns on the top external N-channel MOSFET continuously, passing the input voltage through to the output, with mini- mal voltage drop. Using a fast peak current comparator , the LTC7862 also limits the maximum output current to protect against overcurrent and short-circuit faults. An adjustable timer limits the time that the LTC7862 can spend switching during an overvoltage, overcurrent, or startup condition. When the timer expires, the external MOSFETs are turned off for a cooldown period and then the LTC7862 restarts. By strictly limiting how long the LTC7862 can switch, when the power loss is relatively high, the components and thermal design can be opti- mized for normal pass-through operation while still safely operating through high voltage input surges and/or over- current events. 28V, 20A with 100V Overvoltage Protection
APPLICATIONS
n VOUT Clamp Stops High Voltage Input Surges n 100% Duty Cycle Pass-Through Mode During Normal Operation n Switches During Overvoltage or Overcurrent T ransients and Faults and During Startup n High Efficiency Switching Enables Long Duration Surge Protection and High Output Currents n Wide VIN Range: 4V to 140V (150V Abs Max) n Adjustable Output Voltage Clamp Up to 60V n Adjustable Output Overcurrent Protection n RSENSE or Inductor DCR Current Sensing n Power Inductor Reduces Input EMI in Normal Mode n Adjustable Soft-Start for Inrush Current Limiting n Programmable Fault Timer n Open-Drain Fault Warning Indicator n 2.7% Retry Duty Cycle During Faults n Adjustable Switching Frequency: 50kHz to 900kHz n Adjustable Input Voltage Turn-On Threshold n Adjustable Input Overvoltage Lockout Threshold n 20-Pin 4mm × 5mm QFN and TSSOP Packages n Automotive/Avionic/Industrial Surge Protection n Automotive Load Dump Protection n Vehicle Power Including ISO7637 n Military Power Including MIL1275 All registered trademarks and trademarks are the property of their respective owners. Overvoltage Protector Regulates Output at 28V During VIN T ransient MTOP ×2 MBOT L, 6.8µH 24.3k 0.47µF CINB 2.2µF CINA 22µF 4.7µF 100pF 6.8nF 22µF 100k 0.1µF 4.75k 0.1µF COUTB 6.8µF COUTA 100µF 36.5k 2.05k 2.2µF 2.21k VFB DRVUV FREQ ITH RUN INTVCC VIN BG SW TG BOOST TMR SENSE+ SENSE– L TC7862 VIN 8V TO 100V DRVCC SS OVLO EXTVCC GND WARNB *VOUT CLAMPED AT 34V 20A INTVCC WARNB DRVCC
7862 TA01a
MTOP/MBOT : INFINEON BSC035N10NS5 L: COILCRAFT SER2918H-682KL C INA: SUNCON 160CE22LH CINB: TDK C4532X7R2A225K230KA COUTA: SUN 63CE100LX COUTB: TDK C4532X7R1H685K250KB D1: NEXPERIA: PNE20010ER * VOUT FOLLOWS VIN WHEN VIN < 34V V OUT CLAMPS AT 34V WHEN VIN > 34V 28V 34V 100V INPUT SURGE VIN VOUT 100ms/DIV VIN/VOUT 50V/DIV SW 100V/DIV WARNB 5V/DIV
7862 TA01b
Rev 0 For more information www.analog.com PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Top Side Driver Voltage BOOST Switch Voltage (SW) BG, TG FREQ, DRVUV Voltages (Note 1) FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 150°C, θJA = 38°C/W , θJC = 10°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB FOR RATED ELECTRICAL AND THERMAL CHARACTERISTICS TOP VIEW SENSE SENSE– SS VFB ITH TMR FREQ WARNB TG SW OVLO INTV CC DRVUV RUN EXTV CC VIN DRVCC GND BG BOOST 20 19 18 17 7 8 TOP VIEW UFD PACKAGE 20-LEAD (4mm × 5mm) PLASTIC QFN TJMAX = 150°C, θJA = 43°C/W, θJC = 3.4°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB FOR RATED ELECTRICAL AND THERMAL CHARACTERISTICS 9 10 16SS VFB ITH TMR FREQ WARNB DRVUV RUN EXTV CC VIN DRVCC GND SENSE– SENSE+ OVLO INTV CC TG SW BOOST BG ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC7862EFE#PBF LTC7862EFE#TRPBF LTC7862FE 20-Lead Plastic TSSOP –40°C to 125°C LTC7862IFE#PBF LTC7862IFE#TRPBF LTC7862FE 20-Lead Plastic TSSOP –40°C to 125°C LTC7862HFE#PBF LTC7862HFE#TRPBF LTC7862FE 20-Lead Plastic TSSOP –40°C to 150°C LTC7862EUFD#PBF LTC7862EUFD#TRPBF 7862 20-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LTC7862IUFD#PBF LTC7862IUFD#TRPBF 7862 20-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LTC7862HUFD#PBF LTC7862HUFD#TRPBF 7862 20-Lead (4mm × 5mm) Plastic QFN –40°C to 150°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. http://www.linear .com/product/LTC7862#orderinfo SS, OVLO Voltages Operating Junction Temperature Range (Notes 2, 3) LTC 7862E, LTC7862I LTC 7862H Storage Temperature Range
Rev 0For more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input Supply Operating Voltage Range (Note 9) DRVUV = 0V l 4 140 V VOUT Regulated Output Clamp Voltage Set Point 60 V VFB Regulated Feedback Voltage (Note 4); ITH Voltage = 1.2V 0°C to 85°C l 0.792 0.788 0.800 0.800 0.808 0.812 V V I FB Feedback Current (Note 4) –0.006 ±0.050 µA Feedback Voltage Line Regulation (Note 4) V IN = 4.5V to 150V 0.002 0.02 %/V Feedback Voltage Load Regulation (Note 4) Measured in Servo Loop, ∆ITH Voltage = 1.2V to 0.7V l 0.01 0.1 (Note 4) Measured in Ser vo Loop, ∆ITH Voltage = 1.2V to 1.6V l –0.01 –0.1 gm T ransconductance Amplifier gm (Note 4) ITH = 1.2V, Sink/Source 5µA 2 mmho IQ Input DC Supply Current (Note 5) VFB = 0.77V 1.2 mA Shutdown RUN = 0V 10 20 µA UVLO Undervoltage Lockout DRVCC Ramping Up DR VUV = 0V DR VUV = INTVCC l l 4.0 7.5 4.2 7.8 V V D RVCC Ramping Down DR VUV = 0V DR VUV = INTVCC l l 3.6 6.4 3.8 6.7 4.0 7.0 V V V RUN ON RUN Pin ON Threshold VRUN Rising l 1.1 1.2 1.3 V VRUN Hyst RUN Pin Hysteresis 80 mV OVLO Overvoltage Lockout Threshold VOVLO Rising l 1.1 1.2 1.3 V OVLO Hyst OVLO Hysteresis 100 mV OVLO Delay 1 µs Feedback Overvoltage Protection Measured at V FB, Relative to Regulated VFB 7 10 13 % ISENSE+ SENSE + Pin Current ±1 µA ISENSE– SENSE – Pin Current SENSE+ = SENSE– = 28V 900 µA Maximum TG Duty Factor In Dropout 100 % ISS Soft-Start Charge Current VSS = 0V 8 10 12 µA VSENSE(MAX) Maximum Current Sense Threshold V FB = 0.7V, VSENSE– = 28V l 43 50 57 mV The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, VEXTVCC = 0V, VDRVUV = 0V unless otherwise noted.
Rev 0 For more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Gate Driver TG Pull-up On-Resistance TG Pull-down On-Resistance VDRVUV = INTVCC 2.2 1.0 Ω Ω BG Pull-up On-Resistance BG Pull-down On-Resistance VDRVUV = INTVCC 2.0 1.0 Ω Ω TG T ransition Time: Rise T ime Fall T ime (Note 6) VDRVUV = INTVCC CLOAD = 3300pF CLOAD = 3300pF ns ns BG T ransition Time: Rise T ime Fall T ime (Note 6) VDRVUV = INTVCC CLOAD = 3300pF CLOAD = 3300pF ns ns T op Gate Off to Bottom Gate On Delay Synchronous Switch-On Delay Time CLOAD = 3300pF Each Driver , VDRVUV = INTVCC (Note 6) ns Bottom Gate Off to T op Gate On Delay Top Switch-On Delay Time CLOAD = 3300pF Each Driver , VDRVUV = INTVCC (Note 6) ns tON(MIN) TG Minimum On-Time (Note 7) VDRVUV = INTVCC 80 ns Charge Pump for High Side Driver Supply ICPUMP Charge Pump Output Current VBOOST =16V, VSW = 12V, VFREQ = 0V VBOOST =19V, VSW = 12V, VFREQ = 0V µA µA D RVCC LDO Regulator DRVCC Voltage from VIN LDO VEXTVCC = 0V 7V < VIN < 150V, DRVUV = 0V 11V < VIN < 150V, DRVUV = INTVCC 5.8 8.6 6.0 9.0 6.2 9.4 V V D RVCC Load Regulation from VIN LDO I CC = 0mA to 50mA, VEXTVCC = 0V DRVUV = 0V DRVUV = INTV CC 1.4 0.9 2.5 2.0 D RVCC Voltage from EXTVCC LDO 7V < V EXTVCC < 13V, DRVUV = 0V 11V < VEXTVCC < 13V, DRVUV = INTVCC 5.8 8.6 6.0 9.0 6.2 9.4 V V D RVCC Load Regulation from EXTVCC LDO ICC = 0mA to 50mA DRVUV = 0V, VEXTVCC = 8.5V DRVUV = INTVCC, VEXTVCC = 13V 0.7 0.5 2.0 2.0 EXT VCC LDO Switchover Voltage EXTV CC Ramping Positive DRVUV = 0V DRVUV = INTV CC 4.5 7.4 4.7 7.7 4.9 8.0 V V EXT VCC Hysteresis 250 mV INTVCC LDO Regulator VINTVCC INTVCC Voltage ICC = 0mA to 2mA 4.7 5.0 5.2 V Oscillator and Phase-Locked Loop Programmable Frequency RFREQ = 25k 105 kHz Programmable Frequency RFREQ = 65k 375 440 505 kHz Programmable Frequency RFREQ =105k 835 kHz Low Fixed Frequency VFREQ = 0V 320 350 380 kHz High Fixed Frequency VFREQ = INTVCC 485 535 585 kHz ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, VEXTVCC = 0V, VDRVUV = 0V unless otherwise noted.
Rev 0For more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Fault Timer and WARNB Output ISWITCHING TMR Pull-Up Current (Switching) TMR = 0V, V FB = 0.83V l –35 –40 –45 µA IDROPOUT TMR Pull-Down Current (Dropout) TMR = 1V, V FB = 0.77V l 0.7 1.1 1.4 µA ICOOLDOWN TMR Pull-Down Current (Cool-Down) TMR = 2.5V l 0.7 1.1 1.4 µA TMR Switching Off Threshold l 2.13 2.19 2.23 V TMR Retry Threshold 0.19 0.25 0.31 V TMR Switching Set Time (Initial Fault Period) per 1µF 52 55 58 ms/µF TMR Switching Set T ime (Retry Period) per 1µF 50 ms/µF TMR Cool-Down T ime per 1µF 1700 ms/µF DRETRY Retry Duty Cycle During a Sustained Fault 1.8 2.7 3.5 % VWARNB WARNB Voltage Low IWARNB = 2mA 0.02 0.04 V IWARNB WARNB Leakage Current VWARNB = 3.3V 10 µA tWARNB Delay from TG Going High to WARNB Going High Impedance 60 µs ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = 12V, VRUN = 5V, VEXTVCC = 0V, VDRVUV = 0V unless otherwise noted. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Ratings for extended periods may affect device reliability and lifetime. Note 2: The LTC7862 is tested under pulsed load conditions such that T J ≈ TA. The LTC7862E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC7862I is guaranteed over the –40°C to 125°C operating junction temperature range and the LTC7862H is guaranteed over the –40°C to 150°C operating junction temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. High temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125ºC. The junction temperature (T J, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD • θJA) where θJA = 38°C/W for the TSSOP package and θJA = 43°C/W for the QFN package. Note 3 : This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. The maximum rated junction temperature will be exceeded when this protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. Note 4: The LTC7862 is tested in a feedback loop that servos V ITH to a specified voltage and measures the resultant VFB. The specification at 85°C is not tested in production and is assured by design, characterization and correlation to production testing at other temperatures (125°C for the LTC7862E and LTC7862I, 150°C for the LTC7862H). For the LTC7862I and LTC7862H, the specification at 0°C is not tested in production and is assured by design, characterization and correlation to production testing at –40°C. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See the Applications Information section. Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 7: The minimum on-time condition is specified for an inductor peak-to-peak ripple current >40% of I MAX (See Minimum On-Time Considerations in the Applications Information section). Note 8: Do not apply a voltage or current source to these pins. They must be connected to capacitive loads only, otherwise permanent damage may occur . Note 9: The minimum input supply operating range is dependent on the DRV CC UVLO thresholds as determined by the DRVUV pin setting. Note 10: All voltages with respect to GND unless otherwise noted. Positive currents are into pins; negative currents are out of pins unless otherwise noted.
Rev 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS SENSE– Pin Input Current vs VSENSE Voltage SENSE– Pin Input Bias Current vs Temperature Undervoltage Lockout Threshold vs Temperature Current Limit vs Feedback Voltage DRV CC and EXTVCC vs Load Current EXTVCC Switchover and DRVCC Voltages vs Temperature EXTVCC Switchover and DRVCC Voltages vs Temperature Soft Start-Up Regulated Feedback Voltage vs Temperature TEMPERATURE (°C) –75 –50 –25 100 125 150 792 794 796 798 800 802 804 806 808 REGULATED FEEDBACK VOL TAGE (mV)
7801 G02
V SENSE COMMON MODE VOL TAGE (V) 100 200 300 400 500 600 700 800 900 1000 SENSE CURRENT (µA)
7862 G06
V OUT ≥ INTV CC + 0.5V V OUT ≤ INTV CC – 0.5V TEMPERATURE (°C) –75 –50 –25 100 125 150 100 200 300 400 500 600 700 800 900 1000 SENSE CURRENT (µA)
7862 G07
DRVUV = INTV CC DRVUV = 0V TEMPERATURE (°C) –75 –50 –25 100 125 150 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 DRV CC VOL TAGE (V)
7862 G08
FEEDBACK VOL TAGE (mV) 100 200 300 400 500 600 700 800 100 MAXIMUM CURRENT SENSE VOL TAGE (mV)
7862 G09
TA = 25°C, unless otherwise noted. FIGURE 8 CIRCUIT VIN = VOUT = 28V 2ms/DIV RUN 10V/DIV WARNB 5V/DIV VOUT 10V/DIV
7862 G01
EXTVCC = 0V , DRVSET = INTVCC EXTVCC = 13V , DRVSET = INTVCC V IN LDO EXTVCC = 0V , DRVSET=0V EXTVCC = 5V , DRVSET = 0V EXTVCC = 8.5V , DRVSET = 0V LOAD CURRENT (mA) DRV CC VOL TAGE (V)
7862 G03
EXTVCC = 8.5V ICC = 0mA EXTVCC = 8.5V ICC = 50mA DRVUV = 0V TEMPERATURE (°C) –75 –50 –25 100 125 150 4.0 4.5 5.0 5.5 6.0 6.5 DRV CC VOL TAGE (V)
7862 G04
EXTVCC = 13V ICC = 0mA EXTVCC = 13V ICC = 50mA DRVUV = INTVCC TEMPERATURE (°C) –75 –50 –25 100 125 150 7.0 7.5 8.0 8.5 9.0 9.5 10.0 DRV CC VOL TAGE (V)
7862 G05
Rev 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Maximum Current Sense Threshold vs ITH Voltage RUN/OVLO Threshold vs Temperature OVLO RISING RUN RISING RUN FALLING OVLO FALLING TEMPERATURE (°C) –75 –50 –25 100 125 150 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 RUN/OVLO PIN VOL TAGE (V)
7862 G11
5% DUTY CYCLE V ITH (V) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 –40 –20 100 CURRENT SENSE VOL TAGE (mV)
7862 G10
Quiescent Current vs Temperature Oscillator Frequency vs Temperature SS Pull-Up Current vs Temperature Shutdown Current vs Temperature Shutdown Current vs Input Voltage V IN = 12V TEMPERATURE (°C) –75 –50 –25 100 125 150 SHUTDOWN CURRENT (µA)
7862 G13
V IN = 6.3V INPUT VOL TAGE (V) 105 120 135 150 SHUTDOWN CURRENT (µA)
7862 G14
FREQ = 0V FREQ = INTV CC TEMPERATURE (°C) –75 –50 –25 100 125 150 300 350 400 450 500 550 600 FREQUENCY (kHz)
7862 G16
TEMPERATURE (°C) –75 –50 –25 100 125 150 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 SS CURRENT (µA)
7862 G17
vs SW Voltage in Pass-Through Mode FREQ = 350kHz 10MΩ BETWEEN BOOST AND SW DRVUV = 0V 150°C 25°C –55°C SW VOL TAGE (V) (BOOST - SW) VOL TAGE (V)
7862 G18
DRVUV = INTVCC DRVUV = 0V TEMPERATURE (°C) –75 –50 –25 100 125 150 0.5 1.0 1.5 2.0 QUIESCENT CURRENT (mA)
7862 G15
TA = 25°C, unless otherwise noted. EXTV CC = 0V DRVUV = 0V DRVUV = INTV CC INPUT VOL TAGE (V) 105 120 135 150 DRV CC VOL TAGE (V)
7862 G12
Rev 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS BOOST Charge Pump Charging Current vs Frequency BOOST Charge Pump Charging Current vs SW Voltage V BOOST = 16V V SW = 12V 150°C 25°C –55°C OPERATING FREQUENCY (kHz) 100 200 300 400 500 600 700 800 900 1000 100 CHARGE PUMP CHARGING CURRENT (µA)
7862 G19
FREQ = 350kHz VBOOST - VSW = 7V 150°C 25°C –55°C SW VOL TAGE (V) 100 CHARGE PUMP CHARGING CURRENT (µA)
7862 G20
VBOOST - VSW = 4V TMR Pull-Up Current vs Temperature TMR Pull-Down Current vs Temperature Sustained Overvoltage Fault TEMPERATURE (°C) –75 –50 –25 100 125 150 –45 –44 –43 –42 –41 –40 –39 –38 –37 –36 –35 TMR CURRENT (µA)
7862 G21
TEMPERATURE (°C) –75 –50 –25 100 125 150 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 TMR CURRENT (µA)
7862 G22
VOUT = 28V , CTMR = 1µF 1s/DIV VIN/VOUT 50V/DIV TMR 2V/DIV WARNB 5V/DIV
7862 G23
TA = 25°C, unless otherwise noted. V IN = 12V OUTPUT CURRENT (A) 250 500 750 1000 1250 1500 1750 2000 2250 2500 POWER LOSS (mW)
7862 G24
V IN = 28V FIGURE 8 CIRCUIT V IN = 14V OUTPUT CURRENT (A) 250 500 750 1000 1250 1500 1750 2000 POWER LOSS (mW)
7862 G25
V IN = 48V OUTPUT CURRENT (A) 250 500 750 1000 1250 1500 POWER LOSS (mW)
7862 G26
Power Loss vs Output Current in Pass-Through Mode Power Loss vs Output Current in Pass-Through Mode Power Loss vs Output Current in Pass-Through Mode
Rev 0For more information www.analog.com SS (Pin 1/Pin 3): Soft-Start Input. The LTC7862 attempts to regulate the V FB voltage to the smaller of 0.8V or the voltage on the SS pin. An internal 10μA pull-up current source is connected to this pin. A capacitor to ground at this pin sets the ramp time to final regulated output volt- age during startup or during a retry. V FB (Pin 2/Pin 4): Feedback Input. This pin receives the remotely sensed feedback voltage from an external resis- tor divider across the output. ITH (Pin 3/Pin 5): Error Amplifier Output and Switching Regulator Compensation Point. The current comparator trip point increases with this control voltage. TMR (Pin 4/Pin 6): Programmable Fault Timer Input. A timing capacitor C TMR, connected between this pin and GND, sets the amount of time that can be spent switching (during an overvoltage, overcurrent, and/or startup condi- tion.) It also sets the cool-down time before the LTC7862 will retry. See Applications Information. FREQ (Pin 5/Pin 7): Frequency Control Pin for the Internal VCO. Connecting the pin to GND forces the VCO to a fixed low frequency of 350kHz. Connecting the pin to INTV CC forces the VCO to a fixed high frequency of 535kHz. Other frequencies between 50kHz and 900kHz can be pro - grammed by using a resistor between FREQ and GND. An internal 20µA pull-up current develops the voltage to be used by the VCO to control the frequency. WARNB (Pin 6/Pin 8): Open-Drain Logic Output. This pin pulls low to GND whenever the LTC7862 is switch - ing (during an overvoltage, overcurrent, and/or startup condition.) The typical pull-down impedance is 10Ω. The WARNB pin enters a high-impedance state 60µs after LTC7862 enters dropout with the top external MOSFET on continuously. The WARNB pin is also pulled low during shutdown and during the cool-down period before a retry. TG (Pin 7/Pin 9): High Current Gate Drive for Top N-Channel MOSFET . This is the output of the floating high side driver with a voltage swing from SW to BOOST . SW (Pin 8/Pin 10): Switch Node Connection to Inductor . BOOST (Pin 9/Pin 11): Bootstrapped Supply to the Topside Floating Driver . A capacitor is connected between the BOOST and SW pins and an external low leakage diode is tied between the BOOST and DRVCC pins. Voltage swing at the BOOST pin is from approximately DRVCC to (VIN + DRVCC). When TG is statically on during normal opera - tion, BOOST is approximately 9V above SW . BG (Pin 10/Pin 12) : High Current Gate Drive for Bottom (Synchronous) N-Channel MOSFET . Voltage swing at this pin is from ground to DRVCC. GND (Pin 11, Exposed Pin 21/Pin 13, Exposed Pad Pin 21): Ground. All GND pins must be tied together for oper- ation. The exposed pad must be soldered to PCB ground for rated electrical and thermal performance. DRVCC (Pin 12/Pin 14): Output of the V IN or EXTV CC Low Dropout Regulators. The gate drivers are powered from this voltage source. The DRV CC voltage is set by the DRVUV pin. Must be decoupled to ground with a mini - mum of 4.7µF ceramic or other low ESR capacitor , as close as possible to the IC. Do not use the DRVCC pin for any other purpose. VIN (Pin 13/Pin 15): Main Supply Pin. A bypass capacitor should be tied between this pin and GND. EXTVCC (Pin 14/Pin 16): External Power Input to an Internal LDO linear regulator Connected to DRV CC. This LDO supplies DRV CC power from EXTV CC, bypassing the internal LDO powered from V IN whenever EXTV CC is higher than its switchover threshold (4.7V or 7.7V depending on the DRVUV pin). See DRVCC Regulators in the Applications Information section. Do not exceed 14V on this pin. Do not connect EXTV CC to a voltage greater than VIN. RUN (Pin 15/Pin 17): Run Control Input. Forcing this pin below 1.12V shuts down the controller . Forcing this pin below 0.7V shuts down the entire LTC7862, reducing qui- escent current to approximately 10µA. This pin can be tied to VIN for always-on operation. Do not float this pin. PIN FUNCTIONS (QFN/TSSOP)
Rev 0 For more information www.analog.com DRVUV (Pin 16/Pin 18) : DRVCC Regulation and UVLO Program Pin. This pin sets the regulated output voltage of the DRVCC linear regulator . Tying this pin to GND sets DRVCC to 6.0V. Tying this pin to INTV CC sets DRVCC to 9V. This pin also determines the higher or lower DRV CC UVLO and EXTV CC switchover thresholds, as listed on the Electrical Characteristics table. Connecting DRVUV to GND chooses the lower thresholds whereas tying DRVUV to INTVCC chooses the higher thresholds. Do not float this pin. INTVCC (Pin 17/Pin 19): Output of the Internal 5V Low Dropout Regulator . Many of the low voltage analog and digital circuits are powered from this voltage source. A low ESR 0.1µF ceramic bypass capacitor should be con- nected between INTV CC and GND, as close as possible to the LTC7862. OVLO (Pin 18/Pin 20) : Overvoltage Lockout Input. A voltage on this pin above 1.2V disables switching of the controller . The DRVCC and INTVCC supplies maintain regulation during an OVLO event. Exceeding the OVLO threshold triggers a soft-start reset. If the OVLO function is not used, connect this pin to GND. SENSE + (Pin 19/Pin 1): The (+) Input to the Differential Current Comparator . The ITH pin voltage and controlled offsets between the SENSE– and SENSE+ pins in conjunc- tion with RSENSE set the current trip threshold. SENSE– (Pin 20/Pin 2): The (–) Input to the Differential Current Comparator . When SENSE– is greater than INTVCC, the SENSE– pin supplies power to the current comparator . PIN FUNCTIONS (QFN/TSSOP) TIMING DIAGRAM 7862 TD TG TG TMR TMR COOLDOWN COOLDOWN DROPOUT DROPOUT WARNB WARNB SWITCHING OFF SWITCHING OFF 40µA PULL-UP CURRENT 40µA PULL-UP CURRENT 1.1µA PULL-DOWN CURRENT 1.1µA PULL-DOWN CURRENT (NOT TO SCALE) (NOT TO SCALE) 2.19V 2.19V 250mV 250mV SWITCHING SWITCHING VIN SURGE VIN SURGE VIN SURGE GOES AWAY VIN SURGE GOES AWAY SWITCHING OFF SWITCHING OFF
Rev 0For more information www.analog.com FUNCTIONAL DIAGRAM 20µA 10µA COOLDOWN SHDN 2mV TMR 40µA DROPOUT CTMR
7862 BD01
R A R B C C R C C IN CB L R SENSE C OUT V OUT C SS WARNB DROPOUT COOLDOWN SHDN OVLO RUN 1.2V VCO FREQ V IN DRV CC SS ITH VFB SENSE– SENSE+ GND BG SW TG BOOST DRV CC LDO/UVLO CONTROL INTV CC EXTV CC DRVUV INTV CC LDO 4.7V/ 7.7V V IN LDO EXTV CC LDO 3.5V CHARGE PUMP DROPOUT DETECT SWITCH LOGIC DRV CC TOP BOT DROPOUT TOPON Q S R EA ICMP IR 0.88V CLK 1.8V SLOPE COMP 0.80V SS V MTOP (MAIN) MBOT (SYNCHRONOUS) IN DB DRVCC EN EN 1.1µA DROPOUT COOLDOWN SHDN 2.19V 0.25V Q S COOLDOWN R
Rev 0 For more information www.analog.com OPERATION High Efficiency Switching Surge Stopper Overview The LTC7862 is a high efficiency switching surge stop - per controller . “Normal” operation for the LTC7862 is in “dropout” mode, in which the top external N-channel MOSFET is turned on continuously (100% duty cycle) passing the input voltage through to the output with minimal voltage drop. During an input overvoltage event, the LTC7862 switches the gates of the top and bottom N-channel MOSFETs to act as a switching DC/DC step- down regulator . This maintains the output voltage at a safe, user-programmed clamp voltage level. Similarly, the LTC7862 switches in response to an overcurrent or short- circuit event. The LTC7862 also switches during startup to limit inrush current and to smoothly ramp the output voltage. If the time spent during any of these switching events exceeds the time programmed by the fault timer pin (TMR), the LTC7862 will cease switching for a cool- down period and then attempt to restart. An LTC7862 high efficiency switching surge stopper can be thought of as a pre-regulator . Consider as an example a MIL1275 application, where the input voltage connects to a nominal 28V vehicle power bus. The power bus can drop as low as 12V during engine cranking, and can also surge up to 100V with a total surge duration lasting up to 500ms. A switching surge stopper can be placed between the input power bus and any downstream load to protect the load from potentially destructive voltage levels. The output voltage of the switching surge stopper is pre-regu- lated or clamped to a safe voltage, such as 34V. Whenever the input voltage is above 34V, the LTC7862 switches and limits the output voltage to 34V. Whenever the input voltage is less than 34V, the LTC7862 is in normal mode and passes the input voltage through to the output with no switching. For both a traditional linear regulator surge stopper (such as LTC4363) and the LTC7862 high efficiency switching surge stopper , the power loss increases significantly dur- ing the input voltage surge when regulation begins. In a linear regulator surge stopper , the power loss is simply the output current times the difference between the input and output voltages, which can be very large. In a switch- ing surge stopper , the power loss is determined by the switching regulator’ s conversion efficiency, which is relatively high. This enables the LTC7862 high efficiency switching surge stopper to deliver much higher output current and power levels compared to a traditional linear regulator surge stopper . Furthermore, by using the LTC7862’s timer , the time spent switching in regulation can be limited, allowing the oper- ating power to be pushed beyond what could otherwise be achieved if the switching regulator were required to run continuously in steady-state. The use of the timer improves reliability and reduces component size com - pared to a continuous solution. The timer also allows the external components to be optimized for the normal pass-through mode in which the switching surge stop - per spends the vast majority of its operating life. In this normal mode, the switching surge stopper is effectively acting as a wire with a conduction power loss (sometimes referred to as an insertion loss) equal to the output cur - rent times the sum of the resistances of the top MOSFET , inductor , and current sense resistor . In particular , a relatively low RDS(ON) (with typically high gate charge) top MOSFET can be selected. This reduces power loss in normal operation, but significantly increases the power loss when switching due to transition losses in the top MOSFET . Usually, in traditional high input voltage switching step-down regulators, a low gate charge (with typically high RDS(ON)) top MOSFET is desired to minimize transition power losses. But since the LTC7862’s timer limits the time spent switching, this increased power loss can be safely tolerated. Likewise, the inductor value and switching frequency can be chosen to minimize the insertion loss at the expense of switching losses. This allows the LTC7862 switching surge stopper to operate at a higher switching frequency than what would be feasible in a continuous solution without a timer . This results in a physically smaller inductor with a lower inductance and lower DC resistance.
Rev 0For more information www.analog.com OPERATION Main Control Loop The LTC7862 uses a constant frequency, peak current mode step-down architecture. During switching opera - tion, the external top MOSFET is turned on when the clock sets the RS latch, and is turned off when the main current comparator , ICMP , resets the RS latch. The peak inductor current at which ICMP trips and resets the latch is controlled by the voltage on the ITH pin, which is the output of the error amplifier , EA. The error amplifier com- pares the output voltage feedback signal at the V FB pin (which is generated with an external resistor divider con- nected across the output voltage, VOUT, to ground) to the internal 0.800V reference voltage. When the load current increases, it causes a slight decrease in V FB relative to the reference, which causes the EA to increase the ITH voltage until the average inductor current matches the new load current. After the top MOSFET is turned off each cycle, the bot - tom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current comparator IR, or the beginning of the next clock cycle. DRVCC/EXTVCC/INTVCC Power Power for the top and bottom MOSFET drivers is derived from the DRV CC pin. The DRV CC supply voltage can be programmed to 6V or 9V using the DRVUV pin. T wo sepa- rate LDOs (low dropout linear regulators) can provide power from V IN to DRV CC. The internal V IN LDO uses an internal P-channel pass device between the V IN and DRVCC pins. When the EXTVCC pin is tied to a voltage below its swi - tchover voltage (4.7V or 7.7V depending on the DRVUV pin), the V IN LDO is enabled and supplies power from VIN to DRVCC. If EXTVCC is taken above its switchover voltage, the V IN LDO is turned off and an EXTVCC LDO is turned on. Once enabled, the EXTVCC LDO supplies power from EXTVCC to DRVCC. Using the EXTVCC pin allows the DRVCC power to be derived from a high efficiency external source such as one derived from the LTC7862 switching regulator output. The INTVCC supply powers most of the other internal circuits in the LTC7862. The INTV CC LDO regulates to a fixed value of 5V and its power is derived from the DRVCC supply. Top MOSFET Driver , Charge Pump and Pass-Through Mode The top MOSFET driver is biased from the floating boot- strap capacitor , C B, which recharges during each switch- ing cycle through an external diode, D B, whenever SW goes low. If the input voltage is below the regulated output (clamp) voltage, the loop enters dropout and turns on the top MOSFET continuously. The LTC7862 includes an internal charge pump that allows the top MOSFET to be turned on continuously at 100% duty cycle. This charge pump deliv- ers current to CB to keep it biased at approximately 8.5V. Shutdown and Start-Up (RUN, SS Pins) The LTC7862 can be shut down using the RUN pin. Connecting the RUN pin below 1.12V shuts down the main control loop. Connecting the RUN pin below 0.7V disables the controller and most internal circuits, including the DRVCC and INTVCC LDOs. In this state, the LTC7862 draws only 10μA of quiescent current. The RUN pin has no internal pull-up current, so the pin must be externally pulled up or driven directly by logic. The RUN pin can tolerate up to 150V (absolute maxi - mum), so it can be conveniently tied to VIN in always-on applications where the controller is enabled continuously and never shut down. The start-up of the output voltage V OUT is controlled by the voltage on the SS pin. When the voltage on the SS pin is less than the 0.8V internal reference, the LTC7862 regulates the V FB voltage to the SS pin voltage instead of the 0.8V reference. This allows the SS pin to be used to program a soft-start by connecting an external capacitor from the SS pin to GND. An internal 10μA pull-up current charges this capacitor creating a voltage ramp on the SS pin. As the SS voltage rises linearly from 0V to 0.8V (and
pulse-skipping mode at light load currents. to reverse (discontinuous operation). to maintain low output ripple voltage. 900kHz, as shown in Figure 1. on until the overvoltage condition is cleared.
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Figure 1. Relationship Between Oscillator Frequency
current comparators to be used in inductor DCR sensing. smaller current to the higher current. sensitive small-signal nodes. Figure 2. Sense Lines Placement with Inductor or Sense Resistor
7862 F02
compensation on the current limit performance.
compared to inductor DCR sensing. Figure 3. Current Sensing Methods
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Rev 0For more information www.analog.com The values for R1 and R2 are: R1= R1||R2 RD ; R2= R1•RD 1−RD The maximum power loss in R1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: PLOSSR1= VIN(MAX) −VOUT( ) • VOUT Ensure that R1 has a power rating higher than this value. If high efficiency is necessary at light loads, consider this power loss when deciding whether to use DCR sensing or sense resistors. Light load power loss can be mod - estly higher with a DCR network than with a sense resis- tor , due to the extra switching losses incurred through R1. However , DCR sensing eliminates a sense resistor , reduces conduction losses and provides higher efficiency at heavy loads. Peak efficiency is about the same with either method. Inductor Value Calculation The operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. So why would anyone ever choose to operate at lower frequencies with larger components? The answer is efficiency. A higher frequency generally results in lower efficiency because of MOSFET switching and gate charge losses. In addi - tion to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. APPLICATIONS INFORMATION The inductor value has a direct effect on ripple current. The inductor ripple current, ∆IL, decreases with higher inductance or higher frequency and increases with higher VIN: ΔIL = 1 (f)(L) VOUT 1− VOUT VIN Accepting larger values of ∆IL allows the use of low induc- tances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ∆IL = 0.3(IMAX). The maximum ∆IL occurs at the maximum input voltage. Inductor Core Selection Once the value for L is known, the type of inductor must be selected. High efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermal- loy cores. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance value selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred for high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. Ferrite core material saturates hard, which means that induc - tance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate!
Rev 0 For more information www.analog.com APPLICATIONS INFORMATION Power MOSFET Selection T wo external power MOSFETs must be selected for the LTC7862 controller: one N-channel MOSFET for the top (main) switch, and one N-channel MOSFET for the bottom (synchronous) switch. The peak-to-peak drive levels are set by the DRVCC volt- age. This voltage can be 6V or 9V depending on configu- ration of the DRVUV pin. Therefore, both logic-level and standard-level threshold MOSFETs can be used in most applications depending on the programmed DRVCC volt- age. Pay close attention to the BVDSS specification for the MOSFETs as well. Selection criteria for the power MOSFET for normal pass- through operation include the on-resistance R DS(ON), input voltage and maximum output current. The MOSFET power dissipation at maximum output cur- rent are given by: P MAIN = (IOUT(MAX))2 (1+ )RDS(ON) PSYNC = 0 (Synchronous FET is OFF during normal pass- through operation) where is the temperature dependency of R DS(ON). The term (1 + ) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but = 0.005/°C can be used as an approximation for low voltage MOSFETs. Selection criteria for the power MOSFETs during timer- enabled switching operation include the on-resistance RDS(ON), Miller capacitance C MILLER, input voltage and maximum output current. Miller capacitance, CMILLER, can be approximated from the gate charge curve usually pro- vided on the MOSFET manufacturers’ data sheet. CMILLER is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in V DS. This result is then multiplied by the ratio of the application applied V DS to the gate charge curve specified VDS. When the IC is switching in continuous mode the duty cycles for the top and bottom MOSFETs are given by: MAIN SWITCH DUTY CYCLE = VOUT VIN SYNCHRONOUS SWITCH DUTY CYCLE= VIN −VOUT VIN The MOSFET power dissipations at maximum output cur- rent are given by: PMAIN = VOUT VIN IOUT(MAX)( ) 1+ δ( ) RDS(ON) + (VIN)2 IOUT(MAX) ⎠⎟(RDR)(CMILLER) • VDRVCC −VTHMIN + 1 VTHMIN ⎦⎥(f) PSYNC = VIN −VOUT VIN IOUT(MAX)( ) 1+ δ( ) RDS(ON) where δ is the temperature dependency of R DS(ON) and RDR (approximately 2Ω) is the effective driver resistance at the MOSFET’s Miller threshold voltage. V THMIN is the typical MOSFET minimum threshold voltage. Both MOSFETs have I2R losses while the main N-channel equations include an additional term for transition losses, which are highest at high input voltages. For V IN < 20V the high current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rap- idly increase to the point that the use of a higher RDS(ON) device with lower C MILLER actually provides higher effi - ciency. The synchronous MOSFET losses are greatest at high input voltage when the top switch duty factor is low or during a short-cir cuit when the synchronous switch is on close to 100% of the period. The MOSFET’s temperature rise due to power dissipation must be considered. Refer to Thermal Considerations sec- tion for more details.
manufacturer if there is any question. (C1) and the VIN pin provides further isolation. capacitance and ∆IL is the ripple current in the inductor . since ∆IL increases with input voltage.
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Figure 4. Setting Output Voltage RUN pin below 1.12V shuts down the main control loop. internal circuits, including the DRVCC and INTVCC LDOs. 15MΩ impedance to an internal 3V clamp.
Figure 5. Adjustable UV and OV Lockout in Figure 5 to meet specific VIN voltage requirements.
7862 F05
using the previous equations with R5 = 0Ω. using the previous equations with R3 = 0Ω. Figure 6. Using the SS Pin to Program Soft-Start
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Rev 0For more information www.analog.com DRVCC Regulators The LTC7862 features two separate low dropout linear regulators (LDO) that can supply power at the DRV CC pin. The internal V IN LDO uses an internal P-channel pass device between the V IN and DRVCC pins. The inter- nal EXTVCC LDO uses an internal P-channel pass device between the EXTVCC and DRVCC pins. The DRVCC supply is regulated to 6V or 9V, depending on how the DRVUV pin is set. The internal V IN and EXTVCC LDOs can supply a peak current of at least 50mA. The DRVCC pin must be bypassed to ground with a minimum of 4.7μF ceramic capacitor . Good bypassing is needed to supply the high transient currents required by the MOSFET gate drivers. The DRVUV pin programs the DRVCC supply voltage and also selects different DRVCC UVLO and EXTVCC switchover threshold voltages. Tables 2a and 2b summarize the dif- ferent DRVUV pin configurations along with the voltage settings that go with each configuration. Tying the DRVUV pin to INTVCC programs DRVCC to 9V. Tying the DRVUV pin to GND programs DRVCC to 6V. Table 2a. DRVUV PIN DRVCC VOL TAGE GND 6V INTVCC 9V Table 2b. DRVUV DRVCC UVLO RISING/FALLING THRESHOLDS EXTVCC SWITCHOVER RISING/FALLING THRESHOLD GND 4.0V/3.8V 4.7V/4.45V INTVCC 7.5V/6.7V 7.7V/7.45V APPLICATIONS INFORMATION High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maxi- mum junction temperature rating for the LTC7862 to be exceeded. The DR VCC current, which is dominated by the gate charge current, may be supplied by the VIN LDO, or the EXTVCC LDO. When the voltage on the EXTVCC pin is less than its switchover threshold (4.7V or 7.7V as deter- mined by the DRVUV pin described above), the VIN LDO is enabled. Power dissipation in this case is highest and is equal to V IN • IDRVCC and is dissipated inside the IC. The gate charge current is dependent on operating frequency. When the voltage applied to EXTV CC rises above its switchover threshold, the V IN LDO is turned off and the EXTVCC LDO is enabled. The EXTVCC LDO remains on as long as the voltage applied to EXTVCC remains above the switchover threshold minus the comparator hysteresis. The EXTV CC LDO attempts to regulate the DRVCC voltage to the voltage as programmed by the DRVUV pin, so while EXTVCC is less than this voltage, the LDO is in dropout and the DRVCC voltage is approximately equal to EXTVCC. When EXTVCC is greater than the programmed voltage, up to an absolute maximum of 14V, DRV CC is regulated to the programmed voltage. Using the EXTV CC LDO allows the MOSFET driver and control power to be derived from the LTC7862’s switch- ing regulator output (4.7V/7.7V ≤ VOUT ≤ 14V). If more current is required through the EXTVCC LDO than is speci- fied, an external Schottky diode can be added between the EXTVCC and DRVCC pins. In this case, do not apply more than 10V to the EXTVCC pin and make sure that EXTV CC ≤ VIN.
ered from the internal VIN LDO.
- EXTVCC connected directly to the regulator output
- EXTVCC connected to the regulator output through an
bias current through the Zener diode. capacitance of the topside MOSFET(s). will be more current than the charge pump can provide.
7862 F07
Figure 7. Using a Zener Diode Between VOUT and EXTVCC to bias other pins, such as FREQ and WARNB.
Rev 0For more information www.analog.com APPLICATIONS INFORMATION Fault Conditions: Output Overvoltage Protection (Crowbar) The overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels. The crowbar causes huge currents to flow, that blow the fuse to protect against a shorted top MOSFET if the short occurs while the con- troller is operating. A comparator monitors the output for over voltage condi- tions. The comparator detects faults greater than 10% above the nominal output voltage. When this condition is sensed, the top MOSFET is turned off and the bottom MOSFET is turned on until the overvoltage condition is cleared. The bottom MOSFET remains on continuously for as long as the overvoltage condition persists; if VOUT returns to a safe level, normal operation automatically resumes. A shorted top MOSFET will result in a high current con - dition which will open the system fuse. The switching regulator will regulate properly with a leaky top MOSFET by altering the duty cycle to accommodate the leakage. Fault Conditions: Overtemperature Protection At higher temperatures, or in cases where the internal power dissipation causes excessive self heating on chip, the overtemperature shutdown circuitry will shut down the LTC7862. When the junction temperature exceeds approximately 175°C , the overtemperature circuitry disables the DRV CC LDO, causing the DRV CC supply to collapse and effectively shutting down the entire LTC7862 chip. Once the junction temperature drops back to the approximately 155°C, the DRVCC LDO turns back on. Long term overstress (TJ > 150°C) should be avoided as it can degrade the performance or shorten the life of the part. Minimum On-Time Considerations Minimum on-time tON(MIN) is the smallest time duration that the LTC7862 is capable of turning on the top MOSFET . It is determined by internal timing delays and the gate charge required to turn on the top MOSFET . Low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUT VIN(f) If the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. The output voltage will continue to be regulated, but the ripple voltage and current will increase. The minimum on-time for the LTC7862 is approximately 80ns. However , as the peak sense voltage decreases the minimum on-time gradually increases up to about 130ns. If the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and volt- age ripple.
Rev 0 For more information www.analog.com Thermal Considerations The sustained or static power loss in normal pass-through operation must be limited to ensure suitable maximum component temperatures during all normal operating con- ditions. The temperature rise of a switching surge stopper is best measured empirically. Power loss for the pass- through power path is I 2RSW-ON and may be calculated according to the equation below. I2RSW-ON = I2 • (RSENSE + RDS(ON)(TOPMOSFET) + RINDUCTOR) The dynamic or transient power loss during switching operation is of concern with respect to component tem - perature rise and is principally managed by the timer func- tion which sets a maximum time in this mode. Thermal mass and thermal resistance play key roles in determining the peak temperatures of components at the point in time when the timer cycles off and shuts down. Worst-case operation for a single fault shorted output is typically with the input voltage in the high normal operat- ing range and the output shorted. For this condition, the bottom synchronous MOSFET is typically the hottest com- ponent, as it conducts nearly all the peak current at a high duty cycle. Worst-case operation for a single fault input voltage surge is with the input at the maximum expected input voltage and the maximum operational load current. An input voltage surge and output short is a double fault and may not be required. Specific fault testing and design margin is determined by system requirements. Thermal evaluation and timer setting can be most easily done empirically by observing key component tempera - tures dynamically in various fault conditions. Observe peak temperatures with an instrument with sufficient bandwidth to track temperatures, such as an infrared (IR) camera. One with video capability is ideal. Set a maximum temperature rise goal based on compo - nent maximum junction temperature ratings, maximum expected ambient temperature, and allowed junction to case temperature rise. Start at lower input voltages and/ or longer TMR timer settings and change after empirical system verification and measurement. APPLICATIONS INFORMATION Fault Timer (TMR) The LTC7862 is a switching surge stopper . The LTC7862 switches only during startup, during an overcurrent fault, and/or during an input overvoltage surge. The primary function of a switching surge stopper is to limit the output to a programmed maximum voltage during an input volt- age surge. Limiting the output voltage “surge stops” the input voltage surge and prevents it from propagating to the system and potentially causing damage. The switching surge stopper external components are typically optimized to minimize the total resistance in nor- mal (dropout) operation when the top MOSFET is on con- tinuously. The LTC7862’s fault timer is used to limit the time spent switching. The fault timer is programmed to allow the switching surge stopper components to operate within a safe temperature range with the increased power losses incurred during switching. Since the LTC7862 timer may stop switching before reaching thermal equilibrium, the power rating can be significantly increased compared to what could be achieved without a timer . Likewise, for a given output power rating, a smaller , cooler , and less costly solution can be achieved by using the timer . Connecting a capacitor from the TMR pin to ground sets the amount of time that the LTC7862 is allowed to switch. This same capacitor also sets a cooldown period before the LTC7862 is allowed to switch again. During normal operation, a 1.1µA current source pulls down on the TMR pin. While the LTC7862 is switching, a 40µA current source pulls up on the TMR pin. If the TMR pin is charged up to 2.19V, the LTC7862 stops switching with both external MOSFETs held off (TG and BG held low). This limits the switching time to: TSWITCHING = 2.19V • CTMR /40µA If the LTC7862 returns to normal operation before the timer reaches 2.19V, the 1.1µA pull-down current source discharges TMR, and the LTC7862 is allowed to switch immediately if conditions warrant.
Rev 0For more information www.analog.com APPLICATIONS INFORMATION If the timer reaches 2.19V, the LTC7862 is not allowed to switch again until TMR is discharged down to 0.25V by a 1.1µA current source. This sets a time period that permits the switching surge stopper components to cool down before attempting to switch again. This cooldown period is given by: TCOOLDOWN = (2.19V – 0.25V) • CTMR /1.1µA After this cooldown period, the LTC7862 may try to switch again. On this retry, the time spent switching is limited to TRETRY = 1.94V • CTMR /40µA During a sustained fault condition, this results in a retry duty cycle that is to first order independent of C TMR and is defined by: D = 100•TRETRY/(TCOOLDOWN + TRETRY) = 100•1/36.4 ≈ 2.7% Warning Indicator (WARNB) The WARNB pin is connected to the open drain of an internal N-channel MOSFET . The MOSFET turns on and pulls the WARNB pin low to ground (GND) whenever the LTC7862 is switching (i.e, not in dropout) during an over- voltage or overcurrent fault or during startup. The WARNB pin is also pulled low during shutdown and during the cooldown period after a fault timeout. The MOSFET is turned off and the WARNB pin enters a high-impedance state 60µs after the LTC7862 enters normal operation (dropout) with the top external MOSFET (TG) on con - tinuously. The WARNB pin is normally pulled up by an external resistor to a voltage source no greater than 6V. Checking T ransient Response The regulator loop response can be checked by looking at the load current transient response. Switching regula- tors take several cycles to respond to a step in DC (resis- tive) load current. When a load step occurs, V OUT shifts by an amount equal to ILOAD (ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT generating the feedback error signal that forces the regulator to adapt to the current change and return VOUT to its steady-state value. During this recovery time V OUT can be monitored for excessive overshoot or ringing, which would indicate a stability problem. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The availability of the ITH pin not only allows optimization of control loop behavior , but it also provides a DC coupled and AC filtered closed-loop response test point. The DC step, rise time and settling at this test point truly reflects the closed-loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the first page circuit will provide an adequate starting point for most applications. The ITH series R C-CC filter sets the dominant pole-zero loop compensation. The values can be modified slightly to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop gain and phase. An output current pulse of 20% to 80% of full-load current having a rise time of 1μs to 10μs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Placing a power MOSFET directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. The initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. This is why it is better to look at the ITH pin signal which is in the feedback loop and is the filtered and compensated control loop response. The gain of the loop will be increased by increasing RC and the bandwidth of the loop will be increased by decreas - ing CC. If R C is increased by the same factor that C C is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual over- all supply performance.
Rev 0 For more information www.analog.com APPLICATIONS INFORMATION A second, more severe transient is caused by switching in loads with large (>1μF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. If the ratio of CLOAD to COUT is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 • CLOAD. Thus a 10μF capacitor would require a 250μs rise time, limiting the charging current to about 200mA. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. 1. Are the signal and power grounds kept separate ? The combined IC signal ground pin and the ground return of C DRVCC must return to the combined C OUT (–) terminals. The path formed by the top N-channel MOSFET , bottom N-channel MOSFET and the C IN capacitor should have short leads and PC trace lengths. The output capacitor (– ) terminals should be connected as close as possible to the (–) terminals of the input capacitor by placing the capacitors next to each other . 2. Does the LTC7862 V FB pin’s resistive divider con- nect to the (+) terminal of COUT? The resistive divider must be connected between the (+) terminal of COUT and signal ground. The feedback resistor connections should not be along the high current input feeds from the input capacitor(s). 3. Are the SENSE – and SENSE + leads routed together with minimum PC trace spacing? The filter capacitor between SENSE + and SENSE– should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the SENSE resistor . 4. I s the DRV CC and decoupling capacitor connected close to the IC, between the DRV CC and the ground pin? This capacitor carries the MOSFET drivers’ cur- rent peaks. 5. K eep the SW , TG, and BOOST nodes away from sensi - tive small-signal nodes. All of these nodes have very large and fast moving signals and therefore should be kept on the output side of the LTC7862 and occupy minimum PC trace area. Use a modified star ground technique: a low imped- ance, large copper area central grounding point on the same side of the PC board as the input and output capacitors with tie-ins for the bottom of the DRV CC decoupling capacitor , the bottom of the voltage feed- back resistive divider and the GND pin of the IC. PC Board Layout Debugging It is helpful to use a DC- 50MHz current probe to moni - tor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchro- nize the oscilloscope to the internal oscillator and probe the actual output voltage as well. Check for proper per - formance over the operating voltage and current range expected in the application. The frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold. The duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise PCB imple - mentation. Variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or volt - age sensing inputs or inadequate loop compensation. Over compensation of the loop can be used to tame a poor PC layout if regulator bandwidth optimization is not required. Reduce V IN from its nominal level to verify operation of the regulator in dropout. Check the operation of the undervoltage lockout circuit by further lowering VIN while monitoring the output to verify operation. Investigate whether any problems exist only at higher out- put currents or only at higher input voltages. If problems coincide with high input voltages and low output currents, look for capacitive coupling between the BOOST , SW , TG, and possibly BG connections and the sensitive voltage and current pins. The capacitor placed across the current sensing pins needs to be placed immediately adjacent to
Rev 0For more information www.analog.com APPLICATIONS INFORMATION the pins of the IC. This capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. If problems are encountered with high current output loading at lower input voltages, look for inductive coupling between CIN, the top MOSFET and the bottom MOSFET to the sensitive current and voltage sensing traces. In addition, investigate common ground path voltage pickup between these components and the GND pin of the IC. An embarrassing problem, which can be missed in an otherwise properly working switching regulator , results when the current sensing leads are hooked up backwards. The output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized. Compensation of the voltage loop will be much more sensitive to component selection. This behavior can be investigated by temporarily shorting out the current sensing resistor—don’t worry, the regulator will still maintain control of the output voltage.
Figure 8. 8V to 100V Input, 34V Maximum 20A Output at 200kHz Figure 9. 8V to 140V Input, 34V Maximum 10A Output at 535kHz
7862 F08
7862 F09
Figure 10. 8V to 140V Input, 18V Maximum 10A Output at 535kHz Figure 11. 8V to 140V Input, 54V Maximum 5A Output at 535kHz with Reverse Input Protection
7862 F10
7862 F11
Rev 0 For more information www.analog.com PACKAGE DESCRIPTION Please refer to http://www.linear .com/product/LTC7862#packaging for the most recent package drawings. 20-Lead Plastic QFN (4mm × 5mm) (Reference L TC DWG # 05-08-1711 Rev B) 4.00 ±0.10 (2 SIDES)
1.50 REF
5.00 ±0.10 (2 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ±0.10 19 20 BOTTOM VIEW—EXPOSED PAD
2.50 REF
0.75 ±0.05 R = 0.115 TYP PIN 1 NOTCH R = 0.20 OR C = 0.35 0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05 (UFD20) QFN 0506 REV B RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 2.65 ±0.05 4.10 ±0.05 5.50 ±0.05 3.10 ±0.05 4.50 ±0.05 PACKAGE OUTLINE R = 0.05 TYP 2.65 ±0.10 3.65 ±0.10 3.65 ±0.05 20-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1711 Rev B)
Rev 0For more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION Please refer to http://www.linear .com/product/LTC7862#packaging for the most recent package drawings. FE20 (CB) TSSOP REV L 0117 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF RECOMMENDED SOLDER PAD LAYOUT 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 1 3 4 5 6 7 8 9 10 DETAIL A DETAIL A IS THE PART OF THE LEAD FRAME FEATURE FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 11 12 14 13 6.40 – 6.60* (.252 – .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 2.74 (.108) 0.45 ±0.05
0.65 BSC
4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 3.86 (.152) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev L) Exposed Pad Variation CB DETAIL A 0.60 (.024) REF 0.28 (.011) REF
Figure 12. 8V to 140V Input, 5A 535kHz Surge Stopper for 24V or 28V Systems