LTC7050 AD | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 16
Technical content
Rev. 0For more information www.analog.com Document Feedback TYPICAL APPLICATION FEATURES DESCRIPTION Dual SilentMOS Smart Power Stage in 5mm × 8mm LQFN The LT C®7050 dual monolithic power stage fully inte - grates high speed drivers with low resistance half-bridge power switches plus comprehensive monitoring and protection circuitry in an electrically and thermally opti - mized package. With a suitable high frequency control - ler , this power stage forms a compact, high current volt- age regulator system with state-of-the-art efficiency and transient response. SilentMOS technology utilizes second generation Silent Switcher 2 architecture reducing both EMI and switch- node voltage overshoot while maximizing efficiency at high switching frequencies. High speed current sensing provides low latency switch current information, enabling tight current balancing and immediate overcurrent protection. Thermally-enhanced packaging provides dual 40A rated continuous output current capability. 12VIN, 1V/70AOUT 1MHz Dual-Phase POL Converter Efficiency vs IOUT at 1MHz VSW Waveform at 1MHz n 70A Peak Output Current per Channel n SilentMOS™ Smart Power Stage n Utilizes Low EMI/EMC Silent Switcher®2 Architecture n Ultra-low SW-Voltage Overshoot n Frequency Up to 2MHz n VIN Up to 14V n Up to 94% Efficiency at 1MHz with 1.8VOUT n Integrated Boost Diodes and Capacitors n Accurate Switch Current Monitoring n Power MOSFET Overcurrent Protection n Input Overvoltage and Bias Undervoltage Protection n Thermal Monitor with Overtemperature Flag n 3.3V/5V Compatible T ri-State PWM Input n 5mm × 8mm LQFN Package
APPLICATIONS
n High Current Servers and Workstations n Networking/Telecom Microprocessor Supplies n Small Form-Factor POL Converter All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 9525351. VOUT PVCC 10/uni03A9 4.7nF 3.3nF 100pF 10µF 1µF 47pF
7050 TA01a
PINS NOT SHOWN IN L TC7050 CIRCUIT : TDIO, TMON/FL T PINS NOT SHOWN IN L TC3861 CIRCUIT : CLKIN, CONFIG, VSNSN2, VSNSOUT2, VSNSP2, CLKOUT , PHSMD, PGOOD1, PGOOD2, PWMEN1, PWMEN2 VINPVCCVCC PVCCVCC ISNS1 RUN1,2 SW2 VOUT 70A 2.61k 33.2/uni03A9 330µF 100µF PWM1 FL TB1,2 PWM2 ISNS2P ISNS2N ISNS1P L TC3861 ISNS1N RUN1 PWM1 RUN2 FREQ FB2 VCC VCC ILIM2 VSNSOUT1 FB1 COMP1, 2 VSNSP1 VIN 4.5V TO 14V VINSNS VSNSN1 ILIM1 SGNDSS1, 2 IAVG L TC7050 PGNDSGND 10µF ×10 180nH 180nH 33.2/uni03A9 1k 0.1µF 0.1µF 100pF 5.9k 10k 280/uni03A9 12k 50k 59k 10k L = L = VLBU9664100L T-R18L EFFICIENCY POWER LOSS INDUCTOR LOSS INCLUDED LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W)
7050 TA01b
V SW1 2V/DIV
7050 TA01c
VIN = 12V IOUT = 60A 12.5V
Rev. 0 For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS (Note 1) 212017 18 3742 3841 40 39 1916 LQFN PACKAGE 42-LEAD (8mm × 5mm × 0.95mm) TJ(MAX OPER) = 125°C, θJA = 10.8°C/W ON OPTIMIZED 6-LAYER 3.6 INCH × 2.8 INCH PCB EXPOSED PADS (VIN, PGND, SW) MUST BE SOLDERED TO PCB TOP VIEW VIN VIN VIN PGND PGND PGND SW1 SW2 VIN VIN PGND PGND PGND SW1SW2 PGND PGND PGND VIN VIN TDIO PWM1 FLTB1 ISNS1 RUN1 SGND VCC PVCC PVCC PGND RUN2 ISNS2 FLTB2 PWM2 TMON SW1 SW1 SW1 SW1 SW1 SW1 PGND PGND PGND SW2 SW2 SW2 SW2 SW2 SW2 ORDER INFORMATION PART NUMBER PART MARKING* FINISH CODE PAD FINISH PACKAGE TYPE MSL RATING TEMPERATURE RANGE LTC7050AV#PBF 7050 e4 Au (RoHS) LQFN (Laminate Package with QFN Footprint) 3 –40°C to 125°C
- Contact the factory for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609.
- *Device temperature grade is identified by a label on the shipping container .
- Recommended LGA and BGA PCB Assembly and Manufacturing Procedures
- LGA and BGA Package and Tray Drawings Parts ending with PBF are RoHS and WEEE compliant.
Rev. 0For more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Power Input Supply Range l 14 V VIN Overvoltage Lockout Threshold VIN Rising l 14.9 15.7 V VIN Overvoltage Lockout Hysteresis 0.4 V VIN Overvoltage Lockout Delay (Note 3) 1 µs VIN Shutdown Current VIN = 12V, RUN1 = RUN2 = 0 25 µA VCC VCC Input Supply Range l 4.5 5 5.5 V VCC(UVLO) VCC Undervoltage Lockout Threshold VCC Rising l 4.05 4.15 4.25 V VUVLO_HYST VCC Undervoltage Lockout Hysteresis 0.2 V IVCC(SD) VCC Supply Current in Shutdown RUN1 = RUN2 = 0V 14 µA IVCC_active VCC Supply Current in Active RUN1 = RUN2 = 5V, PWM = Float 2.5 mA PVCC Driver Input Supply Range l 4.5 5 5.5 V PVCC(UVLO) PVCC Undervoltage Lockout Threshold PVCC Rising l 3.9 4.0 4.1 V PVUVLO_HYST PVCC Undervoltage Lockout Hysteresis 0.35 V IPVCC(SD) PVCC Supply Current in Shutdown RUN1 = RUN2 = 0V 300 µA IPVCC_active PVCC and VCC Supply Current in Active RUN1 = RUN2 = 5V, PWM = Float 2.5 mA tUVLO Undervoltage Time Lockout Delay, from VCC and PVCC to SW Low PVCC, VCC Rising RUN = 5V PWM = 0 (Note 3) 1 µs RUN Input VIH_RUN RUN High Threshold RUN Rising l 2.2 2.45 2.7 V VRUN_HYS RUN Hysteresis 0.2 V RPD_RUN EN Pull-Down Resistor 30 kΩ Td_RUNH Propagation Delay for RUN Low to High From RUN Low ≥ High to SW = 0, PWM = 0 (Note 3) 12 µs Td_RUNL Propagation Delay for RUN High to Low From RUN High ≥ Low to SW High Z, PWM = 0 (Note 3) 0.1 µs PWM Input VIH_PWM PWM High Threshold l 2.7 V VIL_PWM PWM Low Threshold l 0.8 V VTR_PWM PWM Tri-State Range l 1.5 2.1 V VPWM_HYS PWM Hysterisis Active to Tri-State or Tri-State to Active 300 mV RPD_PWM PWM Pull-Down Resistor To SGND 9.6 kΩ RPU_PWM PWM Pull-Up Resistor To VCC 18.8 kΩ tPWMHI-SW Delay Time, PWM High to SW High No Fault Condition (Note 3) 10 ns tPWMLO-SW Delay Time, PWM Low to SW Low No Fault Condition(Note 3) 10 ns tTri_Lo_Delay Tri-State to Low Propagation Delay PWM Going Low to SW Going Low 20 ns tTri_Hi_Delay Tri-State to High Propagation Delay PWM Going High to SW Going High 30 ns tTri_Hold Active to Tri-State Delay Time PWM Going to High Z to SW High Z (Note 3) 20 ns tPWM_MINON PWM Minimum ON-Time 20 ns VPWM_FLOAT PWM Floating Voltage l 1.6 1.7 1.8 V The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, PVCC = VCC = 5V unless otherwise noted.
Rev. 0 For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, PVCC = VCC = 5V unless otherwise noted. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC7050A is specified over the –40°C to 125°C operating junction temperature range. High Junction temperatures degrade operating lifetimes. Note the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. The junction temperature (TJ, in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD • θJA) where θJA (in °C/W) is the package thermal impedance. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ISNS Output AIMON Current Sense Gain (IMON/IOUT) VISNS = 1.5V IOUT = 5A to 25A, PWM = 0 8.5 10 11.5 µA/A ISNS Overall Accuracy IOUT = 25A, VISNS = 1.5V, PWM = 0, Accuracy at Trim 250 ±12.5 µA IOUT = –10A, VISNS = 1.5V, PWM = 0 100 µA VIMON IMON Operational Voltage Range l 1.2 2.0 V FL TB Output RFL TB-PD Fault Bar Open-Drain Pull-Down Resistance FL TB Low 1 kΩ TMON/FL T Output ATMON Thermal Monitor Gain 0°C < TJ < 150°C (Note 3) 8 mV/°C VTMON Thermal Monitor Voltage TJ = 0°C (Note 3) 0.6 V TJ = 25°C 780 800 825 mV TJ = 125°C (Note 3) 1.6 V OTP Overtemperature Protection Accuracy (Note 3) 150 °C OTP_Hys Overtemperature Hysteresis (Note 3) 40 °C ISOURCE_TMON Thermal Monitor Maximum Source Current TJ = 25°C, TMON Forced at 0V 1 mA ISINK_TMON Thermal Monitor Maximum Sink Current TJ = 25°C, TMON Forced at 1.28V 60 µA VTdiode Tdiode Forward Voltage Drop TJ = 25°C, IF = 0.1mA 678 mV Tdiode Voltage Drop Temperature Coefficient IF = 0.1mA (Note 3) –1.8 mV/°C SW Node VSW_Float SW Floating Voltage VIN = 12V 0.7 V RSW-PGND SW Pull-Down Resistance 1.2 kΩ Overcurrent Limits I_OCP Positive Overcurrent Threshold PWM = H 80 90 100 A I_NCP Negative Overcurrent Threshold PWM = L –45 A tBlank_OC Positive Overcurrent Blanking Time PWM = H (Note 3) 22 nS tBlank_NC Negative Overcurrent Blanking Time PWM = L (Note 3) 55 nS I_ZCP Positive Zero Current Threshold 5 A I_ZCN Negative Zero Current Threshold –8 A Note 3: This parameter is not tested but is guaranteed by design. Note 4: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 5: The LTC7050 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS 12VIN to 1VOUT Efficiency 12VIN to 1.8VOUT Efficiency Power Dissipation vs Load T A = 25°C, VIN = 12V, PVCC = VCC = 5V unless otherwise noted. VSNS vs ILOAD VSNS vs Temperature VSNS vs VIN VSNS Gain vs VIN VSNS Gain vs Frequency VSNS Gain vs Temperature L = L = VLBU9664100L-R18L EFFICIENCY POWER LOSS 600kHz 1MHz LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W) IN OUT
7050 G01
L = L = VLBU9664100L T-R18L EFFICIENCY POWER LOSS INDUCTOR LOSS INCLUDED DUAL PHASE INTERLEAVING 600kHz 1MHz LOAD CURRENT (A) 100 EFFICIENCY (%) POWER LOSS (W) IN OUT
7050 G02
V IN = 12V V OUT = 1V L = L = 180nH fSW = 600kHz DUAL PHASE INTERLEAVING LOAD CURRENT (A) POWER LOSS (W) vs Load
7050 G03
V IN = 12V V OUT = 1V V SNS = I SNS × 100 I LOAD (A) –10 V SNS (mV)
7050 G04
TEMPERATURE (°C) –50 –25 100 125 150 V SNS (mV)
7050 G05
V IN = 12V V OUT = 1V LOAD = 25A V SNS = I SNS × 100 V IN = 12V V OUT = 1V LOAD = 25A V SNS = I SNS × 100 VIN (V) V SNS (mV)
7050 G06
V IN (V) 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 V SNS GAIN(mV/A)
7050 G07
V IN = 12V V OUT = 1V V SNS = I SNS × 100 FREQUENCY (MHz) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 9.0 9.2 9.4 9.6 9.8 10.0 10.2 10.4 10.6 10.8 V SNS GAIN (mV/A)
7050 G08
V IN = 12V V OUT = 1V V SNS = I SNS × 100 V IN = 12V V OUT = 1V V SNS = I SNS × 100 TEMPERATURE (°C) –50 –25 100 125 150 9.7 9.8 9.9 10.0 10.1 10.2 10.3 10.4 10.5 10.6 10.7 V SNS GAIN (mV/A)
7050 G09
Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS IPVCC vs FrequencyIVCC vs Frequency VCC UVLO vs Temperature PVCC UVLO vs Temperature PVIN OVLO vs Temperature Current Limit vs Temperature PWM Threshold vs Temperature V IN = 12V V OUT = 1V I LOAD = 25A, DUAL PHASE FREQUENCY (MHz) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.0 110 130 150 170 I PVCC (mA) PVCC
7050 G10
TEMPERATURE (°C) –50 –25 100 125 150 3.8 3.9 4.0 4.1 4.2 4.3 VCC VOL TAGE (V) vs Temperature
7050 G11
TEMPERATURE (°C) –50 –25 100 125 150 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 PVCC VOL TAGE (V)
7050 G12
TEMPERATURE (°C) –50 –25 100 125 150 14.1 14.3 14.5 14.7 14.9 15.1 15.3 15.5 15.7 PVIN VOL TAGE (V) vs Temperature
7050 G13
fSW = 1MHz TEMPERATURE (°C) 100 125 150 80.0 82.5 85.0 87.5 90.0 92.5 95.0 97.5 100.0 CURRENT LIMIT (A)
7050 G14
TEMPERATURE (°C) –50 –25 100 125 150 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 PWM THRESHOLD VOL TAGE (V) vs Temperature
7050 G15
T A = 25°C, VIN = 12V, PVCC = VCC = 5V unless otherwise noted. V IN = 12V V OUT = 1V I LOAD = 25A, DUAL PHASE FREQUENCY (MHz) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.0 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 I VCC (mA)
Rev. 0For more information www.analog.com RUN Threshold vs Temperature TDIO Forward Voltage TMON vs Temperature ON OFF TEMPERATURE (°C) –50 –25 100 125 2.0 2.1 2.2 2.3 2.4 2.5 RUN THRESHOLD (V) RUN Threshold vs Temperature
7050 G16
TEMPERATURE (°C) –50 –25 100 125 150 300 350 400 450 500 550 600 650 700 750 800 FORWARD VOL TAGE (mV) vs Temperature
7050 G17
TEMPERATURE (°C) –50 –25 100 125 200 400 600 800 1000 1200 1400 1600 TMON VOL TAGE (mV)
7050 G18
TYPICAL PERFORMANCE CHARACTERISTICS Overcurrent Protection Switching Rising Edge VSNS = ISNSx500 5µs/DIV
7050 G19
PVIN = 12V I LOAD = 60A, DUAL PHASE fSW =1MHz 5ns/DIV V SW1 2V/DIV
7050 G20
12.5V T A = 25°C, VIN = 12V, PVCC = VCC = 5V unless otherwise noted.
Rev. 0 For more information www.analog.com PIN FUNCTIONS RUN1, RUN2: Run Pin. When this pin is driven high, the is enabled. SW node is in high-Z state when RUN is low. PWM1, PWM2: PWM Input Pin. With RUN driven high, SW will nominally follow this pin high, low, and high-Z. Nominal 3V CMOS logic levels; can be driven with 3V to 5V CMOS signals. Resistor divider holds voltage at 1.7V when in high-Z state. ISNS1, ISNS2: Current Sense Pin. This pin sources/sinks instantaneous current equal to 1/100,000 the SW node current, positive and negative. F LTB1, FL TB2: Fault Bar Pin. This open-drain pin pulls down when the chip/channel encounters a fault condition such as OC or OCN. TMON/FL T: Temperature Monitor/Fault Pin. This pin pro- vides a voltage, referred to SGND, of 0.6V to 1.8V cor - responding to die temperature of 0°C to 150°C for a gain of 8mV/°C. Above 150°C, the pin is pulled high to indicate an overtemperature (OT) fault. The pin has limited current sinking capability, so multiple like pins can be tied together for highest temperature and single-OT-fault reporting. TDIO: Temperature Diode Pin. This pin provides a refer - ence diode to SGND for use in measuring die temperature. PVCC: 5V Driver Supply. This pin powers the low side gate driver directly and the high side gate driver through an internal bootstrapped supply riding on SW . Bypass this pin with a 10µF ceramic capacitor to PGND in close proximity to chip. VCC: 5V Supply. Bypass this pin with a 1µF ceramic capac- itor to SGND in close proximity to chip. VIN: Power Stage Supply. This pin is connected to SW through the high side N-channel FET . SW1, SW2: Power Stage Switch Node. The output of the power stage, this node is connected to V IN through the high side N-channel FET and to PGND through the low side N-channel FET . PGND: Power Stage Ground. This pin is connected to SW through the low side N-channel FET . Also powers the drivers. SGND: Circuit Ground.
Rev. 0For more information www.analog.com BLOCK DIAGRAM HG2 LG2 BST2 PVCC VIN LG2 PVCC 7050 BD VCC PWM1 18.8k RUN1 SDB1 ISNS2 SW2 PGND SGND TDIO FL TB2 FL TB1 ISNS1 PGND SW1 9.6k 2.4V PWMHI1 PWMLO1 CH1 LOGIC FAUL T LOGIC ISNS1 AMPS AND COMPARATORS 1.2V TMON/FL T VCC 60µA VCC 30k BIAS/SUPPL Y COMPARATORS BIAS TMON PWM2 18.8k RUN2 SDB2 SD2 SD1 9.6k 2.4V PWMHI2 PWMLO2 CH2 LOGIC 1.2V 30k HG1 LG1 PVCC VIN LG1 PVCC ISNS2 AMPS AND COMPARATORS BST1 1.2k 1.2k
states of the LTC7050 is illustrated in Figure 1. Figure 1. Three-State Input Operation
7050 F01
Figure 2. VTMON vs Die Temperature
7050 F02
diode as well as higher-frequency operation. detected by associated current comparators. responding to a die temperature range of 0°C to 150°C. temperature falls 20°C (typical) below the threshold. junction diode while the cathode is connected to SGND. die temperature using direct VBE method or ΔVBE method. to-SW voltage is recharged sufficiently.
overcurrent (OC) comparator and set the internal OC state. and PWMLO-to-low-side-FET operation resumes. are illustrated in Figure 3. In either OC or OCN condition, FL TB is pulled down. turn off until the current has been ramped down. Figure 3. Over Current Conditions
7050 F03
Table 1. Fault Management and Shutdown Mode Summary Overtemperature Low Yes Pull Up to VCC. that the gain ISNS/ISW remains constant. negative overcurrent protection.
7050 F04
Rev. 0For more information www.analog.com APPLICATIONS INFORMATION stage timing delays and the gate charge required to turn on the top FET . Low duty cycle applications may approach this minimum on-time limit (see Equation 1). tON(MIN) < VOUT VIN • fSW (1) Input Capacitors The LTC7050 should be connected to a VIN supply through low impedance power planes. Ceramic input capacitors should be placed as close to the package as physically possible, with size and quantity appropriate for tempera- ture rise with ripple current as calculated below. For a buck converter , the switching duty cycle can be esti- mated by Equation 2. D = VOUT VIN (2) Without considering the inductor ripple current, for each output, the RMS current of the input capacitor can be estimated by Equation 3. ICIN(RMS) = IOUT(MAX) η • D • 1–D( ) (3) where η is the estimated efficiency of the power section. Inductor Selection Given the desired input and output voltages, the inductor value and operating frequency, f SW, directly determine the inductor’s peak-to-peak ripple current (Equation 4). IRIPPLE = VOUT VIN VIN −VOUT fSW •L (4) Lower ripple current reduces core losses in the inductor , ESR losses in the output capacitors and output voltage ripple. Thus, highest efficiency operation is obtained at low frequency with a small ripple current. Achieving this, however , requires a large inductor . A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). Note that the largest ripple current occurs at the highest input voltage. To guarantee that ripple cur - rent does not exceed a specified maximum, the inductor should be chosen according to Equation 5. L ≥ VIN −VOUT fSW •IRIPPLE ⎠⎟•VOUT VIN (5) Once the inductance value is determined, the type of inductor must be selected. Core loss is independent of core size for a fixed inductor value, but it is very depen- dent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing sat- uration. Ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Output Capacitors The LTC7050 is designed for high frequency switching and low output voltage ripple noise. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output volt- age ripple and transient requirements. COUT can be a low ESR tantalum capacitor , a low ESR polymer capacitor , or ceramic capacitors. At 1MHz, the typical output capaci - tance range is from 500µF to 1000µF. Additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. Bypassing and Grounding The LTC7050 requires proper bypassing on the PV CC and VCC supplies due to its high speed switching (nano- seconds) and large AC currents (amperes). Careless component placement and PCB trace routing may cause excessive ringing and under/overshoot. Follow the fol - lowing steps to obtain the optimum performance from the LTC7050.
Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION Figure 5. (a) Schematic C12 C14 C11 C13 C10 PWM1 PWM2 RUN1 RUN2 I SNS1 I SNS2 FL TB1 FL TB2 PV CC V CC V IN SW1 SW2 VOUT L TC7050 SGND TDIO TMON V IN PGND PGND
7050 F4a
(b) Example PCB Layout
- Mount the bypass capacitors as close as possible between the V CC and SGND pins, and the PV CC and PGND pins. The traces should be shortened as much as possible to reduce lead inductance.
- Use a low inductance, low impedance ground plane to reduce any ground drop and stray capacitance. Any significant ground drop will degrade signal integrity.
- Plan the power/ground routing carefully. Know where the large load switching current is coming from and going to. Maintain separate ground return paths for the input pin and the output power stage.
- Be sure to solder the Exposed Pad on the back side of the LTC7050 packages to the board. Failure to make good thermal contact between the exposed back side and the copper board will result in far greater thermal resistances. PCB Layout Due to the LTC7050’s high power density and high speed, high frequency operation, proper PCB layout and compo- sition are critical to maximizing performance. At a minimum, the PCB should be 4-layer with at least top and bottom layers 2oz. copper . As much as possible, top and bottom layers should be continuous V IN and PGND areas. At least one inner layer , preferably the second, should be a continuous PGND plane. Copper-filled vias should be used under the package exposed pads to connect top and bottom PCB layers. θJCbottom is <1°C /W . Anything less than copper-filled vias will compromise θJA greatly. The inductor pads should be placed as close as possible to the package, with traces as short and wide as possible. If possible, SW traces should be doubled up with the second layer , taking care not to couple to sensitive traces. A recommended PCB layout is shown in Figure 5b.
Rev. 0For more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION 1.40 2.40 0.45 0.25 0.25 0.25 0.25 0.25 1.15 0.95 1.25 2.85 2.85 2.975 2.975 0.85 42-Lead (5mm × 8mm × 0.95mm) (Reference L TC DWG # 05-08-1571 Rev B) DETAIL B PACKAGE TOP VIEW X PACKAGE BOTTOM VIEW SEE NOTES E D b e e b 1.40 2.40 0.45 0.25 0.25 0.45 0.25 0.15 0.15 0.25 0.25 1.15 0.95 1.251.50 2.85 2.85 2.975 2.975 0.9 0.7 LQFN 42 1220 REV BPACKAGE IN TRAY LOADING ORIENTATION DETAIL B SUBSTRATE MOLD CAP // bbb Z Z DETAIL A DETAIL C SUGGESTED PCB LAYOUT TOP VIEW 0.000 0.000 0.50 0.50 1.00 1.00 1.50 1.50 2.00 2.00 3.50 3.00 2.50 3.50 2.50 3.00 1.50 0.50 2.00 1.00 1.00 37 42 21 16 aaa Z 2× M X YZccc MXY Z ccc PACKAGE OUTLINE
0.25 REF
0.70 REF
8.50 ±0.05 5.50 ±0.05 TRAY PIN 1 BEVEL COMPONENT PIN 1 L TXXXX A ddd Z 42× 42b e SYMBOL A L b D E e aaa bbb ddd eee fff MIN 0.85 0.30 0.22 NOM 0.95 0.40 0.25 5.00 8.00 0.50 1.05 0.03 0.50 0.28 0.10 0.10 0.10 0.15 0.08 NOTES SUBSTRATE THK MOLD CAP HT DIMENSIONS Z DETAIL C DETAIL A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. PRIMARY DATUM -Z- IS SEATING PLANE METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN SO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE
6 THE EXPOSED HEAT FEATURE IS SEGMENTED AND ARRANGED
IN A MATRIX FORMAT . IT MAY HAVE OPTIONAL CORNER RADII ON EACH SEGMENT MXY Z eee MZ fff L e/2 PIN 1 NOTCH 0.225 × 45° PIN 1 CORNER Y aaa Z2× 0.15 0.15 1.50 0.7 0.40
Rev. 0 For more information www.analog.com ANALOG DEVICES, INC. 2021 www.analog.com RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC7051 SilentMOS Smart Power Stage in 5mm × 8mm LQFN 140A Peak Current, Silent Switcher 2 Architecture, VIN Up to 14V, 5mm × 8mm LQFN Package LTC7050-1 Dual SilentMOS Smart Power Stage in 5mm × 8mm LQFN 70A Peak Current per Channel, Silent Switcher 2 Architecture, VIN Up to 16V, 5mm × 8mm LQFN Package LTC7051-1 SilentMOS Smart Power Stage in 5mm × 8mm LQFN 140A Peak Current, Silent Switcher 2 Architecture, VIN Up to 16V, 5mm × 8mm LQFN Package LTC3888/LTC3888-1 Dual Output 8-Phase Step-Down DC/DC Controller with Digital Power System Management 4.5V ≤ VIN ≤ 26.5V, 0.3V ≤ VOUT ≤ 3.45V, I2C/PMBus Control, Programmable Loop Compesation, 5mm × 8mm QFN-52 LTC3884/LTC3884-1 Dual Output PolyPhase Step-Down Controller with Sub- Milliohm DCR Sensing and Digital Power System Management 4.5V ≤ VIN ≤ 38V, 0.5V ≤ VOUT ≤ 5.5V, I2C/PMBus Control, Programmable Loop Compesation, 5mm × 8mm QFN-52 LTC7851 Quad Output Multiphase Step-Down Voltage Mode DC/DC Controller with Accurate Current Sharing Operates with DrMOS, Power Blocks or External Drivers/ MOSFETs, VIN Range Depends on External Components, 4.5V≤ VCC ≤ 5.5V, 0.6V ≤ VOUT ≤ VCC –0.5V LTC7852/LTC7252-1 Dual Output 6-Phase Current Mode Synchronous Buck Controller with Current Monitoring Operates with DrMOS, Power Blocks, 0.5V ≤ VOUT ≤ 2V, Hiccup Mode Overcurrent Protection, Flexible Phase Configuration LTC3861 Dual, Multiphase Step-Down Voltage Mode DC/DC Controller with Accurate Current Sharing Operates with Power Blocks, DrMOS or External MOSFETs 3V≤ VIN ≤ 24V LTC3882/LTC3882-1 Dual Output Multiphase Step-Down DC/DC Voltage Mode Controller with Digital Power System Management 3V ≤ VIN ≤ 38V, 0.5V ≤ VOUT1,2 ≤ 5.25V, ±0.5% VOUT Accuracy I2C/PMBus Interface, uses DrMOS or Power Blocks LTC3887/LTC3887-1 Dual Output Multiphase Step-Down DC/DC Controller with Digital Power System Management, 70mS Start-Up 4.5V ≤ VIN ≤ 24V, 0.5V ≤ VOUT0,1 (±0.5%) ≤ 5.5V, 70mS Start-Up, I2C/PMBus Interface, –1 Version uses DrMOS or Power Blocks TYPICAL APPLICATIONS LTC7050 and LTC3884-1 Schematic 470µF 1µF 215nH 215nH 10µF ×10 3.3nF 150k 43.2k 10pF 2.61k 1µF 3.3nF 150k 43.2k 10pF 10k 10k 6.8nF 100pF 10nF 1µF 10µF 4.7µF 47µF PWM1 V OUT1 1V/30A PWM2 RUN1 RUN2 I SENSE1 I SENSE2 FL TB1 FL TB2 PV CC V CC V IN SW1 SW2 V OUT2 1.8V/30A PINS NOT SHOWN IN L TC7050 CIRCUIT : TMON PINS NOT SHOWN IN L TC3884-1 CIRCUIT : PGOOD0, PGOOD1, TSNS1, SYNC, ASEL0, ASEL1, VOUT0_CFG, VOUT1_CFG, FREQ_CFG,PHASE_CFG L TC7050 PV CC PGND SGND V CC L1, L2: FP1007R3-R22-R V CC L TC3884-1 RUN0 PWM0 ISENSE0+ RUN1 ISENSE0– ISENSE1+ ISENSE1– INTV CC PWM1 VDD33 VDD33 PGND SGND TSNS0 TDIO V IN VDD33 SW1 SW2 V IN 7V TO 14V VSENSE0– VSENSE0+ VSENSE1– VSENSE1+ V OUT1 V OUT2 ITH ITH0 ITH1 ITH fSW: 575kHz INTV CC INTV CC SDA SCL ALERT PMBus INTERFACE FAUL T0 FAUL T1 47µF 470µF 6.8nF 100pF