LTM2810 AD | Alldatasheet
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Rev. AFor more information www.analog.com TYPICAL APPLICATION FEATURES DESCRIPTION 7.5kVRMS SPI/Digital or I2C µModule Isolator with Transformer Driver The LTM®2810 is a complete galvanic digital µModule ® (micromodule) isolator . No external components are required. Individual 3V to 5.5V supplies power each side of the digital isolator . Separate logic supply pins allow easy interfacing with different logic levels from 1.62V to 5.5V, independent of the main supply. Module options are available with compatibility to SPI (LTM2810-S) and I 2C (LTM2810-I), master mode only, specifications. The module includes an integrated transformer driver on the logic side and an LDO on the isolated side to regulate the rectified transformer output. The LDO output is nomi- nally 5V but may be overdriven. Coupled inductors provide 7500VRMS of isolation between the input and output logic interface. This device is ideal for systems with different ground potentials, allowing unin - terrupted communication through large common mode transients faster than 50kV/μs. Isolated 4MHz SPI Interface LTM2810-I Operating Through 70kV/µs CM T ransients
APPLICATIONS
n 6-Channel Logic Isolator: 7500VRMS for 1 Minute n 16.2mm Creepage n CSA (IEC/UL) Approved, File #255632 n 3V to 5.5V Supply Operation n T ransformer Driver with Integrated Isolated Side LDO n SPI/Digital (LTM2810-S) or I2C (LTM2810-I) Options n High Common Mode T ransient Immunity: 50kV/μs n High Speed Operation: n 10MHz Digital Isolation n 4MHz/8MHz SPI Isolation n 400kHz I2C Isolation n Operation Up to 125°C (H-Grade) n 1.62V to 5.5V Logic Supplies for Flexible Digital Interfacing n ±25kV ESD HBM Across the Isolation Barrier n Maximum Continuous Working Voltage: 1kVRMS, 1.6kVDC n Low Current Shutdown Mode (<10µA) n 22mm × 6.25mm × 2.06mm BGA Package n EV/HEV Systems n Industrial and Metering Systems n Test and Measurement Equipment n Medical Equipment All registered trademarks and trademarks are the property of their respective owners. Document Feedback
2810 TA01b
SCL2 = I1 DI1 ST2 ST1 VCC VL PVCC VIN ON DI2 DI3 DO1 DO1E O2N ON2 VL2 O2P SCK2 MOSI SS MISO SCK MOSI SS MISO GND L TM2810-S GND2 01E
2810 F01a
2.2µF
Rev. A For more information www.analog.com ABSOLUTE MAXIMUM RATINGS Supply Voltages Isolated Supply Voltages Logic Signals DI1, DI2, DI3, DO1, DO1E, DO2P , Isolated Signals AVL2, I1, I2, I3, O1, O1E, O2P , O3, ON2, Operating Temperature Range (Note 4) (Note 1) LTM2810-I LTM2810-S BGA PACKAGE 36-PIN (22mm × 6.25mm × 2.06mm) TJMAX = 125°C, JA = 49.6°C/W , JCBOTOM = 34°C/W , JCTOP = 26°C/W , JB = 33.7°C/W VALUES DETERMINED PER JESD51-9, WEIGHT = 0.5g TOP VIEW X W V U T S R P N M L K J H G F E D C B A 1 2 3 4 5 6 SDA2 GND2 ON2 VL2 O3 SCL2 AVL2 GND2 VIN DI3 SDA SCL DO3 GND DO1 PVCC ON VL ST1 GND VCC ST2 GND BGA PACKAGE 36-PIN (22mm × 6.25mm × 2.06mm) TJMAX = 125°C, JA = 49.6°C/W , JCBOTOM = 34°C/W , JCTOP = 26°C/W , JB = 33.7°C/W VALUES DETERMINED PER JESD51-9, WEIGHT = 0.5g TOP VIEW X W V U T S R P N M L K J H G F E D C B A 1 2 3 4 5 6 I3 I2 GND2 O1E GND2 ON2 VL2 O3 O2N O2P O1 AVL2 GND2 VIN DI3 DI2 DO2N DI1 DO3 DO2P DO1 PVCC ON VL ST1 GND DO1E VCC ST2 GND PIN CONFIGURATION
Rev. AFor more information www.analog.com ORDER INFORMATION
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Input Supplies Operating Voltage Range VCC, PVCC, VL (LTM2810-I), VL2 VL (LTM2810-S) VIN l l l 3.0 1.62 3.6 5.5 5.5 V V V VL2 Output Variation (Note 7) VL2 + 1V ≤ VIN ≤ 38V, ILOAD = 0 to 100mA l –0.2 0.2 V AVL2 Adjust Pin Voltage (Note 7) VL2 + 1V ≤ VIN ≤ 38V, ILOAD = 0 to 100mA l 580 600 620 mV Supply Current ICC, PICC, IL, ON = ON2 = 0V IVIN, VIN = 6V, ON2 = 0V ICC, PICC IVIN, VIN = 5V, VL2 Adjusted to 3V IL (LTM2810-S) IL (LTM2810-I) l l l l l 3.2 3.6 150 µA µA mA mA µA µA VL2 Current Limit VIN = 7V, VL2 = 0V VIN = VL2(NOMINAL) + 1V, ∆VL2 = –5% l 110 200 mA mA ST1, ST2 Output Current (Note 2) 400 mA Logic – DI1, DI2, DI3, DO1, DO1E, DO2N, DO2P , DO3, I1, I2, I3, O1, O1E, O2N, O2P , O3, ON, ON2 (VL = VL or VL2) VITH Input Threshold Voltage 1.62V ≤ VL < 2.35 l 0.25 • VL 0.75 • VL V 2.35V ≤ VL l 0.33 • VL 0.67 • VL V IIN Input Current l 0 ±5 µA VO Output Voltage ILOAD = 1mA, 1.62V ≤ VL < 3V ILOAD = 4mA, 3V ≤ VL DO1 (LTM2810-I), ILOAD = 2mA, 3V ≤ VL DO2N, ILOAD = 1mA, 1.62V ≤ VL < 3V DO2N, O2N, ILOAD = 4mA, 3V ≤ VL DO2P , ILOAD = 1mA, 1.62V ≤ VL < 3V DO2P , O2P , ILOAD = 4mA, 3V ≤ VL l l l l l l l 0.4 0.4 0.4 0.4 0.4 VL – 0.4 VL – 0.4 VL – 0.4 VL – 0.4 VL – 0.4 V V V V V V V Output High Resistance (Note 3) 40 Ω Output Low Resistance (Note 3) 40 Ω The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. PVCC = VCC = 5V, VL = VL2 = 3.3V, VIN = GND = GND2 = 0V, ON = VL, and ON2 = VL2 unless otherwise noted. Specifications apply to all options unless otherwise noted. LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTM2810CY-I#PBF LTM2810CY-I#PBF LTM2810Y-I 36-Lead (22mm × 6.25mm × 2.06mm) BGA 0°C to 70°C LTM2810IY-I#PBF LTM2810IY-I#PBF LTM2810Y-I 36-Lead (22mm × 6.25mm × 2.06mm) BGA –40°C to 85°C LTM2810HY-I#PBF LTM2810HY-I#PBF LTM2810Y-I 36-Lead (22mm × 6.25mm × 2.06mm) BGA –40°C to 125°C LTM2810CY-S#PBF LTM2810CY-S#PBF LTM2810Y-S 36-Lead (22mm × 6.25mm × 2.06mm) BGA 0°C to 70°C LTM2810IY-S#PBF LTM2810IY-S#PBF LTM2810Y-S 36-Lead (22mm × 6.25mm × 2.06mm) BGA –40°C to 85°C LTM2810HY-S#PBF LTM2810HY-S#PBF LTM2810Y-S 36-Lead (22mm × 6.25mm × 2.06mm) BGA –40°C to 125°C
- Device temperature grade is indicated by a label on the shipping container .
- Pad or ball finish code is per IPC/JEDEC J-STD-609.
- BGA Package and Tray Drawings
- This product is not recommended for second side reflow. This product is moisture sensitive. For more information, go to Recommended BGA PCB Assembly and Manufacturing Procedures.
Rev. A For more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I2C – SCL, SCL2, SDA, SDA2 (LTM2810-I) (VL = VL or VL2) VITH Input Threshold Voltage 3V ≤ VL ≤ 5.5V l 0.3 • VL 0.7 • VL V VHYS Input Hysteresis 3V ≤ VL ≤ 5.5V 0.05 • VL V IIN Input Current l 0 ±5 µA VO Output Voltage SCL2, ILOAD = 2mA, 3V ≤ VL ≤ 5.5V l 0.4 VL – 0.4 V VOL Output Low Voltage SDA, ILOAD = 3mA SDA2 = No Load, SDA = 0V, 4.5V ≤ VL < 5.5V SDA2 = No Load, SDA = 0V, 3V ≤ VL < 4.5V l l l 0.3 0.4 0.45 0.55 V V V SDA, SDA2 Slew Rate l 1 V/µs ISC Short-Circuit Current SDA2 = 0, SDA = VL 0V ≤ SCL2 ≤ VL SDA = 0, SDA2 = VL SDA = VL, SDA2 = 0 l ±30 –1.8 100 mA mA mA mA ESD (HBM) (Note 2) Isolation Boundary (VIN, VL2, GND2) to (PVCC, VCC, VL, GND) in Any Combination ±25 kV SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Driver – ST1, ST2 Drive Frequency 2 MHz Duty Cycle 49 50 51 % Power Supply Generator VL2 Supply Start-Up Time VIN to VL2 > 4.75V 50 ms Logic Timing Maximum Data Rate Input Output, CL = 15pF (Note 3) Bidirectional SPI Communication Unidirectional SPI Communication l l l MHz MHz MHz tPHL, tPLH Propagation Delay Input Output, CL = 15pF (Figure 1) l 30 45 100 ns tPZH, tPZL DO1, O1 Enable Time (Figure 2) xO1E = to xO1 High, RPD = 1kΩ, xI1 = High l 50 ns ONx Enable Time (Figure 4) ONx = to xOx High, RPD = 1kΩ, xIx = High l 60 μs tPHZ, tPLZ DO1, O1 Disable Time (Figure 2) xO1E = to xO1 Low, RPD = 1kΩ, xI1 = High l 50 ns ONx Disable Time (Figure 4) ONx = to xOx Low, RPD = 1kΩ, xIx = High l 100 ns I2C Timing Maximum Data Rate (Note 3) l 400 kHz tPHL, tPLH Propagation Delay (Figure 3) SCL SCL2 SDA SDA2 SDA2 SDA, RPU = 1kΩ l l l 150 150 300 250 300 500 ns ns ns tR Rise Time (30% to 70%) (Figure 3) SDA2, CL = 200pF SDA, RPU = 1kΩ, CL = 200pF SCL2, CL = 200pF l l l 350 350 250 ns ns ns tF Fall Time (70% to 30%) (Figure 3) SDA2, CL = 200pF SDA, RPU = 1kΩ, CL = 200pF SCL2, CL = 200pF l l l 250 250 250 ns ns ns The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. PVCC = VCC = 5V, VL = VL2 = 3.3V, VIN = GND = GND2 = 0V, ON = VL, and ON2 = VL2 unless otherwise noted. Specifications apply to all options unless otherwise noted. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. PVCC = VCC = 5V, VL = VL2 = 3.3V, VIN = GND = GND2 = 0V, ON = VL, and ON2 = VL2 unless otherwise noted. Specifications apply to all options unless otherwise noted.
Rev. AFor more information www.analog.com SWITCHING CHARACTERISTICS ISOLATION CHARACTERISTICS REGULATORY INFORMATION SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tPZH, tPZL ONx Enable Time ON = to SDA Low, RPU = 1kΩ, SDA2 = 0V ON2 = to (SCL2, SDA2) Low, (SCL, SDA) = 0V l l μs μs tPHZ, tPLZ ONx Disable Time ON = to SDA High, RPU = 1kΩ, SDA2 = 0V ON2 = to SCL2 High, SCL = 0V ON2 = to SDA2 High, SDA = 0V l l l 225 ns ns ns tSP Pulse Width of Spikes Suppressed by Input Filter l 0 50 ns SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VISO Rated Dielectric Insulation Voltage 1 Minute, Derived from 1 Second Test
1 Second (Notes 5, 6)
Common Mode T ransient Immunity PVCC = VCC = VL = ON = 5V, VL2 = ON2 = 5V VCM = 1kV, ∆t = 20ns (Note 2) 50 75 kV/µs VIORM Maximum Continuous Working Voltage (Notes 2, 5) 1600 1000 VDC VRMS Partial Discharge VPD = 2650VPEAK (Note 5) 5 pC CTI Comparative T racking Index IEC 60112 (Note 2), Material Group I 600 VRMS Depth of Erosion IEC 60112 (Note 2) 0.017 mm DTI Distance Through Insulation (Note 2) 0.2 mm Input to Output Resistance (Notes 2, 5) 1 5 TΩ Input to Output Capacitance (Notes 2, 5) 2 pF Creepage Distance (Note 2) 16.2 mm CSA (Note 8) CSA 60950-1-07+A1+A2 and IEC 60950-1, second edition, +A1 +A2: Basic Insulation at 1600VRMS Reinforced Insulation at 800VRMS CSA 62368-1-14 and IEC 62368-1-14:2014, second edition: Basic Insulation at 1600VRMS Reinforced Insulation at 800VRMS CSA 60601-1:14 and IEC 60601-1, third edition, +A1: T wo means of patient protection (2 MOPP) at 500VRMS UL 1577-2015: Single Protection, 7500VRMS Isolation Voltage File 255632 The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. PVCC = VCC = 5V, VL = VL2 = 3.3V, VIN = GND = GND2 = 0V, ON = VL, and ON2 = VL2 unless otherwise noted. Specifications apply to all options unless otherwise noted. T A = 25°C.
Rev. A For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS PVCC Supply Current vs Temperature VCC Supply Current vs Temperature VL Supply Current vs Temperature T A = 25°C, PVCC = VCC = 5V, VL = VL2 = 3.3V, GND = GND2 = 0V, ON = VL, and ON2 = VL2, unless otherwise noted. VIN Supply Current vs Temperature Logic Input Threshold vs VL Supply Voltage Logic Output Voltage vs Load Current VLx SUPPL Y VOL TAGE (V) THRESHOLD VOL TAGE (V) 3.5 2.5 0.5 1.0 2.0 3.0 1.5 4 52
2810 G05
|LOAD CURRENT| (mA) OUTPUT VOL TAGE (V) 21 3
2810 G06
VLx = 5.5V VLx = 3.3V VLx = 1.62V PV CC = 3V PV CC = 3.3V PV CC = 3.6V PV CC = 4.5V PV CC = 5V PV CC = 5.5V TEMPERATURE (°C) –50 –25 100 125 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 CURRENT (mA)
2810 G01
V CC = 3.3V V CC = 5V TEMPERATURE (°C) –50 –25 100 125 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 CURRENT (mA)
2810 G02
V L = 3.3V V L = 5V TEMPERATURE (°C) –50 –25 100 125 100 110 120 130 140 150 160 170 180 190 200 CURRENT (µA)
2810 G03
V IN = 4V V IN = 38V TEMPERATURE (°C) –50 –25 100 125 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 CURRENT (mA)
2810 G04
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Guaranteed by design and not subject to production test. Note 3: Guaranteed by other measured parameters and is not tested directly. Note 4: This µModule isolator includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above specified maximum operating junction temperature may result in device degradation or failure. Note 5: Device is considered a 2-terminal device. Pin group A1 through C6 shorted together and pin group V1 through X6 shorted together . Note 6: The rated dielectric insulation voltage should not be interpreted as a continuous voltage rating. Note 7: Maximum junction temperature limits operating conditions. The regulated output voltage specification does not apply for all possible combinations of input voltage and output current. Limit the output current range if operating at the maximum input-to-output voltage differential. Limit the input-to-output voltage differential if operating at maximum output current. Current limit foldback will limit the maximum output current as a function of input-to-output voltage. Note 8: Ratings are for pollution degree 2, material group 3 and overvoltage category II where applicable. Ratings for other environmental and electrical conditions to be determined from the appropriate safety standard.
Rev. AFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS T A = 25°C, PVCC = VCC = 5V, VL = VL2 = 3.3V, GND = GND2 = 0V, ON = VL, and ON2 = VL2, unless otherwise noted. SDA Low Level Output Voltage vs Temperature SDA2 Low Level Output Voltage vs Temperature Supply Current vs Data Rate, All Channels ST1 and ST2 Current Limit vs Temperature Histogram VL2 T ransient Response Thermal Derating ST1 and ST2 Current Limit vs Temperature Histogram TEMPERATURE (°C) –50 OUTPUT VOL TAGE (V) 0.5 0.4 0.3 0.2 0.1 500 100
2810 G07
12525–25 75 L TM2810-I SDA RPU = 1.1k VL = 3.3V VL = 5V TEMPERATURE (°C) –50 OUTPUT VOL TAGE (V) 0.5 0.4 0.3 0.2 0.1 500 100
2810 G08
12525–25 75 L TM2810-I VL2 = 3.3V VL2 = 5V I L AT V L = 3.3V I CC AT V CC = 3.3V or 5V I AT V = 3.3V I L AT V L = 5V I AT V = 5V FREQUENCY (Hz) 10k 100k 10M CURRENT (mA)
2810 G09
= 5V 130°C 25°C –60°C CURRENT LIMIT (mA) 350 375 400 425 450 475 500 525 550 575 600 DISTRIBUTION (%)
2810 G10
= 3.3V 130°C 25°C –60°C CURRENT LIMIT (mA) 500 540 580 620 660 700 740 780 820 860 900 DISTRIBUTION (%)
2810 G11
V IN = 6V 50µs/DIV V 50mV/DIV I LOAD 50mA/DIV
2810 G12
AMBIENT TEMPERATURE (°C) 100 125 150 0.5 1.0 1.5 2.0 2.5 3.0 POWER DISSIPATION (W)
2810 G13
INTERNAL OPERATING TEMPERATURE θ JA = 50°C/W
Rev. A For more information www.analog.com PIN FUNCTIONS LTM2810-S, Logic Side DI3 (A1): Digital Input, Referenced to VL and GND. Logic input connected to O3 through the isolation barrier . The logic state on DI3 translates to the same logic state on O3. Connect to GND or VL if not used. DI2 (A2): Digital Input, Referenced to VL and GND. Logic input connected to O2N and O2P through the isolation barrier . The logic state on DI2 translates to the same logic state on O2N and O2P . Connect to GND or VL if not used. DI1 (A3): Digital Input, Referenced to VL and GND. Logic input connected to O1 through the isolation barrier . The logic state on DI1 translates to the same logic state on O1. Connect to GND or VL if not used. ON (A4): Enable, Referenced to VL and GND. Enables data communication through the isolation barrier . If ON is high the part is enabled and communications are functional to the isolated side. If ON is low the logic side is held in reset, all digital outputs are in a high impedance state. Connect to VL if not driven. VL (A5): Logic Supply. Interface supply voltage for pins DI1, DI2, DI3, DO1, DO2P , DO3, DO1E, and ON. Operating voltage is 1.62V to 5.5V. Internally bypassed with 1μF. ST1, ST2 (A6, C6): Bridge Driver Outputs, Referenced to PVCC and GND. Each output runs at 50% duty cycle, ST1 is 180 degrees out of phase with ST2. Operating frequency is 2MHz. Bridge driver is enabled when PV CC is between 3V to 5.5V and ON is high. DO3 (B1) : Digital Output, Referenced to V L and GND. Logic output connected to I3 through the isolation bar - rier . Under the condition of an isolation communication failure this output is in a high impedance state. DO2N (B2): Open Drain Pull-Down Output to GND. Logic output connected to I2 through the isolation barrier . Under the condition of an isolation communication failure this output is in a high impedance state. DO2P (B3): Open Drain Pull-Up Output to VL. Logic out- put connected to I2 through the isolation barrier . Under the condition of an isolation communication failure this output is in a high impedance state. DO1 (B4) : Digital Output, Referenced to V L and GND. Logic output connected to I1 through the isolation bar - rier . Under the condition of an isolation communication failure this output is in a high impedance state. PVCC (B5): Bridge Driver Supply Voltage. Operating volt- age is 3V to 5.5V, connect to GND to disable bridge driver . Internally bypassed with 2.2μF. DO1E (C4): Digital Output Enable, Referenced to V L and GND. A logic high on DO1E places the logic side DO1 pin in a high impedance state, a logic low enables the output. Connect to GND or VL if not used. VCC (C5): Supply Voltage. Operating voltage is 3V to 5.5V. Internally bypassed with 1μF. GND (B6, C1 to C3): Circuit Ground. LTM2810-S, Isolated Side O1E (V4): Digital Output Enable, Referenced to V L2 and GND2. A logic high on O1E places the isolated side O1 pin in a high impedance state, a logic low enables the output. Connect to GND2 or VL2 if not used. VIN (V6): Internal LDO Input Voltage. Operating voltage is 3.6V to 38V. Internally bypassed with 0.1μF. O3 (W1): Digital Output, Referenced to V L2 and GND2. Logic output connected to DI3 through the isolation bar- rier . Under the condition of an isolation communication failure O3 defaults to a high state. O2N (W2): Open Drain Pull-Down Output to GND2. Logic output connected to DI2 through the isolation barrier . Under the condition of an isolation communication failure O2N defaults to a low state. O2P (W3): Open Drain Pull-Up Output to VL2. Logic out- put connected to DI2 through the isolation barrier . Under the condition of an isolation communication failure O2P defaults to a low state. O1 (W4): Digital Output, Referenced to V L2 and GND2. Logic output connected to DI1 through the isolation bar- rier . Under the condition of an isolation communication failure O1 defaults to a low state. AVL2 (W5): VL2 LDO Adjust Pin.
Rev. AFor more information www.analog.com PIN FUNCTIONS I3 (X1): Digital Input, Referenced to VL2 and GND2. Logic input connected to DO3 through the isolation barrier . The logic state on I3 translates to the same logic state on DO3. Connect to GND2 or VL2 if not used. I2 (X2): Digital Input, Referenced to VL2 and GND2. Logic input connected to DO2N and DO2P through the isolation barrier . The logic state on I2 translates to the same logic state on DO2N and DO2P . Connect to GND2 or VL2 if not used. I1 (X3): Digital Input, Referenced to VL2 and GND2. Logic input connected to DO1 through the isolation barrier . The logic state on I1 translates to the same logic state on DO1. Connect to GND2 or VL2 if not used. ON2 (X4): Enable, Referenced to VL2 and GND2. Enables data communication through the isolation barrier . If ON2 is high the part is enabled and communications are func- tional to the logic side. If ON2 is low the isolated side is held in reset, O1, O2N and O2P are in a low state, and O3 is in a high state. Connect to VL2 if not driven. VL2 (X5, X6): Logic Supply, Referred to GND2. Interface supply voltage for pins O1, O2P , O3, I1, I2, I3, O1E, and ON2. Operating voltage is 3V to 5.5V. Internally bypassed with 6.6μF. GND2 (V1 to V3, V5, W6): Isolated Ground. LTM2810-I, Logic Side DI3 (A1): Digital Input, Referenced to VL and GND. Logic input connected to O3 through the isolation barrier . The logic state on DI3 translates to the same logic state on O3. Connect to GND or VL if not used. SDA (A2, B2): Serial I2C Data Pins, Referenced to VL and GND. Bidirectional logic pins connected to isolated side SDA2 pins through the isolation barrier . Under the condi- tion of an isolation communication failure pins are in a high impedance state. Pull up to VL if not used. SCL (A3): Serial I 2C Clock Input, Referenced to V L and GND. Logic input connected to isolated side SCL2 pin through the isolation barrier . Clock is unidirectional from logic to isolated side. Pull up to VL if not used. ON (A4): Enable, Referenced to VL and GND. Enables data communication through the isolation barrier . If ON is high the part is enabled and communications are functional to the isolated side. If ON is low the logic side is held in reset, all digital outputs are in a high impedance state. Connect to VL if not driven. VL (A5): Logic Supply. Interface supply voltage for pins SCL, DI3, DO1, DO3, and ON. Operating voltage is 3V to 5.5V. Internally bypassed with 1μF. ST1, ST2 (A6, C6): Bridge Driver Outputs, Referenced to PVCC and GND. Each output runs at 50% duty cycle, ST1 is 180 degrees out of phase with ST2. Operating frequency is 2MHz. Bridge driver is enabled when PV CC is between 3V to 5.5V and ON is high. DO3 (B1) : Digital Output, Referenced to V L and GND. Logic output connected to I3 through the isolation bar - rier . Under the condition of an isolation communication failure this output is in a high impedance state. DO1 (B4) : Digital Output, Referenced to V L and GND. Logic output connected to I1 through the isolation bar - rier . Under the condition of an isolation communication failure this output is in a high impedance state. PVCC (B5): Bridge Driver Supply Voltage. Operating volt- age is 3V to 5.5V, connect to GND to disable bridge driver . Internally bypassed with 2.2μF. VCC (C5): Supply Voltage. Operating voltage is 3V to 5.5V. Internally bypassed with 1μF. GND (B3, B6, C1 to C4): Circuit Ground. LTM2810-I, Isolated Side VIN (V6): Internal LDO Input Voltage. Operating voltage is 3.6V to 38V. Bypassed with 0.1μF. O3 (W1): Digital Output, Referenced to V L2 and GND2. Logic output connected to DI3 through the isolation bar- rier . Under the condition of an isolation communication failure O3 defaults to a high state. SDA2 (W2, W3, X2): Serial I 2C Data Pins, Referenced to VL2 and GND2. Bidirectional logic pins connected to logic side SDA pins through the isolation barrier . Output is biased high by a 1.8mA current source. Do not connect
Rev. A For more information www.analog.com PIN FUNCTIONS an external pull-up device to SDA2. Under the condition of an isolation communication failure outputs default to a high state. Pins connected internally. SCL2 (W4): Serial I 2C Clock Output, Referenced to V L2 and GND2. Logic output connected to logic side SCL pin through the isolation barrier . Clock is unidirectional from logic to isolated side. SCL2 has a push-pull output stage; do not connect an external pull-up device. Under the con- dition of an isolation communication failure this output defaults to a high state. AVL2 (W5): VL2 LDO Adjust Pin. I3 (X1): Digital Input, Referenced to VL2 and GND2. Logic input connected to DO3 through the isolation barrier . The logic state on I3 translates to the same logic state on DO3. Connect to GND2 or VL2 if not used. I1 (X3): Digital Input, Referenced to VL2 and GND2. Logic input connected to DO1 through the isolation barrier . The logic state on I1 translates to the same logic state on DO1. Connect to GND2 or VL2 if not used. ON2 (X4): Enable, Referenced to VL2 and GND2. Enables data communication through the isolation barrier . If ON2 is high the part is enabled and communications are func- tional to the logic side. If ON2 is low the isolated side is held in reset, all digital outputs are in a high state. Connect to VL2 if not driven. VL2 (X5, X6): Logic Supply, Referred to GND2. Interface supply voltage for pins SCL2, SDA2, I1, I3, O3, and ON2. Operating voltage is 3V to 5.5V. Internally bypassed with 6.6μF. GND2 (W6, V1 to V5): Isolated Ground.
Rev. AFor more information www.analog.com BLOCK DIAGRAM LTM2810-S GND2 10nF VINST1 ST2 AVL2 VL2 3.3VOUT REG ISOLATED COMMUNICATIONS INTERFACE 6.6µF PVCC ON VL GND VCC PVCC DI1 DI2 DI3 DO1E DO1 DO2P D02N D03 0.1µF 2.2µF O1E ON2 VL VCC O2N O2P
2810 BD-S
2.2µF 1µF 1µF 13K 56.2K
Rev. A For more information www.analog.com BLOCK DIAGRAM LTM2810-I GND2 10nF VINST1 ST2 AVL2 VL2 5VOUT REG ISOLATED COMMUNICATIONS INTERFACE 6.6µF PVCC ON VL GND VCC PVCC SCL SDA DI3 DO1 D03 0.1µF 2.2µF ON2 VL VCC SCL2 SDA2
2810 BD-I
2.2µF 1µF 1µF
Figure 1. Logic Timing Measurements Figure 2. Logic Enable/Disable Time
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Figure 3. I2C Timing Measurements Figure 4. ONx Enable/Disable Time
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Figure 5. Supplies are Independent networks where grounds can take on different voltages. as fast as 50kV/μs providing excellent noise isolation. internally with a 1µF ceramic capacitor . is bypassed internally with a 2.2µF ceramic capacitor . left unconnected if VL2 is driven by an external supply. of the SPI/Digital version, as shown in Figure 5.
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There is no interdependency between VCC, VL, and PVCC. specified operating ranges and may sequence in any order . VL2 is bypassed internally by a 6.6µF ceramic capacitor . options for the isolation transformer and rectifier topology. illustrated by Figures 14 to 18. is no jitter on the associated output channels, only delay. pulse width uncertainty, and data direction requirements. clock phase (CPHA) summarized in Table 1. Table 1. SPI Mode
Rev. AFor more information www.analog.com APPLICATIONS INFORMATION The maximum data rate for bidirectional communication is 4MHz, based on a synchronous system, as detailed in the timing waveforms. Slightly higher data rates may be achieved by skewing the clock duty cycle and minimizing the DO1 (SDO) to DI1 (SCK) setup time, however the clock rate is still dominated by the system propagation delays. A discussion of the critical timing paths relative to Figure 6 and Figure 7 follows. For SPI communication DI1 = SCK, DI2 = SDI, DI3 = CS, DO1 = SDO, O1 = SCK2, O2N and O2P = SDI2, O3 = CS2, and I1 = SDO2.
- CS to SCK (master sample SDO, 1st SDO valid) t0 → t1 ≈ 50ns, CS to CS2 propagation delay t1 → t1+ Isolated slave device propagation (response time), asserts SDO2 t1 → t3 ≈ 50ns, SDO2 to SDO propagation delay t3 → t5 Setup time for master SDO to SCK
- SDI to SCK (master data write to slave) t2 → t4 ≈ 50ns, SDI to SDI2 propagation delay t5 → t6 ≈ 50ns, SCK to SCK2 propagation delay t2 → t5 ≥ 50ns, SDI to SCK, separate packet non-zero setup time t4 → t6 ≥ 50ns, SDI2 to SCK2, separate packet non- zero setup time
- SDO to SCK (master sample SDO, subsequent SDO valid) t8 Setup data transition SDI and SCK t8 → t10 ≈ 50ns, SDI to SDI2 and SCK to SCK2 propagation delay t10 SDO2 data transition in response to SCK2 t10 → t11 ≈ 50ns, SDO2 to SDO propagation delay t11 → t12 Setup time for master SDO to SCK Maximum data rate for single direction communication, master to slave, is 8MHz, limited by the systems encod- ing/decoding scheme or propagation delay. Timing details for both variations of clock phase are shown in Figure 8, Figure 9, and Table 3. Additional requirements to insure maximum data rate are:
- CS is transmitted prior to (asynchronous) or within the same (synchronous) data packet as SDI
- SDI and SCK setup data transition occur within the same data packet. Referencing Figure 6, SDI can precede SCK by up to 13ns (t 7 → t8) or lag SCK by 3ns (t 8 → t9) and not violate this requirement. Similarly in Figure 8, SDI can precede SCK by up to 13ns (t 4 → t5) or lag SCK by 3ns (t5 → t6).
Figure 7. SPI Timing, Bidirectional, CPHA = 1 Figure 6. SPI Timing Bidirectional, CPHA = 0
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Table 2. Bidirectional SPI Timing Event Description output enabled, initial data is not equivalent to slave device data output. t0, t1, t17, t18 0, 1 Propagation delay chip select, logic to isolated side, 50ns typical. t1 0, 1 Slave device chip select output data enable. t2 0 Start of data transmission, data setup. 1 Start of transmission, data and clock setup. Data transition must be within –13ns to 3ns of clock edge. t1 to t3 0, 1 Propagation delay of slave data, isolated to logic side, 50ns typical. t3 0, 1 Slave data output valid, logic side. t2 to t4 0 Propagation delay of data, logic side to isolated side. 1 Propagation delay of data and clock, logic side to isolated side. t5 0, 1 Logic side data sample time, half clock period delay from data setup transition. t5, t6 0, 1 Propagation delay of clock, logic to isolated side. t6 0, 1 Isolated side data sample time. t8 0, 1 Synchronous data and clock transition, logic side. t7, t8 0, 1 Data to clock delay, must be ≤ 13ns. t8, t9 0, 1 Clock to data delay, must be ≤ 3ns. t8, t10 0, 1 Propagation delay clock and data, logic to isolated side. t10, t14 0, 1 Slave device data transition. t10, t11, t14, t15 0, 1 Propagation delay slave data, isolated to logic side. t11, t12 0, 1 Slave data output to sample clock setup time. t13 0 Last data and clock transition logic side. 1 Last sample clock transition logic side. t13, t14 0 Propagation delay data and clock, logic to isolated side. 1 Propagation delay clock, logic to isolated side. t15 0 Last slave data output transition logic side. 1 Last slave data output and data transition, logic side. t15, t16 1 Propagation delay data, logic to isolated side. t17 0, 1 Asynchronous chip select transition, end of transmission. Disable slave data output logic side. t18 0, 1 Chip select transition isolated side, slave data output disabled.
Figure 8. SPI Timing, Unidirectional, CPHA = 0 Figure 9. SPI Timing, Unidirectional, CPHA = 1
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Table 3. Unidirectional SPI Timing Event Description t0 0, 1 Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns. t0, t1 0, 1 Propagation delay chip select, logic to isolated side. t2 0 Start of data transmission, data setup. 1 Start of transmission, data and clock setup. Data transition must be within –13ns to 3ns of clock edge. t2, t3 0 Propagation delay of data, logic side to isolated side. 1 Propagation delay of data and clock, logic side to isolated side. t3 0, 1 Logic side data sample time, half clock period delay from data setup transition. t3 to t5 0, 1 Clock propagation delay, clock and data transition. t4, t5 0, 1 Data to clock delay, must be ≤ 13ns. t5, t6 0, 1 Clock to data delay, must be ≤ 3ns. t5 to t7 0, 1 Data and clock propagation delay. t8 0 Last clock and data transition. t8, t9 0 Clock and data propagation delay. t9, t10 1 Data propagation delay. t11 0, 1 Asynchronous chip select transition, end of transmission. t12 0, 1 Chip select transition isolated side.
greater than 400pF in standard mode. be greater than 1V/μs for proper operation. Figure 10. I2C Timing Diagram Figure 11. Isolated SDA2 Pin Schematic
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the left of the appropriate curve. output driver; do not connect an external pull-up device. SCL2 pin to reduce noise injection onto SDA2.
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Figure 12. Maximum Standard Speed Pull-Up Resistance on SDA Figure 13. Maximum Fast Speed Pull-Up Resistance on SDA
signed per the data sheet PCB layout recommendations. Specific limits per test are detailed in Table 4. Table 4. EMC Immunity Tests
- Input and output supply decoupling is not required, since these components are integrated within the pack- age. An additional bulk capacitor with a value of 6.8µF to 22µF with 1Ω to 3Ω of ESR is recommended. The high ESR of this capacitor reduces board resonances and minimizes voltage spikes caused by hot plugging of the supply voltage. For EMI sensitive applications, an additional low ESL ceramic capacitor of 1µF to 4.7µF, placed as close to the power and ground terminals as possible, is recommended. Alternatively, a number of smaller value parallel capacitors may be used to reduce ESL and achieve the same net capacitance.
- Do not place copper on the PCB between the inner col- umns of pads. This area must remain open to withstand the rated isolation voltage.
- The use of solid ground planes for GND and GND2 is recommended for non-EMI critical applications to optimize signal fidelity, and minimize RF emissions due to uncoupled PCB trace conduction. The drawback of using ground planes where EMI is of concern, is the creation of a dipole antenna structure which can radiate differential voltages formed between GND and GND2. If ground planes are used, it is recommended to minimize their area, and use contiguous planes as any openings or splits can exacerbate RF emissions.
- For large ground planes a small capacitance (≤ 330pF) from GND to GND2, either discrete or embedded within the substrate, provides a low impedance current return path for the module parasitic capacitance, minimizing any high frequency differential voltages and substantially reducing radiated emissions. Discrete capacitance will not be as effective due to parasitic ESL. In addition, volt- age rating, leakage, and clearance must be considered for component selection. Embedding the capacitance within the PCB substrate provides a near ideal capacitor and eliminates component selection issues; however , the PCB must be 4 layers. Care must be exercised in applying either technique to ensure the voltage rating of the barrier is not compromised.
- In applications without an embedded PCB substrate capacitance, a slot may be added between the logic side and isolated side device pins. The slot extends the creepage path between terminals on the PCB side, and may reduce leakage caused by PCB contamination. The slot should be placed in the middle of the device and extend beyond the package perimeter .
Figure 14. Isolated SPI with 5V Input and 5V Regulated Output Figure 15. Isolated I2C with 5V Input and 3.3V Regulated Output
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Figure 16. Isolated SPI with 3.3V Input and 5V Regulated Output Figure 17. Isolated SPI with 3.3V Input with 3.3V and 5V Regulated Outputs
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Figure 18. High Voltage Switch Controller with Current Readback *NOTE: IMON VALID WHEN INP (GATE) IS HIGH FOLLOWED BY 150µs OF BLANKING TIME. TGUP – TS VOL TAGE IS APPROXIMATEL Y 7V .
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Rev. A For more information www.analog.com PACKAGE DESCRIPTION PACKAGE TOP VIEW PIN “A1” CORNER Y X aaa Z aaa Z 36-Lead (22mm × 6.25mm × 2.06mm) (Reference LTC DWG# 05-08-1588 Rev Ø) NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE DETAIL A Øb (36 PLACES) A DETAIL B PACKAGE SIDE VIEW M X YZddd M Zeee D E SUGGESTED PCB LAYOUT TOP VIEW 0.00 9.375 10.375 2.50 0.50 1.50 2.50 1.50 0.50 0.00 10.375 9.375 10.075 10.675 0.50 ±0.025 Ø 36x 2.80 2.20 BGA 36 0817 REV Ø TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” L TMXXXXXX µModule PACKAGE BOTTOM VIEW X W V U T S R P N M L K J H G F E D C B A 123456 DETAIL A SEE NOTES PIN 1 e e F G b 8.375 8.375 SEE NOTES b SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 1.81 0.40 1.41 0.50 0.47 0.46 0.95 NOM 2.06 0.50 1.56 0.60 0.50 22.0 6.25 1.0 20.75 5.0 0.56 1.00 MAX 2.31 0.60 1.71 0.70 0.53 0.66 1.05 0.15 0.10 0.15 0.15 0.08 TOTAL NUMBER OF BALLS: 36 DIMENSIONS NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT Z DETAIL B SUBSTRATE ccc Z Z // bbb Z MOLD CAP 5. PRIMARY DATUM -Z- IS SEATING PLANE
6 PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y
Rev. AFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER A 03/22 Added CSA (UL/IEC) Certifications. 1, 5
Figure 19. High Voltage 30A Power/Energy Monitor with Integrated Sense Resistor