LTC4020

LTC4020 (Rev. E)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 42

Technical content

Rev. EFor more information www.analog.com Document Feedback VIN (V) EFFICIENCY (%) POWER (W) 100 100 10 15

4020 TA01b

VOUT = 14V EFFICIENCY INPUT POWER P (LOSS) TYPICAL APPLICATION FEATURES DESCRIPTION 55V Buck-Boost Multi-Chemistry Battery Charger The LT C®4020 is a high voltage power manager providing PowerPath™ instant-on operation and high efficiency bat- tery charging over a wide voltage range. An onboard buck- boost DC/DC controller operates with battery and/or sys- tem voltages above, below, or equal to the input voltage. The LTC4020 seamlessly manages power distribution between battery and converter outputs in response to load variations, battery charge requirements and input power supply limitations. The LTC4020 battery charger can provide a constant- current/constant-voltage charge algorithm (CC/CV), constant-current charging (CC), or charging with an optimized 4-step, 3-stage lead-acid battery charge pro - file. Maximum converter and battery charge currents are resistor programmable. The IC’s instant-on operation ensures system load power even with a fully discharged battery. Additional safety features include preconditioning for heavily discharged batteries and an integrated timer for termination and protection.

APPLICATIONS

n Wide Voltage Range: 4.5V to 55V Input, Up to 55V Output (60V Absolute Maximums) n Synchronous Buck-Boost DC/DC Controller n Li-Ion and Lead-Acid Charge Algorithms n ±0.5% Float Voltage Accuracy n ±5% Charge Current Accuracy n Instant-On for Heavily Discharged Batteries n Ideal Diode Controller Provides Low Loss PowerPath When Input Power Is Limited n Input Voltage Regulation for High Impedance Input Supplies and Solar Panel Peak Power Operation n Onboard Timer for Protection and Termination n Bad Battery Detection with Auto-Reset n NTC Input for Temperature Qualified Charging n Binary Coded Open-Collector Status Pins n Low Profile (0.75mm) 38-Pin 5mm × 7mm n Portable Industrial and Medical Equipment n Solar-Powered Systems n Military Communications Equipment n 12V to 24V Embedded Automotive Systems Buck-Boost DC/DC Converter Controller with PowerPath Battery Charger Accepts Inputs from 4.5V to 55V and Produces Output Voltages Up to 55V 5V to 30V 6-Cell Lead-Acid Supply/Charger Maximum Power Efficiency vs VIN (Application Circuit on Page 37) L TC4020 RNTC RSENSEB RSENSEA BUCK-BOOST DC/DC CONVERTER PowerPath BATTERY CHARGER

4020 TA01a

All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 7583113 and 8405362.

Rev. E For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS SENSVIN to SENSTOP , SENSBOT to Status Pin Currents Operating Junction Temperature (Note 1) 13 14 15 16 TOP VIEW SGND UHF PACKAGE 38-PIN PLASTIC QFN (5mm × 7mm) TJMAX = 125°C, θJA = 34°C/W, θJC = 2°C/W EXPOSED PAD (PIN 39) IS SGND, MUST BE SOLDERED TO PCB 17 18 19 38 37 36 35 34 33 32 1TG1 BST1 SGND SENSGND SENSBOT SENSTOP SENSVIN RT SHDN VIN_REG MODE STAT1 TG2 BST2 SGND VC ITH VFBMAX ILIMIT CSOUT CSP CSN BGATE BAT SW1 BG1 PVIN PGND INTVCC BG2 SW2 STAT2 TIMER RNG/SS NTC VFB FBG VFBMIN LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4020EUHF#PBF LTC4020EUHF#TRPBF 4020 38-Pin (5mm × 7mm) Plastic QFN –40°C to 125°C LTC4020IUHF#PBF LTC4020IUHF#TRPBF 4020 38-Pin (5mm × 7mm) Plastic QFN –40°C to 125°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. ORDER INFORMATION

Rev. EFor more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). PVIN = SENSVIN = CSP = CSN = BAT = 20V, SHDN = 2V, C(TG1, BG1, TG2, BG2) = 1000pF, VRNG/SS = 2V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Buck-Boost Switching Converter VIN Operating Voltage Range PVIN, SENSVIN l 4.5 55 V UVLO VIN Supply UVLO (Rising) VIN Supply UVLO Hysteresis DC/DC Functions Enabled VIN Falling l 3.6 4.0 0.4 4.4 V V SENSVIN Supply UVLO (Rising) SENSVIN UVLO Hysteresis INTVCC Enabled SENSVIN Falling 3.4 0.3 V V BST Supplies UVLO (Rising) BST Supplies UVLO Hysteresis BST1 – SW1, BST2 – SW2 SW1, SW2 = 0V l 3.0 3.3 0.4 3.8 V V INTVCC Boost Refresh Supply Voltage ILOAD = 5mA l 4.85 5.0 5.15 V Boost Refresh Supply Dropout PVIN = 4.5V, IINTVCC = 5mA 4.46 V Boost Refresh Supply Short-Circuit Current Limit VINTVCC = 0V l 85 150 mA IPVIN PVIN Operating Current Note 3, ITH = 0V l 1.6 3 mA Shutdown Current VSHDN = 0 l 3 6 µA ISENSVIN SENSEVIN Operating Current l 0.25 0.5 mA Shutdown Current VSHDN = 0 l 25 60 µA ISENSTOP SENSETOP Operating Current 32.5 µA Shutdown Current VSHDN = 0 0.1 µA VFBMAX DC/DC Converter Reference Charging Terminated l 2.7 2.75 2.8 V SHDN IC Enable Threshold (Rising) Threshold Hysteresis l 1.175 1.225 100 1.275 V mV SHDN Pin Bias Current 10 nA VSENS DC/DC Converter Inductor Current Limit (Average Value) VSENSVIN – VSENSTOP, VSENSGND – VSENSBOT l 45 50 60 mV Reverse Current Inhibit (Average Value) VITH Falling (TG2 Disabled) VITH Rising (TG2 Enabled) l 0 2 mV mV ILIMIT Inductor Current Limit Programming VILIMIT = 0.5V, VILIMIT/VSENS(MAX) 20 V/V ILIMIT Pin Bias Current l 47.5 50 52.5 µA RNG/SS RNG/SS Pin Bias Current l 47.5 50 52.5 µA ITH Error Amp Current Limit VFBMAX = 0, VITH = 1.3V 8 µA Error Amp T ransconductance VFBMAX = 2.75V; VITH = 1.3V 95 µS VC High Side Current Sense T ransconductance (VSENSVIN – VSENSETOP) to IVC, VC = 1.8V 200 µS Low Side Current Sense T ransconductance (VSENSGND – VSENSEBOT) to IVC, VC = 1.8V 200 µS DCMAX Maximum Duty Cycle BG2: tON • fO l 70 80 % fO Switching Frequency RRT = 100k RRT = 50k RRT = 250k l 235 250 500 100 265 kHz kHz kHz tON Minimum On Time BG2 l 150 250 ns tOFF Minimum Off Time TG1 l 300 500 ns tTR Gate Drive T ransition Time TG1, BG1, TG2, BG2 5 ns tNOL Gate Drive Non-Overlap time (TG1 – SW1) to BG1, (TG2 – SW2) to BG2 75 ns

Rev. E For more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Battery Charger VBAT Charger Output Voltage Range l 55 V VFB Float Reference Auto Recharge Voltage Precondition Threshold (Rising) Precondition Hysteresis CC/CV Charging (MODE = 0V) % of Float Reference % of Float Reference l l l 2.4875 2.475 96.5 2.5 97.5 2.5125 2.525 98.5 V V mV Absorption Reference Float Reference Bulk Charge Threshold (Falling) Precondition Threshold (Rising) Precondition Hysteresis Lead-Acid Charging (MODE = INTVCC) % of Absorption Reference % of Absorption Reference % of Absorption Reference l l l l 2.4875 2.475 91.5 2.5 92.5 87.5 2.5125 2.525 93.5 V V mV Voltage Reference CC Charging (MODE = NC) l 2.4875 2.475 2.5 2.5125 2.525 V V VIN_REG Input Regulation Reference % of Float (CC/CV), Safety (CC), or Absorption (LA) Reference l 98 100 102 % VFBMIN Instant-On Reference % of Float (CC/CV) or Absorption (LA) Reference l 84 85 86 % C/10 Detection Enable (Rising) Hysteresis (Falling) 2.175 V mV Instant-On Charge Current Reduction Threshold VCSN – VBAT, Note 4 0.45 V C/10 Detection Enable C/10 Detection Hysteresis VCSN – VBAT Falling VCSN – VBAT Rising 1.05 150 V mV Charge Current Reduction Gain ΔVCS(MAX)/Δ(VCSN – VBAT), Note 4 –33 mV/V IBATQ Battery Bias Currents with PowerPath Switcher Disabled ICSP + ICSN + IBAT l 9 18 µA CSN, CSP Charger Current Sense Pin Operating Bias Currents ICSP = ICSN, Charging Enabled 40 µA Charger Current Sense Limit Voltage VCSP – VCSN l 47.5 50 52.5 mV Charger Current Sense Termination Voltage (C/10) VCSP – VCSN, MODE = 0V l 3 5 7 mV Charger Current Sense Precondition Voltage VCSP – VCSN, VFB = 1.5 l 1.5 3 4.5 mV Sense Input UVLO UVLO Hysteresis VCSP Rising (Charging Enabled) VCSP Falling (Charging Disabled) l 1.6 1.75 100 1.9 V mV CSOUT Offset VCSP = VCSN l 0.225 0.25 0.290 V Gain ΔVCSOUT/Δ(VCSP – VCSN) l 19 20 21 V/V RNG/SS Current Limit Programming VRNG/SS = 0.5V, VRNG/SS/VCS(MAX) l 18 20 22 V/V NTC NTC Range Limit (High) NTC Range Limit (Low) NTC Range Hysteresis VNTC Rising VNTC Falling % of VNTC(H,L) l l 1.30 0.27 1.35 0.3 1.40 0.33 V V INTC NTC Pin Bias Current VNTC = 0.8V l 47.5 50 52.5 µA NTC Disable Current INTC Pin Current (Falling) 3.5 µA NTC Disable Current Hysteresis 2 µA ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). PVIN = SENSVIN = CSP = CSN = BAT = 20V, SHDN = 2V, C(TG1, BG1, TG2, BG2) = 1000pF, VRNG/SS = 2V.

Rev. EFor more information www.analog.com SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VBGATE Gate Clamp Voltage VCSN – VBGATE l 7 9.5 12 V C/10 Detection Enable (Falling) C/10 Detection Enable Hysteresis VCSN < 7V 0.425 0.125 V V BGATE BGATE Pull-Down Current Charging Enabled 15 µA BGATE Pull-Up Current Charging Disabled, VCSN – VBGATE = 2V 15 µA BGATE Standby Pull-Down Current VSHDN = 0V 120 µA Ideal Diode Pull-Down Current Charging Disabled, VBAT – VCSN = 0.5V 500 µA Ideal Diode Forward Voltage VBAT – VCSN, VCSN Measured Through 100Ω Series Resistor l 5 14 20 mV TIMER Timer High Threshold 1.5 V Timer Low Threshold 1.0 V C/10 Mode Threshold (Rising) l 0.4 0.5 0.6 V C/10 Mode Hysteresis 225 mV Timer Source/Sink Current VTIMER = 1.25V l 8.5 10 11.5 µA VSTAT(L) Status Pins Enabled Voltage ISTAT1 = 1mA, ISTAT2 = 1mA ISTAT1 = 5mA, ISTAT2 = 5mA l l 0.15 0.75 0.4 2.5 V V IVFBMIN Instant-On Feedback Bias Current 10 nA IVFB Feedback Pin Bias Current 10 nA IVIN_REG Input Regulation Bias Current 10 nA IFBG Pin Current (Disabled) VSHDN = 0V, VFBG = 55V 10 nA RNTC NTC Minimum Disable Resistance l 250 400 kΩ RFBG FBG Resistance to SGND IFBG = 1mA l 20 50 Ω ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). PVIN = SENSVIN = CSP = CSN = BAT = 20V, SHDN = 2V, C(TG1, BG1, TG2, BG2) = 1000pF, VRNG/SS = 2V. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC4020 is tested under pulsed load conditions such that TJ ≈ TA. The LTC4020E is guaranteed to meet specifications from 0°C to 85°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization, and correlation with statistical process controls. The LTC4020I is guaranteed over the full –40°C to 125°C operating junction temperature range. The junction temperature (TJ) is calculated from the ambient temperature (TA) and power dissipation (PD) according to the formula TJ = TA + (PD • θJA). Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. This IC includes overtemperature protection that is intended to protect the device during momentary overload. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: ICC does not include switching currents. VBST1 = VBST2 = VINTVCC and VSW1 = VSW2 = 0V for testing. Note 4: See Typical Performance Characteristics.

Rev. E For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Shutdown Current vs Temperature (IPVIN + ISENSVIN + ISENSTOP) INTVCC Short-Circuit Current Limit vs Temperature Maximum Charge Current (Percent of Programmed ICSMAX) vs RNG/SS Voltage Instant-On: Maximum Charge Current (Percent of ICSMAX) vs VCSN–BAT IBATQ (IBAT + ICSN + ICSP) vs VBAT PowerPath Switcher Disabled IBATQ (IBAT + ICSN + ICSP) vs Temperature PowerPath Switcher Disabled VFLOAT(CC/CV) or , VABSORB(LEAD-ACID) Reference vs Temperature VFLOAT(LEAD-ACID) Reference vs Temperature VFBMAX Reference vs Temperature TEMPERATURE (°C) VOL TAGE (V) 2.80 2.79 2.78 2.77 2.76 2.75 2.74 2.73 2.72 2.71 2.70 50205–10–25–40 80 95 110

4020 G03

TEMPERATURE (°C) STANDBY MODE CURRENT (µA) 60–40–30–20–10 0 10 80 90

4020 G04

TEMPERATURE (°C) INTVCC CURRENT LIMIT (mA) 155 154 153 152 151 150 149 148 147 146 145 50205–10–25–40 80 95 110

4020 G05

RNG/SS VOL TAGE (V) MAXIMUM CHARGE CURRENT (%) 100 0.4 0.8 1.0

4020 G06

1.20.2 0.6 VBAT (V) IBATQ (µA) 11.0 10.5 10.0 8.0 9.5 9.0 8.5 7.0 6.5 7.5 6.0 10 30 4535 40 50

4020 G08

TEMPERATURE (°C) –40 VOL TAGE (V) 2.36 2.35 2.34 2.33 2.32 2.31 2.30 2.29 2.28 2.27 2.26 2.25 20–10 80 95 110

4020 G02

1255 35 50–25 65 TEMPERATURE (°C) –40 VOL TAGE (V) 2.525 2.520 2.510 2.500 2.515 2.505 2.495 2.490 2.485 2.480 2.475 20 35 50–10 80 95 110

4020 G01

1255–25 65 VCSN–BAT (V) MAXIMUM CHARGE CURRENT (%) 100 0.5 1 1.25

4020 G07

TEMPERATURE (°C) IBATQ (µA) 11.0 10.5 10.0 9.5 8.0 9.0 8.5 60–40–30–20–10 0 10 80 90

4020 G09

VBAT = 20V TA = 25°C, unless otherwise noted.

Rev. EFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Ideal Diode VF vs Battery Voltage Ideal Diode VF vs Temperature IINTVCC (mA) VINTVCC (V) 4.5 4.4 4.2 4.1 4.3 4.0 10 30 40

4020 G12

25°C 125°C PVIN = 4.5V V(CSP-CSN) (mV) VCSOUT (V) 1.3 1.2 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 1.1 0.2 10 30 40

4020 G13

BST Refresh Regulator Dropout INTVCC vs IINTVCC CSOUT vs CSP–CSN Switching Frequency vs Input Voltage Switching Frequency vs Temperature IRNG/SS, ILIMIT, INTC vs Temperature Feedback References vs Input Voltage INTVCC vs VIN VIN (V) FEEDBACK REFERENCES (V) 2.80 2.75 2.65 2.60 2.55 2.50 2.45 2.40 2.35 2.30 2.70 2.25 1510 3530 4540 50

4020 G14

VFLOAT (CC/CV; ABSORB) VFLOAT (LEAD-ACID) VIN (V) VINTVCC (V) 5.10 5.08 5.04 5.02 5.00 4.98 4.96 4.94 4.92 5.06 4.90 1510 3530 4540 50

4020 G15

IINTVCC = 5mA TEMPERATURE (°C) –40 IRNG/SS, ILIMIT, INTC (µA) 52.5 52.0 51.0 50.5 50.0 49.5 49.0 48.5 48.0 51.5 47.5 –25 5 20 35 50 65 80 11095

4020 G18

125–10 VBAT (V) IDEAL DIODE VF (mV) 16.0 15.5 15.0 13.5 13.0 12.5 14.5 14.0 12.0 10 25 30 35 40 45 50

4020 G10

TEMPERATURE (°C) –40 IDEAL DIODE VF (mV) –10 35 50 65 80 95 110

4020 G11

125–25 5 20 VBAT = 20V TA = 25°C, unless otherwise noted. VIN (V) SWITCHING FREQUENCY (kHz) 255 254 252 251 250 249 248 247 246 253 245 10 30 40 50

4020 G16

RRT = 100k TEMPERATURE (°C) –40 SWITCHING FREQUENCY (kHz) 255 254 252 251 250 249 248 247 246 253 245 –25 5 20 35 50 65 80 11095

4020 G17

125–10 VIN = 20V RRT = 100k

Rev. E For more information www.analog.com PIN FUNCTIONS TG1 (Pin 1) : VIN side (step-down) primary switch FET gate driver output. BST1 (Pin 2): Boosted supply rail for VIN side (step-down) switch FETs. Connect 1µF capacitor from this pin to SW1. Connect 1A Schottky diode cathode to this pin, anode to INTVCC pin. SGND (Pins 3, 29, Exposed Pad 39) : Signal Ground Reference. Connect to the output decoupling capaci - tor negative terminal and battery negative terminal. The exposed pad (39) must be soldered to PCB ground (SGND) for electrical connection and rated thermal performance. SENSGND (Pin 4): Kelvin connection for PGND used for SENSBOT current sense reference. SENSBOT (Pin 5) : Ground Referred Current Sense Amplifier Input. Inductor current is monitored via a PGND referenced current sense resistor (R SENSEB), typically in series with the source of the VIN side synchronous switch FET . Kelvin connect this pin to the associated sense resis- tor . Inductor current is limited to a maximum average value (ILMAX), and corresponds to 50mV across this sense resistor during normal operation. R SENSEB = 0.05/ILMAX Set RSENSEB = RSENSEA, as described in SENSTOP . A filter capacitor (CSENSB) is typically connected from SENSBOT to SENSGND for noise reduction. C SENSB ~ 1ns/RSENSEB See Applications Information section. SENSTOP (Pin 6): VIN Referred Current Sense Amplifier Input. Inductor current is monitored via a VIN referenced current sense resistor (RSENSEA), typically in series with the drain of the VIN side primary switch FET . Kelvin con- nect this pin to the associated sense resistor . Inductor current is limited to a maximum average value (I LMAX), and corresponds to 50mV across this sense resistor dur- ing normal operation. R SENSEA = 0.05/ILMAX Set RSENSEA = RSENSEB, as described in SENSBOT . SENSVIN (Pin 7): Kelvin connection for input supply (VIN) used for SENSTOP current sense reference. Input power supply pin for most internal low current functions. Typical pin bias current is 0.25mA. RT (Pin 8) : System Oscillator Frequency Control Pin. Connect resistor (RRT) from this pin to ground. Resistor value can range from 50k (500kHz) to 500k (50kHz). RRT = 100k yields 250kHz operating frequency. See Applications Information. SHDN (Pin 9): Precision Threshold Shutdown Pin. Enable threshold is 1.225V (rising), with 100mV of input hys - teresis. When in shutdown, all charging functions are disabled and input supply current is reduced to 27.5µA. Typical SHDN pin input bias current is 10nA. VIN_REG (Pin 10) : Input Voltage Regulation Reference. Battery charge current is reduced when the voltage on this pin falls below 2.5V. Connecting a resistor divider from VIN to this pin enables programming of minimum oper - ational V IN voltage for the battery charging function. This is used to program the peak power voltage for a solar panel, or to help maintain a minimum voltage on a poorly regulated input supply. This pin should not be used to program minimum operational V IN voltage with low impedance supplies. Should the input supply begin to collapse, the LTC4020 reduces the DC/DC converter input power such that programmed minimum VIN opera- tional voltage is maintained. If the voltage regulation feature is not used, connect the VIN_REG pin to V IN or INTVCC. Typical VIN_REG pin input bias current is 10nA. See Applications Information. MODE (Pin 11) : Charger Mode Control Pin. Short this pin to ground to enable a constant-current/constant- voltage (CC/CV) charging algorithm. Connect this pin to pin INTVCC to enable a 4-step, 3-stage lead-acid charging algorithm. Float this pin to force a constant-current (CC) charging function. See Applications Information section. STAT1 (Pin 12): Open-collector status output, typically pulled up through a resistor to a supply voltage. This status pin can be pulled up to voltages as high as 55V when the pin is disabled, and can sink currents up to 1mA when logic low (<0.4V). Pull down currents as high

Rev. EFor more information www.analog.com as 5mA (absolute maximum) are supported for higher current applications, such as lighting LEDs. If the LTC4020 is configured for a CC/CV charging algo- rithm, the STAT1 pin is pulled low while battery charge currents exceed 10% of the programmed maximum (C/10). The STAT1 pin is also pulled low during NTC faults. The STAT1 pin becomes high impedance when a charge cycle is terminated or when charge current is below the C/10 threshold. If the LTC4020 is configured for a CC charging algorithm, the STAT1 pin is pulled low during the entire charging cycle. The STAT1 pin becomes high impedance when the charge cycle is terminated. If the LTC4020 is configured for a lead-acid charging algo- rithm, the STAT1 pin is used as a charge cycle stage indi- cator pin, and pulled low during the bulk and absorption charging stages. The pin is high impedance during the float charging period and during NTC or bad battery faults. See Applications Information section. STAT2 (Pin 13): Open-collector status output, typically pulled up through a resistor to a supply voltage. This sta- tus pin can be pulled up to voltages as high as 55V when disabled, and can sink currents up to 1mA when enabled (<0.4V). Pull down currents as high as 5mA (absolute maximum) are supported for higher current applications, such as lighting LEDs. If the LTC4020 is configured for a CC/CV charging algo- rithms, the STAT2 pin is pulled low during NTC faults or after a bad battery fault occurs. If the LTC4020 is configured for a CC charging algorithms, the STAT2 pin is pulled low during NTC faults. If the LTC4020 is configured for a lead-acid charging algorithm, the STAT2 pin is used as a charge cycle stage indicator pin, and pulled low during the bulk and float charging stages. The pin is high impedance during the absorption charging stage and during NTC or bad bat - tery faults. See Applications Information section. TIMER (Pin 14): End-Of-Cycle Timer Programming Pin. If a timer based charging algorithm is desired, connect a capacitor (CTIMER) from this pin to ground. If no timer functions are desired, connect this pin to ground. End-of-cycle time (in hours) is programmed with the value of CTIMER following the equation: T EOC = CTIMER • 1.46 • 107 During CC/CV or lead-acid charging algorithms, a bad bat- tery fault is generated if the battery voltage does not reach the precondition threshold voltage within 1/8 of TEOC, or: T PRE = CTIMER • 1.82 • 106 A 0.2µF capacitor is typically used for CC/CV charging, which generates a 2.9 hour timer TEOC, and a precondition limit time of 22 minutes. A 0.47µF capacitor is typically used for a lead-acid charger , which generates a 6.8 hour absorption stage safety timeout. RNG/SS (Pin 15): Battery Charge Current Programming Pin. This pin allows dynamic adjustment of maxi - mum charge current, and can be used to employ a soft-start function. Setting the voltage on the RNG/SS pin reduces maxi - mum charge current from the value programmed. The maximum charge current is reduced to the fraction of programmed current (as per the sense resistor , RCS) cor- responding to the voltage set on the pin (in volts). This pin has an effective range from 0 to 1V. For example, with 0.5V RNG/SS on the pin, the maximum charge current will be reduced to 50% of the programmed value set by the sense resistor values. 50µA is sourced from the RNG/SS pin, so maximum charge current can be programmed by connecting a single resistor (RRNG/SS) from RNG/SS to ground, such that the voltage dropped across the resistor is equivalent to the desired pin voltage: V RNG/SS = 50µA • RRNG/SS Soft-start functionality can be implemented by connecting a capacitor (CRNG/SS) from RNG/SS to ground, such that the time required to charge the capacitor is the desired PIN FUNCTIONS

Rev. E For more information www.analog.com soft-start interval (T SS1). The voltage that corresponds to full programmed battery charge current on the RNG/ SS pin is 1V, so the relation for this capacitor reduces to: C RNG/SS = 50µA • TSS1 The RNG/SS pin is pulled low during periods when charg- ing is disabled, including NTC faults, bad battery faults, and normal charge cycle termination. This allows for a graceful start after faults and when initiating new charge cycles, should soft-start functionality be implemented. Both a soft-start capacitor and a programming resistor can be implemented in parallel. RNG/SS voltage can also be manipulated using an active device, such as employing a pull-down transistor to dis- able charge current or to dynamically servo maximum charging current. Because this pin is internally pulled to ground during fault conditions, active devices with low- impedance pull up capability cannot be used. See Applications Information section. NTC (Pin 16): Battery Temperature Monitor Pin. Connect a 10k, β = 3380 NTC thermistor from this pin to ground. The NTC pin is the input to the negative temperature coef- ficient temperature monitoring circuit. This pin sources 50µA, and monitors the voltage created across the 10k thermistor . When the voltage on this pin is above 1.35V (0°C) or below 0.3V (40°C), charging is disabled and an NTC fault is signaled at the STAT1 and STAT2 status pins. If the internal timer is being used, the timer is paused, suspending the charging cycle until the NTC fault condi- tion is relieved. There is approximately 5°C of tempera- ture hysteresis associated with each of the temperature thresholds. The NTC function remains enabled while thermistor resistance to ground is less than 250k. If this function is not desired, leave the NTC pin unconnected or connect a 10k resistor from the NTC pin to ground. The NTC pin contains an internal clamp that prevents excur - sions above 2V, so the pin must not be pulled high with a low impedance source. A low impedance element can be used to pull the pin to ground. VFB (Pin 17): Battery Voltage Feedback Pin. Battery volt- ages are programmed through a feedback resistor divider placed from the BAT pin to FBG. During CC/CV charging, the battery voltage references are: Float Voltage (VFLOAT) = 2.5V T rickle Charge Voltage (VTRK) = 1.75V Auto-Restart Voltage (VRESTART) = 2.4375 During lead-acid charging, the battery voltage references are: Absorption Voltage (VABSOR) = 2.5V Float Charge Voltage (VF LT) = 2.3125V T rickle Charge Voltage (VTRK) = 1.75V Bulk Recharge Voltage (VBULK) = 2.1875V With R FB1 connected from BAT to V FB and R FB2 con - nected from VFB to FBG, the ratio of (R FB1/RFB2) for the desired programmed battery float voltage (CC/CV charg- ing) or absorption voltage (lead-acid charging) follows the relation: R FB1/RFB2 = (VFLOAT/ABSORB)/2.5 – 1 FBG (Pin 18): Voltage Feedback Divider Return. This pin contains a low impedance path to signal ground, used as the ground reference for voltage monitoring feedback resistor dividers. When VIN is not present or the LTC4020 is in shutdown, this pin becomes high impedance, elimi- nating current drain from the battery associated with the feedback resistor dividers. VFBMIN (Pin 19) : Minimum voltage feedback pin for instant-on operation. Minimum DC/DC converter out - put voltage (VOUTMIN) is programmed using this pin for instant-on functionality. VOUTMIN is programmed through a feedback resistor divider placed from the CSP pin to FBG. If the battery voltage is below the voltage level pro - grammed using this pin, the LTC4020 controls the exter- nal PowerPath FET as a linear pass element, allowing the DC/DC converter output to achieve the minimum PIN FUNCTIONS

Rev. EFor more information www.analog.com programmed voltage. Maximum battery charge current is reduced as the voltage across the PowerPath FET increases to control power dissipation. The internal V FBMIN voltage reference is 2.125V. With a resistor (RMIN1) connected from CSP to V FBMIN, and a resistor (RMIN2) connected from VFBMIN to FBG, the ratio of these resistors for the desired minimum converter out- put voltage follows the relation: R MIN1/RMIN2 = (VOUT(MIN)/2.125) – 1 Using the same resistor values for battery voltage pro - gramming, or RFB1 = RMIN1 and RFB2 = RMIN2, yields an instant-on voltage that is 85% of VFLOAT (CC/CV charging) or VABSORB (lead-acid charging): V OUT(MIN) = 0.85 • VFLOAT/ABSORB BAT (Pin 20) : Battery Voltage Monitor Pin. This pin serves as the positive reference for the LTC4020 ideal diode function. If a system load occurs that is large enough to collapse the DC/DC converter output while charging is terminated or disabled, and the battery is disconnected (PowerPath FET is high impedance), the ideal diode function engages the PowerPath. This function powers the system load from the battery, and modulates the PowerPath FET gate such that the system output voltage is maintained with 14mV across the PowerPath FET , provided the voltage drop due to RDS(ON) < 14mV. This allows large loads to be accommodated without excessive power dissipation in the body diode of the PowerPath FET . BGATE (Pin 21): PowerPath FET Gate Driver Output. This pin is controls the multiple functions of the PowerPath FET . This pin is pulled low during a normal charging cycle, minimizing the FET series impedance between the DC/ DC converter output and the battery. The BGATE pin is also forced low when the DC/DC con - verter is disabled, maintaining a low impedance connec- tion to power the system from the battery. When BGATE is pulled low, CSP BGATE is limited inter - nally to 9.5V, so if CSP > 9.5V, BGATE is maintained by an internal clamp at CSP – BGATE = 9.5V. The BGATE pin must be near ground or at the clamp voltage for C/10 detection to occur . If the battery voltage is lower than the instant-on threshold (see VFBMIN), BGATE servos the PowerPath FET imped - ance such that a voltage drop between the CSN pin and the BAT pin is created while battery charging continues. If the VCSN – VBAT voltage exceeds 0.4V, maximum charge current is reduced to decrease power dissipation in the PowerPath FET . When the DC/DC converter is enabled, but the battery charge cycle has terminated, BGATE is pulled high to disconnect the battery from the converter output. The battery is also disconnected in the same manner during NTC faults. The ideal diode function is active during these periods, however , so if a system load occurs that is larger than what the DC/DC converter can accommodate, the battery can supply the required current, and the BGATE pin will be servo controlled to force a voltage drop of only 14mV across the PowerPath FET . The ideal diode function is disabled during bad battery faults. If a PowerPath FET is not being used, such as with a lead- acid charging application, connect a 0.1nF capacitor from BGATE to CSN. CSN (Pin 22) : Battery Charger Current Sense Negative Input. Connect this pin to the negative terminal of the battery charge current sense resistor (RCS) through a 100Ω resistor . Connect a filter capacitor between this pin and the CSP pin for ripple reduction. See Applications Information section. The value of the sense resistor is related to the maximum battery charge current (ICSMAX): R CS = 0.05/ICSMAX This pin also serves as the negative reference for the LTC4020 ideal diode function (see BAT). PIN FUNCTIONS

Rev. E For more information www.analog.com CSP (Pin 23) : Battery Charger Current Sense Positive Input. Connect this pin to the positive terminal of the battery charge current sense resistor (R CS) through a 100Ω resistor . Connect a filter capacitor between this pin and the CSN pin for ripple reduction. See Applications Information section. The value of the sense resistor is related to the maximum battery charge current (ICSMAX) such that: R CS = 0.05/ICSMAX CSOUT (Pin 24) : Current Sense Amplifier Output and Charge Current Monitor . Connect 100pF capacitor to ground. Pin output impedance is 100k, so any loading for moni- tors must be high impedance. The sense output voltage follows the relation: V CSOUT = 0.25 + 20 • (VCSP – VCSN) CSOUT is only active while battery charger functions are operating. CSOUT pin voltage is pulled to 0V after charge cycle termination or during fault conditions. ILIMIT (Pin 25) : Switched Inductor Maximum Current Programming Pin. This pin allows dynamic adjustment of DC/DC converter maximum average inductor current, and can be used to employ a soft-start function. Setting the voltage on the I LIMIT pin reduces maximum average inductor current from the value programmed. The inductor current limit is reduced to the fraction of programmed current (as per the sense resistors) corre - sponding to the voltage set on the pin (in volts). This pin has an effective range from 0 to 1V. For example, with 0.5V on the pin, the maximum inductor current will be reduced to 50% of the programmed value set by the sense resistor values. 50µA is sourced from this pin, so maximum inductor cur- rent can be programmed by connecting a single resis - tor (RILIMIT) from ILIMIT to ground, such that the voltage dropped across the resistor is equivalent to the desired pin voltage: V ILIMIT = 50µA • RILIMIT Soft-start functionality can be implemented by connecting a capacitor (CILIMIT) from ILIMIT to ground, such that the time required to charge the capacitor is the desired soft- start interval (TSS2). The voltage that corresponds to full inductor current on the ILIMIT pin is 1V, so the relation for this capacitor reduces to: C ILIMIT = 50µA • TSS2 ILIMIT voltage can also be manipulated using an active device, such as employing a pull-down transistor to dis- able DC/DC converter current or to dynamically servo maximum current. Because this pin is internally pulled to ground during portions of the converter power-up cycle, active devices with low impedance pull-up capability can- not be used. VFBMAX (Pin 26): DC/DC Converter Output Feedback Pin. Maximum DC/DC converter output voltage (V OUTMAX) is programmed using this pin. When a battery charge cycle is terminated or disabled, and the battery is disconnected (PowerPath FET is high impedance), the converter output will servo to this maximum voltage. The internal V FBMAX voltage reference is 2.75V. With a resistor (RMAX1) connected from CSP to V FBMAX and a resistor (RMAX2) connected from VFBMAX to FBG, the ratio of RMAX1/RMAX2 for the desired maximum DC/DC con - verter output voltage follows the relation: R MAX1/RMAX2 = (VOUTMAX/2.75) – 1 Using the same resistor values for battery voltage pro - gramming, or RFB1 = RMAX1 and RFB2 = RMAX2, yields a voltage while not charging that is 110% of VFLOAT (CC/CV charging) or VABSORB (lead-acid charging): V OUTMAX = 1.1 • VFLOAT/ABSORB If RMAX1/RMAX2 are chosen for a not-charging power- stage output voltage (V OUTMAX) of less than 110% of the full-charge voltage, be sure to choose R MAX1/RMAX2 to allow adequate headroom between V OUTMAX and the battery full-charge voltage to cover voltage drops in the battery-charge current-sense resistor (R CS) and the PowerPath FET . Typically, at least 100mV to 200mV of headroom is required. PIN FUNCTIONS

Rev. EFor more information www.analog.com ITH (Pin 27): DC/DC Converter Voltage Loop Compensation Pin. See Applications Information section for compensa- tion component selection details. VC (Pin 28): DC/DC Converter Current Loop Compensation Pin. See Applications Information section for compensa- tion component selection details. BST2 (Pin 30): Boosted supply rail for V OUT side (step- up) switch FETs. Connect a 1µF capacitor from this pin to SW2. Connect a 1A Schottky diode cathode to this pin, anode to INTVCC pin. TG2 (Pin 31) : VOUT side (step-up) synchronous switch FET gate driver output. SW2 (Pin 32) : Switched node for step-up switches. Connect the switched inductor to this pin. Connect the primary switch FET drain and synchronous switch FET source to this pin. BG2 (Pin 33) : VOUT side (step-up) primary switch FET gate driver output. INTVCC (Pin 34) : Boosted Driver Refresh Supply. This supply is regulated to 5V and is current limited to a typical value of 150mA. Connect a 2.2µF ceramic capacitor from this pin to PGND. Boosted supply refresh diode anodes are connected to this pin. Using this pin to power external 5V circuitry is not recommended. Note that internal VCC regulator has a minimum-specified current-limit value of 85mA. Since the internal regulator supplies gate drive to all four power-stage FETs, 85mA represents a maximum practical limit for total gate-drive current. See Applications Information section. PGND (Pin 35): Switch high current return path for step- up primary and step-down synchronous switches. PVIN (Pin 36) : High Current Input Supply Pin. Connect 10µF decoupling capacitor from this pin to PGND. The PVIN pin provides input supply current for the INTV CC internal 5V linear regulator . BG1 (Pin 37): VIN side (step-down) synchronous switch FET gate driver output. SW1 (Pin 38) : Switched node for step-down switches. Connect the switched inductor to this pin. Connect the primary switch FET source and synchronous switch FET drain to this pin. PIN FUNCTIONS

Figure 1. DC/DC Converter Block Diagram

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Figure 2. Battery Charger Block Diagram

Rev. E For more information www.analog.com OPERATION Functional Overview The LTC4020 is an advanced high voltage power man - ager and multi-chemistry battery charger designed to efficiently transfer power from a variety of sources to a system power supply rail and a battery. The LTC4020 contains a step-up/step-down DC/DC con- troller that allows operation with battery and system volt- ages that are above, below, or equal to the input voltage (VIN). A precision threshold shutdown feature allows incorporation of input voltage UVLO functionality using a simple resistor divider . When in low current shutdown mode, the IC input supply bias is reduced to only 27.5µA. The LTC4020 charger is programmable to produce opti- mized charging profiles for a variety of battery chemistries. The LTC4020 can provide a constant-current/constant- voltage charge characteristic with either C/10 or timed termination for use with lithium based battery systems, a constant-current characteristic with timed termination, or an optimized 4-step, 3-stage lead-acid charge profile. Maximum battery charge current is programmable using a sense resistor , and a charge current range adjust pin allows dynamic adjustment of maximum charge current. A switcher core current limit adjust pin also allows dynamic limiting of power available to the system by virtue of limit- ing maximum current in the DC/DC converter inductor . The LTC4020 preconditions heavily discharged batter - ies by reducing charge current to one-fifteenth of the programmed maximum. Once the battery voltage climbs above an internally set threshold, the IC automatically increases maximum charging current to the full pro - grammed value. A bad battery detection function signals a fault and suspends charging should a battery not respond to preconditioning. Battery temperature is monitored using a thermistor mea- surement system. This feature monitors battery tempera- ture during the charging cycle, suspending the charge cycle and signaling a fault condition if the battery tem - perature moves outside a safe charging range of 0°C to 40°C. The charge cycle automatically resumes when the temperature returns to that safe charging range. Instant-on PowerPath architecture ensures that an appli- cation is powered immediately after an external voltage is applied, even with a completely dead battery, by prioritiz- ing power to the application. Since the controller output (VOUT) and the battery (BAT) are sometimes decoupled, the LTC4020 includes an ideal diode controller , which guarantees that ample power is always available to VOUT if there is insufficient power available from the DC/DC converter . Should there be no input power available (VIN), the LTC4020 makes a low impedance connection from the battery to VOUT though the PowerPath FET . Battery life is maximized during periods of input supply disconnect by reducing the LTC4020 battery standby current to less than 10µA. The LTC4020 contains two digital open-collector outputs that provide charger status and signal fault conditions. These binary coded pins signal battery charging, standby or shutdown modes, battery temperature faults, and bad battery faults. DC/DC Converter Operation (See Figure 1, Block Diagram) The LTC4020 uses a proprietary average current mode DC/DC converter architecture. As shown in Figure 3, when VIN is higher than VOUT dur- ing step-down (buck) operation, switches A (driven by pin TG1) and B (driven by pin B G1) perform the PWM required for accommodating power conversion. Ideally, switch D (driven by pin TG2) would conduct continuously and switch C (driven by pin B G2) would stay off, mak - ing PWM switching action much like that in a synchro - nous buck topology. Switch D uses a bootstrapped driver , however , so switch C conducts for a minimum on time of 150ns each cycle to refresh the driver and switch D is disabled to accommodate this refresh time. A 75ns non-overlap period separates the conduction of the two switches preventing shoot-through currents. When V IN is lower than V OUT during step-up (boost) operation, switches C and D perform the PWM required for accommodating power conversion. Ideally, switch A would conduct continuously and switch B would stay off, making PWM switching action much like that in a

preventing shoot-through currents. taneously to accommodate conversion requirements. compensation network to produce a voltage on pin ITH. inductor current of the DC/DC converter . sentation of inductor current. an offset at the input of the two current sense amplifiers. sense transconductance amplifiers (EA –CA and EA–CB). compensation network to produce a voltage on the pin VC. cycle of the charger’s switches. VOUT, ground, and current sense elements. Figure 3. Converter Switch Diagram Figure 4. Operating Regions vs Duty Cycle (DC)

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for a short time during start-up until the FET is enabled. and battery charger requirements. to detect <C/10 current thresholds. operate regardless of the state of a charge cycle. that is used for time based control of a charge cycle. cycle within the programmed TEOC time. Figure 5. Battery Charger PowerPath Diagram

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Li-Ion, Li-Polymer , and LiFePO4 battery charging. is restored once the voltage on V FB rises above 1.75V. current (CC) portion of the charge cycle. and the charger indicates not charging on the status pins. nected from the converter output. Table 1. Typical CC/CV Charge Cycle Voltages (per Cell) a 4-step, 3-stage lead-acid charging profile. capability is restored, and the bulk charging stage begins. the 2.5V absorption reference voltage.

to 14.4V for a 6-cell battery. 6.8-hour absorption stage safety timeout. capability to the programmed maximum. Table 2. Typical Lead-Acid Charge Cycle Voltages (12V System) other application where a timed current source is desired. precondition mode is not desired. functionality at that level if desired. battery is charged with 2.5A for one hour .

all of the switches are disabled for four (4) clock cycles. Figure 6. VOUT Safety Limit Programming resistive divider , providing feedback to the V FBMAX pin. where RMAX1 and RMAX2 are defined as in Figure 6. limit, that is 10% higher than the battery charge voltage.

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increased switching losses and higher gate drive currents. ing losses yielding higher conversion efficiencies.

• 1 ∆VIN •fO where fO is the operating frequency, VOUT(MAX) is the DC/ DC converter maximum output voltage and V IN(MIN) is the regulation voltage corresponding to 2.5V on VIN_REG. If the input regulation feature is not being used, use the minimum expected input operating voltage. If an application does not require step-down operation, during step-up operation, input ripple current is equivalent

Figure 7. RT vs Operating Frequency

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Figure 8. Using the ILIMIT Pin for Digital Control Figure 9. Driving the ILIMIT Pin with a Current Sink

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be used to drive the ILIMIT pin. exceeding the maximum peak current in the inductor . desired amount of peak-to-peak ripple current, ΔI MAX.

Rev. E For more information www.analog.com Magnetics vendors typically specify inductors with maximum RMS and saturation current ratings. Select an inductor that has a saturation current rating at or above 1.25 • IMAX, and an RMS rating above IMAX. Output Decoupling During periods when the LTC4020 DC/DC converter out- put is not connected to the battery through the PowerPath FET , the system load is driven directly by the converter . The converter creates large switched currents, so a high quality, low ESR decoupling capacitor is recommended to minimize voltage glitches on the VOUT supply. Placing a smaller ceramic decoupling capacitor ( 0.1µF to 10µF) in parallel with the output decoupling capacitor is also recommended for high frequency noise reduction. The VOUT decoupling capacitor (CVOUT) absorbs the majority of the converter ripple current, so it must have an ade - quate ripple current rating. RMS ripple current (IΔRMS) is highest during step up operation, and follows the relation: I∆RMS ~IMAX •DC • 1 DC – 1 having a maximum at DC = 0.5, or VOUT = 2 • VIN, where: ICVOUT(RMS) = IMAX The simple worst-case of ½ • IMAX is commonly used for design, where I MAX is the programmed inductor current limit. Bulk capacitance is a function of desired output ripple voltage (ΔVOUT), and follows the relations: For step-up operation: COUT(BULK) ≥ IMAX •VOUT(MAX) – VIN(MIN) VOUT(MAX)

• 1 ∆VOUT •fO where VOUT(MAX) is the DC/DC converter safety limit, and VIN(MIN) is the VIN regulation threshold. If the VIN regula- tion feature is not being used, use the minimum expected operating voltage. For step-down operation, output ripple current is equiva- lent to inductor ripple current (ΔIMAX), so COUT(BULK) fol- lows the relation: COUT(BULK) ≥ ∆IMAX ∆VOUT •fO Switch FET Selection The LTC4020 requires four external N-channel power MOSFETs, as shown in Figure 3. Specified parameters used for power MOSFET selection are: breakdown voltage (V BR(DSS)), threshold voltage (VGS(TH)), on-resistance (RDS(ON)), reverse transfer capac- itance (CRSS), and maximum inductor current (ILMAX). The drive voltage is set by the INTVCC supply pin, which is typically 5V. Consequently, logic-level threshold MOSFETs must be used in LTC4020 applications. T ransition Losses (PTR): During maximum power opera- tion, all 4 switches change state once per oscillator cycle, so the maximum switching transient power losses (PTR) remain constant over condition. P TR(A, B) ≈ (k)(VIN)2 (ILMAX)(CRSS)(fO) P TR(C, D) ≈ (k)(VOUT)2 (ILMAX)(CRSS)(fO) PTR(A, B) is the transition loss for the VIN side switch FETs A and B, and PTR(C,D) is the transition loss for VOUT side switch FETs C and D, with the switch FETs designated as in Figure 3. The constant k, which accounts for the loss caused by reverse recovery current, is inversely proportional to the gate drive current and has a empiri - cal value approximated by k = 1 in LTC4020 applica - tions. ILMAX is the converter maximum inductor current as programmed by the two sense resistors. C RSS, the MOSFET reverse transfer capacitance, is specified by the MOSFET manufacturer . Conductive Losses (PON): Conductive losses are propor- tional to switch duty cycle. The average conductive losses in a switch at maximum inductor current (ILMAX)is: P ON = ILMAX2 • ρT • RDS(ON) • (TON • fO) where ρT is a normalization factor (unity at 25°C) accounting for the significant variation in on-resistance APPLICATIONS INFORMATION

Rev. EFor more information www.analog.com with temperature. For a maximum junction temperature of 125°C, using a value of ρT = 1.5 is reasonable. If VIN > VOUT (step-down conversion): P ON(A) = ILMAX2 • ρT • RDS(ON(A)) • (VOUT/VIN) P ON(B) = ILMAX2 • ρT • RDS(ON(B)) • (1 – VOUT/VIN) P ON(C+D) = ILMAX2 • ρT • RDS(ON(C, D)) If VIN < VOUT (step-up conversion): P ON(A+B) = ILMAX2 • ρT • RDS(ON(A, B)) P ON(C) = ILMAX2 • ρT • RDS(ON(C)) • (1 – VIN/VOUT) P ON(D) = ILMAX2 • ρT • RDS(ON(D)) • (VIN/VOUT) Optional Schottky Diode (Db, Dd) Selection Schottky diodes can be placed in parallel with the syn - chronous FETs B and D, as shown in Figure 3 as Db and Dd. These diodes conduct during the dead time between the conduction of the power MOSFET switches and are intended to prevent the body diode of synchronous switches from storing charge. To maximize effectiveness of the diodes, the inductance between the switches and the synchronous switches must be minimized, so the diodes should be placed adjacent to their corresponding FET switch. The Dd diode also reduces power dissipation in the D switch during periods of reverse current inhibit operation, during which time the D switch is disabled. Load currents are low during reverse inhibit, and diode Db only con - ducts during switch dead times, so both can have current ratings well below the DC/DC converter inductor current maximum. Typically, a diode with an average current rat- ing at or above one-tenth of ILMAX is adequate, provided the diode has an instantaneous current rating that exceeds the maximum inductor current, or ILMAX + ½ ΔIMAX. Db reverse voltage rating must exceed V IN. Dd reverse voltage rating must exceed VOUT. INTVCC LDO Output, and BST1 and BST2 Supplies Power for the top and bottom MOSFET drivers and most other internal circuitry is derived from the INTVCC pin. An internal 5V low dropout regulator (LDO) supplies INTVCC power from the PVIN pin. INTVCC is decoupled to PGND using a 2.2µF ceramic capacitor . The BST1 and BST2 bootstrapped supply pins power internal high side FET gate drivers, which output to pins TG1 and TG2. BST1 provides switch gate drive above the input power supply voltage for switch FET A, and BST2 provides switch gate drive above the output power supply voltage for switch FET D, as designated in Figure 3. These boosted supply pins allows the use of NFET switches for increased conversion efficiency. These bootstrapped sup- plies are regenerated through external Schottky diodes from the INTVCC pin. Connect two low leakage 1A Schottky diode anodes to the INTVCC pin. Connect one Schottky cathode to the BST1 pin. This diode must be rated for reverse voltage standoff exceeding the maximum input supply voltage. Connect the other diode cathode to the BST2 pin. This diode must be rated for reverse voltage standoff exceeding the con - verter safety limit output, VOUT(MAX). Connect a ceramic capacitor from the BST1 pin to the SW1 pin and another from BST2 pin to the SW2 pin. The value of these two capacitors should be at least 50 times greater than the equivalent total gate capacitance of the corresponding switch FET . Total FET gate charge (QG(TOT)) is typically specified at a specific gate-source voltage (VGS(Q)). Using those parameters, the required boost capacitor values (CBST) follow the relation: C BST > 50 • QG(TOT)/VGS(Q) CBST = 1µF is typically adequate for most applications. During low load operation, start-up, and nonoverlap peri- ods, inductor current is conducted by the silicon body diode of the synchronous FET . This diode stores a sig - nificant amount of charge, so when the primary switch turns on for the next switch cycle, reverse recovery cur- rent is conducted by the main switch to discharge this diode. The resultant short-duration current spike can be orders of magnitude greater than the inductor current itself, resulting in an extremely fast dV/dt on the switched node. Consequently, parasitic inductance associated with the switch FET packaging and/or less-than-ideal layout can induce a voltage spike of 10 or more volts at the leading edge of a switching cycle. This can be particularly APPLICATIONS INFORMATION

Figure 10. INTVCC Pass Element SOA (Safe Operating Area)

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5V supply is available (±5%). charges, and fO is the LTC4020 switching frequency. plenty of overhead for regulator dropout voltage. Figure 11. Connection of External Voltage Regulator for

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from the BAT pin to ground to program battery voltages. nal 2.5V voltage reference by the converter error amplifier . where RFB1 and RFB2 are defined as in Figure 12.

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Figure 12. Battery Voltage Programming

tion mode voltage corresponds to 2.5V on the V FB pin. 13.3V respectively for a 6-cell (12V) battery. higher than the maximum battery charge voltage. Table 3. Common Battery Types: Normalized RFB1 resistor that is connected between the CSP and CSN pins. 5A, use a 0.01Ω sense resistor . current flow to and from the battery. dissipation from charge current passing thorough the FET . dissipation while the output is powered by the battery. Figure 13. Instant-On DC/DC Converter Output vs Battery

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Figure 14. VOUT Instant-On Programming Figure 15. Instant-On Charger Current Sense Limit Reduction

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the battery, independent of the battery voltage. error amplifier , the output of which servos the BGATE pin. where RMIN1 and RMIN2 are defined as in Figure 14.

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output, provided the instant-on feature is not desired. Application Circuits section. corresponding to 85% of the battery charge voltage. the maximum charge current is automatically reduced. prevent excessive power dissipation in the PowerPath FET .

Figure 16. Using the RNG/SS Pin for Digital Control of

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can sink up to 5mA when enabled. cycle, and the STAT2 pin is pulled low during NTC faults. Table 4. Status Pins Charging State Figure 18. Using the RNG/SS Pin for Soft-Start

4020 F18

Figure 17. Driving the RNG/SS Pin with a Current

4020 F17

bad battery and NTC fault conditions.

Rev. E For more information www.analog.com high impedance during the float charging period and dur- ing NTC or bad battery faults. The STAT2 pin is pulled low during bulk and float charging stages, and is high imped- ance during the absorption charging stage and during NTC or bad battery faults. The STAT1 and STAT2 status pins are binary coded, and signal following the table below, where ON indicates pin pulled low, and OFF indicates pin high impedance: TIMER: C/10 Termination The LTC4020 supports a low current based termination scheme. This termination mode is engaged by shorting the TIMER pin to ground. When in CC/CV charge mode, a battery charge cycle ter- minates when the current output from the charger falls to below one-tenth the maximum charge current, or ICSMAX, as programmed with RCS. The C/10 threshold current cor- responds to 5mV across RCS. During lead-acid charging, the LTC4020 initiates float charging when the absorption stage charge cur - rent is reduced to one-tenth of the programmed maximum current. When charging in CC mode, the current source function remains active indefinitely. There is no provision for bad battery detection if C/10 termination is used. TIMER: Timed Functions The LTC4020 supports timer based functions, where bat- tery charge cycle control occurs after a specific amount of time elapses. Timer termination is engaged when a capacitor (CTIMER) is connected from the TIMER pin to ground. C TIMER for a desired end-of-cycle time (T EOC) follows the relation: C TIMER = TEOC • 6.87 • 10–2 (µF) where TEOC is hours. A typical timer T EOC for Li-Ion charge cycle termination is three hours, which requires a 0.2µF timer capacitor . The timer cycle starts when the charger transitions from constant-current to constant-voltage charging, thus, termination at the end of the timer cycle only occurs if the charging cycle was successful. When timer termination is used, the STAT1 status pin is pulled low during a charg- ing cycle until the battery charge current falls below the C/10 threshold. The STAT1 pin stays high impedance with charge currents below C/10, but the charger continues to top off the battery until timer TEOC, when the LTC4020 terminates the charging cycle and the PowerPath FET dis- connects the battery from the DC/DC converter output. During lead-acid charging, the timer acts as an absorp - tion mode safety timer . Normally, the LTC4020 initiates float charging when the absorption stage charge current is reduced to one-tenth of the programmed maximum current, however , the maximum duration of absorption charging is limited by the timer . If the charge current does not fall to one-tenth of the programmed maximum current by TEOC, the LTC4020 forces the battery charger to begin float mode charging. A typical timer T EOC for lead-acid charging is six to eight hours, which is accommodated by a 0.47µF timer capacitor . When charging in CC mode, after charge termination, once the timer reaches T EOC and the charge cycle ter - minates, input power or SHDN must be cycled to initiate another battery charge cycle. A bad battery detection function is available during CC/ CV or lead-acid charging. This fault condition is achieved if the battery does not respond to preconditioning (V FB < 1.75V), such that the charger remains in (or enters) pre- condition mode after one-eighth of the programmed TEOC time. A bad battery fault halts the charging cycle, and the fault condition is reported on the status pins. The bad battery fault remains active until the battery voltage rises above the precondition threshold, or until power or SHDN is cycled. Battery Temperature Qualified Charging: NTC The LTC4020 can accommodate battery temperature monitoring by using an NTC (negative temperature co- efficient) thermistor close to the battery pack. The tem - perature monitoring function is enabled by connecting a 10k, β = 3380 NTC thermistor from the NTC pin to ground. If the NTC function is not desired, leave the pin unconnected. APPLICATIONS INFORMATION

Rev. EFor more information www.analog.com The NTC pin sources 50µA, and monitors the voltage dropped across the 10k thermistor . When the voltage on this pin is above 1.35V (0°C) or below 0.3V (40°C), the battery temperature is out of range, and the LTC4020 trig- gers an NTC fault. The NTC fault condition remains until the voltage on the NTC pin corresponds to a temperature within the 0°C to 40°C range. Both hot and cold thresh - olds incorporate hysteresis that corresponds to 5°C. If higher operational charging temperatures are desired, the temperature range can be expanded by adding series resistance to the 10k NTC resistor . Adding a 910Ω resistor will increase the effective HOT temperature threshold to 45°C. The effect of this additional resistance on the COLD threshold is negligible. During an NTC fault, charging is halted and an NTC fault is indicated on the status pins. If timer termination is enabled, the timer count is suspended and held until the fault condition is relieved. The RNG/SS pin is also pulled low during this fault, to accommodate a graceful restart, in the event that a soft-start function is being incorporated (see DRNG/SS: Dynamic Current Limit Adjust and RNG/ SS: Soft-Start section). DC/DC CONVERTER: EXTERNAL COMPENSATION AND FIL TERING COMPONENTS The LTC4020 average current mode architecture employs two integrating compensation nodes. The current setting loop is compensated at the output of the current sense amplifier on the VC pin, generally with a series R-C net - work (RVC, CVC). The voltage generated on the VC pin is compared with an internal ramp, providing control of the converter duty cycle. The voltage loop is compensated at the output of the error amplifier on the ITH pin, generally with a series R-C net- work (RITH, CITH). The voltage on the ITH pin is imposed onto the current sense amplifier , setting the current level to which the current loop will servo. While determining compensation components, the LTC4020 should initially be configured to eliminate any functional contribution from the Battery Charger Section. This can be easily accomplished by connecting the NTC pin to ground, which disables all battery charging functions and puts the PowerPath FET into a high impedance state. The current loop compensation (VC pin) transfer func - tion crossover frequency is typically set to approximately one-half of the switching frequency ; the voltage loop compensation (ITH pin) transfer function crossover fre - quency is typically set to approximately one-tenth of the switching frequency. Compensation values must be tested at high and low input voltage operational limits, and also V IN ~ VOUT, so that stable operation during all switching modes (buck, boost, buck-boost) is verified. If a network analyzer is not available for determining compensation values, use procedures as outlined in Application Note 19 for adjusting compensation. VC pin compensation: 1. VNTC = VFBMAX = 0V 2. Fix VIN at typical voltage. 3. Fix VOUT at VFB regulation voltage. A charged battery, battery simulator , or a 2-quadrant power supply can be used for VOUT. 4. Impose 1V to 1.5V square wave (1kHz) on ITH pin 5. Monitor inductor current using current probe 6. Adjust compensation values as per Application Note 19 until response is critically damped ITH pin compensation: 1. VNTC = 0V (disables charger) 2. Bring to regulation (VFBMAX = 2.75V) 3. Step load current on output (25% to 75% of IMAX) 4. Monitor VOUT voltage 5. Adjust compensation values as per Application Note 19 until response is critically damped and settled in ~10 to 25 cycles 6. VNTC = 0.8 (enable charger) 7. Exercise battery charger and verify stability in all modes APPLICATIONS INFORMATION

Figure 20. CSN/CSP Ripple Suppression age, and as such is controlled by a very slow moving node. to the VFB input, producing a low frequency pole. current sensing, and can also cause unstable operation. at the CSP and CSN pins to less than 1mVP-P. Figure 21. Instant-On/Ideal Diode Compensation

4020 F21

4020 F20

Figure 19. VFB Ripple Suppression

4020 F19

PowerPath FET by servoing the voltage at the BGATE pin.

Rev. EFor more information www.analog.com used by the IC. Typically, high current paths and transients from the input supply and any local drive supplies must be kept isolated from SGND, to which sensitive circuits such as the error amp reference and the current sense circuits are referred. Effective grounding can be achieved by considering switch current in the ground plane, and the return cur - rent paths of each respective bypass capacitor . The V IN bypass return, INTVCC bypass return, and the sources of the ground-referred switch FETs carry PGND currents. SGND originates at the negative terminal of the V OUT bypass capacitor , and is the small signal reference for the LTC4020. Do not be tempted to run small traces to separate ground paths. A good ground plane is important as always, but PGND referred bypass elements must be oriented such that transient currents in these return paths do not corrupt the SGND reference. During the dead time between synchronous switch and main switch conduction, the body diode of the synchro - nous FET conducts inductor current. Commutating the body diode requires a significant charge contribution from the main switch during initiation of main switch, creat - ing a current spike in the main switch. At the instant the body diode commutates, a current discontinuity is cre - ated between the inductor and main switch, with parasitic inductance causing the switch node to transition in response to this discontinuity. High currents and exces- sive parasitic inductance can generate extremely fast δV/ δt times during this transition. These fast δV/δt transi- tions can sometimes cause avalanche breakdown in the synchronous FET body diode, generating shoot-through currents via parasitic turn-on of the synchronous FET . Layout practices and component orientations that mini - mize parasitic inductance on the switched nodes is critical for reducing these effects. Orient power path components such that current paths in the ground plane do not cross through signal ground areas. Power ground currents are controlled on the LTC4020 via the PGND pin, and this ground references the high cur - rent synchronous switch drive components, as well as the local INTV CC supply. It is important to keep PGND APPLICATIONS INFORMATION and SGND voltages consistent with each other . Separating these grounds with thin traces is not recommended. When a ground referenced switch FET is turned off, gate drive currents return to the LTC4020 PGND pin from the switch FET source. The BOOST supply refresh surge cur- rents also return through this same path. The switch FETs must be oriented such that these PGND return currents do not corrupt the SGND reference. The high δi/δt loop formed by the switch MOSFETs and the input capacitor (CVIN) should have short wide traces to minimize high frequency noise and voltage stress from inductive ringing. Surface mount components are pre - ferred to reduce parasitic inductances from component leads. Switch path currents can be controlled by orienting switch FETs, the switched inductor , and input and output decoupling capacitors in close proximity to each other . Locate the INTVCC, BST1, and BST2 decoupling capaci - tors in close proximity to the IC. These capacitors carry the switch FET gate drive currents. Locate the small sig- nal components away from high frequency switching nodes (TG1, BG1, TG2, BG2, SW1, SW2, BST1, BST2, and INTVCC). High current switching nodes are oriented across the top of the LTC4020 package to simplify layout and prevent corruption of the SGND reference. Locate the output and battery charger feedback resistors in close proximity to the LTC4020 and minimize the length of the high impedance feedback nodes. The SENSV IN and SENSTOP traces should be routed together and SENSBOT and SENSGND should be routed together . Keep these traces as short as possible, and avoid corruption of these lines by high current switching nodes. The LTC4020 packaging has been designed to efficiently remove heat from the IC via the exposed pad on the back- side of the package. The exposed pad is soldered to a copper footprint on the PCB. The exposed pad is electri- cally connected to SGND, so a good connection to a PCB ground plane effectively reduces the thermal resistance of the IC case to ambient air . Please refer to Application Note 136 , which discusses guidelines, techniques, and considerations for switching power supply PCB design and layout.

Rev. E For more information www.analog.com APPLICATIONS INFORMATION LTC4020 Constant-Current/Constant-Voltage (CC/CV) Charging Diagram POWER AVAILABLE? INDICATE NOT CHARGING BGATE PULLED LOW VFB > 2.5 – ε? VFB > 1.75? YES NO NO NO NO NO NO NO NO NO NO NO NO NO YES

4020 CD01

VFB < 1.75? VFB = 2.4375V NTC OUT-OF-RANGE? CHARGE AT CONSTANT-CURRENT INDICATE CHARGING TRICKLE CHARGE (7%) TIMER ACTIVE? BGATE PULLED HIGH INDICATE BAD BATTERY FAUL T INDICATE NTC FAUL T ENABLE IDEAL DIODE FUNCTION TIMERS ACTIVE? PAUSE TIMERS CHARGE TO FIXED VOL TAGE TIMER ACTIVE? RUN SAFETY TIMER SAFETY TIMER AT EOC? STOP CHARGING INDICATE NOT CHARGING STOP CHARGING IBAT < C/10? IBAT < C/10? START CLEAR LOW BATTERY AND SAFETY TIMERS RUN LOW BATTERY TIMER BGATE PULLED LOW INDICATE NOT CHARGING INDICATE CHARGING TERMINATED VFB < 2.5 – ε? INDICATE NOT CHARGING ENABLE IDEAL DIODE FUNCTION YES YES YES YES YES STOP CHARGING NO TIMER AT 1/8 EOC? YES VFB = 2.4375? NO YES

Rev. EFor more information www.analog.com APPLICATIONS INFORMATION LTC4020 Lead-Acid Charging Diagram POWER AVAILABLE? INDICATE NOT CHARGING BGATE PULLED LOW SET ABSORPTION REFERENCE (2.5V) VFB < 2.5 – ε? VFB < 1.75? VFB > 1.75? YES NO NO NO NO NO NO NO NO NO NO NO NO NO YES

4020 CD02

VFB < 2.125? VFB = 2.4375V NTC OUT-OF-RANGE? CHARGE AT CONSTANT-CURRENT BGATE PULLED LOW SET ABSORPTION REFERENCE (2.5V) TIMER ACTIVE? STOP CHARGING BGATE PULLED HIGH INDICATE NOT CHARGING INDICATE NOT CHARGING ENABLE IDEAL DIODE FUNCTION TIMERS ACTIVE? PAUSE TIMERS CHARGE TO FIXED VOL TAGE TIMER ACTIVE? RUN SAFETY TIMER SAFETY TIMER AT EOC? SET FLOAT REFERENCE (2.3125V) INDICATE FLOAT CHARGING STOP CHARGING IBAT < C/10? IBAT < C/10? START CLEAR LOW BATTERY AND SAFETY TIMERS TRICKLE CHARGE (7%) INDICATE BULK CHARGING INDICATE ABSORPTION CHARGING INDICATE BULK CHARGING FLOAT REFERENCE SET (2.3125)? YES YES YES NO YES YES YES YES RUN LOW BATTERY TIMER TIMER AT 1/8 EOC?

Rev. E For more information www.analog.com APPLICATIONS INFORMATION LTC4020 Constant-Current Charging Diagram POWER AVAILABLE? INDICATE NOT CHARGING BGATE PULLED LOW CLEAR TIMER NO NO NO AT EOC? NTC OUT-OF-RANGE? CHARGE AT CONSTANT-CURRENT BGATE PULLED LOW TIMER ACTIVE? INDICATE NTC FAUL T ENABLE IDEAL DIODE FUNCTION TIMERS ACTIVE? PAUSE TIMER STOP CHARGING START INDICATE CHARGING RUN TIMER YES YES YES NO NO YES YES INDICATE NOT CHARGING ENABLE IDEAL DIODE FUNCTION STOP CHARGING

Rev. EFor more information www.analog.com TYPICAL APPLICATION 5V to 30V to 6-cell lead-acid PowerPath charger/system supply. 6A inductor current limit with 2.5A battery charge current limit. Instant-on functionality incorporated for battery voltages below 12.25V, 14.4V absorption voltage, 13.3V float voltage,and 15.6V maximum output voltage (Instant-On and NTC fault only). Status pins light LEDs for visible charge-state monitoring RSENSEA 0.008 Si7272DP Si7272DP Si7272DP CMSH3-40MA Si7272DP RSENSEB 0.008 56µF VIN 5V TO 30V L TC4020 SGNDBACK PGND 4.7µF SBR0560S1 RT, 130k PVIN BG1 SW1 TG1 BST1 SGND SENSGND 95.3k 2nF 2nF SENSBOT SENSTOP SENSVIN RT SHDN VIN_REG MODE STAT1 STAT2 TIMER RNG_SS 6-CELL LEAD-ACID (12V)

4020 TA02

1µF 284k 100k 1µF 0.033µF 33k 2.7k 15µH XAL1010-153MEB SBR0560S1 BZX84C6V2L 680pF 100/uni03A9 Si7135DP RCS 0.02/uni03A9100/uni03A9 1µF 20k 95.3k RNTC 10k 20k 0.33µF 4.7µF 0.1µF 56µF VOUT 2.7k

Rev. E For more information www.analog.com TYPICAL APPLICATION 15V to 55V to 6-cell Li-Ion PowerPath charger/system supply. 6A inductor current limit with 2.5A battery charge current limit. Instant-on functionality for battery voltages below 20.4V, 24V charge termination voltage, and 26.4V maximum output voltage. Status pins light LEDs for visible charge-state monitoring RSENSEA 0.008 Si7960DP Si7960DP Si7960DP MBRS360 Si7960DP RSENSEB 0.008 4.7µF VIN 15V TO 55V LTC4020 SGNDBACK PGND 10µF SBR0560S1 RT, 100k PVIN BG1 SW1 TG1 BST1 SGND 100pF SENSGND SENSBOT SENSTOP SENSVIN RT SHDNSHDN VIN_REG MODE STAT1 STAT2 TIMER RNG_SS

4020 TA03

56µF 0.1µF 10nF 1µF 56k XAL1010-153MEB 15µH SBR0560S1 BZX84C6V2L 680pF 68pF 47k 100/uni03A9 RCS 0.02/uni03A9 Si7461DP 215k 4.7µF 56µF VOUT 24V AT 3.5A MAX 0.033µF 2.7k 2.7k 0.2µF 105k 1µF 100/uni03A9 24.9k 6-CELL Li-ION (24V) RNTC 10k 24.9k 2.2µF 4.7/uni03A9 215k 1nF 10k

Rev. EFor more information www.analog.com TYPICAL APPLICATION 9V to 55V to 9-cell lead-acid (18V) charger/system supply with no PowerPath. External 5V regulator for boosted supplies. 5A inductor current limit with 1.67A battery charge current limit. 21.5V absorption voltage output, 19.9V float voltage output RSENSEA 0.01 RSENSEB 0.01 Si7960DP Si7272DPCMSH3-40MA Si7272DP Si7850DP 56µF VIN 9V TO 55V LTC4020 SGNDBACK PGND 4.7µF RT, 100k 0.033µF MODE SW1 BG1 TG1 BST1 SGND SENSGND SENSBOT SENSTOP SENSVIN RT SHDN VIN_REG PVIN TIMER 9-CELL LEAD-ACID (18V)

4020 TA04

1µF 1.5nF 1µF 249k 100k 43k 43k 15µH BZX84C6V2L 680pF 100/uni03A9 1µF 0.1µF 4.7µF VOUT 56µF XAL1010-153MEB 100/uni03A9 RCS 0.03/uni03A9 100pF 0.33µF 75.9k 825k 226k ADJ OUTIN OUTIN SHDN L T3012EDE GND GND PINS NOT USED IN THIS CIRCUIT: FBG I LIMIT NTC RNG_SS ST AT1, STAT2 *SBR0560S1

Rev. E For more information www.analog.com 5.00 ±0.10 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS PIN 1 TOP MARK (SEE NOTE 6) BOTTOM VIEW—EXPOSED PAD

5.50 REF

5.15 ±0.10 7.00 ±0.10 0.75 ±0.05 R = 0.125 TYP R = 0.10 TYP 0.25 ±0.05 (UH) QFN REF C 1107

0.50 BSC

0.200 REF

0.00 – 0.05 RECOMMENDED SOLDER PAD LAYOUT APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

3.00 REF

3.15 ±0.10 0.40 ±0.10 0.70 ±0.05

5.5 REF

3.00 REF 3.15 ±0.05 4.10 ±0.05 6.10 ±0.05 7.50 ±0.05 0.25 ±0.05 PACKAGE OUTLINE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701 Rev C) PACKAGE DESCRIPTION

Rev. EFor more information www.analog.com

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 01/14 Changed VIN to PVIN. Modified ISENSTOP Operating Current spec and Error Amp T ransconductance spec. Changed C/10 Detection Enable Units, C/10 Detection Hysteresis spec, and conditions for Gate Clamp Voltage. Changed Conditions for BGATE tests and conditions for Pin Current (Disabled) spec. Changed cathode to anode for BST1 and anode to cathode for BST1. Modified equations for TEOC and TPRE and associated TIMER text. Modified equations for RFB1/RFB2 and RMIN1/RMIN2. Changed cathode to anode for BST2 and anode to cathode for BST2. Modified Error Amplified T ransconductance. Modified step-up and step-down equations in Switch FET section. Modified CTIMER equation and associated text. Modified Typical Applications circuit. Modified Typical Application circuit to 12-cell. 3-5 B 09/14 Added (Application Circuit on Page 37) to efficiency curve title. Added Ω unit to RFBG specification. Changed INTVCC Short-Circuit Current Limit vs Temperature curve y-axis units to mA. Added text to the end of the NTC (Pin 16) section. Corrected formula: (VOUTMAX/2.75) – 1. Changed BST1 on lower-right of block diagram to BST2; Insert (VSENS) below 2mV near VC pin. Added 2V Zener diode symbol from NTC pin (cathode) to ground (anode). Added average to first line; changed Charge to Average Inductor in Figure 8 title. Changed inductor to charge. Added ground symbol to bottom of IC symbol (backside connection). Flipped PMOS symbol vertically (Si7461DP); add ground symbol to bottom of IC symbol (backside connection). Added ground symbol to bottom of IC symbol (backside connection). Moved connection of BZX84C6V2L anode from BG2 to SW2 (diode between BST2 and SW2); add ground symbol to bottom of IC symbol (backside connection). C 09/15 Added pin names to Typical Application IC drawing. Added text to end of SENSBOT (5) Pin Functions section. Changed text in RNG/SS section: Inductor to Charge. Changed Operation section to a 0.47µF capacitor on the TIMER pin is typically used, which generates a 6.8-hour absorption stage safety timeout. Changed CSENSBOT ,SENSGND to CSENSB. Changed CSN to CSN. Replaced RCS with RCSZ in the text and in Figure 21. Replaced RSENSE with RCS in Figure 21. Replaced RSENSE with RCS in schematic. 37-39, 42 D 04/16 Modified bulk capacitance equation. 24 E 3/23 Fixed major formatting issues (renumbered figures, added table titles, fixed crossed references). Changed umho to µS and added RNG/SS pin specifications in the Electrical Characteristics table. Changed inductor to battery charge in the RNG/SS (Pin 15) description. Removed (V) in the absorption voltage equation. Modified the VFBMAX (Pin 26) description. Modified the INTVCC (Pin 34) description. Changed μohm to μS in Figure 1 and Figure 2 (Block Diagrams). Modified second paragraph in the CC Charging Overview (MODE = NC) section. Changed high pass to low-pass in the Overcurrent Detection section. Changed cannot to must not. Changed Inductor Selection section (added IMAX equation, modified LMIN equations). Added CRSS description to the PTR equation description paragraph. Implemented major modifications to the External Power for BST1 and BST2 Supplies section. Corrected typical application schematic. All 14-15 Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Rev. E For more information www.analog.com  ANALOG DEVICES, INC. 2013-2023 www.analog.com RELATED PARTS TYPICAL APPLICATION Remote 24V to 55V (48V system) input to 12-cell Li-Ion (48V) PowerPath charger/system supply. 5A inductor current limit with 2.5A battery charge current limit. Minimum VIN is 24V as input regulation limits voltage loss due to line impedance. Battery termination voltage is 48V with maximum output voltage of 52.8V. Instant-on functionality limits minimum regulated output voltage to 40.8V PART NUMBER DESCRIPTION COMMENTS LTC3789 High Efficiency, Synchronous, 4-Switch Buck-Boost Controller Improved LTC3780 with More Features LT3845 High Voltage Synchronous Current Mode Step-Down Controller For Medium/High Power , High Efficiency Supplies LT3650 High Voltage 2A Monolithic Li-Ion Battery Charger 3mm × 3mm DFN-12 and MSOP-12 Packages LT3651 High Voltage 4A Monolithic Li-Ion Battery Charger 4A Synchronous Version of LT3650 Family LT3652/LT3652HV Power T racking 2A Battery Chargers Multi-Chemistry, Onboard Termination LTC4009 High Efficiency, Multi-Chemistry Battery Charger Low Cost Version of LTC4008, 4mm × 4mm QFN-20 LTC4012 High Efficiency, Multi-Chemistry Battery Charger with PowerPath Control Similar to LTC4009 Adding PowerPath Control LT3741 High Power , Constant-Current, Constant-Voltage, Step-Down Controller Thermally Enhanced 4mm × 4mm QFN and 20-Pin TSSOP LT8705 80VIN/VOUT Synchronous Buck-Boost 4-Switch Controller Single Inductor , TSSOP-38 and 5mm × 7mm QFN-38 RSENSEA 0.01 Si7850DP Si7850DP Si7850DP Si7850DP RSENSEB 0.01 VIN 24V TO 55V L TC4020 SGNDBACK PGND RT, 100k PVIN BG1 SW1 TG1 BST1 SGND SENSGND SENSBOT SENSTOP SENSVIN RT SHDN VIN_REG MODE TIMER RNG_SS 12-CELL Li-ION (48V)

4020 TA05

56µF 1µF 191k 10k 12k STAT1 STAT2 1µF SBR0560S1 4.7µF 33k 100/uni03A9 RCS 0.02/uni03A9 Si7465DP SBR0560S1 BZX84C6V2L 680pF 100/uni03A9 365k 1.5nF2nF 0.33µF 356k20k 20k 1µF RNTC 10k 0.1µF 4.7µF 56µF VOUT IHLP-5050FD-5A MBRS360 22µH 0.033µF