LTC4012-3

LTC4012-3 - High Efficiency, Multi-Chemistry Battery Charger with PowerPath Control

Document overview

• Manufacturer or author: Linear Technology Corporation
• PDF pages: 28

Technical content

FeaTures

applicaTions

DescripTion

High Efficiency, Multi-Chemistry Battery Charger with PowerPath Control The L TC®4012-3 is a constant-current/constant-voltage battery charger controller. It uses a synchronous quasi- constant frequency PWM control architecture that will not generate audible noise with ceramic bulk capacitors. Charge current is set by external resistors and can be monitored as an output voltage across the programming resistor. With no built-in termination, the L TC4012-3 charges a wide range of batteries under external control. The L TC4012-3 features fully adjustable output voltage. For charge management and safety, the IC includes an input P-channel MOSFET ideal diode controller, battery (output) overvoltage protection, reverse charge current protection, PWM soft-start and robust non-overlap control for an all N-channel MOSFET PWM power stage. The device includes AC adapter input current limiting, which maximizes the charge rate for a fixed input power level. An external sense resistor programs the input current limit, and the ICL status pin indicates reduced charge current as a result of AC adapter current limiting. Ideal diode control at the adaptor input improves charger efficiency. The CHRG status pin is active during all charging modes, including special indication for low charge current. n General Purpose Battery Charger Controller n Efficient 550kHz Synchronous Buck PWM Topology n ±0.5% Output Float Voltage Accuracy n Programmable Charge Current: 4% Accuracy n Programmable AC Adapter Current Limit: 3% Accuracy n No Audible Noise with Ceramic Capacitors n INFET Low Loss Ideal Diode PowerPath™ Control n Wide Input Voltage Range: 6V to 28V n Wide Output Voltage Range: 2V to 28V n Indicator Outputs for Charging, C/10 Current Detection and Input Current Limiting n Analog Charge Current Monitor n Micropower Shutdown n 20-Pin 4mm × 4mm × 0.75mm QFN Package n Notebook Computers n Portable Instruments n Battery Backup Systems Efficiency at DCIN = 20V CLP FROM ADAPTER 13V TO 20V 0.1µF 5.1k 25m/uni03A9 3.01k 0.1µF 6.8µH 20µF 33m/uni03A9 INFET 0.1µF 2µF 0.1µF 6.04k 26.7k L TC4012-3 DCIN CHRG ICL SHDN ITH PROG CLN BOOST TGATE SW INTVDD BGATETO/FROM MCU GND CSP CSN BAT FBDIV VFB 20µF POWER TO SYSTEM 4.7nF 32.8k 4012-3 TA01 12.3V Li-Ion BATTERY 3.01k 301k + CHARGE CURRENT (A) EFFICIENCY (%) POWER LOSS (mW) 100 100 1000 10000 0.5 1 1.5 2 4012-3 TA02 2.5 3 L TC4012 L TC4012-3 GND X ACP X PIN 5 NAME VOUT = 12.3V RSENSE = 33m/uni03A9 RIN = 3.01k RPROG = 26.7k EFFICIENCY POWER LOSS PART L, L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks and PowerPath and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5723970.

pin conFiguraTionabsoluTe MaxiMuM raTings Operating Temperature Range (Note 1) 20 19 18 17 16 6 7 8 TOP VIEW UF PACKAGE 20-LEAD (4mm s 4mm) PLASTIC QFN 9 10 15CLN CLP INFET DCIN GND CSP CSN PROG ITH BAT BOOST TGATE SW INTV DD BGATE SHDN CHRG ICL V FB FBDIV TJMAX = 125°C, JA = 37°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE L TC4012CUF-3#PBF L TC4012CUF-3#TRPBF 40123 20-Lead (4mm × 4mm) Plastic QFN 0°C to 85°C L TC4012IUF-3#PBF L TC4012IUF-3#TRPBF 40123 20-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Consult L TC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Charge Voltage Regulation VTOL VBAT Accuracy (See Test Circuits) C-Grade I-Grade l l –0.5 –0.8 –1.0 0.5 0.8 1.0 I VFB VFB Input Bias Current VFB = 1.2V ±20 nA RON FBDIV On Resistance ILOAD = 100µA l 85 190 Ω ILEAK-FBDIV FBDIV Output Leakage Current SHDN = 0V , FBDIV = 0V l –1 0 1 µA VBOV VFB Overvoltage Threshold l 1.235 1.281 1.32 V Charge Current Regulation ITOL Charge Current Accuracy with RIN = 3.01k, 6V < BAT < 18V RPROG = 26.7k C-Grade I-Grade l l –9.5 9.5 V SENSE = 0mV , PROG = 1.2V –12.75 –11.67 –10.95 µA AI Current Sense Amplifier Gain (PROG ∆I) with R IN = 3.01k, 6V < BAT < 18V VSENSE Step from 0mV to 5mV , PROG = 1.2V VCS-MAX Maximum Peak Current Sense Threshold Voltage per Cycle (R IN = 3.01k) ITH = 2V , C-Grade ITH = 2V , I-Grade ITH = 5V l l l 140 125 195 325 250 265 430 mV mV mV V C10 C/10 Indicator Threshold Voltage PROG Falling 340 400 460 mV VREV Reverse Current Threshold Voltage PROG Falling 180 253 295 mV Input Current Regulation VCL Current Limit Threshold CLP – CLN C-Grade I-Grade l l 100 100 103 104 108 mV mV mV I CLN CLN Input Bias Current CLN = CLP ±100 nA VICL ICL Indicator Threshold (CLP – CLN) – VCL –8 –5 –2 mV CLP Supply OVR Operating Voltage Range 6 28 V VUVLO CLP Undervoltage Lockout Threshold CLP Increasing l 4.65 4.85 5.25 V VUV(HYST) UVLO Threshold Hysteresis 200 mV ICLPO CLP Operating Current CLP = 20V, No Gate Loads 2 3 mA Shutdown V IL SHDN Input Voltage Low l 300 mV VIH SHDN Input Voltage High l 1.4 V RIN SHDN Pull-Down Resistance 40 kΩ ICLPS CLP Shutdown Current CLP = 12V, DCIN = 0V SHDN = 0V l 15 350 500 µA µA I LEAK-BAT BAT Leakage Current SHDN = 0V or DCIN = 0V, 0V ≤ CSP = CSN = BAT ≤ 18V l –1.5 0 1.5 µA ILEAK-CSN CSN Leakage Current SHDN = 0V or DCIN = 0V, 0V ≤ CSP = CSN = BAT ≤ 20V l –1.5 0 1.5 µA ILEAK-CSP CSP Leakage Current SHDN = 0V or DCIN = 0V, 0V ≤ CSP = CSN = BAT ≤ 20V l –1.5 0 1.5 µA ILEAK-SW SW Leakage Current SHDN = 0V or DCIN = 0V, 0V ≤ SW ≤ 20V l –1 0 2 µA elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. DCIN = 20V, BAT = 12V, GND = 0V unless otherwise noted. (Note 2)

elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. DCIN = 20V, BAT = 12V, GND = 0V unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS INTVDD Regulator INTVDD Output Voltage No Load l 4.85 5 5.15 V ∆VDD Load Regulation IDD = 20mA –0.4 –1 % IDD Short-Circuit Current (Note 5) INTVDD = 0V 50 85 130 mA Switching Regulator VACP AC Present Charge Enable Threshold Voltage DCIN – BAT, DCIN Rising C-Grade I-Grade l l 350 300 500 650 700 mV mV I ITH ITH Current ITH = 1.4V –40/+90 µA fTYP Typical Switching Frequency 467 550 633 kHz fMIN Minimum Switching Frequency CLOAD = 3.3nF 20 25 kHz DCMAX Maximum Duty Cycle CLOAD = 3.3nF 98 99 % tR-TG TGATE Rise Time CLOAD = 3.3nF , 10% – 90% 60 110 ns tF-TG TGATE Fall Time CLOAD = 3.3nF , 90% – 10% 50 110 ns tR-BG BGATE Rise Time CLOAD = 3.3nF , 10% – 90% 60 110 ns tF-BG BGATE Fall Time CLOAD = 3.3nF , 90% – 10% 60 110 ns tNO TGATE, BGATE Non-Overlap Time CLOAD = 3.3nF , 10% – 10% 110 ns PowerPath Control IDCIN DCIN Input Current 0V ≤ DCIN ≤ CLP l –10 60 µA VFTO Forward Turn-On Voltage (DCIN Detection Threshold) DCIN-CLP , DCIN Rising l 15 60 mV VFR Forward Regulation Voltage DCIN-CLP l 15 25 35 mV VRTO Reverse Turn-Off Voltage DCIN-CLP , DCIN Falling l –45 –25 –15 mV VOL(INFET) INFET Output Low Voltage, Relative to CLP DCIN-CLP = 0.1V, IINFET =1µA –6.5 –5 V VOH(INFET) INFET Output High Voltage, Relative to CLP DCIN-CLP = –0.1V, IINFET =–5µA –250 250 mV tIF(ON) INFET Turn-On Time To CLP-INFET > 3V, CINFET = 1nF 85 180 µs tIF(OFF) INFET Turn-Off Time To CLP-INFET < 1.5V, CINFET = 1nF 2.5 6 µs Indicator Outputs V OL Output Voltage Low ILOAD = 100µA, PROG = 1.2V 500 mV ILEAK Output Leakage SHDN = 0V, DCIN = 0V, VOUT = 20V l –10 10 µA IC10 CHRG C/10 Current Sink CHRG = 2.5V l 15 25 38 µA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The L TC4012C-3 is guaranteed to meet performance specifications over the 0°C to 85°C operating temperature range. The L TC4012I-3 is guaranteed to meet performance specifications over the –40°C to 125°C operating temperature range. Note 3: Operating junction temperature T J (in °C) is calculated from the ambient temperature TA and the total continuous package power dissipation PD (in watts) by the formula TJ = TA + (θJA • PD). Refer to the Applications Information section for details. Note 4: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to GND, unless otherwise specified. Note 5: Output current may be limited by internal power dissipation. Refer to the Applications Information section for details.

(500mV/DIV) LOAD STATE TIME (1ms/DIV) CLP = 20V VOUT = 12.3V 4012-3 G06 DISCONNECT RECONNECT 12. 1V 1A Typical perForMance characTerisTics Efficiency at DCIN = 20V , BAT = 8V VFB Line Regulation CHARGE CURRENT (A) EFFICIENCY (%) POWER LOSS(mW) 100 100 1000 10000 0.5 1 1.5 2 4012-3 G01 2.5 3 POWER LOSS EFFICIENCY RSENSE = 33m/uni03A9 RIN = 3.01k Efficiency at DCIN = 20V , BAT = 12V CHARGE CURRENT (A) EFFICIENCY (%) POWER LOSS(mW) 100 100 1000 10000 0.5 1 1.5 2 4012-3 G02 2.5 3

95 EFFICIENCY

RSENSE = 33m/uni03A9 RIN = 3.01k Efficiency at DCIN = 20V , BAT = 16V CHARGE CURRENT (A) EFFICIENCY (%) POWER LOSS(mW) 100 100 1000 10000 0.5 1 1.5 2 4012-3 G03 2.5 3 EFFICIENCY POWER LOSS RSENSE = 33m/uni03A9 RIN = 3.01k CLP (V) VFB ERROR (%) 0.02 0.06 0.10 4012-3 G04 –0.02 –0.06 0.04 0.08 –0.04 –0.08 –0.10 10 15 20 30 L TC4012-3 TEST CIRCUIT BAT (V) RON (/uni03A9) 100 150 175 200 10 20 25 300 4012-3 G05 125 5 15 225 250 275 CLP = BAT + 3V (CLP ≥ 6V) FBDIV Pin RON vs Battery Voltage (TA = 25°C unless otherwise noted. L = IHLP-2525 6.8µH)

Charge Current Line Regulation Input Current Limit DCIN (V) –0.5 CHARGE CURRENT ERROR (%) –0.4 –0.2 –0.1 0.5 0.2 10 15 4012-3 G08 –0.3 0.3 0.4 0.1 20 25 ICHG = 1A ICHG = 2A ICHG = 3A BAT = 6V RSENSE = 33m/uni03A9 RIN = 3.01k Charge Current Load Regulation BAT (V) 11.0 CHARGE CURRENT (A) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 –0.5 12.6 4012-3 G09 11.4 11.8 12.2 13.0 ICHG = 3A ICHG = 2A ICHG = 1A DCIN = 20V RSENSE = 33m/uni03A9 RIN = 3.01k SYSTEM LOAD (A) CURRENT (A)0.5 1.0 1.5 1.5 2.5 4012-3 G10 –0.5 –1.0 0.5 1.0 2.0 2.0 2.5 3.0 IIN ICHG ICL STATE 2.5A BULK CHARGE 2.1A INPUT CURRENT LIMIT PWM Soft-Start ICHG 2A/DIV TIME (500µs/DIV) 4012-3 G11 ITH 1V/DIV PROG 1V/DIV SHDN 5V/DIV TIME (80ns/DIV) EXTERNAL FET DRIVE (1V/DIV) 4012-3 G12 TGATE BGATE Typical perForMance characTerisTics (TA = 25°C unless otherwise noted. L = IHLP-2525 6.8µH) Charge Current Accuracy BAT (V) CHARGE CURRENT ERROR (%) 10 8 20 24 22 4012-3 G07 6 4 2 14 12 16 18 DCIN = 12V RPROG = 26.7k DCIN = 24V R PROG = 35.7k RSENSE = 33m/uni03A9 RIN = 3.01k

Typical perForMance characTerisTics PWM Frequency vs Duty Cycle Battery Shutdown Current DUTY CYCLE (%) PWM FREQUENCY (kHz) 100 200 300 400 500 600 20 40 60 80 4012-3 G13 100 CLP = 6V CLP = 12V CLP = 20V CLP = 25V ICHG = 750mA PWM Frequency vs Charge Current CHARGE CURRENT (A) PWM FREQUENCY (kHz) 100 200 300 400 600 0.5 1.0 1.5 2.0 4012-3 G14 2.5 3.0 500 BAT = 14.5V BAT = 12V BAT = 5V CLP = 15V RSENSE = 33m/uni03A9 RIN = 3.01k BATTERY VOLTAGE (V) BATTERY CURRENT (µA) 5 10 15 4012-3 G15 20 25 LTC4012-3, BAT PINS DCIN = 20V LTC4012-3, ALL PINS DCIN = 0V DC1256-CLASS APPLICATION DCIN = 0V (TA = 25°C unless otherwise noted. L = IHLP-2525 6.8µH) INFET Response Time to DCIN Short to Ground VGS = 0V TIME (1µs/DIV) DCIN = 15V INFET = Si7423DN I OUT = <50mA VOUT = 12.3V COUT = 0.27F 4012-3 G16 PFET VGS (1V/DIV) IDCIN, REVERSE (5A/DIV)

CLN (Pin 1): Adapter Input Current Limit Negative Input. The L TC4012-3 senses voltage on this pin to determine if less charge current should be sourced to limit total input current. The threshold is set 100mV below the CLP pin. An external filter should be used to remove switching noise. This input should be tied to CLP if not used. Operating voltage range is (CLP – 110mV) to CLP . CLP (Pin 2): Adapter Input Current Limit Positive Input. The L TC4012-3 also draws power from this pin, including a small amount for some shutdown functions. Operating voltage range is GND to 28V . INFET (Pin 3): PowerPath Control Output. This output drives the gate of a PMOS pass transistor connected between the DC input (DCIN) and the raw system supply rail (CLP) to maintain a forward voltage of 25mV when a DC input source is present. INFET is internally clamped about 6V below CLP . Maximum operating voltage is CLP , which is used to turn off the input PMOS transistor when the DC input is removed. DCIN (Pin 4): DC Sense Input. One of two voltage sense inputs to the internal PowerPath controller (the other input to the controller is CLP). This input is usually supplied from an input DC power source. Operating voltage ranges from GND to 28.2V. GND (Pin 5): Ground. Internally connected to the Exposed Pad (package paddle). SHDN (Pin 6): Active-Low Shutdown Input. Driving SHDN below 300mV unconditionally forces the L TC4012-3 into the shutdown state. This input has a 40kΩ internal pull-down to GND. Operating voltage range is GND to INTV DD. CHRG (Pin 7): Active-Low Charge Indicator Output. This open-drain output provides three levels of information about charge status using a strong pull-down, 25µA weak pull-down or high impedance. Refer to the Operation and Applications Information sections for further details. This output should be left floating if not used. ICL (Pin 8): Active-Low Input Current Limit Indicator Out- put. This open-drain output pulls to GND when the charge current is reduced because of AC adapter input current limiting. This output should be left floating if not used. V FB (Pin 9): Battery Voltage Feedback Input. An external resistor divider between FBDIV and GND with the center tap connected to V FB programs the charger output voltage. In constant voltage mode, this pin is nominally at 1.2085V. Refer to the Applications Information section for complete details on programming battery voltage. Operating voltage range is GND to 1.25V. FBDIV (Pin 10): Battery Voltage Feedback Resistor Divider Source. The L TC4012-3 connects this pin to BAT when charging is in progress. FBDIV is an open-drain PFET output to BAT with an operating voltage range of GND to BAT. BAT (Pin 11): Battery Pack Connection. The L TC4012-3 uses the voltage on this pin to control PWM operation when charging. Operating voltage range is GND to CLN. ITH (Pin 12): PWM Control Voltage and Compensation Node. The L TC4012-3 develops a voltage on this pin to control cycle-by-cycle peak inductor current. An external R-C network connected to ITH provides PWM loop com- pensation. Refer to the Applications Information section for further details on establishing loop stability. Operating voltage range is GND to INTV DD. PROG (Pin 13): Charge Current Programming and Monitor- ing Pin. An external resistance connected between PROG and GND, along with the current sense and PWM input resistors, programs the maximum charge current. The voltage on this pin can also provide a linearized indicator of charge current. Refer to the Applications Information section for complete details on current programming and monitoring. Operating voltage range is GND to INTV DD. CSN (Pin 14): Charge Current Sense Negative Input. Place an external input resistor (R IN, Figure 1) between this pin and the negative side of the charge current sense resistor. Operating voltage ranges from (BAT – 50mV) to (BAT + 200mV). CSP (Pin 15): Charge Current Sense Positive Input. Place an external input resistor (R IN, Figure 1) between this pin and the positive side of the charge current sense resistor. Operating voltage ranges from (BAT – 50mV) to (BAT + 200mV).

BGATE (Pin 16): External Synchronous NFET Gate Control Output. This output provides gate drive to an external NMOS power transistor switch used for synchronous rectification to increase efficiency in the step-down DC/DC converter. Operating voltage is GND to INTV DD. BGATE should be left floating if not used. INTVDD (Pin 17): Internal 5V Regulator Output. This pin provides a means of bypassing the internal 5V regulator used to power the L TC4012-3 PWM FET drivers. This sup- ply shuts down when the L TC4012-3 shuts down. Refer to the Application Information section for details if additional power is drawn from this pin by the application circuit. SW (Pin 18): PWM Switch Node. The L TC4012-3 uses the voltage on this pin as the source reference for its topside NFET (PWM switch) driver. Refer to the Applications In- formation section for additional PCB layout suggestions related to this critical circuit node. Operating voltage range is GND to CLN. TGATE (Pin 19): External NFET Switch Gate Control Output. This output provides gate drive to an external NMOS power transistor switch used in the DC/DC converter. Operating voltage range is GND to (CLN + 5V). BOOST (Pin 20): TGATE Driver Supply Input. A bootstrap capacitor is returned to this pin from a charge network connected to SW and INTV DD. Refer to the Applications Information section for complete details on circuit topol- ogy and component values. Operating voltage ranges from (INTV DD – 1V) to (CLN + 5V). GND (Exposed Pad Pin 21): Ground. The package paddle provides a single-point ground for the internal voltage reference and other critical L TC4012-3 circuits. It should be soldered to a suitable PCB copper ground pad for proper electrical operation and to obtain the specified package thermal resistance.

1.2085V REFERENCE REGULATOR PWM LOGIC FAUL T DETECTION C/10 DETECTION SHUTDOWN CONTROL OSCILLATORBAT SHUTDOWN CHARGE INPUT CURRENT LIMIT TGATE 20BOOST 12ITH 13PROG 14CSN 15CSP 18SW GND (PADDLE) 4012-3 BD01 BGATE INTVDD TO INTERNAL CIRCIUTS VFB9 CHRG ACP FBDIV GND

6 SHDN

1.2085V 1.2085V TARGET PROG V FB ITH 4012-3 TC01 L TC4012-3 0.6V EA FROM ICL (CLP = CLN) L TC1055

The L TC4012-3 is a synchronous step-down (buck) cur- rent mode PWM battery charger controller . The maximum charge current is programmed by the combination of a charge current sense resistor (R SENSE), matched input resistors (R IN, Figure 1), and a programming resistor (RPROG) between the PROG and GND pins. Battery voltage is programmed with an external resistor divider between FBDIV and GND. In addition, the PROG pin provides a linearized voltage output of the actual charge current. The L TC4012-3 does not have built-in charge termination and is flexible enough for charging any type of battery chemistry. It is a building block IC intended for use with an external circuit, such as a microcontroller , capable of managing the entire algorithm required for the specific battery being charged. The L TC4012-3 features a shut- down input and various state indicator outputs, allowing easy and direct management by a wide range of external (digital) charge controllers. Shutdown The L TC4012-3 remains in shutdown until DCIN is greater than 5.1V and exceeds CLP by 60mV and SHDN is driven above 1.4V . In shutdown, current drain from the battery is reduced to the lowest possible level, thereby increasing standby time. When in shutdown, the ITH pin is pulled to GND and CHRG, ICL, FET gate drivers and INTV DD are all disabled. Charging can be stopped at any time by forcing SHDN below 300mV. AC Present Detection AC present is detected as soon as DCIN exceeds BAT by at least 500mV. Charging is not enabled until this condition is first met. After this event, charging is no longer gated by AC present detection. If battery voltage rises due to ESR, or DCIN droops due to current load, the PWM will remain enabled, even with very low input overhead, unless DCIN falls below the supply voltage on CLP. Input PowerPath Control The input PFET controller performs many important func- tions. First, it monitors DCIN and enables the charger when this input voltage is higher than the raw CLP sys- tem supply. Next, it controls the gate of an external input power PFET to maintain a low forward voltage drop when charging, creating improved efficiency. It also prevents reverse current flow through this same PFET, providing a suitable input blocking function. Finally, it helps avoid synchronous boost operation during invalid operating conditions by detecting elevated CLP voltage and forcing the charger off. If DCIN voltage is less than CLP , then DCIN must rise 60mV higher than CLP to enable the charger and activate the ideal diode control. The gate of the input PFET is driven to a voltage sufficient to regulate a forward drop between DCIN and CLP of about 25mV. If the input voltage differential drops below this point, the FET is turned off slowly. If the voltage between DCIN and CLP drops to less than –25mV, the input FET is turned off in less than 6µs to prevent significant reverse current from flowing back through the PFET, and the charger is disabled. Soft-Start Exiting the shutdown state enables the charger and releases the ITH pin. When enabled, switching will not begin until DCIN exceeds BAT by 500mV and ITH exceeds a threshold that assures initial current will be positive (about 5% to 25% of the maximum programmed current). To limit inrush current, soft-start delay is created with the compensation values used on the ITH pin. Longer soft-start times can be realized by increasing the filter capacitor on ITH, if reduced loop bandwidth is acceptable. The actual charge current at the end of soft-start will depend on which loop (current, voltage or adapter limit) is in control of the PWM. If this current is below that required by the ITH start-up threshold, the resulting charge current transient duration depends on loop compensation but is typically less than 100µs.

can be switched to a higher, bulk charge value. tors to be used in the application. accuracy specified in the Electrical Characteristics table. ming charge current for additional details. Figure 1. PWM Circuit Diagram

11 PWM

begin to assert control over the PWM loop. Table 1. L TC4012-3 Open-Drain Indicator Outputs PWM operation references Figure 1. Figure 2. PWM Waveforms

The ITH output of the error amplifier is a scaled control voltage for one input of the PWM comparator , CC. ITH sets a peak inductor current threshold, sensed by R1, to maintain the desired average current through R SENSE. The current comparator output does this by switching the state of the RS latch at the appropriate time. At the beginning of each oscillator cycle, the PWM clock sets the RS latch and turns on the external topside NFET (bottom-side synchronous NFET off) to refresh the current carried by the external inductor L1. The inductor current and voltage across R SENSE begin to rise linearly. CA buffers this instantaneous voltage rise and applies it to CC with gain supplied by R1. When the voltage across R1 exceeds the peak level set by the ITH output of EA, the top FET turns off and the bottom FET turns on. The inductor cur- rent then ramps down linearly until the next rising PWM clock edge. This closes the loop and sources the correct inductor current to maintain the desired parameter (charge current, battery voltage, or input current). To produce a near constant frequency, the PWM oscillator implements the equation: t CLP BAT CLP kHzOFF = –

• 550 Repetitive, closed-loop waveforms for stable PWM opera- tion appear in Figure 2. PWM Watchdog Timer As input and output conditions vary, the L TC4012-3 may need to utilize PWM duty cycles approaching 100%. In this case, operating frequency may be reduced well below 550kHz. An internal watchdog timer observes the activity on the TGATE pin. If TGATE is on for more than 40µs, the watchdog activates and forces the bottom NFET on (top NFET off) for about 100ns. This avoids a potential source of audible noise when using ceramic input or output capacitors and prevents the boost supply capacitor for the top gate driver from discharging. In low drop out operation, the actual charge current may not be able to reach the programmed full-scale value due to the watchdog function. Overvoltage Protection The L TC4012-3 also contains overvoltage detection that prevents transient battery voltage overshoots of more than about 6% above the programmed output voltage. When battery overvoltage is detected, both external MOSFETs are turned off until the overvoltage condition clears, at which time a new soft-start sequence begins. This is useful for properly charging battery packs that use an internal switch to disconnect themselves for performing functions such as calibration or pulse mode charging. Reverse Charge Current Protection (Anti-Boost) Because the LTC4012-3 always attempts to operate synchronously in full continuous mode (to avoid audible noise from ceramic capacitors), reverse average charge current can occur during some invalid operating condi- tions. INFET PowerPath control avoids boosting a lightly loaded system supply during reverse operation. However, under heavier system loads, CLP may not boost above DCIN, even though reverse average current is flowing. In this case a second circuit monitors indication of reverse average current on PROG. If either of these circuits detects boost operation, The L TC4012-3 turns off both external MOSFETs until the reverse current condition clears. At that point, a new soft-start sequence begins. operaTion

Figure 6. Programming Input Current Limit

3 INFET

Figure 7. Adjusting Input Current Limit Table 3. Common RCL Values the parameters of the input current limit in two ways. some common RCL current limit programming values. CLP remains connected to power.

The overall accuracy of this circuit needs to be better than the power source current tolerance or be margined such that the worse-case error remains under the power source limits. The accuracy of the Figure 7 circuit is a function of the INTV DD, VBE, RCL, RF , R1 and R3 tolerances. To improve accuracy, the tolerance of R F should be changed from 5.1k, 5% to a 2.49k 1% resistor. RCL and the programming resistors R1 and R3 should also be 1% tolerance such that the dominant error is INTV DD (±3%). Bias resistor R2 can be 5%. When choosing NPN transistors, both need to have good gain (>100) at 10µA levels. Low gain NPNs will increase programming errors. Q1 must be a matched NPN pair. Since R F has been reduced in value by half, the capacitor value of CF should double to 0.22µF to remain effective at filtering out any noise. If you wish to reduce R CL power dissipation for a given current limit, the programming equation becomes: R mV k R ICL LIM 100 5 2 49 1– • . If you wish to make the input current limit programmable, the equation becomes: I mV k R RLIM CL 100 5 2 49 1– • . The equation governing R2 for both applications is based on the value of R1. R3 should always be equal to R1. R2 = 0.875 • R1 Figure 8. PROG Voltage Buffer INTVDD PROG <30nA L TC4012-3 4012-3 F08 TO SYSTEM MONITOR+ In many notebook applications, there are situations where two different ILIM values are needed to allow two different power adapters or power sources to be used. In such cases, start by setting R LIM for the high power ILIM configuration and then use Figure 7 to set the lower ILIM value. To toggle between the two I LIM values, take the three ground connections shown in Figure 7, combine them into one common connection and use a small-signal NFET (2N7002) to open or close that common connec- tion to circuit ground. When the NFET is off, the circuit is defeated (floating) allowing I LIM to be the maximum value. When the NFET is on, the circuit will become active and I LIM will drop to the lower set value. Monitoring Charge Current The PROG pin voltage can be used to indicate charge cur- rent where 1.2085V indicates full programmed current (1C) and zero charge current is approximately equal to R PROG • 11.67µA. PROG voltage varies in direct proportion to the charge current between this zero-current (offset) value and 1.2085V. When monitoring the PROG pin voltage, using a buffer amplifier as shown in Figure 8 will minimize charge current errors. The buffer amplifier may be powered from the INTV DD pin or any supply that is always on when the charger is on.

The output capacitor shown across the battery and ground must also absorb PWM output ripple current. The general formula for this capacitor current is: I V V V L fRMS BAT BAT CLP PWM 0 29 1 . • • – For example, IRMS = 0.22A with: VBAT = 12.6V VCLP = 19V L1 = 10µH fPWM = 550kHz High capacity ceramic capacitors (20µF or more) available from a variety of manufacturers can be used for input/out- put capacitors. Other alternatives include OS-CON and POSCAP capacitors from Sanyo. Low ESR solid tantalum capacitors have high ripple cur- rent rating in a relatively small surface mount package, but exercise caution when using tantalum for input or output bulk capacitors. High input surge current can be created when the adapter is hot-plugged to the charger or when a battery is connected to the charger. Solid tan- talum capacitors have a known failure mechanism when subjected to very high surge currents. Select tantalum capacitors that have high surge current ratings or have been surge tested. EMI considerations usually make it desirable to minimize ripple current in battery leads. Adding Ferrite beads or inductors can increase battery impedance at the nominal 550kHz switching frequency. Switching ripple current splits between the battery and the output capacitor in inverse relation to capacitor ESR and the battery impedance. If the ESR of the output capacitor is 0.2 Ω and the battery impedance is raised to 4 Ω with a ferrite bead, only 5% of the current ripple will flow to the battery. Inductor Selection Higher switching frequency generally results in lower ef- ficiency because of MOSFET gate charge losses, but it allows smaller inductor and capacitor values to be used. A primary effect of the inductor value L1 is the amplitude of ripple cu rrent created. The inductor ripple current ∆IL decreases with higher inductance and PWM operating frequency: V V V L fL BAT BAT CLP PWM • – Accepting larger values of ∆IL allows the use of low in- ductance, but results in higher output voltage ripple and greater core losses. Lower charge currents generally call for larger inductor values. The L TC4012-3 limits maximum instantaneous peak in- ductor current during every PWM cycle. To avoid unstable switch waveforms, the ripple current must satisfy: ∆I mV R IL SENSE MAX< 2 150• – so choose: L V f mV R I CLP PWM SENSE MAX 1 0 125 150 >  . •

• – For C-grade parts, a reasonable starting point for setting ripple current is ∆IL = 0.4 • I MAX. For I-grade parts, use ∆IL = 0.2 • IMAX only if the IC will actually be used to charge batteries over the wider I-grade temperature range. The voltage compliance of internal L TC4012-3 circuits also imposes limits on ripple current. Select R IN (in Figure 1) to avoid average current errors in high ripple designs. The following equation can be used for guidance: R I µA R R I µA SENSE L IN SENSE L• •∆ ∆ 50 20≤ ≤ applicaTions inForMaTion

rounding up to the nearest standard value. Table 5. Minimum Typical Inductor Values a bootstrapped BOOST supply for the TGATE FET driver. of D1 and the BOOST pin to remove this jitter, if present. lower ESL and achieve the best results. Figure 11. TGATE Boost Supply

T wo external power MOSFETs must be selected for use with the charger: an N-channel power switch (top FET) and an N-channel synchronous rectifier (bottom FET). Peak gate-to-source drive levels are internally set to about 5V. Consequently, logic-level FETs must be used. In addition to the fundamental DC current, selection criteria for these MOSFETs also include channel resis- tance R DS(ON), total gate charge Q G, reverse transfer capacitance CRSS, maximum rated drain-source voltage BVDSS and switching characteristics such as t d(ON/OFF). Power dissipation for each external FET is given by: P V I T R V k V D TOP BAT MAX DS ON CLP C ( ) ( )• • = +( ) 2 1 δ∆ L LP MAX RSS D BOT CLP BAT M I C kHz P V V I 2 665• • • – • ( ) = ( ) A AX DS ON CLP T R V 2 1 • ( )+( )δ∆ where δ is the temperature dependency of R DS(ON), ∆T is the temperature rise above the point specified in the FET data sheet for R DS(ON) and k is a constant in- versely related to the internal L TC4012-3 top gate driver. The term (1 + δ∆T) is generally given for a MOSFET in the form of a normalized RDS(ON) curve versus temperature, but δ of 0.005/°C can be used as a suitable approxima- tion for logic-level FETs if other data is not available. C RSS = ∆QGD/∆VDS is usually specified in the MOSFET characteristics. The constant k = 2 can be used in esti- mating top FET dissipation. The L TC4012-3 is designed to work best with external FET switches with a total gate charge at 5V of 15nC or less. For VCLP < 20V, high charge current efficiency generally improves with larger FETs, while for VCLP > 20V, top gate transition losses increase rapidly to the point that using a topside NFET with higher R DS(ON) but lower C RSS can actually provide higher efficiency. If the charger will be operated with a duty cycle above 85%, overall efficiency is normally improved by using a larger top FET. The synchronous (bottom) FET losses are greatest at high input voltage or during a short circuit, which forces a low side duty cycle of nearly 100%. Increasing the size of this FET lowers its losses but increases power dissipation in the L TC4012-3. Using asymmetrical FETs will normally achieve cost savings while allowing optimum efficiency. Select FETs with BV DSS that exceeds the maximum VCLP voltage that will occur. Both FETs are subjected to this level of stress during operation. Many logic-level MOSFETs are limited to 30V or less. The L TC4012-3 uses an improved adaptive TGATE and BGATE drive that is insensitive to MOSFET inertial delays, t d(ON/OFF), to avoid overlap conduction losses. Switching characteristics from power MOSFET data sheets apply only to a specific test fixture, so there is no substitute for bench evaluation of external FETs in the target application. In general, MOSFETs with lower inertial delays will yield higher efficiency. Diode Selection A Schottky diode in parallel with the bottom FET and/or top FET in an L TC4012-3 application clamps SW during the non-overlap times between conduction of the top and bottom FET switches. This prevents the body diode of the MOSFETs from forward biasing and storing charge, which could reduce efficiency as much as 1%. One or both diodes can be omitted if the efficiency loss can be tolerated. A 1A Schottky is generally a good size for 3A chargers due to the low duty cycle of the non-overlap times. Larger diodes can actually result in additional efficiency (transition) losses due to larger junction capacitance. Loop Compensation and Soft-Start The three separate PWM control loops of the L TC4012-3 can be compensated by a single set of components at- tached between the ITH pin and GND. As shown in the typical L TC4012-3 application, a 6.04k resistor in series with a capacitor of at least 0.1µF provides adequate loop compensation for the majority of applications.

Figure 12. High Speed Switching Path

4012 F12

to reach full charge current is usually greater than 1.5ms. governed by IC power dissipation. temperature is not exceeded under all operating conditions. components connected to the L TC4012-3 is essential. PCB design priority list will help insure proper topology. Layout the PCB using this specific order. side of the PCB from the switching FETs.

1. Place the inductor input as close as possible to the

from the switch node to any other trace or plane. current sense traces to the L TC4012-3 are not long. and not at the sense resistor location. ground before connecting back to system ground. or any internal ground plane, should be single-point. star point to make the connection. to connect analog ground to system ground. which further improves EMI performance. Figure 13. Kelvin Sensing of Charge Current

4012 F13

4.00 ± 0.10 4.00 ± 0.10 NOTE: 1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-1)—TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT , SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONL Y A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ± 0.10 20 19 BOTTOM VIEW—EXPOSED PAD

2.00 REF

2.45 ± 0.10 0.75 ± 0.05 R = 0.115 TYP R = 0.05 TYP 0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UF20) QFN 01-07 REV A RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 2.00 REF 2.45 ± 0.05 3.10 ± 0.05 4.50 ± 0.05 PACKAGE OUTLINE PIN 1 NOTCH R = 0.20 TYP OR 0.35 s 45° CHAMFER2.45 ± 0.10 2.45 ± 0.05 20-Lead Plastic QFN (4mm × 4mm) (Reference L TC DWG # 05-08-1710 Rev A)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER B 3/10 I-Grade Part Added. Reflected Throughout the Data Sheet 1 to 28 (Revision history begins at Rev B)

Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com  LINEAR TECHNOLOGY CORPORATION 2009 LT 0610 REV B • PRINTED IN USA relaTeD parTs PART NUMBER DESCRIPTION COMMENTS L TC4006 Small, High Efficiency, Fixed Voltage, Lithium-Ion Battery Chargers with Termination Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current Limit and Thermistor Sensor, 16-pin SSOP Package L TC4007 High Efficiency, Programmable Voltage, Lithium-Ion Battery Charger with Termination Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current Limit, Thermistor Sensor and Indicator Outputs L TC4008/L TC4008-1 High Efficiency, Programmable Voltage/Current Battery Chargers Constant-Current/Constant-Voltage Switching Regulator, Resistor Voltage/Current Programming, Thermistor Sensor and Indicator Outputs, AC Adapter Current Limit (Omitted on 4008-1) L TC4009/L TC4009-1 L TC4009-2 High Efficiency, Multichemistry Battery Charger Constant-Current/Constant-Voltage Switching Regulator in a 20-Lead L TC4012/L TC4012-1 L TC4012-2 High Efficiency, Multi Chemistry Battery Chargers with PowerPath Control Constant-Current/Constant-Voltage Switching Regulator in a 20-Lead

3 Indicator Outputs

L TC4060 Standalone Linear NiMH/NiCd Fast Charger Complete NiMH/NiCd Charger in a Small 16-Pin Package, No Sense Resistor or Blocking Diode Required L TC4411 2.6A Low Loss Idea Diode No External MOSFET, Automatic Switching Between DC sources, 140mΩ On Resistance in ThinSOT TM package L TC4412/L TC4412HV Low Loss PowerPath Controllers Very Low Loss Replacement for Power Supply ORing Diodes Using Minimal External Complements, Operates up to 28V (36V for HV) L TC4413 Dual 2.6A, 2.5V to 5.5V Ideal Diodes Low Loss Replacement for ORing Diodes, 100mΩ On Resistance L TC4414 36V, Low Loss PowerPath Controller for Large PFETs Low Loss Replacement for ORing Diodes, Operates up to 36V L TC4416 Dual Low Loss PowerPath Controllers Low Loss Replacement for ORing Diodes, Operates up to 36V, Drives Large PFETs, Programmable, Autonomous Switching Typical applicaTion 12.6V 4 Amp Charger CLP FROM ADAPTER 15V AT 4A BULK CHARGE 0.1µF R8 5.1k R14 100k R15 0/uni03A9* D1 7 18 D3 R12 294k C10 10pF 25m/uni03A9 R9 3.01k 0.1µF 2µF 4.7µH R11 25m/uni03A9 12.6V Li-Ion BATTERY DCIN CHRG 0.1µF R 6.04k 10k 26.7k 53.6k L TC4012-3 ICL SHDN ITH PROG CLN BOOSTGND INFET TGATE SW INTV DD BGATETO/FROM MCU GND CSP CSN BAT FBDIV VFB 10µF POWER TO SYSTEM TO POWER SYSTEM LOAD WHEN ADAPTER IS NOT PRESENT , USE SCHOTTKY DIODE D5 OR THE COMBINATION OF R14, R2 D6 AND Q4 18V ZENER 0.1µF 4.7nF 10µF R10 3.01k R13 31.2k

40123 TA03

D3: CMDSH-3 D4: MBR230LSFT1 Q1: 2N7002 Q2, Q3: Si7218DN Q4, Q5: Si7423DN L1: 1HLP-2525CZER4R7M11 *: SEE TGATE BOOST SUPPL Y IN APPLICATIONS INFORMATION OR