Power Management

LTC3111

Analog Devices

6A Low Noise, High Performance Buck-Boost DC/DC Converter Rev. 0

Manufacturer: Analog Devices

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LTC3111 - 15V, 1.5A Synchronous Buck-Boost DC/DC Converter

Document overview

Manufacturer or author: Linear Technology Corporation
PDF pages: 32

Technical content

For more information www.linear .com/L TC3111 LOAD CURRENT (A) 0.0001 EFFICIENCY (%) 100 0.001 1 100.01 0.1

3111 TA01b

VIN = 2.7V VIN = 5V VIN = 12V BURST PWM TYPICAL APPLICATION FEATURES DESCRIPTION 15V, 1.5A Synchronous Buck-Boost DC/DC Converter The LT C®3111 is a fixed frequency, synchronous buck- boost DC/DC converter with an extended input and output range. The unique 4-switch, single inductor architecture provides low noise and seamless operation from input voltages above, below or equal to the output voltage. With an input and output range of 2.5V to 15V, the LTC3111 is well suited for a wide variety of single or multiple-cell batteries, back-up capacitor or wall adapter source applica- tions. Low RDS(ON) internal N-channel MOSFET switches and selectable PWM or Burst Mode operation produce high efficiency over a wide range of operating conditions. An accurate RUN pin allows the user to program the turn-on threshold voltage of the converter. Other features include: short-circuit protection, internal soft-start and thermal shutdown. The LTC3111 is offered in both thermally enhanced 14-lead (3mm × 4 mm × 0.75mm) DFN and 16-lead MSOP packages. 5V, 800kHz Wide Input Voltage Buck-Boost Regulator

APPLICATIONS

n Regulated Output with VIN Above, Below or Equal to VOUT n 2.5V to 15V Input and Output Voltage Range n 1.5A Continuous Output Current: VIN ≥ 5V, VOUT = 5V, PWM Mode n Single Inductor n Accurate RUN Threshold n Up to 95% Efficiency n 800kHz Switching Frequency, Synchronizable Between 600kHz and 1.5MHz n 49µA No-Load Quiescent Current in Burst Mode® Operation n Output Disconnect in Shutdown n Shutdown Current < 1µA n Internal Soft-Start n Small, Thermally Enhanced 14-Lead (3mm × 4mm × 0.75mm) DFN and 16-Lead MSOP Packages n 3.3V or 5V from 1, 2 or 3 Li-Ion, Multiple-Cell Alkaline/NiMH Batteries n RF T ransmitters n Military, Industrial Power Systems L, LT, LT C, LT M, Linear Technology, the Linear logo, Burst Mode, L Tspice are registered trademarks and No RSENSE and PowerPath are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 6404251, 6166527, 5481178, 6304066, 6580258. SW1 0.1µF 27pF 1µF 33pF 191k

3111 TA01a

26.1k 0.1µF VIN 2.5V TO 15V 4.7µH SW2 BST1 BST2 VIN L TC3111 PGNDSGND VOUT 22µF VOUT 1.5A IN > 5V)10µF PWM/SYNCBURST PWM RUN FB VCCSNSGND COMP OFF ON Efficiency at 5VOUT

For more information www.linear .com/L TC3111 PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS 0.3V to (VIN + 0.3V) 0.3V to (VOUT + 0.3V) VSW1 – 0.3V) to (VSW1 + 6V) VSW2 – 0.3V) to (VSW2 + 6V) 0.3V to 6V (Notes 1, 3) SGND PWM/SYNC V CC NC V OUT SW2 BST2 COMP FB SNSGND RUN V IN SW1 BST1 TOP VIEW PGND DE PACKAGE 14-LEAD (4mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 43°C/W, θJC = 5°C/W EXPOSED PAD (PIN 15) IS PGND, MUST BE SOLDERED TO PCB COMP FB SNSGND RUN V IN SW1 BST1 PGND SGND PWM/SYNC V CC NC V OUT SW2 BST2 PGND TOP VIEW PGND MSE PACKAGE 16-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 40°C/W, θJC = 10°C/W EXPOSED PAD (PIN 17) IS PGND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3111EDE#PBF LTC3111EDE#TRPBF 3111 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C LTC3111IDE#PBF LTC3111IDE#TRPBF 3111 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C LTC3111HDE#PBF LTC3111HDE#TRPBF 3111 14-Lead (4mm × 3mm) Plastic DFN –40°C to 150°C LTC3111MPDE#PBF LTC3111MPDE#TRPBF 3111 14-Lead (4mm × 3mm) Plastic DFN –55°C to 150°C LTC3111EMSE#PBF LTC3111EMSE#TRPBF 3111 16-Lead Plastic MSOP –40°C to 125°C LTC3111IMSE#PBF LTC3111IMSE#TRPBF 3111 16-Lead Plastic MSOP –40°C to 125°C LTC3111HMSE#PBF LTC3111HMSE#TRPBF 3111 16-Lead Plastic MSOP –40°C to 150°C LTC3111MPMSE#PBF LTC3111MPMSE#TRPBF 3111 16-Lead Plastic MSOP –55°C to 150°C Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LT C Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ Operating Junction Temperature Range (Notes 2, 5) LTC3 40°C to 125°C LTC3 40°C to 150°C LTC3 55°C to 15 0° C 65°C to 150°C Lead Temperature (Soldering, 10sec) MS 0°C

For more information www.linear .com/L TC3111 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = VOUT = PWM/SYNC = RUN = 5V unless otherwise noted. PARAMETER CONDITION MIN TYP MAX UNITS Input Operating Range l 2.5 15 V VIN UVLO Threshold Rising l 1.9 2.1 2.3 V VIN UVLO Hysteresis 200 mV VCC UVLO Threshold Rising l 2.2 2.35 2.5 V VCC UVLO Hysteresis 190 mV Output Voltage Adjust Range l 2.5 15 V INTVCC Clamp Voltage VIN = 5V or 15V l 3.9 4.2 4.5 V Quiescent Current—Burst Mode Operation FB = 1V, PWM /SYNC = 0V 55 80 µA Quiescent Current—Shutdown RUN = VOUT = VCC = 0V, Not Including Switch Leakage 0 1 µA Feedback Voltage PWM Operation l 0.78 0.8 0.82 V Feedback Leakage FB = 0.8V 0 50 nA NMOS Switch Leakage Switches A, B, C, D, VIN = VOUT = 15V 0.5 5 µA NMOS Switch On-Resistance Switch A 90 mΩ Switch B, C, D 105 mΩ Input Current Limit l 2.3 3 3.7 A Peak Current Limit 5.8 A Burst Current Limit PWM/SYNC = 0V 0.8 A Burst Zero Current Threshold PWM/SYNC = 0V 0.1 A Reverse Current Limit –1 A Maximum Duty Cycle Percentage of the Period SW2 is Low in Boost Mode (Note 7) l 85 90 % Minimum Duty Cycle Percentage of the Period SW1 is Low in Buck Mode (Note 7) l 0 % SW1, SW2 Minimum Low Time (Note 7) 160 ns Frequency PWM/SYNC = 5V l 700 800 900 kHz SYNC Frequency Range (Note 6) l 600 1500 kHz PWM/SYNC Threshold l 0.5 0.9 1.5 V RUN Threshold to Enable VCC Rising l 0.35 0.8 1.15 V RUN Threshold to Disable VCC Falling l 0.3 V RUN Threshold to Enable Switching Rising l 1.15 1.18 1.23 V RUN Hysteresis 120 mV Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetimes. Note 2: The LTC3111 is tested under pulsed load conditions such that T J ≈ TA. The LTC3111E is guaranteed to meet specifications from 0°C to 85°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3111I is guaranteed to meet performance specifications from –40°C to 125°C junction temperature, the LTC3111H is guaranteed to meet performance specifications from –40°C to 150°C junction temperature and the LTC3111MP is guaranteed and tested to meet performance specifications from –55°C to 150°C junction temperature. High junction temperatures degrade operating lifetimes: operating lifetime is derated for junction temperatures greater than 125°C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors.

For more information www.linear .com/L TC3111 TYPICAL PERFORMANCE CHARACTERISTICS Maximum Output Current in PWM Mode vs VIN Maximum Load Current in Burst Mode Operation vs V IN Wide VIN to 5VOUT Efficiency Wide VIN to 5VOUT Power Loss Wide VIN to 3.3VOUT Efficiency Wide VIN to 3.3VOUT Power Loss

ELECTRICAL CHARACTERISTICS

Note 3: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperatures will exceed 150°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 4: Voltage transients on the switch pins beyond the DC limit specified in the Absolute Maximum Ratings, are non-disruptive to normal operation when using good layout practices, as shown on the demo board or described in the data sheet and application notes. Note 5: The junction temperature (T J in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) according to the formula: TJ = TA + (PD • θJA) where θJA (in °C/W) is the package thermal impedance. Note 6: SYNC frequency range is tested with a square wave. Operation with 100ns minimum high or low time is assured by design. Note 7: Switch timing measurements are made in an open-loop test configuration. T iming in the application may vary somewhat from these values due to differences in the switch pin voltage during the non-overlap durations when the switch pin voltage is influenced by the magnitude and direction of the inductor current. TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified VIN (V) MAXIMUM OUTPUT CURRENT (A) 0.2 0.6 0.8 1.0 8 9 10 12 11 14 13 2.0 1.8

3111 G01

0.4 3 4 5 6 7 15 1.2 1.4 1.6 VOUT = 3.3V , L = 4.7µH VOUT = 5V , L = 6.8µH VOUT = 12V , L = 10µH INPUT CURRENT LIMIT = 2.3A VIN (V) 2 3 4 MAXIMUM OUTPUT CURRENT (mA) 400 600

3111 G02

5 6 7 8 9 10 11 12 13 14 15 800 300 500 100 700 VOUT = 3.3V VOUT = 5V VOUT = 12V LOAD CURRENT (A) EFFICIENCY (%) 100 0.0001 0.01 0.1 1 10

3111 G03

0.001 VIN = 2.7V VIN = 5V VIN = 12V BURST PWM LOAD CURRENT (A) 0.0001 0.001 0.0001 0.001POWER LOSS (W) 0.1 0.01 0.1 1 10

3111 G04

0.01 VIN = 2.7V VIN = 5V VIN = 12V BURST PWM LOAD CURRENT (A) 0.0001 0.001 EFFICIENCY (%) 100 0.01 10.1

3111 G05

VIN = 2.7V VIN = 5V VIN = 12V BURST PWM LOAD CURRENT (A) 0.01 POWER LOSS (W) 0.1 0.01 0.1 1

3111 G06

0.0001 0.001 0.0001 0.001 VIN = 2.7V VIN = 5V VIN = 12V BURST PWM

For more information www.linear .com/L TC3111 TYPICAL PERFORMANCE CHARACTERISTICS 800kHz PWM Mode No-Load Input Current Burst Mode No-Load Current with VCC from VIN or Back-Fed from VOUT with an Optional Diode VCC Voltage vs VIN PWM Mode No Load VCC Voltage vs VCC Current Normalized N-Channel MOSFET Resistance vs V CC Wide VIN to 12VOUT Efficiency TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified Wide VIN to 12VOUT Power Loss 12VIN to 12VOUT Efficiency at f = 600kHz, 800kHz, 1MHz and 1.5MHz with L = 10µH LOAD CURRENT (A) 0.0001 0.001 EFFICIENCY (%) 100 0.01 10.1

3111 G07

VIN = 2.7V VIN = 5V VIN = 12V PWM BURST LOAD CURRENT (A) 0.0001 0.001 0.0001 0.001POWER LOSS (W) 0.1 0.01 0.1 1 10

3111 G08

0.01 VIN = 2.7V VIN = 5V VIN = 12V BURST PWM LOAD CURRENT (A) EFFICIENCY (%) 100 0.01 10.1

3111 G09

f = 600kHz f = 800kHz f = 1MHz f = 1.5MHz VIN (V) VIN CURRENT (mA)

31111 G10

VIN (V) VIN CURRENT (µA) 150 200 250 9 10 11 12 13 14 450

3111 G11

VOUT = 5V VIN (V) VCC VOLTAGE (V) 3.7 4.1 4.5 73 84 95 106 11

3111 G12

3.3 2.9 3.5 3.9 4.3 3.1 2.7 2.5 12 13 14 CURRENT FROM VCC (mA) VCC (V)3.9 4.0 4.1 60 7030 40 50

3111 G13

3.8 3.7 10 20 80 3.6 3.5 4.2 VCC (V) 2.5 NORMALIZED MOSFET RESISTANCE 1.05 1.10 1.15 4.0 5.0

3111 G14

1.00 0.95 0.90 3.0 3.5 4.5 1.20 1.25 1.30 Normalized N-Channel MOSFET Resistance vs Temperature TEMPERATURE (°C) –50 0.6 NORMALIZED MOSFET RESISTANCE0.7 0.9 1.0 1.1 1.6 1.3 0 50

3111 G15

0.8 1.4 1.5 1.2 100 150

For more information www.linear .com/L TC3111 TYPICAL PERFORMANCE CHARACTERISTICS RUN Threshold to Enable/Disable VCC vs VIN PWM Mode Input, Peak and Reverse Current Limits vs Temperature Burst Mode Peak Current, I ZERO Limits vs Temperature Feedback Pin Program Voltage vs Temperature RUN Threshold to Enable/Disable V CC vs Temperature VCC and VIN UVLO Voltage Thresholds vs Temperature RUN Threshold to Enable/Disable Switching vs VIN TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified TEMPERATURE (°C) –50 FEEDBACK PIN PROGRAM VOLTAGE (mV) 798.5 799.0 799.5 150

3111 G16

798.0 797.5 796.5 0 50 100 797.0 800.5 800.0 TEMPERATURE (°C) –50 VCC AND VIN UVLO THRESHOLDS (V) 2.0 2.1 2.2 150

3111 G17

1.9 1.8 1.7 1.5 0 50 100 1.6 2.4

2.3 VCC UVLO RISING

VIN (V) RUN THRESHOLD TO ENABLE VCC (V) 0.80 0.90 1.00

3111 G18

0.70 0.60 0.75 0.85 0.95 0.65 0.55 0.50 4 6 8 123 115 7 9 13 14 RISING FALLING TEMPERATURE (°C) –50 0.50RUN THRESHOLDS TO ENABLE VCC (V) 0.55 0.65 0.70 0.75 1.00 0.85 0 50

3111 G19

0.60 0.90 0.95 0.80 100 150 RISING FALLING VIN (V) RUN THRESHOLD TO ENABLE SWITCHING (V) 1.10 1.05 1.30 1.25

3111 G20

1.20 1.15 1.00 4 6 8 123 115 7 9 13 14 15 RISING FALLING TEMPERATURE (°C) –50 RUN PIN THRESHOLD TO ENABLE SWITCHING (V) 1.10 1.05 1.20 1.30 100

3111 G21

1.15 1.25 1.00 0 50 150 RISING FALLING TEMPERATURE (°C) –50 ILIMIT, IPEAK AND IREVERSE (A) 150

3111 G22

TEMPERATURE (°C) –50 0 50 100 150 ILMIT, IPEAK, AND IREVERSE (A) 0.6 0.8 1.0

3111 G23

0.4 0.2 0.5 0.7 0.9 0.3 0.1 IZERO PEAK CURRENT LIMIT RUN Threshold to Enable/Disable Switching vs Temperature

For more information www.linear .com/L TC3111 TYPICAL PERFORMANCE CHARACTERISTICS 5VIN to 5VOUT Burst to PWM Response 12VIN to 5VOUT Burst Mode VOUT Ripple 12VIN to 5VOUT PWM VOUT Ripple 7.5VIN to 5VOUT Start-Up Response 1.5MHz SYNC Signal Capture and Release 12VIN to 5VOUT SW1 and SW2 Waveforms 3VIN to 5VOUT 0.05A to 0.25A Load Response 5VIN to 5VOUT 0.05A to 0.5A Load Response 12VIN to 5VOUT 0.05A to 0.5A Load Response TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified VOUT 200mV/DIV INDUCTOR CURRENT 500mA/DIV LOAD CURRENT 200mA/DIV 500µs/DIV FRONT PAGE APPLICATION

3111 G24

500µs/DIV FRONT PAGE APPLICATION

3111 G25

500µs/DIV FRONT PAGE APPLICATION

3111 G26

500µs/DIVILOAD = 10mA L = 4.7µH COUT = 22µF

3111 G27

20µs/DIVILOAD = 50mA L = 4.7µH C OUT = 22µF

3111 G28

1µs/DIVILOAD = 500mA L = 4.7µH C OUT = 22µF

3111 G29

500µs/DIVILOAD = 500mA L = 4.7µH C OUT = 22µF

3111 G30

100µs/DIV 3111 G31 INDUCTOR CURRENT 500mA/DIV SW1 10V/DIV SW2 5V/DIV 1µs/DIV 3111 G32

For more information www.linear .com/L TC3111 TYPICAL PERFORMANCE CHARACTERISTICS 3.3VOUT Die Temperature Rise vs Continuous Load Current 4-Layer Demo Board at 25°C 5VOUT Die Temperature Rise vs Continuous Load Current 4-Layer Demo Board at 25°C 12V OUT Die Temperature Rise vs Continuous Load Current 4-Layer Demo Board at 25°C SW1, SW2 Minimum Low Time vs V CC SW1, SW2 Minimum Low Time vs Temperature V OUT Short-Circuit Response and Recovery VCC Short-Circuit Response and Recovery TA = 25°C, VIN = 5V, VOUT = 5V, unless otherwise specified INDUCTOR CURRENT 1A/DIV VOUT 2V/DIV 1ms/DIV 3111 G33 INDUCTOR CURRENT 1A/DIV VCC 5V/DIV VOUT 2V/DIV 1ms/DIV 3111 G34 SOFT-START LOAD CURRENT (A) DIE TEMPERATURE RISE (°C) 1.6

3111 G35

VIN = 2.7V VIN = 12V VIN = 5V LOAD CURRENT (A) DIE TEMPERATURE (°C) 0.4 0.8 1.2 1.6

3111 G36

VIN = 2.7V VIN = 12V VIN = 5V LOAD CURRENT (A) DIE TEMPERATURE RISE (°C) 1.8 1.6

3111 G37

VIN = 2.7V VIN = 12V VIN = 5V VCC (V) SW1, SW2 MINIMUM LOW TIME (ns) 100 150 200 300 2.5 3 3.5 4

3111 G38

4.5 5 250 ILOAD = 300mA SW1, VIN = 4V SW2, VIN = 6V TEMPERATURE (°C) –50 SW1, SW2 MINIMUM LOW TIME (ns)70 110 130 150 250 190 0 50

3111 G39

ILOAD = 300mA SW1, VIN = 4V SW2, VIN = 6V

For more information www.linear .com/L TC3111 PIN FUNCTIONS (DFN/MSOP) COMP (Pin 1/Pin 1): Error Amp Output. An R-C network connected from this pin to FB sets the loop compensa- tion for the voltage converter. Refer to the Applications Information section for component selection details. FB (Pin 2/Pin 2): Feedback Voltage Input. Connect the VOUT resistor divider tap to this pin. The output voltage can be adjusted from 2.5V to 15V by the following equation: VOUT = 0.8V • 1 + R1   where R1 is the resistor between VOUT and FB and R2 is the resistor between FB and GND SNSGND (Pin 3/Pin 3): This pin must be connected to ground. RUN (Pin 4/Pin 4): Input to Enable or Disable the IC and Set Custom Input Undervoltage Lockout (UVLO) Thresholds. The RUN pin can be driven by an external logic signal to enable and disable the IC. In addition, the voltage on this pin can be set by a resistive voltage divider connected to the input supply in order to provide accurate turn-on and turn-off (UVLO) thresholds determined by: VIN(RUN) = 1.2V • 1 + R5   The IC is enabled if RUN exceeds 1.2V nominally. Once enabled, the UVLO threshold has a built-in hysteresis of approximately 120mV, turn-off will occur when the voltage on RUN drops to below 1.08V nominally. To continuously enable the IC, RUN can be tied directly to the input voltage up to the absolute maximum rating. This pin should not be left unconnected. VIN (Pin 5/Pin 5): Input Supply Voltage. This pin should be bypassed to the ground plane with at least 10µF of low ESR, low ESL ceramic capacitance. Place this capacitor as close to the pin as possible and provide as short a return path to the ground plane as possible. SW1 (Pin 6/Pin 6): The external inductor and internal switches A and B are connected here. BST1 (Pin 7/Pin 7): Boosted Floating Driver Supply for A-Switch Driver. Connect a 0.1µF capacitor from this pin to SW1. BST2 (Pin 8/Pin 10): Boosted Floating Driver Supply for D-Switch Driver. Connect a 0.1µF capacitor from this pin to SW2. SW2 (Pin 9/Pin 11): The external inductor and internal switches C and D are connected here. V OUT (Pin 10/Pin 12): Regulated Output Voltage. This pin should be connected to a low ESR ceramic capacitor. The capacitor should be placed as close to the pin as possible and have a short return to the ground plane. NC (Pin 11/Pin 13): Not Connected. This pin should be connected to ground. V CC (Pin 12/Pin 14): External Capacitor Connection for the Regulated VCC Supply. This supply is used to operate internal circuitry and switch drivers. VCC will track VIN up to 4.2V typical, but will maintain this voltage when VIN > 4.2V. Connect a 1µF ceramic capacitor from this pin to GND. This pin can be tied to an external supply up to 5.5V. Refer to the Operation section of this data sheet under Power VCC from an External Source for more details. PWM/SYNC (Pin 13/Pin 15): Burst Mode Control and Synchronization Input. A DC voltage < 0.5V commands Burst Mode operation independent of load current, >1.5V commands 800kHz fixed frequency mode. A digital pulse train between 600kHz and 1.5MHz applied to this pin will override the internal oscillator and set the operating fre - quency. The pulse train should have a minimum high time or low time greater than 100ns (Note 6). Note the LTC3111 has reduced power capability when operating in Burst Mode operation. This pin should not be left unconnected. SGND (Pin 14/Pin 16): Signal Ground. Terminate the RUN input voltage divider and output voltage divider to SGND. PGND (Exposed Pad Pin 15/Pin 8, 9, Exposed Pad Pin 17) Power Ground. The exposed pad must be soldered to the PCB and electrically connected to ground through the shortest and lowest impedance connection possible.

For more information www.linear .com/L TC3111 SIMPLIFIED BLOCK DIAGRAM ERROR AMP PWM/SYNC COMP FB GND 0.8V VIN VCC –1A VOUT SOFT-START RAMP 3111 BD 800k OSCILLATOR 4.2V REGULATOR/ CLAMP REFERENCE Burst Mode OPERATION PLL ++– ILIMIT IPEAK IZERO ADRV BDRV VCC CDRV DDRV LOGIC REVERSE ILIM DRIVERS VCC START VIN UVLO VCC UVLO RUNRUN STOP BST1 BST2VIN VOUTSW1 SW2 4.7µH VCC 0.8V 1.2V 5.8A 0.1A 2.1V START 1.2V VIN + 2.35V –BDRV ADRV VCC VCC COUT VCC CDRV DDRV GND CIN

loads when Burst Mode operation is commanded. of the Electrical Characteristics). installed in the application circuit. minimizing any DC error in the output voltage.

3111 F01

Figure 1. Error Amplifier and Compensation Network The buck-boost converter has two current limit circuits. resistance from the FB to ground should exceed 100kΩ. an instantaneous hard output short.

normal operating current limit. internal soft-start circuit with a nominal duration of 2ms. impaired performance or reliability. Figure 4. The curves were taken at room temperature, powered from an alternate source or VOUT after start-up.

the buck-boost converter is shown in Figure 2. loop transfer function throughout the operational modes. comprised of resistors R1 and R2 as show in Figures 1. on the compensation network. that the Thevenin resistance be greater than 100kΩ. thresholds with the addition of an external resistor divider. a start-up sequence will ensue.

3111 F02

Figure 2. Buck-Boost Switch Topology duty cycle to support the output regulation voltage. riod, providing a direct current path from V IN to V OUT. which will vary with load current.

programmable turn on and turn off threshold. feeding VCC from a voltage above 4.2V is higher efficiency. cal) in amps and η is the efficiency. transitions from and to burst and PWM mode operation.

3111 F03

Figure 3. Accurate RUN Comparator

seconds, which is typically 160ns. 15μH if the converter is to be used in the boost region. for 5VOUT and 10μH for 12VOUT. Performance Characteristics section of this data sheet. minimizes the chances of interference with other circuitry. sizing, and EMI requirements of a particular application. generally decreases with increased inductance. Table 1. Representative Buck-Boost Surface Mount Inductors

VOUT – VIN + tLOW • f • VIN VOUT where f is the frequency in Hz, COUT is the output capaci- tance in μ F, ILOAD is the output current in amps and tLOW is the switch pin minimum low time in seconds, which is typically 160ns. In addition to output ripple generated across the output capacitor, there is also output ripple produced across the internal resistance of the output capacitor. The ESR- generated output voltage ripple is proportional to the series resistance of the output capacitor and is given by the following expression: ∆VP-P BUCK( ) = ILOAD •RESR 1– tLOW • f ≅ ILOAD •RESR ∆VP-P BOOST( ) = ILOAD •RESR • VOUT VIN 1– tLOW • f( ) ≅ ILOAD •RESR • VOUT VIN where RESR is the series resistor of the output capacitor and all other terms are as previously defined. Input Capacitor Selection It is recommended that a low ESR ceramic capacitor with a value of at least 10μF be located as close to the VIN pin as possible. In addition, the return trace from the pin to the ground plane should be made as short as possible. It is important to minimize any stray resistance from the converter to the battery or power source. If cabling is required to connect the LTC3111 to the battery or power supply, a higher ESR capacitor or a series resistor with a low ESR capacitor in parallel with the low ESR capacitor may be required to damp out ringing caused by the cable inductance. Capacitor Vendor Information Both the input bypass capacitors and output capacitors used with the LTC3111 must be low ESR and designed to handle the large AC currents generated by switching converters. This is important to maintain proper functioning of the IC and to reduce input/output ripple. Many modern low voltage ceramic capacitors experience significant loss in capacitance from their rated value with increased DC bias voltages. For example, it is not uncommon for a small surface mount ceramic capacitor to lose more than 50% of its rated capacitance when operated near its rated voltage. As a result, it is sometimes necessary to use a larger value capacitance or a capacitor with a larger case size than required in order to actually realize the intended capacitance at the full operating voltage. For details, con- sult the capacitor vendor’s curve of capacitance versus DC bias voltage. The capacitors listed in Table 2 provide a sampling of small surface mount ceramic capacitors that are well suited to LTC3111 application circuits. All listed capacitors are either X5R or X7R dielectric in order to ensure that capacitance loss over temperature is minimized.

Table 2. Representative Bypass and Output Capacitors

For more information www.linear .com/L TC3111 APPLICATIONS INFORMATION PCB Layout Considerations The LTC3111 switches large currents at high frequencies. Special attention should be paid to the PCB layout to en- sure a stable, noise-free and efficient application circuit. Figure 4 presents a representative PCB layout to outline some of the primary considerations. A few key guidelines are outlined below: All cir culating high current paths should be kept as short as possible. This can be accomplished by keeping the routes to all circled components in the figure below as short and as wide as possible. Capacitor ground connections should via down to the ground plane in the shortest route possible. The bypass capacitors on VIN should be placed as close to the IC as possible and should have the shortest possible paths to ground. 2. The exposed pad is the power ground connection for the LTC3111. Multiple vias should connect the back pad directly to the ground plane. In addition maximi - zation of the metallization connected to the back pad will improve the thermal environment and improve the power handling capabilities of the IC. 3. The circled components and their connections should all be placed over a complete ground plane to minimize loop cross-sectional areas. This minimizes EMI and reduces inductive drops. 4. Connections to all of the circled components should be made as wide as possible to reduce the series resistance. This will improve efficiency and maximize the output current capability of the buck-boost converter. THERMAL AND PGND VIAS Figure 4a. Top and Fabrication Layer of Example PCB Figure 4b. Bottom and Fabrication Layer of Example PCB COUT CBST1 CBST2 CIN

For more information www.linear .com/L TC3111 5. To prevent large circulating currents from disrupting the output voltage sensing, the ground for each resistor divider should be returned to the ground plane using a via placed close to the IC and away from the power connections. 6. Keep the connection from the resistor dividers to the feedback pins (FB pin) as short as possible and away from the switch pin connections. 7. Crossover connections should be made on inner copper layers if available. If it is necessary to place these on the ground plane, make the trace on the ground plane as short as possible to minimize the disruption to the ground plane. Buck Mode Small-Signal Model The LTC3111 uses a voltage mode control loop to maintain regulation of the output voltage. An externally compen - sated error amplifier drives the COMP pin to generate the appropriate duty cycle of the power switches. Use of an external compensation network provides the flexibility for optimization of closed-loop performance over the wide variety of output voltages, switching frequencies, and external component values supported by the LTC3111. The small-signal transfer function of the buck-boost con- verter is different in the buck and boost modes of operation an d care must be taken to ensure stability in both operating regions. When stepping down from a higher input voltage to a lower output voltage, the converter will operate in buck mode and the small-signal transfer function from the error amplifier output COMP, to the converter output voltage is given by the following equation: VO VCOMP BUCK = GBUCK 1+ s 2• π • fZ 1+ s 2• π • fO •Q + s 2• π • fO The gain term, G BUCK, is comprised of three different components: the gain of the analog divider, the gain of the pulse-width modulator, and the gain of the power stage as given by the following expressions where VIN is the input voltage to the converter, f is the switching frequency, R is the load resistance, and t LOW is the switch pin mini- mum low time, which is typically 160ns. The parameter RS represents the average series resistance of the power stage and can be approximated as twice the average power switch resistance plus the DC resistance of the inductor. GBUCK = GDIVIDER •GPWM •GPOWER GDIVIDER = 18 VIN GPWM = 2.5• 1– t LOW • f( ) GPOWER = VIN •R 1– tLOW • f( ) • R + RS( ) Notice that the gain of the analog divider cancels the input voltage dependence of the power stage. As a result, the buck mode gain is approximated by a constant as given by the following equation: GBUCK = 45• R R+ RS ≅ 45 = 33dB The buck mode transfer function has a single zero which is generated by the ESR of the output capacitor. The zero frequency, fZ, is given by the following expression where RC and CO are the ESR and value of the output filter ca- pacitor respectively. fZ = 1 2• π •RC •CO In most applications, an output capacitor with a very low ESR is utilized in order to reduce the output voltage ripple to acceptable levels. Such low values of capacitor ESR result in a very high frequency zero and as a result the zero is commonly too high in frequency to significantly impact compensation of the feedback loop. The denominator of the buck mode transfer function exhibits a pair of resonant poles generated by the LC filtering of the power stage. The resonant frequency of the power stage, f O, is given by the following expression where L is the value of the inductor: fO = 1 2• π • R+ RS L •CO R+ RC( ) ≅ 1 2• π • L •C O APPLICATIONS INFORMATION

For more information www.linear .com/L TC3111 The quality factor, Q, has a significant impact on compen- sation of the voltage loop since a higher Q factor produces a sharper loss of phase near the resonant frequency. The quality factor is inversely related to the amount of damping in the power stage and is substantially influenced by the average series resistance of the power stage, R S. Lower values of R S will increase the Q and result in a sharper loss of phase near the resonant frequency and will require more phase boost or lower bandwidth to maintain an adequate phase margin. Q = L •CO R+ RC( ) • R + RS( ) R •RC •CO + L + CO •RS • R + RC( ) ≅ L •CO L R + CO •RS Boost Mode Small-Signal Model When stepping up from a lower input voltage to a higher output voltage, the buck-boost converter will operate in boost mode where the small-signal transfer function from control voltage, VCOMP, to the output voltage is given by the following expression: VO VCOMP BOOST = GBOOST 1+ s 2• π • fZ  • 1– s 2• π • fRHPZ 1+ s 2• π • fO •Q + s 2• π • fO In boost mode operation, the transfer function is character- ized by a pair of resonant poles and a zero generated by the ESR of the output capacitor as in buck mode. However, in addition there is a right-half-plane zero which generates increasing gain and decreasing phase at higher frequen- cies. As a result, the crossover frequency in boost mode operation generally must be set lower than in buck mode in order to maintain sufficient phase margin. The boost mode gain, G BOOST, is comprised of three components: the analog divider, the pulse width modula- tor and the power stage. The gain of the PW M remains the same as in buck mode operation, but the gain of the analog divider and power stage in boost mode are given by the following equation: GDIVIDER = 18 VOUT GPOWER = VOUT 2 1– tLOW • f( ) • VIN By combining the individual terms, the total gain in boost mode can be reduced to the following expression. Notice that unlike in buck mode, the gain in boost mode is a function of both the input and output voltage: GBOOST = 45• VOUT VIN In boost mode operation, the frequency of the right-half- plane zero, f RHPZ, is given by the following expression. The frequency of the right-half-plane zero decreases at higher loads and with larger inductors: fRHPZ − R • 1– tLOW • f( ) 2 • VIN 2• π •L • VOUT 2 In boost mode, the resonant frequency of the power stage has a dependence on the input and outputvoltage as shown by the following equation: fO = 1 2• π • RS + R • VIN2 VOUT 2 L •CO • R + RC( ) ≅ 1 2• π • VIN VOUT

1 L •CO Finally, the magnitude of the quality factor of the power stage in boost mode operation is given by the following expression: Q = L •CO •R • R S + R • VIN2 VOUT 2 L + CO •RS •R APPLICATIONS INFORMATION

For more information www.linear .com/L TC3111 APPLICATIONS INFORMATION Compensation Of The Voltage Loop The small-signal models of the LTC3111 reveal that the transfer function from the error amplifier output, COMP, to the output voltage is characterized by a set of resonant poles and a possible zero generated by the ESR of the output capacitor as shown in the Bode plot of Figure 5. In boost mode operation, there is an additional right-half- plane zero that produces phase lag and increasing gain at higher frequencies. Typically, the compensation network is designed to ensure that the loop crossover frequency is low enough that the phase loss from the right-half-plane zero is minimized. The low frequency gain in buck mode is a constant, but varies with both V IN and VOUT in boost mode. For charging or other applications that do not require an optimized output voltage transient response, a simple Type I compensation network as shown in Figure 6 can be used to stabilize the voltage loop. To ensure sufficient phase margin, the gain of the error amplifier must be low enough that the resultant crossover frequency of the control loop is well below the resonant frequency. In most applications, the low bandwidth of the Type I com- pensated loop wi ll not provide sufficient transient response performance. To obtain a wider bandwidth feedback loop, optimize the transient response, and minimize the size of the output capacitor, a Type III compensation network as shown in Figure 7 is required. A Bode plot of the typical Type III compensation network is shown in Figure 8. The Type III compensation network provides a pole near the origin which produces a very high loop gain at DC to minimize any steady-state error in the regulation voltage. Tw o zeros located at f ZERO1 and fZERO2 provide sufficient phase boost to allow the loop crossover frequency to be set above the resonant frequency, f O, of the power stage. The Type III compensation network also introduces a second and third pole. The second pole, at frequency fPOLE2, reduces the error amplifier gain to a zero slope to prevent the loop crossover from extending 0.8V

3111 F06

Figure 6: Error Amplifier with Type I Compensation 0.8V

3111 F07

Figure 7: Error Amplifier with Type III Compensation Figure 5: Buck-Boost Converter Bode Plot GAIN PHASE BOOST MODE BUCK MODE –20dB/DEC –40dB/DEC fO 3111 F05fRHPZ

For more information www.linear .com/L TC3111 APPLICATIONS INFORMATION too high in frequency. The third pole at frequency fPOLE3 provides attenuation of high frequency switching noise. The transfer function of the compensated Type III error amplifier from the input of the resistor divider to the output of the error amplifier, COMP, is: VCOMP VO = GCOMP • 1+ s 2• π • fZERO1  • 1 + s 2• π • fZERO2 s • 1 + s 2• π • fPOLE2  • 1 + s 2• π • fPOLE3 The compensation gain is given by the following equation. The simpler approximate value is sufficiently accurate in most cases since C FB is typically much larger in value than CPOLE. GCOMP ≅ 1 R1• CFB + CPOLE( ) ≅ 1 R1•CFB The pole and zero frequencies of the Type III compensation network can be calculated from the following equations where all frequencies are in Hz, resistances are in ohms, and capacitances are in farads. fZERO1 = 1 2• π •RFB •CFB fZERO2 = 1 2• π R1+ RFF( ) •CFF ≅ 1 2• π •R1•CFF fPOLE2 = 1 2• π • CFB •CPOLE CFB + CPOLE

RFB ≅ 1 2• π •RFB •CPOLE fPOLE3 = 1 2• π •RFF •CFF In most applications the compensation network is designed so that the loop crossover frequency is above the resonant frequency of the power stage, but sufficiently below the boost mode right-half-plane zero to minimize the additional phase loss. Once the crossover frequency is decided upon, the phase boost provided by the compensation network is centered at that point in order to maximize the phase margin. A larger separation in frequency between the zeros and higher order poles will provide a higher peak phase boost but may also increase the gain of the error amplifier which can push out the loop crossover to a higher frequency. The Q of the power stage can have a significant influence on the design of the compensation network because it determines how rapidly the 180° of phase loss in the power stage occurs. For very low values of series resistance, R the Q will be higher and the phase loss will occur sharply. In such cases, the phase of the power stage will fall rapidly to –180° above the resonant frequency and the total phase margin must be provided by the compensation network. fZERO1 PHASE GAIN –20dB/DEC –20dB/DEC fZERO2

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Figure 8: Type III Compensation Bode Plot

less phase boost is required of the compensation network. in Figure 9. The nominal frequency of this pole is 400kHz. the phase contributed by this additional pole is negligible. designing the compensation network. application are given below. factor in determining the bandwidth of the control loop.

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Figure 9. Internal Loop Filter

Figure 10. Converter Bode Plot VIN = 3.5V, VOUT = 5V, R = 10Ω

3111 F10

yields the desired 45° of phase margin. target crossover frequency for the compensated loop. with the desired phase boost, center frequency and gain.

For more information www.linear .com/L TC3111 APPLICATIONS INFORMATION A reasonable choice is to pick the frequency of the poles, fP, to be 50 times higher than the frequency of the zeros, fZ, which provides a peak phase boost of approximately 60° as was assumed previously. Next, the phase boost must be centered so that the peak phase occurs at the target crossover frequency. The frequency of the maximum phase boost, fCENTER, is the geometric mean of the pole and zero frequency as: fCENTER = fP • fZ = 50 • fZ ≅ 7 • fZ Therefore, in order to center the phase boost given a factor of 50 separation between the pole and zero frequencies, the zero should be located at one-seventh of the crossover frequency and the poles should be located at seventh times the crossover frequency as given by the following equation: fZ = fC 7 = 40kHz 7 = 5.71kHz fP = 7 • fC = 7 • 40kHz= 280kHz This placement of the poles and zeros will yield a peak phase boost of 60° that is centered at the crossover frequency, fC. Next, in order to produce the desired target crossover frequency, the gain of the compensation network at the point of maximum phase boost, GCENTER, must be set to –13.5dB. The gain of the compensated error amplifier at the point of the phase gain is given by: GCENTER = 10 •log 2• π • fP 2• π • fZ( ) 3 • R1•C FB( ) dB Assuming a multiple of 50 separation between the pole and zero frequencies this can be simplified to the follow- ing expression: GCENTER = 20 •log 50 2• π • fC •R1•CFB  dB This equation completes the set of constraints needed to determine the compensation component values. Specifi- cally, the two zeros, fZERO1 and fZERO2, should be located near 5.71kHz. The two poles, fPOLE2 and fPOLE3, should be located near 280kHz and the gain should be set to provide a gain at the crossover frequency of GCENTER = –13.5dB. The first step in defining the compensation component values is to pick a value for R1 that provides an acceptably low quiescent current through the resistor divider. A value of R1 = 1MΩ is a reasonable choice. Next, the value of CFB can be found in order to set the error amplifier gain at the crossover frequency to –13.5dB as follows: GCENTER = –13.5dB= 20 •log 50 2• π • 40kHz •1 MΩ •CFB CFB = 50 2• π • 40kHz •1 MΩ •10 – 13.5 ≅ 1000pF The compensation poles can be set at 280kHz and the zeros at 5.71kHz by using the expressions for the pole and zero frequencies given in the previous sections. Setting the frequency of the first zero, fZERO1, to 5.71kHz results in the following value for RFB: RFB = 1 2• π •5.71kHz•1000pF ≅ 28.0kΩ This leaves the free parameter, C POLE, to set frequency fPOLE1 to the common pole frequency of 280kHz as given: CPOLE = 1 2• π •280kHz •28kΩ ≅ 22pF

For more information www.linear .com/L TC3111 Figure 11: Compensation Error Amplifier Bode Plot Figure 12: Complete Loop Bode Plot (Hz) –20 (dB) (DEG) –10 10 1k 10k 1M

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–30 100 100k 0 0 –40 –45 –90 40kHz, 57° 40kHz, –14dB GAIN PHASE (Hz) 0 –90 (dB) (DEG) 100 1k 10k 100k 1M

3111 F12

–10 –20 –30 –40 –45 –135 –180 –225 –270 135 180 40kHz, 59° GAIN PHASE APPLICATIONS INFORMATION Next, CFF can be chosen to set the second zero, fZERO2, to the common zero frequency of 5.71kHz. CFF = 1 2• π •5.71 kHz•1 MΩ ≅ 27pF Finally, the resistor value RFF can be chosen to place the second pole at 280kHz. RFF = 1 2• π •280kHz •27pF ≅ 20kΩ Now that the pole frequencies, zero frequencies and gain of the compensation network have been established, the next step is to generate a Bode plot for the compensated error amplifier to confirm its gain and phase properties. A Bode plot of the error amplifier with the designed com- pensation component values is shown in Figure 11. The Bode plot confirms that the peak phase occurs at 40kHz and the phase boost at that point is 57°. In addition, the gain at the peak phase frequency is –14dB which is close to the design target. The final step in the design process is to compute the Bode plot for the entire designed compensation network and confirm its phase margin and crossover frequency. The complete loop Bode plot for this example is shown in Figure 12. The loop crossover frequency is 40kHz and the phase margin is approximately 59°. The Bode plot for the complete loop should be checked over all operating conditions and for variations in component values to ensure that sufficient phase margin exist in all cases. The stability of the loop should also be confirmed via time domain simulation and by the transient response of the converter in the actual circuit.

For more information www.linear .com/L TC3111 TYPICAL APPLICATIONS 1, 2, 3 Li-Ion to 5V Wide VIN to 5VOUT Efficiency SW1 0.1µF 27pF 1µF 33pF 191k 154k R

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26.1k 0.1µF VIN 3V TO 12.6V 4.7µH SW2 BST1 BST2 VIN L TC3111 PGND VOUT 22µF VOUT 750mA V IN > 4V10µF

1 TO 3-CELL

R 274k 698k 1.13M LOAD CURRENT (A) EFFICIENCY (%) 100 0.0001 0.001 0.1 1 10

3111 TA02b

0.01 VIN = 3.6V VIN = 7.2V VIN = 10.8V

For more information www.linear .com/L TC3111 TYPICAL APPLICATIONS LTC3111 Synchronized to a 1.5MHz Clock, 5V/1A Output 3.3V Backup from a High Voltage Capacitor Bank Runs Down to VIN = 2V with 500mA Load SW1 0.1µF 15pF MBR0520L OPTIONAL 191k

3111 TA03a

57.6k 0.1µF VIN 2.5V TO 15V 2.2µH SW2 BST1 BST2 VIN L TC3111 SGND PGND VOUT 1.5MHz CLOCK 22µF 1µF VOUT V IN > 5V10µF PWM/SYNC RUN FB VCCSNSGND COMP OFF ON SW1 0.1µF 33pF 36pF MBR0520L OPTIONAL 316k

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24.3k 0.1µF VIN 2V TO 15V 4.7µH SW2 BST1 BST2 VIN L TC3111 VOUT VCC 33µF 1µF VOUT 3.3V 500mA100µFCIN 214mF PWM/SYNC RUN FB V CC VCCSNSGND COMP SGND PGND VIN 5V/DIV VOUT 2V/DIV IOUT 500mA/DIV

2 SEC/DIV 3111 TA04b

For more information www.linear .com/L TC3111 TYPICAL APPLICATIONS Stepped Response from 1 or 2 Li-Ion to 12V Adapter Source VOUT = 5V SW1 0.1µF 27pF 1µF 33pF 191k

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26.1k 0.1µF 12V ADAPTER 4.7µH SW2 BST1 BST2 VIN L TC3111 VOUT VCC 1- OR 2-SERIES Li-Ion CELLS 22µF VOUT 1.5A V IN > 5V47µF PWM/SYNC RUN FB SNSGND COMP OFF ON B520C BURST PWM LT®4352 IDEAL DIODE SGND PGND VIN 2V/DIV TWO Li-Ion CELLS VOUT 500mV/DIV INDUCTOR CURRENT 1A/DIV 1ms/DIVIOUT = 500mA 3111 TA05b Custom Input Undervoltage Lockout Thresholds SW1 0.1µF 27pF 1µF 33pF 191k316k

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26.1k 0.1µF VIN 5V TO 15V ENABLED WHEN VIN REACHED 5V DISABLED WHEN VIN FALLS BELOW 4.5V 4.7µH SW2 BST1 BST2 VIN L TC3111 VOUT VCC VCC VCC 22µF VOUT 1.5A10µF PWM/SYNC RUN FB SNSGND COMP SGND PGND VIN 10V/DIV VOUT 5V/DIV INDUCTOR CURRENT 1A/DIV 2ms/DIVRLOAD = 3.3/uni03A9 3111 TA08b VIN 10V/DIV VOUT 5V/DIV INDUCTOR CURRENT 1A/DIV 2ms/DIVRLOAD = 3.3/uni03A9 3111 TA08c

For more information www.linear .com/L TC3111 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 3.00 ±0.10 (2 SIDES) 4.00 ±0.10 (2 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.40 ±0.10 BOTTOM VIEW—EXPOSED PAD 1.70 ±0.10 0.75 ±0.05 R = 0.115 TYP R = 0.05 TYP

3.00 REF

1.70 ±0.05 148 PIN 1 TOP MARK (SEE NOTE 6)

0.200 REF

0.00 – 0.05 (DE14) DFN 0806 REV B PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 2.20 ±0.05 0.70 ±0.05 3.60 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.25 ±0.05

0.50 BSC

3.30 ±0.05 3.30 ±0.10 14-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1708 Rev B)

For more information www.linear .com/L TC3111 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MSOP (MSE16) 0213 REV F 0.53 ±0.152 (.021 ±.006) SEATING PLANE 0.18 (.007) 1.10 (.043) MAX 0.17 –/uni00A00.27 (.007 – .011) TYP 0.86 (.034) REF 0.50 (.0197) BSC 16151413121110 1 2 3 4 5 6 7 8 1 8 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 0.254 (.010) 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 5.10 (.201) MIN 3.20 – 3.45 (.126 – .136) 0.889 ±0.127 (.035 ±.005) RECOMMENDED SOLDER PAD LAYOUT 0.305 ±0.038 (.0120 ±.0015) TYP 0.50 (.0197) BSC BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 ±0.102 (.112 ±.004) 2.845 ±0.102 (.112 ±.004) 4.039 ±0.102 (.159 ±.004) (NOTE 3) 1.651 ±0.102 (.065 ±.004) 1.651 ±0.102 (.065 ±.004) 0.1016 ±0.0508 (.004 ±.002) 3.00 ±0.102 (.118 ±.004) (NOTE 4) 0.280 ±0.076 (.011 ±.003) REF 4.90 ±0.152 (.193 ±.006) DETAIL “B” DETAIL “B” CORNER TAIL IS PART OF THE LEADFRAME FEATURE. FOR REFERENCE ONL Y NO MEASUREMENT PURPOSE

0.12 REF

0.35 REF 16-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1667 Rev F)

For more information www.linear .com/L TC3111 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 1/14 Clarified graphs 1, 4, 5, 6

For more information www.linear .com/L TC3111  LINEAR TECHNOLOGY CORPORATION 2013 LT 0114 REV A • PRINTED IN USA Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L TC3111 RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LTC3533 2A (IOUT), 2MHz Synchronous Buck-Boost DC/DC Converter VIN: 1.8V to 5.5V, VOUT: 1.8V to 5.25V, IQ = 40μA, ISD < 1μA, DFN Package LTC3113 3A (IOUT), 2MHz Low Noise Buck-Boost DC/DC Converter VIN: 1.8V to 5.5V, VOUT: 1.8V to 5.5V, IQ = 40μA, ISD < 1μA, DFN and TSSOP Packages LTC3534 7V, 500mA (IOUT), Synchronous Buck-Boost DC/DC Converter VIN: 2.4V to 7V, VOUT: 1.8V to 7V, IQ = 25μA, ISD < 1μA, DFN and GN Packages LTC3129/ LTC3129-1 15V, 200mA (IOUT), Synchronous Buck-Boost DC/DC Converter with 1.3µA Quiescent Current VIN: 2.42V to 15V, VOUT: 1.4V to 15.75V, IQ = 1.3μA, ISD < 100nA, QFN and MSOP Packages LTC3112 15V, 2.5A (IOUT), Synchronous Buck-Boost DC/DC Converter VIN: 2.7V to 15V, VOUT = 5V, IQ = 50μA, ISD < 1μA, DFN and TSSOP Packages LTC3785 10V, High Efficiency, Synchronous, No RSENSE™ Buck-Boost Controller VIN: 2.7V to 10V, VOUT: 2.7V to 10V, IQ = 86μA, ISD < 15μA, QFN Package LTC3115-1/ LTC3115-2 40V, 2A (I OUT), Synchronous Buck-Boost DC/DC Converter VIN: 2.7V to 40V, VOUT = 2.7V to 40V, IQ = 30μA, ISD < 1μA, DFN and TSSOP Packages LTC3789 High Efficiency, Synchronous, 4-Switch Buck-Boost Converter V IN: 4V to 38V, VOUT: 0.8V to 38V, IQ = 3mA, ISD < 60μA, QFN and SSOP Packages LTC3122 15V, 2.5A (IOUT), Synchronous Step-Up DC/DC Converter with Output Disconnect VIN:1.8V to 5.5V, VOUT: 2.2V to 15V. IQ = 25µA, ISD < 1µA, DFN and MSOP Packages Regulated 12V Output from Wide Range Input Supply Wide VIN to 12VOUT Efficiency SW1 0.1µF 39pF 1µF 18pF 2.21M 158k

3111 TA06a

44.2k 0.1µF VIN 2.5V TO 15V 10µH SW2 BST1 BST2 VIN L TC3111 VOUT VCC VCC 22µF VOUT 12V 0.5A, VIN > 5V 1.0A, VIN > 9V10µF PWM/SYNCBURST PWM RUN FB SNSGND COMP OFF ON SGND PGND LOAD CURRENT (A) 0.0001 EFFICIENCY (%) 100 0.001 0.01 0.1 1 10

3111 TA06b

VIN = 5V VIN = 12V BURST PWM

Product Information

LTC3111 specifications and overview.

Summary

6A Low Noise, High Performance Buck-Boost DC/DC Converter Rev. 0

Description

6A Low Noise, High Performance Buck-Boost DC/DC Converter Rev. 0

Source title LTC3111 Datasheet(PDF) - Analog Devices

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