LTC2000

LTC2000 – 16-/14-/11-Bit 2.5Gsps DACs

Document overview

• Manufacturer or author: Analog Devices
• PDF pages: 54

Technical content

For more information www.linear .com/L TC2000 BLOCK DIAGRAM FEATURES DESCRIPTION 16-/14-/11-Bit 2.5Gsps DACs The LT C®2000 is a family of 16-/14-/11-bit 2.5Gsps cur- rent steering DACs with exceptional spectral purity. The single (1.25Gsps mode) or dual (2.5Gsps mode) port source synchronous LVDS interface supports data rates of up to 1.25Gbps using a 625MHz DDR data clock, which can be either in quadrature or in phase with the data. An internal synchronizer automatically aligns the data with the DAC sample clock. Additional features such as pattern generation, LVDS loo- pout and junction temperature sensing simplify system development and testing. A serial peripheral interface (SPI) port allows configura - tion and read back of internal registers. Operating from 1.8V and 3.3V supplies, the LTC2000 consumes 2.2W at 2.5Gsps and 1.3W at 1.25Gsps.

APPLICATIONS

n 80dBc SFDR at 70MHz fOUT n >68dBc SFDR from DC to 1000MHz fOUT n 40mA Nominal Full-Scale, ±1V Output Compliant n 10mA to 60mA Adjustable Full-Scale Current Range n Single or Dual Port DDR LVDS and DHSTL Interface n Low Latency (7.5 Cycles for Single Port,

11 Cycles for Dual Port)

n >78dBc 2-Tone IMD from DC to 1000MHz fOUT n –165dBc/Hz Additive Phase Noise at 1MHz Offset for 65MHz f OUT n 170-Lead (9mm × 15mm) BGA Package n Broadband Communication Systems n DOCSIS CMTS n Direct RF Synthesis n Radar n Instrumentation n Automatic Test Equipment All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 8330633. LVDS RECEIVERS DDR DATA FLIP-FLOPS 4:1 TSTP/N PD CS SCK SDI SDO SVDD 50/uni03A9 IOUTP IOUTN FSADJ REFIO 50/uni03A9 10k 2000 BD CKP/NGNDDVDD33DVDD18 AVDD33AVDD18 GAIN ADJUST CLOCK SYNC CLK RECEIVER DELAY ADJUST DCKOP/N DCKIP/N DBP/N[15:0] DAP/N[15:0] CLK DIVIDER ÷2 OR ÷4 REF SPIPATTERN GENERATOR JUNCTION TEMPERATURE 16-BIT DAC fOUT (MHz) SFDR (dBc) 100 200 400 600 800

2000 TA01b

DIGITAL AMPLITUDE = 0dBFS IOUTFS = 40mA SFDR vs fOUT, fDAC = 2.5Gsps

For more information www.linear .com/L TC2000 TABLE OF CONTENTS

Description

T T T Operation D Sin S P P R S D A DA D L L C M M M Pa S O G S ynchronizing Multiple LTC2000s in S ynchronizing Multiple LTC2000s in P T

For more information www.linear .com/L TC2000 PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS 3V to Min (AVDD33 + 0.3V, 4V) 3V to Min (DVDD33 + 0.3V, 4V) 3V to Min (DVDD33 + 0.3V, 4V) 3V to Min (DVDD33 + 0.3V, 4V) 3V to Min (AVDD33 + 0.3V, 4V) (Notes 1, 2) LTC2000-16 LTC2000-14 LTC2000-11 S R Q P N M L K J H GND GND DVDD33AVDD33 GND G F E D C B A 2 3 4 5 6 7 8 9 10 BGA PACKAGE 170-LEAD (9mm × 15mm × 1.54mm) TOP VIEW AVDD18 DVDD18 TJMAX = 125°C, θJA = 20°C/W , θJB = 8°C/W , θJCtop = 9°C/W , θJCbottom = 3°C/W S R Q P N M L K J H DVDD33 AVDD18 GND GND GND G F E D C B A 2 3 4 5 6 7 8 9 10 BGA PACKAGE 170-LEAD (9mm × 15mm × 1.54mm) TOP VIEW AVDD33 DVDD18 TJMAX = 125°C, θJA = 20°C/W , θJB = 8°C/W , θJCtop = 9°C/W , θJCbottom = 3°C/W S R Q P N M L K J H GND GND DVDD33 AVDD18 GND G F E D C B A 2 3 4 5 6 7 8 9 10 BGA PACKAGE 170-LEAD (9mm × 15mm × 1.54mm) TOP VIEW AVDD33 DVDD18 TJMAX = 125°C, θJA = 20°C/W , θJB = 8°C/W , θJCtop = 9°C/W , θJCbottom = 3°C/W CS, PD, SCK, SDI, SDO ...–0. 3V to Min (SVDD + 0.3V, 4V) Operating Temperature Range LTC2 70°C LTC2 C to 85°C 5°C C to 125°C 0°C

For more information www.linear .com/L TC2000 ORDER INFORMATION LTC2000 C Y –16 #PBF LEAD FREE DESIGNATOR PBF = Lead Free RESOLUTION 16 = 16-Bit Resolution 14 = 14-Bit Resolution 11 = 11-Bit Resolution PACKAGE T YPE 170-Lead (15mm × 9mm × 1.54mm) BGA TEMPERATURE GRADE C = Commercial Temperature Range (0°C to 70°C) I = Industrial Temperature Range (–40°C to 85°C) PRODUCT PART NUMBER PART NUMBER BALL FINISH PART MARKING* PACKAGE TYPE MSL RATING TEMPERATURE RANGE LTC2000CY-16#PBF SAC305 (RoHS) LTC2000Y-16 BGA 3 0°C to 70°C LTC2000CY-14#PBF SAC305 (RoHS) LTC2000Y-14 BGA 3 0°C to 70°C LTC2000CY-11#PBF SAC305 (RoHS) LTC2000Y-11 BGA 3 0°C to 70°C LTC2000IY-16#PBF SAC305 (RoHS) LTC2000Y-16 BGA 3 –40°C to 85°C LTC2000IY-14#PBF SAC305 (RoHS) LTC2000Y-14 BGA 3 –40°C to 85°C LTC2000IY-11#PBF SAC305 (RoHS) LTC2000Y-11 BGA 3 –40°C to 85°C LTC2000IY-16 Sn/Pb LTC2000Y-16 BGA 3 –40°C to 85°C Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear .com/packaging/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. http://www.linear .com/product/LTC2000#orderinfo

For more information www.linear .com/L TC2000 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating SVDD = 1.71V to 3.465V, RFSADJ = 500Ω, 12.5Ω load from IOUTP/N to GND including internal 50Ω termination, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Performance Resolution LTC2000-16 l 16 Bits LTC2000-14 l 14 Bits LTC2000-11 l 11 Bits DNL Differential Nonlinearity LTC2000-16 l ±0.5 ±2.7 LSB LTC2000-14 l ±0.2 ±1 LSB LTC2000-11 l ±0.1 ±0.5 LSB INL Integral Nonlinearity LTC2000-16 l ±1 ±4 LSB LTC2000-14 l ±0.5 ±2 LSB LTC2000-11 l ±0.2 ±1 LSB Offset Error LTC2000-16 l ±0.05 % FSR LTC2000-14 l ±0.06 % FSR LTC2000-11 l ±0.09 % FSR Offset Error Drift 1 ppm/°C Gain Error ±0.5 % FSR Gain Error Drift 5 ppm/°C Power Supply Rejection Ratio Full-Scale; AVDD33 = 3.135V to 3.465V 69 dB Analog Output Full-Scale Output Current RFSADJ = 500Ω 40 mA Output Compliance Range l –1 1 V Output Resistance IOUTP/N to GND l 42 50 58 Ω Output Capacitance 6 pF Output Bandwidth RIOUTP/N = 12.5Ω, –3dB Excluding sin(x)/x 2.1 GHz AC Performance Maximum Update Rate Dual-Port Mode Single-Port Mode l l 2.5 1.25 Gsps Gsps SFDR Spurious Free Dynamic Range fDAC = 1.25Gsps, 0dBFS fOUT = 50MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 100MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 250MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 500MHz, LIN_DIS = 0, LIN_GN = 75% dBc dBc dBc dBc Spurious Free Dynamic Range f DAC = 2.5Gsps, 0dBFS fOUT = 100MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 200MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 500MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 1000MHz, LIN_DIS = 0, LIN_GN = 75% l dBc dBc dBc dBc f OUT = 500MHz, LIN_DIS = 1 fOUT = 1000MHz, LIN_DIS = 1 dBc dBc IMD 2-T one Intermodulation Distortion fOUT2 = fOUT1 + 1.25MHz fDAC = 1.25Gsps, –6dBFS fOUT = 50MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 100MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 250MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 500MHz, LIN_DIS = 0, LIN_GN = 75% 100 dBc dBc dBc dBc 2-T one Intermodulation Distortion fOUT2 = fOUT1 + 1.25MHz fDAC = 2.5Gsps, –6dBFS fOUT = 100MHz, LIN_DIS = 1 fOUT = 200MHz, LIN_DIS = 1 fOUT = 500MHz, LIN_DIS = 1 fOUT = 1000MHz, LIN_DIS = 1 dBc dBc dBc dBc f OUT = 500MHz, LIN_DIS = 0, LIN_GN = 75% fOUT = 1000MHz, LIN_DIS = 0, LIN_GN = 75% dBc dBc

For more information www.linear .com/L TC2000 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating SVDD = 1.71V to 3.465V, RFSADJ = 500Ω, 12.5Ω load from IOUTP/N to GND including internal 50Ω termination, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS NSD Noise Spectral Density 0dBFS Single Tone, fDAC = 2.5Gsps, IOUTFS = 40mA LTC2000-16, fOUT = 100MHz LTC2000-16, fOUT = 350MHz LTC2000-16, fOUT = 550MHz LTC2000-16, fOUT = 950MHz –166 –161 –158 –156 dBm/Hz dBm/Hz dBm/Hz dBm/Hz LTC2000-14, f OUT = 100MHz LTC2000-14, fOUT = 350MHz LTC2000-14, fOUT = 550MHz LTC2000-14, fOUT = 950MHz –164 –160 –158 –155 dBm/Hz dBm/Hz dBm/Hz dBm/Hz LTC2000-11, f OUT = 100MHz LTC2000-11, fOUT = 350MHz LTC2000-11, fOUT = 550MHz LTC2000-11, fOUT = 950MHz –156 –155 –154 –153 dBm/Hz dBm/Hz dBm/Hz dBm/Hz Phase Noise f DAC = 2.5Gsps, fOUT = 65MHz 0dBFS Single Tone, IOUTFS = 40mA 10kHz Offset 1MHz Offset –147 –165 dBc/Hz dBc/Hz WCDMA ACLR WCDMA ACLR (Single Carrier) Adjacent/Alternate Adjacent Channel f DAC = 2.5Gsps, fOUT = 350MHz fDAC = 2.5Gsps, fOUT = 950MHz dBc dBc Latency Latency (Note 5) Single-Port Mode Dual-Port Mode, DAP/N Data Dual-Port Mode, DBP/N Data 7.5 Cycles Cycles Cycles Aperture Delay CKP/N Rising to I OUTP/N T ransition 3 ns Settling Time 2.2 ns Reference Output Voltage l 1.225 1.25 1.275 V Input Voltage l 1.1 1.4 V Reference Temperature Coefficient ±25 ppm/°C Output Impedance 10 kΩ DAC Clock Inputs (CKP , CKN) Differential Input Voltage Range l ±0.3 ±1.8 V Common-Mode Input Voltage Set Internally 1 V Sampling Clock Frequency l 50 2500 MHz Input Impedance 5 kΩ LVDS Inputs (DCKIP , DCKIN, DAP/N, DBP/N) Differential Input Voltage Range l ±0.2 ±0.6 V Common-Mode Voltage Range l 0.4 1.8 V Differential Input Impedance l 95 120 145 Ω Maximum Data Rate l 1250 Mbps LVDS Clock Frequency l 25 625 MHz

For more information www.linear .com/L TC2000 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating SVDD = 1.71V to 3.465V, RFSADJ = 500Ω, 12.5Ω load from IOUTP/N to GND including internal 50Ω termination, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LVDS Output (DCKOP , DCKON) Differential Output Voltage 100Ω Differential Load, DCKO_ISEL = 0 50Ω Differential Load, DCKO_ISEL = 1 l l 0.24 0.24 0.36 0.36 0.48 0.48 V V Common-Mode Output Voltage l 1.075 1.2 1.325 V Internal Termination Resistance DCKO_TRM = 1 100 Ω CMOS Digital Inputs (CS, PD, SCK, SDI) VIH Digital Input High Voltage l 70 %VSVDD VIL Digital Input Low Voltage l 30 %V SVDD ILK Digital Input Leakage VIN = GND or SVDD l ±10 µA CIN Digital Input Capacitance 8 pF CMOS Digital Output (SDO) V OH Digital Output High Voltage ISOURCE = 0.2mA l 85 %VSVDD VOL Digital Output Low Voltage ISINK = 1.6mA l 15 %V SVDD Hi-Z Output Leakage l ±10 µA Hi-Z Output Capacitance 8 pF Power Supply V VDD33 AVDD33, DVDD33 Supply Voltage l 3.135 3.3 3.465 V VVDD18 AVDD18, DVDD18 Supply Voltage l 1.71 1.8 1.89 V VSVDD SVDD SPI Supply Voltage l 1.71 3.465 V IAVDD33 AVDD33 Supply Current, AVDD33 = 3.3V PD = SVDD PD = GND l l 0.1 mA µA IDVDD33 DVDD33 Supply Current, DVDD33 = 3.3V PD = SVDD PD = GND l l 0.1 mA µA IAVDD18 AVDD18 Supply Current, AVDD18 = 1.8V f DAC = 2500MHz fDAC = 1250MHz fDAC = 0Hz, PD = SVDD fDAC = 0Hz, PD = GND l l l l 720 375 790 420 180 mA mA mA µA I DVDD18 DVDD18 Supply Current, DVDD18 = 1.8V f DAC = 2500MHz fDAC = 1250MHz fDAC = 0Hz, PD = SVDD fDAC = 0Hz, PD = GND l l l l 350 190 0.1 395 215 240 mA mA mA µA I SVDD SVDD Supply Current (Note 4), SVDD = 3.3V fSCK = 0Hz l 0.1 5 µA Total Power Dissipation fDAC = 2500MHz fDAC = 1250MHz fDAC = 0Hz, PD = SVDD fDAC = 0Hz, PD = GND 2180 1270 310 mW mW mW µW

For more information www.linear .com/L TC2000 The l denotes the specifications which apply over the full operating temperature to 3.465V, RFSADJ = 500Ω, output load 50Ω double terminated, unless otherwise specified. TIMING CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t1 SDI Valid to SCK Setup (Note 3) l 4 ns t2 SDI Valid to SCK Hold (Note 3) l 4 ns t3 SCK High Time (Note 3) l 9 ns t4 SCK Low Time (Note 3) l 9 ns t5 CS Pulse Width (Note 3) l 10 ns t6 SCK High to CS High (Note 3) l 7 ns t7 CS Low to SCK High (Note 3) l 7 ns t10 CS High to SCK High (Note 3) l 7 ns t13 SCK Low to SDO Valid Unloaded (Note 3) l 10 ns SCK Frequency 50% Duty Cycle (Note 3) l 50 MHz t11 LVDS DAP/N, DBP/N to DCKI Setup Time (Note 3) DCKI_Q = 1 DCKI_Q = 0, DCKI_TADJ = 000 l l 200 600 ps ps t

12 LVDS DAP/N, DBP/N to DCKI Hold Time

(Note 3) DCKI_Q = 1 DCKI_Q = 0, DCKI_TADJ = 000 l l 200 –200 ps ps Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltages are with respect to GND. Note 3: Guaranteed by design and not production tested. Note 4: Digital inputs at 0V or SV DD. Note 5: Latency is the delay from a transition on DCKIP/N until the CKP/N transition which causes the sample on DAP/N or DBP/N to appear at the DAC output I OUTP/N, as measured in DAC sample clock (CKP/N) cycles.

For more information www.linear .com/L TC2000 TYPICAL PERFORMANCE CHARACTERISTICS DNL vs IOUTFS and Temperature Offset Error vs Temperature Gain Error vs Temperature Reference Output Voltage vs Temperature Supply Current vs fDAC Shutdown Current vs Temperature LTC2000-16 Integral Nonlinearity (INL) LTC2000-16 Differential Nonlinearity (DNL) INL vs I OUTFS and Temperature IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V, AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, unless otherwise noted. CODE –32768 INL (LSB) 32768

2000 G01

–16384 0 16384 CODE –32768 DNL (LSB) 32768

2000 G02

–16384 0 16384 TEMPERATURE (°C) –50 INL (LSB) –25 0 25 50

2000 G03

INL (POS) INL (NEG) 10mA 20mA 40mA 60mA TEMPERATURE (°C) –50 DNL (LSB) –25 0 25 50

2000 G04

DNL (POS) DNL (NEG) 10mA 20mA 40mA 60mA TEMPERATURE (°C) –50 –1.0 GAIN ERROR (% FSR)–0.5 0.5 1.0 –25 0 25 50

2000 G06

TEMPERATURE (°C) –50

1.240 VREF (V)

1.245 1.250 1.255 1.260 –25 0 25 50

2000 G07

fDAC (MHz) I (mA) 300 400 500 1500 2500

2000 G08

TEMPERATURE (°C) –50 –0.06 OFFSET ERROR (%FSR) –0.04 –0.02 0.02 0.06 –25 0 25 50

2000 G05

0.04

16 BIT

14 BIT

11 BIT

TEMPERATURE (°C) –50 I (µA)15

2000 G09

0 50–25 25 75 100 DVDD18 AVDD18 SVDD AVDD33 DVDD33

For more information www.linear .com/L TC2000 TYPICAL PERFORMANCE CHARACTERISTICS SFDR vs fOUT and Temperature, fDAC = 2.5Gsps SFDR vs fOUT and Digital Amplitude (dBFS), fDAC = 2.5Gsps SFDR vs fOUT and IOUTFS, fDAC = 2.5Gsps HD2 vs fOUT and fDAC HD3 vs fOUT and fDAC Single-Tone Spectrum at fOUT = 70MHz, fDAC = 2.5Gsps Single-Tone Spectrum at f OUT = 990MHz, fDAC = 2.5Gsps SFDR vs fOUT and fDAC IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V, AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted. FREQUENCY (MHz) –90 10dB/DIV –80 –60 –50 –40 1012 2004 2500

2000 G10

–70 516 1508 –30 –20 –10 RBW = 2kHz, VBW = 5kHz REF = 5dBm, ATTEN = 25dB SWEEP = 620s (1001 PTS)fDAC-fOUT IMAGE FREQUENCY (MHz) –90 10dB/DIV –80 –60 –50 –40 1012 2004 2500

2000 G11

–70 516 HD3 1508 –30 –20 –10 RBW = 2kHz VBW = 5kHz REF = 5dBm ATTEN = 25dB SWEEP = 620s (1001 PTS) fDAC-fOUT IMAGE HD2 AND HD3 IN 2ND NYQUIST BAND fOUT (MHz) SFDR (dBc) 100 200 400 600 800

2000 G12

2.5Gsps 2.0Gsps 1.6Gsps 1.25Gsps DIGITAL AMPLITUDE = 0dBFS fOUT (MHz) SFDR (dBc) 100 200 400 600 800

2000 G13

90°C 25°C –40°C DIGITAL AMPLITUDE = 0dBFS fOUT (MHz) SFDR (dBc) 100 200 400 600 800

2000 G14

–3dBFS –6dBFS –12dBFS –16dBFS fOUT (MHz) SFDR (dBc) 100 200 400 600 800

2000 G15

fOUT (MHz) HD2 (dBc) 100 200 400 600 800

2000 G16

2.5Gsps 2.0Gsps 1.6Gsps 1.25Gsps DIGITAL AMPLITUDE = 0dBFS fOUT (MHz) HD3 (dBc) 100 200 400 600 800

2000 G17

2.5Gsps 2.0Gsps 1.6Gsps 1.25Gsps DIGITAL AMPLITUDE = 0dBFS HD2 vs fOUT and Digital Amplitude (dBFS), fDAC = 2.5Gsps fOUT (MHz) HD2 (dBc) 100 200 400 600 800

2000 G18

–3dBFS –6dBFS –12dBFS –16dBFS

For more information www.linear .com/L TC2000 TYPICAL PERFORMANCE CHARACTERISTICS 2-Tone IMD vs fOUT and fDAC 2-Tone IMD vs fOUT and Digital Amplitude, fDAC = 2.5Gsps SFDR vs fOUT and Linearization Setting, fDAC = 2.5Gsps LTC2000-16 Single-Tone NSD vs fOUT and fDAC LTC2000-16 Single-Tone NSD vs f OUT and IOUTFS HD3 vs fOUT and Linearization Setting, fDAC = 2.5Gsps 2-Tone IMD vs fOUT and Linearization Setting, f DAC = 2.5Gsps HD3 vs fOUT and Digital Amplitude (dBFS), fDAC = 2.5Gsps 2-Tone IMD vs fOUT and fDAC with Default Linearization IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V, AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted. fOUT (MHz) HD3 (dBc) 100 200 400 600 800

2000 G19

–3dBFS –6dBFS –12dBFS –16dBFS fOUT (MHz) IMD (dBc) 100 110 200 400 600 800

2000 G22

2.5Gsps 2.0Gsps 1.6Gsps 1.25Gsps DIGITAL AMPLITUDE = –6dBFS F2 = F1 + 1.25MHz LIN_DIS = 0 LIN_GN = 75% fOUT (MHz) HD3 (dBc) 100 200 400 600 800

2000 G25

LIN_GN = 100% LIN_GN = 75% LIN_GN = 50% LIN_DIS = 1 DIGITAL AMPLITUDE = 0dBFS fOUT (MHz) IMD (dBC) 100 110 200 400 600 800

2000 G20

2.5Gsps 2.0Gsps 1.6Gsps 1.25Gsps DIGITAL AMPLITUDE = –6dBFS F2 = F1 + 1.25MHz LIN_DIS = 1 fOUT (MHz) IMD (dBC) 100 110 200 400 600 800

2000 G21

–6dBFS –12dBFS –16dBFS F2 = F1 + 1.25MHz LIN_DIS = 1 fOUT (MHz) –170 NSD (dBm/Hz) –165 –160 –155 –150 –145 200 400 600 800

2000 G26

2.5Gsps 1.25Gsps DIGITAL AMPLITUDE = 0dBFS 40mA FULL-SCALE CURRENT 0dBm SINGLE-TONE fOUT (MHz) IMD (dBC) 100 110 200 400 600 800

2000 G23

LIN_GN = 100% LIN_GN = 75% LIN_GN = 50% LIN_GN = 1% DIGITAL AMPLITUDE = –6dBFS F2 = F1 + 1.25MHz fOUT (MHz) –170 NSD (dBm/Hz) –165 –160 –155 –150 60mA 40mA 20mA –145 200 400 600 800

2000 G27

DIGITAL AMPLITUDE = 0dBFS fDAC = 2.5Gsps 12.5/uni03A9 TOTAL OUTPUT LOAD fOUT (MHz) SFDR (dBc) 100 200 400 600 800

2000 G24

LIN_GN = 100% LIN_GN = 75% LIN_GN = 50% LIN_DIS = 1 DIGITAL AMPLITUDE = 0dBFS

For more information www.linear .com/L TC2000 Single Carrier DOCSIS Mid Band Wideband ACLR, fDAC = 2.5Gsps Single Carrier DOCSIS Mid Band Narrowband ACLR, f DAC = 2.5Gsps Single Carrier DOCSIS Low Band Wideband ACLR, f DAC = 2.5Gsps Single Carrier DOCSIS Low Band Narrowband ACLR, f DAC = 2.5Gsps TYPICAL PERFORMANCE CHARACTERISTICS IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V, AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted. FREQUENCY (MHz) 10dB/DIV –60 –40 –20 850

2000 G28

–80 –100 –70 –50 –30 –90 –110 –120 250 450 650150 350 550 750 950 –89.9dBm/6MHz –87.3dBm/6MHz –89.2dBm/6MHz –11.2dBm/6MHz RBW = 20kHz VBW = 2kHz REF = –20dBm ATTEN = 5dB SWEEP = 60s FREQUENCY (MHz) CARRIER POWER = –11.16dBm, CENTER FREQ = 200MHz 173 10dB/DIV –60 –40 –20 213

2000 G31

–80 –100 –70 –50 –30 –90 –110 –120 183 193 203 223 RBW = 30kHz VBW = 3kHz REF = –20dBm ATTEN = 5dB SWEEP = 24s OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz BW 750kHz 5.25MHz 6MHz 6MHz 6MHz LOWER –100.31dBm –96.02dBm –96.47dBm –96.40dBm –96.40dBm UPPER –94.84dBm –94.67dBm –95.48dBm –96.29dBm –96.57dBm FREQUENCY (MHz) 10dB/DIV –60 –40 –20 850

2000 G29

–80 –100 –70 –50 –30 –90 –110 –120 250 450 650150 350 550 750 950 –84.1dBm/6MHz –11.7dBm/6MHz RBW = 20kHz VBW = 2kHz REF = –20dBm ATTEN = 5dB SWEEP = 60s FREQUENCY (MHz) CARRIER POWER = –11.66dBm, CENTER FREQ = 550MHz 523 10dB/DIV –60 –40 –20 563

2000 G32

–80 –100 –70 –50 –30 –90 –110 –120 533 543 553 573 OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz BW 750kHz 5.25MHz 6MHz 6MHz 6MHz LOWER –95.63dBm –93.01dBm –94.66dBm –95.19dBm –94.97dBm UPPER –93.62dBm –92.97dBm –94.51dBm –94.87dBm –95.15dBm RBW = 30kHz VBW = 3kHz REF = –20dBm ATTEN = 5dB SWEEP = 24s Single Carrier DOCSIS High Band Wideband ACLR, fDAC = 2.5Gsps FREQUENCY (MHz) 10dB/DIV –60 –40 –20 850

2000 G30

–80 –100 –70 –50 –30 –90 –110 –120 250 450 650150 350 550 750 950 –89.2dBm/6MHz–89.2dBm/6MHz RBW = 20kHz VBW = 2kHz REF = –20dBm ATTEN = 5dB SWEEP = 60s –89.4dBm/6MHz –14dBm/6MHz Single Carrier DOCSIS High Band Narrowband ACLR, fDAC = 2.5Gsps FREQUENCY (MHz) CARRIER POWER = –14.04dBm, CENTER FREQ = 980MHz 953 10dB/DIV –60 –40 –20 993

2000 G33

–80 –100 –70 –50 –30 –90 –110 –120 963 973 983 1003 OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz BW 750kHz 5.25MHz 6MHz 6MHz 6MHz LOWER –89.47dBm –87.24dBm –93.04dBm –93.52dBm –93.33dBm UPPER –89.52dBm –87.00dBm –92.94dBm –92.51dBm –92.03dBm RBW = 30kHz VBW = 3kHz REF = –20dBm ATTEN = 5dB SWEEP = 24s LTC2000-16

For more information www.linear .com/L TC2000

32 Carrier DOCSIS Mid Band

Narrowband ACLR, fDAC = 2.5Gsps

32 Carrier DOCSIS High Band

Wideband ACLR, f DAC = 2.5Gsps Narrowband ACLR, f DAC = 2.5Gsps 32-Carrier DOCSIS Low Band Wideband ACLR, f DAC = 2.5Gsps 32-Carrier DOCSIS Low Band Narrowband ACLR, f DAC = 2.5Gsps 32-Carrier DOCSIS Mid Band Wideband ACLR, f DAC = 2.5Gsps FREQUENCY (MHz) 10dB/DIV –60 –40 850

2000 G34

–80 –100 –70 –50 –30 –90 –110 –120 –130 250 450 650150 350 550 750 950 RBW = 20kHz VBW = 2kHz REF = –30dBm ATTEN = 5dB SWEEP = 60s FREQUENCY (MHz) CARRIER POWER = –28.64dBm, CENTER FREQ = 386MHz 359 10dB/DIV –60 –40 399

2000 G37

–80 –100 –70 –50 –30 –90 –110 –120 –130 369 379 389 409 OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz BW 750kHz 5.25MHz 6MHz 6MHz 6MHz LOWER –39.32dBm –29.01dBm –28.68dBm –28.54dBm –28.49dBm UPPER –103.86dBm –95.18dBm –94.68dBm –94.97dBm –95.08dBm RBW = 30kHz VBW = 3kHz REF = –30dBm ATTEN = 5dB SWEEP = 24s FREQUENCY (MHz) 10dB/DIV –60 –40 850

2000 G35

–80 –100 –70 –50 –30 –90 –110 –120 –130 250 450 650150 350 550 750 950 RBW = 20kHz VBW = 2kHz REF = –30dBm ATTEN = 5dB SWEEP = 60s FREQUENCY (MHz) CARRIER POWER = –28.42dBm, CENTER FREQ = 500MHz 473 10dB/DIV –60 –40 513

2000 G38

–80 –100 –70 –50 –30 –90 –110 –120 –130 483 493 503 523 OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz BW 750kHz 5.25MHz 6MHz 6MHz 6MHz LOWER –102.49dBm –94.71dBm –94.02dBm –94.36dBm –93.72dBm UPPER –39.23dBm –28.92dBm –28.69dBm –28.71dBm –28.74dBm RBW = 30kHz VBW = 3kHz REF = –30dBm ATTEN = 5dB SWEEP = 24s FREQUENCY (MHz) 10dB/DIV –60 –40 850

2000 G36

–80 –100 –70 –50 –30 –90 –110 –120 –130 250 450 650150 350 550 750 950 RBW = 20kHz VBW = 2kHz REF = –30dBm ATTEN = 5dB SWEEP = 60s FREQUENCY (MHz) CARRIER POWER = –29.31dBm, CENTER FREQ = 800MHz 773 10dB/DIV –60 –40 813

2000 G39

–80 –100 –70 –50 –30 –90 –110 –120 –130 783 793 803 823 OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz BW 750kHz 5.25MHz 6MHz 6MHz 6MHz LOWER –98.23dBm –90.00dBm –89.76dBm –89.72dBm –89.76dBm UPPER –40.42dBm –29.56dBm –29.20dBm –29.25dBm –29.55dBm RBW = 30kHz VBW = 3kHz REF = –30dBm ATTEN = 5dB SWEEP = 24s TYPICAL PERFORMANCE CHARACTERISTICS IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V, AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted. LTC2000-16

For more information www.linear .com/L TC2000

128 Carrier DOCSIS Low Band

Wideband ACLR, fDAC = 2.5Gsps

157 Carrier DOCSIS Gap Channel

Wideband ACLR, f DAC = 2.5Gsps Narrowband ACLR, f DAC = 2.5Gsps

157 Carrier Tones with Gap Channel

Wideband ACLR, f DAC = 2.5Gsps Narrowband ACLR, f DAC = 2.5Gsps Narrowband ACLR, f DAC = 2.5Gsps FREQUENCY (MHz) 10dB/DIV –60 –40 850

2000 G40

–80 –100 –70 –50 –30 –90 –110 –120 –130 250 450 650150 350 550 750 950 RBW = 20kHz, VBW = 2kHz REF = –30dBm, ATTEN = 5dB SWEEP = 60s FREQUENCY (MHz) CARRIER POWER = –37.59dBm, CENTER FREQ = 832MHz 805 10dB/DIV –60 –40 845

2000 G43

–80 –100 –70 –50 –30 –90 –110 –120 –130 815 825 835 855 OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz BW 750kHz 5.25MHz 6MHz 6MHz 6MHz LOWER –48.37dBm –37.97dBm –37.33dBm –37.13dBm –37.15dBm UPPER –103.39dBm –95.72dBm –95.55dBm –96.33dBm –95.91dBm RBW = 30kHz VBW = 3kHz REF = –30dBm ATTEN = 5dB SWEEP = 24s TYPICAL PERFORMANCE CHARACTERISTICS IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V, AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted. LTC2000-16 FREQUENCY (MHz) 10dB/DIV –60 –40 830

2000 G41

–80 –100 –70 –50 –30 –90 –110 –120 –130 230 430 630130 330 530 730 930 RBW = 20kHz, VBW = 2kHz REF = –30dBm, ATTEN = 5dB SWEEP = 60s FREQUENCY (MHz) 10dB/DIV –60 –40 830

2000 G42

–80 –100 –70 –50 –30 –90 –110 –120 –130 230 430 630130 330 530 730 930 RBW = 20kHz, VBW = 2kHz, REF = –30dBm, ATTEN = 5dB, SWEEP = 60s, LIN_DIS = 1 FREQUENCY (MHz) GAP CHANNEL POWER = –96.45dBm, CENTER FREQ = 508MHz 481 10dB/DIV –60 –40 521

2000 G44

–80 –100 –70 –50 –30 –90 –110 –120 –130 491 501 511 531 OFFSET FREQ 3.375MHz 6.375MHz 12.00MHz 18.00MHz 24.00MHz BW 750kHz 5.25MHz 6MHz 6MHz 6MHz LOWER –48.05dBm –36.61dBm –36.32dBm –36.48dBm –36.54dBm UPPER –47.93dBm –36.50dBm –36.27dBm –36.45dBm –36.57dBm RBW = 30kHz, VBW = 3kHz REF = –30dBm, ATTEN = 5dB SWEEP = 24s FREQUENCY (MHz) 510 –130 10dB/DIV –120 –100 –90 –80 –30 –60 515 520

2000 G45

–110 –50 –40 –70 525 RBW = 30kHz, VBW = 3kHz REF = –30dBm, ATTEN = 10dB SWEEP = 24s, LIN_DIS = 1

For more information www.linear .com/L TC2000 TYPICAL PERFORMANCE CHARACTERISTICS IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V, AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted. LTC2000-16 Single Carrier WCDMA ACLR vs fOUT, fDAC = 2.5Gsps LTC2000-16 Single Carrier WCDMA ACLR at 350MHz, f DAC = 2.5Gsps Additive Phase Noise, f OUT = 65MHz, fDAC = 2.5Gsps LTC2000-14 Differential Nonlinearity (DNL) LTC2000-14 Single-Tone NSD vs f OUT and fDAC LTC2000-14 Integral Nonlinearity (INL) fOUT (MHz) –90 ACLR (dBc) –80 –70 –60 –50 200 400 600 800

2000 G46

FREQUENCY (MHz) CARRIER POWER = –17.06dBm, CENTER FREQ = 350MHz 323 –60 –40 363

2000 G47

–8010dB/Hz –100 –70 –50 –30 –90 –110 –120 –130 333 343 353 373 OFFSET FREQ 5.00MHz 10.00MHz 15.00MHz 20.00MHz 25.00MHz BW 3.84MHz 3.84MHz 3.84MHz 3.84MHz 3.84MHz LOWER –94.15dBm –95.61dBm –95.72dBm –96.97dBm –96.07dBm UPPER –94.40dBm –94.99dBm –95.55dBm –96.37dBm –96.50dBm RBW = 30kHz VBW = 3kHz REF = –20dBm ATTEN = 5dB SWEEP = 24s OFFSET FREQUENCY (kHz) –160PHASE NOISE (dBc/Hz) –150 –130 –110 –100 0.01 1 10 1000

2000 G48

–170 0.1 100 –120 –140 –180 CODE –8192 INL (LSB) 8192

2000 G49

–4096 0 4096 fOUT (MHz) –170 NSD (dBm/Hz) –165 –160 –155 –150 –145 200 400 600 800

2000 G51

2.5Gsps 1.25Gsps DIGITAL AMPLITUDE = 0dBFS 40mA FULL-SCALE CURRENT 0dBm SINGLE TONE CODE –8192 DNL (LSB) 0.5 8192

2000 G50

–0.5 –1.0 –4096 0 4096 1.0

For more information www.linear .com/L TC2000 TYPICAL PERFORMANCE CHARACTERISTICS IOUTFS = 40mA, TA = 25°C, AVDD18 = DVDD18 = 1.8V, AVDD33 = DVDD33 = 3.3V, RLOAD = 12.5Ω, LIN_DIS = 0, LIN_ GN = 75% unless otherwise noted. LTC2000-11 Differential Nonlinearity (DNL) LTC2000-11 Single-Tone NSD vs f OUT and fDAC LTC2000-11 Integral Nonlinearity (INL) CODE –1024 INL (LSB) 0.5 1024

2000 G52

–0.5 –1.0 –512 0 512 1.0 CODE –1024 DNL (LSB) 0.25 1024

2000 G53

–0.25 –1.50 –512 0 512 0.50 fOUT (MHz) –170 NSD (dBm/Hz) –165 –160 –155 –150 –145 200 400 600 800

2000 G54

2.5Gsps 1.25Gsps DIGITAL AMPLITUDE = 0dBFS 40mA FULL-SCALE CURRENT 0dBm SINGLE TONE

For more information www.linear .com/L TC2000 PIN FUNCTIONS AVDD18: 1.8V Analog Supply Voltage Input. 1.71V to 1.89V. AVDD33: 3.3V Analog Supply Voltage Input. 3.135V to 3.465V. CKP , CKN: DAC Sample Clock Inputs. Maximum clock frequency (fDAC) is 2500MHz. Clock signal should be AC coupled. CS: Serial Interface Chip Select Input. When CS is low, SCK is enabled for shifting data on SDI into the register . When CS is taken high, SCK is disabled and SDO is high impedance. DAP[15:0], DAN [15:0]: Port A LVDS Data Inputs. Maximum data rate is 1.25Gbps. Port A is used only in dual-port mode. Connect to GND if not used. The data input format is two’s complement. DBP[15:0], DBN [15:0]: Port B LVDS Data Inputs. Maximum data rate is 1.25Gbps . In single-port mode, only Port B is used. In dual-port mode, the sample from Port B appears at I OUTP/N one cycle after the sample from Port A. The data input format is two’s complement. DCKIP , DCKIN: LVDS Data Clock Inputs. Maximum fre - quency (f DCKI) is 625MHz. In dual-port mode, f DCKI = fDAC/4. In single-port mode, fDCKI = fDAC/2 DCKOP , DCKON: LVDS Data Clock Outputs. Maximum fre- quency is 625MHz. Select frequency (f DAC/4 or fDAC/2), output current (3.5mA or 7mA), and termination (none or 100Ω) using register 0x02. DVDD33: 3.3V Digital Supply Voltage Input. 3.135V to 3.465V. FSADJ: Full-Scale Adjust Pin. The DAC full-scale current is 16 • (VREFIO/RFSADJ). Connect a 500Ω resistor from FSADJ to GND to set the full-scale current to 40mA. GND: Ground. IOUTP, IOUTN: DAC Analog Current Outputs. Differential output is nominally ± 40mA. Maximum update rate is 2.5Gsps. The output current is evenly divided between IOUTP and IOUTN when the two’s compliment DAC code is set to mid-scale (all zeros). PD (Pin S1): Active Low Power-Down Input. When PD is low, the LTC2000 supply current is less than 440µA. To exit power-down mode switch PD high to SV DD. REFIO: Reference Voltage Input or Output. The 1.25V internal reference is available at the pin through a 10k internal resistor . May be overdriven with an external refer- ence voltage between 1.1V and 1.4V. SCK: Serial Interface Clock Input. Maximum frequency is 50MHz. SDI: Serial Interface Data Input. Data on SDI is clocked in on the rising edge of SCK. SDO: Serial Interface Data Output. Data is clocked out onto SDO by the falling edge of SCK. SDO is high imped- ance when CS is high. SVDD: SPI Supply Voltage Input. 1.71V to 3.465V. TSTP , TSTN: Test Output Pins. May be optionally used to measure internal temperature or timing of LVDS inputs. See Measuring Internal Junction Temperature and Measuring LVDS Input Timing Skew sections in Applications Information. Use SPI internal registers 0x18 and 0x19 to control TSTP/N. Connect to GND if not used. Note: For pin locations, refer to the Pin Locations section of this data sheet.

For more information www.linear .com/L TC2000 BLOCK DIAGRAM LVDS RECEIVERS DDR DATA FLIP-FLOPS 4:1 TSTP/N PD CS SCK SDI SDO SVDD 50/uni03A9 IOUTP IOUTN FSADJ REFIO 50/uni03A9 10k 2000 BD CKP/NGNDDVDD33DVDD18 AVDD33AVDD18 GAIN ADJUST CLOCK SYNC CLK RECEIVER DELAY ADJUST DCKOP/N DCKIP/N DBP/N[15:0] DAP/N[15:0] CLK DIVIDER ÷2 OR ÷4 REF SPIPATTERN GENERATOR JUNCTION TEMPERATURE 16-BIT DAC

2000 F01

2000 F02

2000 F03

Figure 1. Serial Interface Timing Figure 2. LVDS Interface Timing (DCKI_Q = 0, DCK_TADJ = 000) Figure 3. LVDS Interface Timing (DCKI_Q = 1) rate (DDR) data input clock (DCKIP/N) at up to 625MHz. in phase with the data arriving on the data input ports.

For more information www.linear .com/L TC2000 OPERATION Note that the sample clock (CKP/N) frequency is always four times the DDR data input clock (DCKIP/N) fre - quency in dual-port mode. For example, to use the DAC at 2.5Gsps, apply a 2.5GHz clock to CKP/N and a 625MHz clock to DCKIP/N and send data into both ports A and B (DAP/N, DBP/N) at 1.25Gsps per port. Latency is defined as the delay from the DCKIP/N transi- tion that samples a DAC code to the CKP/N rising transi- tion which causes that sample to appear at the DAC output IOUTP/N. In dual-port mode the latency from DAP/N to IOUTP/N is 10 sample clock cycles and the latency from DBP/N to I OUTP/N is 11 cycles, starting from the CKP/N rising edge that immediately follows the DCKIP/N transi- tion that sampled the DAC code (Figure 4b). Single-Port Mode In single-port mode, data is written to port B (DBP/N) only, allowing DAC output sampling rates of up to 1.25Gsps. Figures 4c and 4d show a block diagram and sample waveforms representing single-port operation. Samples are written to port B (DBP/N) and sampled on both the falling and rising edges of the DDR data input clock (DCKIP/N) by two groups of flip-flops. The contents of these flip-flops are then interleaved into a single data stream by the 2:1 MUX and sampled by the DAC sample clock (CKP/N) at frequencies up to 1.25GHz. Note that in single-port mode the sample clock (CKP/N) frequency is always twice the DDR data input clock (DCKIP/N) frequency. For example, to use the DAC at 1.25Gsps, apply a 1.25GHz clock to CKP/N and a 625MHz clock to DCKIP/N and send data into port B (DBP/N) at 1.25Gsps. In single-port mode, port A (DAP/N) should be grounded. Due to the design of the internal clock syn- chronizer in single port mode, there is a half cycle shift in the single port latency. The latency from DBP/N to IOUTP/N in single-port mode is 7.5 sample clock cycles, starting from the CKP/N falling edge that immediately follows the DCKIP/N transition that sampled the DAC code (Figure 4d). After incoming data is sampled by DCKIP/N, an internal multiplexer interleaves the data for resampling by the DAC sample clock (CKP/N). See Figures 4a and 4b. After a pipeline delay (latency) of up to 11 DAC sample clock cycles, the rising edges of CKP/N update the DAC code and a proportional differential output current is steered between the two outputs (IOUTP/N). Note it takes about 3ns (aperture delay) from the CKP/N rising edge that updates a DAC code to the actual I OUTP/N transition for that DAC code. An internal clock synchronizer monitors the incoming phase of DCKIP/N and chooses the appropriate phase for the multiplexer control signals to ensure that the data is sampled correctly by CKP/N. The LTC2000 also generates an LVDS clock output (DCKOP/N) by dividing the sample clock frequency to simplify clocking of the host FPGA or ASIC. Additional features such as pattern generation, LVDS loopout, and junction temperature sensing simplify system development and testing. The serial peripheral interface (SPI) port allows configura- tion and read back of the internal registers which control the above functions. Dual-Port Mode In dual-port mode, data is written to both ports A and B simultaneously and then subsequently interleaved inside the LTC2000, allowing DAC output sampling rates of up to 2.5Gsps. Figures 4a and 4b show a simplified block diagram and sample waveforms for dual-port operation. The LVDS data input ports A and B are sampled on both the falling and rising edges of the DDR data input clock (DCKIP/N) by four groups of flip-flops. The contents of these flip-flops are then interleaved by the 4:1 MUX and sampled by the DAC sample clock (CKP/N) at frequencies up to 2.5GHz, with data from port A (DAP/N) preceding data from port B (DBP/N) at the DAC output.

For more information www.linear .com/L TC2000 OPERATION 16-BIT DAC 4:1 MUX N+3 N+2 N+1 N 50/uni03A9 IOUTP IOUTN 50/uni03A9

2000 F04a

DBP/N[15:0] DAP/N[15:0] DCKIP/N CKP/N DAP/N[15:0] N N+2 N+4 N+6 N+8 N+10 DBP/N[15:0] DCKIP/N CKP/N IOUTP/N N+1 N+3 1 2 3 4 5

10 CYCLE LATENCY

2000 F04b

11 CYCLE LATENCY

Figure 4a. Simplified Block Diagram – Dual-Port Operation Figure 4b. Sample Waveforms – Dual-Port Operation

For more information www.linear .com/L TC2000 OPERATION 16-BIT DAC 2:1 MUXN+1 N 50/uni03A9 IOUTP IOUTN 50/uni03A9

2000 F04c

DBP/N[15:0] DCKIP/N CKP/N DBP/N[15:0] DCKIP/N CKP/N IOUTP/N N N+1 0.5 1.5

7.5 CYCLE LATENCY

N N+2 N+3 N+4 N+5 N+6 N+6 N+7 Figure 4c. Simplified Block Diagram – Single-Port Operation Figure 4d. Sample Waveforms – Single-Port Operation

2000 F05

Figure 5. SPI Command and Data Input signifies a read (R/W = 1) or write (R/W = 0) operation. continue to be written to the same address. in the SPI Register Summary section. reset once all power supplies are stable. acceptable external reference range is 1.1V to 1.4V.

is equal to the voltage at REFIO, which is typically 1.25V. (–32) will increase the current by 14.3% to 45.7mA. the range of the GAIN_ADJ register . Table 1. Power-On Reset and Power-Down SPI Registers when CS returns high. All registers reset to 0x00, except address 0x08 which resets to 0x08. 1 DAC_PD DAC Power Down. Set DAC_PD = 1 to power down the DAC and FSADJ bias circuits. 0x02 0 CK_PD CKP/N Clock Receiver Power Down. CKP/N clock receiver is powered down when CK_PD = 1. 0x03 0 DCKI_EN DCKIP/N Clock Receiver Enable. Set DCKI_EN = 1 to enable the DCKI clock receiver . port A LVDS receivers are powered down and port A data will be zeroes. port B LVDS receivers are powered down and port B data will be zeroes. Note: Registers 0x01 to 0x04 reset to 0x00 (default). Figure 6. LTC2000 Full-Scale Adjust from 20mA to 60mA

2000 F06

Table 2. Full-Scale Gain Adjustment Note: Register 0x09 resets to 0x00 (default). full-scale DAC code). I OUTN is complementary to I OUTP. mately 0.2% full-scale, or 80µA for IOUTFS = 40mA. the temperature tracking of RLOAD with RFSADJ.

Table 3. DAC Sample Clock, and Divided Clock Output SPI Registers 1 CK_OK CKP/N Clock Present Indicator . When CK_OK = 1, clock is present at CKP/N pins and f DAC > 50MHz. When CK_OK = 0, DAC output is forced to mid-scale. CK_OK is read only. 5 DCKO_DIV DCKOP/N Divide Select. When DCKO_DIV = 0, f DCKOP/N = fDAC/4. When DCKO_DIV = 1, FDCKOP/N = fDAC/2. 7 DCKO_TRM DCKOP/N Internal Termination On. When DCKO_TRM = 0, there is no internal termination at DCKOP/N. When DCKO_TRM = 1, there is 100Ω between DCKOP and DCKON. Note: Register 0x02 resets to 0x00 (default). 40mA, VDIFF will swing between 1V and –1V. The specified output compliance voltage range is ± 1V. in the best distortion performance. CKP/N (see Generating the DAC Sample Clock section). DAC sample clock receiver is on by default. differential output current. LVDS transmitter and save power when not in use. mode, provide a 625MHz clock on DCKIP/N.

Table 4. LVDS Clock SPI Registers 0x03 0 DCKI_EN DCKIP/N Clock Receiver Enable. DCKI_EN = 1 enables LVDS clock receiver . 1 DCKI_OK DCKIP/N Clock Present Indicator . When DCKI_OK = 1, clock is present at DCKIP/N pins and f DCKIP/N > 25MHz. When DCKI_OK = 0, DAC output is forced to mid-scale unless pattern generator is enabled (PGEN_EN = 1). 2 DCKI_Q DCKIP/N Quadrature Phase Select. For DCKI_Q = 0, DCKIP/N should be in phase with DAP/N and DBP/N. Set DCKI_Q = 1 to use DCKI in quadrature with DAP/N and DBP/N. DCKI_TADJ DCKIP/N Delay Adjust. Use with DCKI_Q = 0 to adjust delay of DCKIP/N relative to DAP/N and DBP/N. For DCKI_Q = 1, DCKIP/N delay matches DAP/N and DBP/N and is unaffected by DCKI_TADJ. Note: Register 0x03 resets to 0x00 (default). internal data path is held at reset. on DCKIP/N, DAP/N, and DBP/N are nominally matched. and DBP/N (see Figure 2 of the Timing Diagram section). LVDS Input Timing Skew section). data input format is two’s complement. and allows sample rates up to 2.5Gsps. DAC code to mid-scale as desired.

DB_EN = 1 and provide data to LVDS port B (DBP/N) only. precede the data on port B at the DAC output. Table 5. LVDS Data Input SPI Registers down and port A data is 0x0000. down and port B data is 0x0000. code. DATA_SP = 0 sets dual-port mode and data from both ports A and B are used. from data ports A and B to be used to update the DAC code. Note: Register 0x04 resets to 0x00 (default).

2000 F07

Figure 7. Simplified Block Diagram — Clock Synchronizer in Dual-Port Mode

Table 6. Clock Synchronizer SPI Registers 0x05 [1:0] SYNC_PS Synchronizer Phase Select. Selects phase of internal data multiplexer . SYNC_PS is read-only when SYNC_MSYN = 0. based upon SYNC_PH. When SYNC_MSYN = 1, SYNC_PS must be set by the user . the DAC sample clock (CKP/N) divider used to control the data multiplexer . SYNC_PH is read only. Note: Registers 0x05 and 0x06 reset to 0x00 (default). data is sampled correctly by CKP/N. (register 0x03) to enable the LVDS data clock receiver . Table 6. For further details see the Synchronizing Multiple

For more information www.linear .com/L TC2000 OPERATION Minimizing Harmonic Distortion The LTC2000 contains proprietary dynamic linearization circuitry which dramatically reduces 3rd order harmonic distortion in the DAC output. SPI registers 0x07 and 0x08 are used to control these circuits (see Table 7). Optimal performance is normally achieved by setting LIN_VMX and LIN_VMN (register 0x08) to correspond to the maximum and minimum voltages expected at I OUTP/N. At power-on reset the default values are 0b1000 and 0b0000, which are appropriate for IOUTP/N swinging between 500mV and GND. If an application requires a different voltage swing, LIN_VMX and LIN_VMN can be programmed by writing to register 0x08 (see Table 7). For applications in which I OUTP/N swing below GND, use LIN_VMN = 0b0000. In some applications where 2-tone intermodulation dis - tortion (IMD) is a critical specification, it may be desired to vary the amount of 3rd order harmonic correction. For high sampling frequencies (fDAC > 2Gsps), adjusting LIN_GN in register 0x07 (see Table 7) can improve 2-tone intermodulation distortion at the expense of higher 3rd order harmonic distortion. For best IMD performance at high sampling frequencies, users may also choose to dis- able dynamic linearization by setting LIN_DIS = 1. SFDR and IMD curves in the Typical Performance Characteristics section show more detail regarding this effect. Note that for fDAC < 2Gsps, it is recommended to leave the dynamic linearization enabled. Measuring LVDS Input Timing Skew It is important to ensure that the LVDS inputs (DCKIP/N, DAP/N, DBP/N) are well aligned. Skew between clock and data lines, for example due to board trace length mismatch or output timing mismatch inside the host FPGA or ASIC, will degrade the setup and hold margin of the incoming data. The LTC2000 includes an internal test multiplexer which may be used during development to verify timing alignment by comparing the timing of LVDS inputs one pair at a time through the TSTP/N pins. Use SPI register 0x18 to control this test multiplexer (see Table 8). Be sure TDIO_EN = 0 in register 0x19 and then set LMX_EN = 1 to enable the test multiplexer output. The signal from the LVDS data input will be driven onto TSTP/N by an NMOS differential pair steering a 6.6mA sink current onto an external load. Connect a pair of 50Ω resistors from TSTP/N to 3.3V and observe TSTP/N on a high speed oscilloscope. Apply clocks to CKP/N and DCKIP/N and apply the pat - tern shown in Figure 8 to port B for single-port mode or ports A and B for dual-port mode. This pattern is designed to simplify comparison of rising-to-rising and falling-to- falling edge timing for each input pair . Set LMX_ADR to select a pair of LVDS inputs for timing comparison. Set LMX_MSEL = 0 to observe the first signal at TSTP/N. Set LMX_MSEL = 1 to observe the second signal with inverted output polarity. For example, to compare DB15P/N to DCKIP/N, first write 0x60 to register 0x18 to set LMX_EN = 1, LMX_ADR = 10000, and LMX_SEL = 0. The signal from DB15P/N will be driven onto TSTP/N. Write 0x61 to register 0x18 to set LMX_SEL = 1 and cause DCKIP/N to appear at TSTP/N with inverted polarity. Record the skew between the two signals and repeat this measurement for each pair of inputs. After all pairs have been measured, add the skews to calculate the total skew from DCKIP/N to each data input (DAP/N, DBP/N). In this way the skew of all LVDS data inputs (DAP/N, DBP/N) relative to DCKIP/N can be accurately measured to within 100ps. Note that due to internal delays inside the test multiplexer , it is only valid to compare timing between neighboring LVDS pairs using the same LMX_ADR setting. Similarly, the multiplexer itself contains up to 400ps of skew between rising and falling edges, so it is only valid to compare the timing of a rising edge at TSTP/N to another rising edge, and a falling edge to another falling edge. Note that Figure 8 shows the suggested input pattern for the LTC2000-16. LTC2000-14 users should apply codes 0x1555 and 0x2AAA, and LTC2000-11 users should apply codes 0x555 and 0x2AA. Also note that for the LTC2000-14 and LTC2000 -11 in dual-port mode, the tim- ing skew of LVDS port A (DAP/N) cannot be compared to that of the LVDS clock (DCKIP/N) and LVDS port B (DBP/N), as there is no single test multiplexer address (LMX_ADR) that enables a timing comparison between signals DA0N/P and DCKIP/N (see Table 8). It is recom - mended to keep LMX_EN = 0 during normal operation.

Table 7. Dynamic Linearization SPI Registers 0x07 0 LIN_DIS Dynamic Linearization Disable. Disabled when LIN_DIS = 1. DAC output. LIN_GN = 000 is normally optimal. correspond to the maximum voltage expected at IOUTP/N. Reset state is LIN_VMX = 1000, which corresponds to 0.51V. LIN_VMX must be greater than LN_VMN. correspond to the minimum voltage expected at IOUTP/N. Reset state is LIN_VMN = 0000, which corresponds to 0.0V. LIN_VMN must be less than LN_VMX. Note: Register 0x07 resets to 0x00 (default). Register 0x08 resets to 0x08 (default).

Table 8. SPI Registers for Measuring LVDS Input Timing Skew 6 LMX_EN LVDS Test MUX Enable. Set LMX_EN=1 to compare timing of neighboring signals at TSTP/N. Ensure TDIO_EN = 0 when LMX_EN = 1.

00000 DA14P/N DA15N/P DA12P/N DA13N/P DA9P/N DA10N/P

01010 DA4P/N DA5N/P DA2P/N DA3N/P — DA0N/P

01011 DA3P/N DA4N/P DA1P/N DA2N/P — —

01100 DA2P/N DA3N/P DA0P/N DA1N/P — —

01101 DA1P/N DA2N/P — DA0N/P — —

01110 DA0P/N DA1N/P — — — —

01111 DCKIP/N DA0N/P DCKIP/N — DCKIP/N —

10000 DB15P/N DCKIN/P DB13P/N DCKIN/P DB10P/N DCKIN/P

10001 DB14P/N DB15N/P DB12P/N DB13N/P DB9P/N DB10N/P

11011 DB4P/N DB5N/P DB2P/N DB3N/P — DB0N/P

11100 DB3P/N DB4N/P DB1P/N DB2N/P — —

11101 DB2P/N DB3N/P DB0P/N DB1N/P — —

11110 DB1P/N DB2N/P — DB0N/P — —

11111 DB0P/N DB1N/P — — — —

Note: Register 0x18 resets to 0x00 (default).

2000 F08

Figure 8. Sample Pattern for Measuring LVDS Input Timing Skew (LTC2000-16)

voltage at TSTP is VTSTP = 2.02V – 5.5mV/°C • (TJ – 25°C). ture. Typical uncalibrated accuracy is ±5°C. Table 9. Internal Junction Temperature SPI Registers 0x19 0 TDIO_EN TSTP/N Junction Temperature Diode Enable. Set TDIO_EN = 1 to measure internal junction temperature (T J) at TSTP/N. Ensure LMX_EN = 0 when TDIO_EN = 1. 1 TDIO_SEL Selects which internal temperature diode is observable at TSTP/N. For TDIO_SEL = 1, the typical voltage at TSTP with respect to TSTN is VTSTP = 2.02V – 5.5mV/°C • (TJ – 25°C). Junction temperature can be calculated as TJ = 25°C + (2.02V – VTSTP)/(5.5mV/°C). Typical accuracy is ±5°C. For TDIO_SEL = 0, an unbiased diode is connected b/w TSTP/N for use with external temperature sensors. Note: Register 0x19 resets to 0x00 (default).

1. Set DCKO_DIV = 0 in register 0x02, DATA_SP = 0 and
2. Write 128 bytes of pattern data to address 0x1F

begin to output the 64 sample pattern. sample pattern prior to setting PGEN_EN = 1. See Table 10.

Table 11. SPI Register List

3 Reserved Reserved

[5:4] DAC_RES DAC Resolution Indicator . DAC_RES = 00 for LTC2000-16. DAC_RES = 01 for LTC2000-14. DAC_RES = 11 for LTC2000-11. Note that for PD = GND or FULL_PD = 1, DAC_RES = 00.

7 Reserved Reserved

2 SYNC_MSYN Clock Synchronizer Manual Mode Select. SYNC_MSYN = 0: SYNC_PS is set automatically. SYNC_MSYN = 1: SYNC_PS is set by the user .

0 R/W

0x1E 0 PGEN_EN Pattern Generator Enable. Set PGEN_EN = 1 to use the internal 64 sample pattern generator to provide data to the DAC. Set DATA_SP = 0, DCKO_DIV = 0, and DATA_EN = 1 when PGEN_EN = 1. 0x1F [7:0] PGEN_D Pattern Generator Data. Write 128 bytes of data to this address to fill the pattern generator with 64 samples. Data is written MSB first. Reading this location causes the pattern generator data to be shifted out through SDO. 0x1F prior to setting PGEN_EN = 1 to avoid corrupting the data inside the pattern generator . Note: Registers 0x1E and 0x1F reset to 0x00 (default).

0x19 0 TDIO_EN TSTP/N Junction Temperature Diode Enable. TDIO_EN = 1 enables temperature (TJ) measurement. Ensure LMX_EN = 0 when TDIO_EN = 1.

1. Apply valid supply voltages to AV DD33, DV DD33,
2. Write 0x 01 to address 0x01 to perform a software reset.
3. Apply a clock to CKP/N at the desired fDAC frequency.
4. Apply a clock to DCKIP/N at fDAC/4 for dual-port mode

or fDAC/2 for single-port mode.

1. Apply zeroes to ports A and B (DAP/N, DBP/N) for

dual-port mode, or only to port B for single-port mode.

1. Write to address 0x 03 to enable the DCKIP/N LVDS

(DCKI) and data (DA, DB) are in phase with each other . Set address 0x03 to 0x05 if they are in quadrature.

1. Write 0x03 to address 0x04 for dual-port mode, or

enable the DAP/N and DBP/N LVDS receivers.

1. Wait at least 1ms for the synchronizer to finish
2. Apply desired data pattern to ports A and B (DAP/N,

ples at the DAC output when using dual-port mode. source current into an external load referenced to GND. figured for differential (or balanced) operation.

2000 F09

Figure 9. Differential Resistor Output Load Figure 10. T ransformer-Based Output Configuration

2000 F10

• • can drive only differential loads with impedance levels and amplitudes appropriate for the DAC outputs. Differential transformer-coupled output configurations usually give the best AC performance and provide excel- lent rejection of common mode distortion and noise over a broad frequency range. Figure 10 shows a transformer output configuration that uses a Mini-Circuits TC1-1-13M and a JTX-2-10T RF transformer for differential to single- ended conversion. For any output configuration, any imbalances in the out- put impedance between the IOUTP and IOUTN pins results in asymmetrical signal swings that lead to distortion (mostly even order). Careful consideration is needed to select the best output configuration for a given application. Generating the DAC Sample Clock For best AC performance, it is important that the DAC sample clock waveforms be clean, with low phase noise and good jitter performance, as the phase noise and spu- rious content of the clock source will appear directly in the DAC output spectrum. A differential clock should be AC coupled onto the CKP/N pins, since the DC bias point of CKP/N is set internally to 1V through a 5kΩ impedance. Figure 11 shows the DAC sample clock receiver input and common-mode voltage control. While the differential input voltage range of the clock receiver spans from ± 300mV to ± 1.8V, a signal with the highest possible slew rate and amplitude and a balanced duty cycle is recommended. T races that carry

Figure 11. DAC Sample Clock Receiver

2000 F11

the CKP/N pins of the LTC2000 as possible. There are several ways to generate the DAC sample clock. transformer or balun (see Figure 12). the LTC6946 data sheet for details. synchronized in dual-port mode. details on the operation of the clock synchronizer . any timing mismatch between the DAC sample clocks. tions (t11, t12) in the Timing Characteristics section.

2000 F13

Figure 13. DAC Sample Clock Generation with the LTC6946 Figure 12. DAC Sample Clock Generation with an

• • 50/uni03A9 100pF L TC2000 F12 1nF 1nF50/uni03A9 L TC2000 MINI-CIRCUITS TC1-1-13M RF SIGNAL GENERATOR CKP CKN

output timing will be limited to 30ps. sured in sample clock cycles).

2000 F14

0.1 CYCLES 10 CYCLES

2000 F15a

9 CYCLES

10 CYCLES

Figure 14. System with Multiple LTC2000 DACs Synchronized

DAC X is being updated one cycle later than DAC Y. Table 12. Adjusting Latency in Dual-Port Mode keep SYNC_PS as the default value.

For more information www.linear .com/L TC2000 APPLICATIONS INFORMATION Synchronizing Multiple LTC2000s in Single-Port Mode Figure 15b shows sample waveforms for synchronizing two LTC2000s in single port mode. Synchronizing mul - tiple LTC2000s in single port mode is essentially the same procedure as when operating in dual port mode— DAC sample clocks must all be aligned to arrive at the CKP/N pins of all DACs simultaneously and timing mismatch between LVDS data clock signals at the DCKIP/N pins of all DACs must be less than 0.4 cycles of the DAC sam - ple clock, minus any timing mismatch between the DAC sample clocks. To determine whether any DACs are being updated one cycle late in single port mode, first use the phase com - parator outputs SYNC_PH and Table 13 to determine the delay from the DCKIP/N rising edge to the next CKP/N fall- ing edge (as opposed to rising edge in dual port mode) for each DAC. If the difference between the delays indicated by SYNC_PH is greater than 0.4 cycles, the DCKIP/N ris- ing edges are arriving in different sample clock cycles. For the example in Figure 15b , we might read 0x15 for SYNC_PH on DAC X and 0x20 on DAC Y. Table 13 shows that the DCKIP/N to CKP/N delay is greater than 0.8 cycles for DAC X and less than 0.1 cycles for DAC Y, and thus the difference between them is at least 0.7 cycles. This indicates that DAC X is being updated one cycle later than DAC Y. Consult Table 13 and use the same procedure described above in the dual-port mode case to correct the SYNC_PS settings for those DACs that are updating one cycle late. In this single port example, writing 0x06 to register 0x05 of DAC X would set SYNC_MSYN = 1 and SYNC_PS = 10, reducing the latency of DAC X by one cycle and aligning its output with DAC Y, as shown in Figure 15b. Note that variations in system temperature or supply volt- age may cause the phase of the data clock (DCKIP/N) and sample clock (CKP/N) to vary with time. When using the LTC2000 with SYNC_MSYN = 1, it is recommended that users monitor SYNC_PH and adjust SYNC_PS using Tables 12 or 13 as needed to maintain proper alignment. The synchronization procedures described above also work for systems with more than two DACs. Simply deter- mine the minimum DCKIP/N to CKP/N delay of all DACs by reading SYNC_PH, and then adjust the SYNC_PS settings to subtract one cycle of latency to those DACs whose DCKIP/N to CKP/N delays are at least 0.4 cycles more than the minimum. Sample verilog code implementing the synchronization of multiple LTC2000s using Tables 12 and 13 can be found at: http ://www.linear .com/docs/44845 DBP/N[15:0] DAC X DCKIP/N DAC X IOUTP/N DAC X IOUTP/N (ADJUSTED) DAC Y IOUTP/N DAC Y DCKIP/N CKP/N N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9

0.8 CYCLES

0.1 CYCLES 7.5 CYCLES N

2000 F15b

6.5 CYCLES

7.5 CYCLES

Figure 15b. Sample Waveforms — Synchronizing Multiple LTC2000s in Single Port Mode

Table 13. Adjusting Latency in Single-Port Mode keep SYNC_PS as the default value. be carefully matched to ensure proper phase alignment. coupling into the analog output and DAC sample clock. away from the LVDS inputs and CKP/N signals. schematic can be found below.

For more information www.linear .com/L TC2000 APPLICATIONS INFORMATION DAP[15:0] DAN[15:0] DCKIP DCKIN DBP[15:0] DBN[15:0] SV DD AVDD33 DVDD33 AVDD18 DVDD18 DCKOP DCKON CKP R29 50/uni03A9 R26 50/uni03A9 CKN TSTP TSTN I OUTP IOUTN REFIO FSADJ

2000 F16M1

3.3V 1.8V 47µF 47µF L TC2000 GND C43 0.01µF C66 1pF C42 100pF GND GND IN C41 100pF ANAREN B0430J50100AHF C47 10pFL6 1nH CLOCK SOURCE R40 50/uni03A9 R46 50/uni03A9 R45 500/uni03A9 C40 10µF R47 50/uni03A9 R48 50/uni03A9 Figure 16 Layer 2Layer 1

For more information www.linear .com/L TC2000 APPLICATIONS INFORMATION Layer 3 Layer 4

For more information www.linear .com/L TC2000 APPLICATIONS INFORMATION Layer 6Layer 5

For more information www.linear .com/L TC2000 Layer 7 Layer 8 APPLICATIONS INFORMATION

For more information www.linear .com/L TC2000 PIN LOCATIONS (LTC2000-16) LTC2000-16 BGA Pinout PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 GND B1 GND C1 AVDD18 D1 AVDD18 E1 AVDD18 F1 GND A2 CKN B2 GND C2 AVDD18 D2 AVDD18 E2 AVDD18 F2 GND A3 CKP B3 GND C3 AVDD18 D3 AVDD18 E3 DV DD18 F3 GND A4 GND B4 GND C4 AVDD18 D4 DV DD18 E4 DV DD18 F4 GND A5 DV DD18 B5 DV DD18 C5 DV DD18 D5 DV DD18 E5 DV DD18 F5 GND A6 GND B6 GND C6 GND D6 GND E6 GND F6 GND A7 DAN15 B7 DAN14 C7 DAN13 D7 DAN12 E7 DAN11 F7 DAN10 A8 DAP15 B8 DAP14 C8 DAP13 D8 DAP12 E8 DAP11 F8 DAP10 A9 DBN15 B9 DBN14 C9 DBN13 D9 DBN12 E9 DBN11 F9 DBN10 A10 DBP15 B10 DBP14 C10 DBP13 D10 DBP12 E10 DBP11 F10 DBP10 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 I OUTP J1 I OUTN K1 GND L1 GND M1 REFIO G2 GND H2 GND J2 GND K2 GND L2 GND M2 FSADJ G3 GND H3 GND J3 GND K3 GND L3 GND M3 GND G4 GND H4 GND J4 GND K4 GND L4 GND M4 AVDD33 G5 GND H5 GND J5 GND K5 GND L5 GND M5 DV DD33 G6 GND H6 GND J6 GND K6 GND L6 GND M6 GND G7 DAN9 H7 DAN8 J7 DCKON K7 DAN7 L7 DAN6 M7 DAN5 G8 DAP9 H8 DAP8 J8 DCKOP K8 DAP7 L8 DAP6 M8 DAP5 G9 DBN9 H9 DBN8 J9 DCKIN K9 DBN7 L9 DBN6 M9 DBN5 G10 DBP9 H10 DBP8 J10 DCKIP K10 DBP7 L10 DBP6 M10 DBP5 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION N1 GND P1 AV DD33 Q1 AVDD33 R1 GND S1 PD N2 GND P2 AVDD33 Q2 AVDD33 R2 GND S2 CS N3 GND P3 AVDD33 Q3 AVDD33 R3 TSTN S3 SDO N4 AVDD33 P4 AVDD33 Q4 AVDD33 R4 TSTP S4 SDI N5 DV DD33 P5 DV DD33 Q5 DV DD33 R5 GND S5 SCK N6 GND P6 GND Q6 GND R6 GND S6 SV DD N7 DAN4 P7 DAN3 Q7 DAN2 R7 DAN1 S7 DAN0 N8 DAP4 P8 DAP3 Q8 DAP2 R8 DAP1 S8 DAP0 N9 DBN4 P9 DBN3 Q9 DBN2 R9 DBN1 S9 DBN0 N10 DBP4 P10 DBP3 Q10 DBP2 R10 DBP1 S10 DBPO

For more information www.linear .com/L TC2000 PIN LOCATIONS (LTC2000-16) S R Q P N M L K J H DVDD33 AVDD33 GND GND GND GNDREFIO FSADJ PD CS GND CKN CKP GND GND DAN2 DAP2 DBN2 DBP2 DAN3 DAP3 DBN3 DBP3 DAN4 DAP4 DBN4 DBP4 DAN5 DAP5 DBN5 DBP5 DAN6 DAP6 DBN6 DBP6 DAN7 DAP7 DBN7 DBP7 DCKON DCKOPIOUTN IOUTP DCKIPDCKIN DAN8 DAP8 DBN8 DBP8 DAN9 DAP9 DBN9 DBP9 DAN10 DAP10 DBN10 DBP10 DAN11 DAP11 DBN11 DBP11 DAN12 DAP12 DBN12 DBP12 DAN13 DAP13 DBN13 DBP13 DAN14 DAP14 DBN14 DBP14 DAN15 DAP15 DBN15 DBP15 TSTN TSTP DAN1 DAP1 DBN1 DBP1 SDO SDI SCK SV DD DAN0 DAP0 DBN0 DBP0 G F E D C B A 2 3 4 5 6 7 8 9 10 TOP VIEW AVDD18 DVDD18

For more information www.linear .com/L TC2000 PIN LOCATIONS (LTC2000-14) LTC2000-14 BGA Pinout PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 GND B1 GND C1 AVDD18 D1 AVDD18 E1 AVDD18 F1 GND A2 CKN B2 GND C2 AVDD18 D2 AVDD18 E2 AVDD18 F2 GND A3 CKP B3 GND C3 AVDD18 D3 AVDD18 E3 DV DD18 F3 GND A4 GND B4 GND C4 AVDD18 D4 DV DD18 E4 DV DD18 F4 GND A5 DV DD18 B5 DV DD18 C5 DV DD18 D5 DV DD18 E5 DV DD18 F5 GND A6 GND B6 GND C6 GND D6 GND E6 GND F6 GND A7 DAN13 B7 DAN12 C7 DAN11 D7 DAN10 E7 DAN9 F7 DAN8 A8 DAP13 B8 DAP12 C8 DAP11 D8 DAP10 E8 DAP9 F8 DAP8 A9 DBN13 B9 DBN12 C9 DBN11 D9 DBN10 E9 DBN9 F9 DBN8 A10 DBP13 B10 DBP12 C10 DBP11 D10 DBP10 E10 DBP9 F10 DBP8 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 I OUTP J1 I OUTN K1 GND L1 GND M1 REFIO G2 GND H2 GND J2 GND K2 GND L2 GND M2 FSADJ G3 GND H3 GND J3 GND K3 GND L3 GND M3 GND G4 GND H4 GND J4 GND K4 GND L4 GND M4 AVDD33 G5 GND H5 GND J5 GND K5 GND L5 GND M5 DV DD33 G6 GND H6 GND J6 GND K6 GND L6 GND M6 GND G7 DAN7 H7 DAN6 J7 DCKON K7 DAN5 L7 DAN4 M7 DAN3 G8 DAP7 H8 DAP6 J8 DCKOP K8 DAP5 L8 DAP4 M8 DAP3 G9 DBN7 H9 DBN6 J9 DCKIN K9 DBN5 L9 DBN4 M9 DBN3 G10 DBP7 H10 DBP6 J10 DCKIP K10 DBP5 L10 DBP4 M10 DBP3 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION N1 GND P1 AV DD33 Q1 AVDD33 R1 GND S1 PD N2 GND P2 AVDD33 Q2 AVDD33 R2 GND S2 CS N3 GND P3 AVDD33 Q3 AVDD33 R3 TSTN S3 SDO N4 AVDD33 P4 AVDD33 Q4 AVDD33 R4 TSTP S4 SDI N5 DV DD33 P5 DV DD33 Q5 DV DD33 R5 GND S5 SCK N6 GND P6 GND Q6 GND R6 GND S6 SV DD N7 DAN2 P7 DAN1 Q7 DAN0 R7 GND S7 GND N8 DAP2 P8 DAP1 Q8 DAP0 R8 GND S8 GND N9 DBN2 P9 DBN1 Q9 DBN0 R9 GND S9 GND N10 DBP2 P10 DBP1 Q10 DBP0 R10 GND S10 GND

For more information www.linear .com/L TC2000 PIN LOCATIONS (LTC2000-14) S R Q P N M L K J H GND AVDD33 DVDD33 TSTN TSTP PD CS SDO SDI SCK SV DD GND DAN0 DAP0 DBN0 DBP0 DAN1 DAP1 DBN1 DBP1 DAN2 DAP2 DBN2 DBP2 DAN3 DAP3 DBN3 DBP3 DAN4 DAP4 DBN4 DBP4 DAN5 DAP5 DBN5 DBP5 DCKON DCKOP DCKIN DCKIP DAN6 DAP6 DBN6 DBP6 DAN7 DAP7 DBN7 DBP7 DAN8 DAP8 DBN8 DBP8 DAN9 DAP9 DBN9 DBP9 DAN10 DAP10 DBN10 DBP10 DAN11 DAP11 DBN11 DBP11 DAN12 DAP12 DBN12 DBP12 DAN13 DAP13 DBN13 DBP13 GND GND GND AVDD18 IOUTP IOUTN REFIO FSADJ DVDD18 CKN CKP G F E D C B A 2 3 4 5 6 7 8 9 10 TOP VIEW

For more information www.linear .com/L TC2000 PIN LOCATIONS (LTC2000-11) LTC2000-11 BGA Pinout PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 GND B1 GND C1 AVDD18 D1 AVDD18 E1 AVDD18 F1 GND A2 CKN B2 GND C2 AVDD18 D2 AVDD18 E2 AVDD18 F2 GND A3 CKP B3 GND C3 AVDD18 D3 AVDD18 E3 DV DD18 F3 GND A4 GND B4 GND C4 AVDD18 D4 DV DD18 E4 DV DD18 F4 GND A5 DV DD18 B5 DV DD18 C5 DV DD18 D5 DV DD18 E5 DV DD18 F5 GND A6 GND B6 GND C6 GND D6 GND E6 GND F6 GND A7 DAN10 B7 DAN9 C7 DAN8 D7 DAN7 E7 DAN6 F7 DAN5 A8 DAP10 B8 DAP9 C8 DAP8 D8 DAP7 E8 DAP6 F8 DAP5 A9 DBN10 B9 DBN9 C9 DBN8 D9 DBN7 E9 DBN6 F9 DBN5 A10 DBP10 B10 DBP9 C10 DBP8 D10 DBP7 E10 DBP6 F10 DBP5 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 I OUTP J1 I OUTN K1 GND L1 GND M1 REFIO G2 GND H2 GND J2 GND K2 GND L2 GND M2 FSADJ G3 GND H3 GND J3 GND K3 GND L3 GND M3 GND G4 GND H4 GND J4 GND K4 GND L4 GND M4 AVDD33 G5 GND H5 GND J5 GND K5 GND L5 GND M5 DV DD33 G6 GND H6 GND J6 GND K6 GND L6 GND M6 GND G7 DAN4 H7 DAN3 J7 DCKON K7 DAN2 L7 DAN1 M7 DAN0 G8 DAP4 H8 DAP3 J8 DCKOP K8 DAP2 L8 DAP1 M8 DAP0 G9 DBN4 H9 DBN3 J9 DCKIN K9 DBN2 L9 DBN1 M9 DBN0 G10 DBP4 H10 DBP3 J10 DCKIP K10 DBP2 L10 DBP1 M10 DBP0 PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION N1 GND P1 AV DD33 Q1 AVDD33 R1 GND S1 PD N2 GND P2 AVDD33 Q2 AVDD33 R2 GND S2 CS N3 GND P3 AVDD33 Q3 AVDD33 R3 TSTN S3 SDO N4 AVDD33 P4 AVDD33 Q4 AVDD33 R4 TSTP S4 SDI N5 DV DD33 P5 DV DD33 Q5 DV DD33 R5 GND S5 SCK N6 GND P6 GND Q6 GND R6 GND S6 SV DD N7 GND P7 GND Q7 GND R7 GND S7 GND N8 GND P8 GND Q8 GND R8 GND S8 GND N9 GND P9 GND Q9 GND R9 GND S9 GND N10 GND P10 GND Q10 GND R10 GND S10 GND

For more information www.linear .com/L TC2000 PIN LOCATIONS (LTC2000-11) S R Q P N M L K J H G F E D C B A 2 3 4 5 6 7 8 9 10 TOP VIEW GND PD CS SDO SDI TSTN TSTP SCK SV DD GND DANO DAPO DBNO DBPO DAN1 DAP1 DBN1 DBP1 DAN2 DAP2 DBN2 DBP2 DAN3 DAP3 DBN3 DBP3 DAN4 DAP4 DBN4 DBP4 DAN5 DAP5 DBN5 DBP5 DAN6 DAP6 DBN6 DBP6 DAN7 DAP7 DBN7 DBP7 DAN8 DAP8 DBN8 DBP8 DAN9 DAP9 DBN9 DBP9 DAN10 DAP10 DBN10 DBP10 DCKON DCKOP DCKIN DCKIP GND AVDD33 DVDD18 AVDD18 DVDD33 GND IOUTP IOUTN REFIO FSADJ GND CKN CKP

For more information www.linear .com/L TC2000 Please refer to http://www.linear .com/product/LTC2000#packaging for the most recent package drawings. PACKAGE DESCRIPTION S R Q P N M L K J H G F E D C B A 1 2 3 4 5 610 9 8 7 PACKAGE TOP VIEW PIN “A1” CORNER Y X aaa Z aaa Z DETAIL A PACKAGE BOTTOM VIEW SEE NOTES PIN 1 170-Lead (15.00mm × 9.00mm × 1.54mm) (Reference LTC DWG# 05-08-1890 Rev C) BGA 170 0517 REV C TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1” NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS BALL DESIGNATION PER JESD MS-028 AND JEP95 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE DETAIL A Øb (170 PLACES) A DETAIL B PACKAGE SIDE VIEW M X Y Z ddd M Z eee D E e e b F G SUGGESTED PCB LAYOUT TOP VIEW 0.00 3.20 3.20 6.40 4.00 4.00 4.80 4.80 5.60 5.60 6.40 0.80 0.80 1.60 1.60 2.40 2.40 3.60 2.80 2.00 2.80 1.20 0.40 2.00 1.20 0.40 3.60 0.00 5.35 5.85 L TXXXXXX b 0.40 ±0.025 Ø 170x 3.05 2.55 SEE NOTES SYMBOL A b D E e F G aaa bbb ccc ddd eee MIN 1.39 0.35 1.04 0.45 0.37 0.39 0.65 NOM 1.54 0.40 1.14 0.50 0.40 15.00 9.00 0.80 12.80 7.20 0.44 0.70 MAX 1.69 0.45 1.24 0.55 0.43 0.49 0.75 0.15 0.10 0.12 0.15 0.08 TOTAL NUMBER OF BALLS: 170 DIMENSIONS NOTES BALL HT BALL DIMENSION PAD DIMENSION SUBSTRATE THK MOLD CAP HT Z 5. PRIMARY DATUM -Z- IS SEATING PLANE

6 PACKAGE ROW AND COLUMN LABELING MAY VARY

AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULL Y DETAIL B SUBSTRATE ccc Z Z // bbb Z MOLD CAP

For more information www.linear .com/L TC2000 Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 04/17 Added lead-finish option 4 B 12/17 Update to text regarding series resistance requirement 33

For more information www.linear .com/L TC2000  ANALOG DEVICES, INC. 2014 LT 1217 REV B • PRINTED IN USA www.linear .com/L TC2000 RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LTC1666/LTC1667/ LTC1668 12-/14-/16-Bit 50Msps DACs with 10mA Full Scale VCC = ±5V, –1V to 1V Output Compliance, 28-Pin SSOP Package LTC2153/LTC2158 Single/Dual 14-/12-Bit 310Msps ADCs 88dB SFDR, 1.25GHz Bandwidth Sample-and-Hold LTC2630 Single 12-/10-/8-Bit Rail-to-Rail DACs with Internal Reference V CC = 2.7V to 5.5V, SC70 Package LTC2991 Octal I2C Voltage, Current, and Temperature Monitor V CC = 3V to 5.5V, 16-Lead MSOP Package LTC2997 Remote/Internal Temperature Sensor VCC = 2V to 5.5V, 170µA, 6-Lead 2mm × 3mm DFN Package LT 5521 Very High Linearity Active Mixer 10MHz to 3.7GHz, 24.2dBm OIP3 at 1.95GHz LT5579 High Linearity Upconverting Mixer 1.5GHz to 3.8GHz, 27.3dBm OIP3 at 2.14GHz LT5578 High Linearity Upconverting Mixer 400MHz to 2.7GHz, 24.3dBm IIP3 at 1.95GHz LTC6406 3GHz, Low Noise, Rail-to-Rail Input Differential Amplifier/Driver Low Noise: 1.6nV/√ Hz RTI , 18mA at 3V, Low Distortion LTC6430-15 High Linearity Differential RF/IF Amplifier 20MHz to 2GHz Bandwidth, 50dBm OIP3 at 240MHz, 15.2dB Gain LTC6946 Ultralow Noise and Spurious Integer-N Synthesizer with Integrated VCO 0.37GHz to 5.7GHz, –226dBc/Hz Normalized In-Band Phase Noise, –274dBc/Hz Normalized In-Band 1/f Noise LTC2000 High Speed DAC Driving LT5579 Mixer as an Upconverting T ransmitter with Low Noise Power Supply Solution DAP[15:0] DAN[15:0] DCKIP DCKIN DBP[15:0] DBN[15:0] SV DD AVDD18 DVDD18 DCKOP DCKON CKP R29 50/uni03A9 R26 50/uni03A9 CKN TSTP TSTN I OUTN IOUTP REFIO FSADJ

2000 TA01

3.3V L TC2000Y-16 AV DD33 L T1763CS8-3.3 L T1763CS8-3.3 DVDD33 GND C43 0.01µF C66 1pF C42 100pF GND GND IN C41 100pF ANAREN B0430J50100AHF C65 10pFL6 1nH CLOCK SOURCE R52 20/uni03A9 C66 47pF 2.7nH 2.7nH L11 1.5nH 4 1 2 1 2 1 2 1 2 L10 1.5nH L12 1.8nH LO INPUT RF OUTPUTC65 47pF R50 0/uni03A9 R49 0/uni03A9 C25 0.1µF C26 0.1µFR51 20/uni03A9 7.15k R45 500/uni03A9 C40 10µF R53 11.5/uni03A9 R54 11.5/uni03A9 C68 82pF C67 82pF C68 22pF C69 1.2pF C74 10µF C73 1µF C72 100pF C71 10pF SHDN IN GND GND GND OUT SEN BYP 7 4 0.01µF 47µF1µF SHDN IN GND GND GND OUT SEN BYP 7 4 0.01µF 47µF1µF SHDN V IN GND GND OUTF OUTS GND GND 10µF 3.24k4.7µF 1µF 1µF 47µF 1µF 3.3V IF– L T5579 0.1dB CHEBYCHEV , BW = 535MHz VCC 3.3V GND IF+ LO RF L TC6655CH MS8-2.048 VOUT VOUT VOUT PAD SET V IN VIN VCTRL L T3080EDD 3.3V 3.24k4.7µF 47µF VOUT VOUT VOUT PAD SET V IN VIN VCTRL L T3080EDD 3.3V