LTC2433-1 LINEAR | Alldatasheet
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2433-1 is a differential input micropower 16-bit No Latency DS TM analog-to-digital converter with an inte- grated oscillator. It provides 0.12LSB INL and 1.45 mV RMS noise independent of V REF. It uses delta-sigma technology and provides single conversion settling of the digital filter. Through a single pin, the LTC2433-1 can be configured for better than 87dB input differential mode rejection at 50Hz and 60Hz –2%, or it can be driven by an external oscillator for a user defined rejection frequency. The internal oscillator requires no external frequency setting components. The converter accepts any external differential reference voltage from 0.1V to V CC for flexible ratiometric and remote sensing measurement configurations. The full- scale differential input range is from – 0.5 •␣ VREF to 0.5 • VREF. The reference common mode voltage, VREFCM, and the input common mode voltage, VINCM, may be indepen- dently set anywhere between GND and V CC. The DC common mode input rejection is better than 140dB. The LTC2433-1 communicates through a flexible 3-wire digital interface which is compatible with SPI and MICROWIRE TM protocols. n Direct Sensor Digitizer n Weight Scales n Direct Temperature Measurement n Gas Analyzers n Strain-Gage Transducers n Instrumentation n Data Acquisition n Industrial Process Control , LTC and LT are registered trademarks of Linear Technology Corporation. n 16-Bit Differential ADC in a Tiny MSOP n Low Supply Current: 200mA, 4mA in Autosleep n Rail-to-Rail Differential Input/Reference n 0.12LSB INL, No Missing Codes n 0.16LSB Full-Scale Error and 5mV Offset n 1.45mV RMS Noise, Independent of VREF n Very Low Transition Noise: <0.02LSB n Operates with a Reference as Low as 100mV with 16-Bit Resolution n Internal Oscillator—No External Components Required n 87dB Min, Simultaneous 50Hz and 60Hz Notch Filter n Single Supply 2.7V to 5.5V Operation n Pin Compatible with the 20/24-Bit LTC2431/LTC2411 n Available in 10-Lead MSOP Package Differential Input 16-Bit No Latency DS ADC No Latency DS is a trademark of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. Minimum Resolvable Signal vs VREF VCC REF+ FO IN+ IN– SCK REF– SDO GND CS 11 0
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= EXTERNAL CLOCK SOURCE = INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION 3-WIRE SPI INTERFACE 1µF (100mV) 4.9k 100Ω 5V REF LTC2433-1 VREF (V) *FOR VREF ‡ 0.5V THE RESOLUTION IS LIMITED BY STEP SIZE MINIMUM RESOLVABLE SIGNAL (µV)* 2 4 5
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(Notes 1, 2) Analog Input Voltage Reference Input Voltage CC + 0.3V) Operating Temperature Range TJMAX = 125°C, qJA = 110°C/W LTC2433-1CMS LTC2433-1IMS PARAMETER CONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes) 0.1V £ VREF £ VCC, –0.5 • VREF £ VIN £ 0.5 • VREF, (Note 5) l 16 Bits Integral Nonlinearity (Note 15) 5V £ VCC £ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6) 0.06 LSB 5V £ VCC £ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V, (Note 6) l 0.12 1.25 LSB REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6) 0.30 LSB Offset Error (Note 15) 2.5V £ REF+ £ VCC, REF– = GND, l 52 0 mV GND £ IN+ = IN– £ VCC, (Note 13) Offset Error Drift 2.5V £ REF+ £ VCC, REF– = GND, 20 nV/ °C GND £ IN+ = IN– £ VCC Positive Full-Scale Error (Note 15) 2.5V £ REF+ £ VCC, REF– = GND, l 0.16 1.25 LSB IN+ = 0.75REF+, IN– = 0.25 • REF+ Positive Full-Scale Error Drift 2.5V £ REF+ £ VCC, REF– = GND, 0.04 ppm of V REF/°C IN+ = 0.75REF+, IN– = 0.25 • REF+ Negative Full-Scale Error (Note 15) 2.5V £ REF+ £ VCC, REF– = GND, l 0.16 1.25 LSB IN+ = 0.25 • REF+, IN– = 0.75 • REF+ Negative Full-Scale Error Drift 2.5V £ REF+ £ VCC, REF– = GND, 0.04 ppm of V REF/°C IN+ = 0.25 • REF+, IN– = 0.75 • REF+ Total Unadjusted Error 5V £ VCC £ 5.5V, REF+ = 2.5V, REF– = GND, VINCM = 1.25V 0.20 LSB 5V £ VCC £ 5.5V, REF+ = 5V, REF– = GND, VINCM = 2.5V 0.20 LSB REF+ = 2.5V, REF– = GND, VINCM = 1.25V, (Note 6) 0.25 LSB Output Noise 5V £ VCC £ 5.5V, REF+ = 5V, REF– = GND, 1.45 mVRMS GND £ IN– = IN+ £ VCC, (Note 12) The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4, 6) MS PART MARKING LTAEY LTAEZ Consult LTC Marketing for parts specified with wider operating temperature ranges. V CC REF+ REF– IN+ IN– F O SCK SDO CS GND TOP VIEW MS10 PACKAGE 10-LEAD PLASTIC MSOP ABSOLUTE AXI U RATI GSW WW U PACKAGE/ORDER I FOR ATIOUU W
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IN+ Absolute/Common Mode IN+ Voltage l GND – 0.3 V CC + 0.3 V IN– Absolute/Common Mode IN– Voltage l GND – 0.3 V CC + 0.3 V VIN Input Differential Voltage Range l –VREF/2 V REF/2 V (IN+ – IN–) REF+ Absolute/Common Mode REF+ Voltage l 0.1 V CC V REF– Absolute/Common Mode REF– Voltage l GND V CC – 0.1 V VREF Reference Differential Voltage Range l 0.1 V CC V (REF+ – REF–) CS (IN+)I N + Sampling Capacitance 6 pF CS (IN–)I N – Sampling Capacitance 6 pF CS (REF+)R E F + Sampling Capacitance 6 pF CS (REF–)R E F – Sampling Capacitance 6 pF IDC_LEAK (IN+)I N + DC Leakage Current CS = V CC = 5V, IN+ = GND l –100 1 100 nA IDC_LEAK (IN–)I N – DC Leakage Current CS = V CC = 5V, IN– = 5.5V l –100 1 100 nA IDC_LEAK (REF+)R E F + DC Leakage Current CS = V CC = 5V, REF+ = 5.5V l –100 1 100 nA IDC_LEAK (REF–)R E F – DC Leakage Current CS = V CC = 5V, REF– = GND l –100 1 100 nA The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4) PARAMETER CONDITIONS MIN TYP MAX UNITS Input Common Mode Rejection DC 2.5V £ REF+ £ VCC, REF– = GND, l 130 140 dB GND £ IN– = IN+ £ VCC (Note 5) Input Common Mode Rejection 2.5V £ REF+ £ VCC, REF– = GND, l 140 dB 49Hz to 61.2Hz GND £ IN– = IN+ £ VCC, (Notes 5, 7) Input Normal Mode Rejection (Note 5, 7) l 87 dB 49Hz to 61.2Hz Reference Common Mode 2.5V £ REF+ £ VCC, GND £ REF– £ 2.5V, l 130 140 dB Rejection DC V REF = 2.5V, IN– = IN+ = GND (Note 5) Power Supply Rejection, DC REF + = 2.5V, REF– = GND, IN– = IN+ = GND 120 dB Power Supply Rejection, REF + = 2.5V, REF– = GND, IN– = IN+ = GND, (Note 7) 120 dB Simultaneous 50Hz/60Hz –2% CO VERTER CHARACTERISTICSU U UA ALOG I PUT A D REFERE CEU U
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VCC Supply Voltage l 2.7 5.5 V ICC Supply Current Conversion Mode CS = 0V (Note 14) l 200 300 mA Sleep Mode CS = V CC (Notes 11, 14) l 41 3 mA Sleep Mode CS = V CC, 2.7V £ VCC £ 3.3V 2 mA (Notes 11, 14) The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIH High Level Input Voltage 2.7V £ VCC £ 5.5V l 2.5 V CS, FO 2.7V £ VCC £ 3.3V 2.0 V VIL Low Level Input Voltage 4.5V £ VCC £ 5.5V l 0.8 V CS, FO 2.7V £ VCC £ 5.5V 0.6 V VIH High Level Input Voltage 2.7V £ VCC £ 5.5V (Note 8) l 2.5 V SCK 2.7V £ VCC £ 3.3V (Note 8) 2.0 V VIL Low Level Input Voltage 4.5V £ VCC £ 5.5V (Note 8) l 0.8 V SCK 2.7V £ VCC £ 5.5V (Note 8) 0.6 V IIN Digital Input Current 0V £ VIN £ VCC l –10 10 mA CS, FO IIN Digital Input Current 0V £ VIN £ VCC (Note 8) l –10 10 mA SCK CIN Digital Input Capacitance 10 pF CS, FO CIN Digital Input Capacitance (Note 8) 10 pF SCK VOH High Level Output Voltage I O = –800mA l VCC – 0.5 V SDO VOL Low Level Output Voltage I O = 1.6mA l 0.4 V SDO VOH High Level Output Voltage I O = –800mA (Note 9) l VCC – 0.5 V SCK VOL Low Level Output Voltage I O = 1.6mA (Note 9) l 0.4 V SCK IOZ Hi-Z Output Leakage l –10 10 mA SDO POWER REQUIRE E TSW U DIGITAL I PUTS A D DIGITAL OUTPUTSU U
Note 9: The converter is in internal SCK mode of operation such that the SCK pin is used as digital output. In this mode of operation the SCK pin has a total equivalent load capacitance C LOAD = 20pF. Note 10: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 11: The converter uses the internal oscillator. FO = 0V. Note 12: 1.45mV RMS noise is independent of VREF. Since the noise performance is limited by the quantization, lowering VREF improves the effective resolution. Note 13: Guaranteed by design and test correlation. Note 14: The low sleep mode current is valid only when CS is high. Note 15: These parameters are guaranteed by design over the full supply and temperature range. Automated testing procedures are limited by the LSB step size (V REF/65,536). Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7V to 5.5V unless otherwise specified. VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2; VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2. Note 4: FO pin tied to GND or to an external conversion clock source with fEOSC = 139,800Hz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a precise analog input voltage. Maximum specifications are limited by the LSB step size (VREF/216) and the single shot measurement. Typical specifications are measured from the center of the quantization band. Note 7: FO = GND (internal oscillator) or fEOSC = 139,800Hz – 2% (external oscillator). Note 8: The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is f ESCK and is expressed in kHz. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fEOSC External Oscillator Frequency Range l 2.56 2000 kHz tHEO External Oscillator High Period l 0.25 390 ms tLEO External Oscillator Low Period l 0.25 390 ms tCONV Conversion Time F O = 0V l 143.8 146.7 149.6 ms External Oscillator (Note 10) l 20510/fEOSC (in kHz) ms fISCK Internal SCK Frequency Internal Oscillator (Note 9) 17.5 kHz External Oscillator (Notes 9, 10) f EOSC/8 kHz DISCK Internal SCK Duty Cycle (Note 9) l 45 55 % fESCK External SCK Frequency Range (Note 8) l 2000 kHz tLESCK External SCK Low Period (Note 8) l 250 ns tHESCK External SCK High Period (Note 8) l 250 ns tDOUT_ISCK Internal SCK 19-Bit Data Output Time Internal Oscillator (Notes 9, 11) l 1.06 1.09 1.11 ms External Oscillator (Notes 9, 10) l 152/fEOSC (in kHz) ms tDOUT_ESCK External SCK 19-Bit Data Output Time (Note 8) l 19/fESCK (in kHz) ms t1 CS fl to SDO Low Z l 0 200 ns t2 CS › to SDO High Z l 0 200 ns t3 CS fl to SCK fl (Note 9) l 0 200 ns t4 CS fl to SCK › (Note 8) l 50 ns tKQMAX SCK fl to SDO Valid l 220 ns tKQMIN SDO Hold After SCK fl (Note 5) l 15 ns t5 SCK Set-Up Before CS fl l 50 ns t6 SCK Hold After CS fl l 50 ns The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) TI I G CHARACTERISTICSUW
VCC (Pin 1): Positive Supply Voltage. Bypass to GND with a 10mF tantalum capacitor in parallel with 0.1mF ceramic capacitor as close to the part as possible. REF+ (Pin 2), REF– (Pin 3): Differential Reference Input. The voltage on these pins can have any value between GND and VCC as long as the reference positive input, REF +, is maintained more positive than the reference negative input, REF –, by at least 0.1V. IN+ (Pin 4), IN – (Pin 5): Differential Analog Input. The voltage on these analog inputs can have any value between GND and V CC. Within these limits the converter bipolar input range (VIN = IN+ – IN–) extends from – 0.5 • (VREF) to 0.5 • (V REF). Outside this input range the converter produces unique overrange and underrange output codes. GND (Pin 6): Ground. Connect this pin to a ground plane through a low impedance connection. CS (Pin 7): Active LOW Digital Input. A LOW on this pin enables the SDO digital output and wakes up the ADC. Following each conversion the ADC automatically enters the Sleep mode and remains in this low power state as long as CS is HIGH. A LOW-to-HIGH transition on CS during the Data Output transfer aborts the data transfer and starts a new conversion. SDO (Pin 8): Three-State Digital Output. During the Data Output period, this pin is used as serial data output. When the chip select CS is HIGH (CS = VCC) the SDO pin is in a high impedance state. During the Conversion and Sleep periods, this pin is used as the conversion status output. The conversion status can be observed by pulling CS LOW. SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal Serial Clock Operation mode, SCK is used as digital output for the internal serial interface clock during the Data Output period. In External Serial Clock Operation mode, SCK is used as digital input for the external serial interface clock during the Data Output period. A weak internal pull- up is automatically activated in Internal Serial Clock Op- eration mode. The Serial Clock Operation mode is deter- mined by the logic level applied to the SCK pin at power up or during the most recent falling edge of CS. F O (Pin 10): Frequency Control Pin. Digital input that controls the ADC’s notch frequencies and conversion time. When the FO pin is connected to GND (FO = 0V), the converter uses its internal oscillator and rejects 50Hz and 60Hz simultaneously. When F O is driven by an external clock signal with a frequency fEOSC, the converter uses this signal as its system clock and the digital filter has 87dB minimum rejection in the range f EOSC/2560 –14% and 110dB minimum rejection at fEOSC/2560 –4%. UUUPI FU CTIO S
Figure 1. Functional Block Diagram
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(see Figure 1). Its operation is made up of three states. conversion is complete, the device enters the sleep state. The part remains in the sleep state as long as CS is HIGH. conversion. There is no latency in the conversion result. reliably latch data on the rising edge of SCK (see Figure 3). data bits which are logic HIGH. multiple analog voltages is easy. Figure 2. LTC2433-1 State Transition Diagram
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The LTC2433-1 performs offset and full-scale calibrations every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation de- scribed above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with re- spect to time, supply voltage change and temperature drift. Power-Up Sequence The LTC2433-1 automatically enters an internal reset state when the power supply voltage V CC drops below approxi- mately 2V. This feature guarantees the integrity of the conversion result and of the serial interface mode selec- tion. (See the 2-wire I/O sections in the Serial Interface Timing Modes section.) When the V CC voltage rises above this critical threshold, the converter creates an internal power-on-reset (POR) signal with a typical duration of 1ms. The POR signal clears all internal registers. Following the POR signal, the LTC2433-1 starts a normal conversion cycle and follows the succession of states described above. The first con- version result following POR is accurate within the speci- fications of the device if the power supply voltage is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval. Reference Voltage Range This converter accepts a truly differential external refer- ence voltage. The absolute/common mode voltage speci- fication for the REF + and REF– pins covers the entire range from GND to V CC. For correct converter operation, the REF+ pin must always be more positive than the REF– pin. The LTC2433-1 can accept a differential reference voltage from 0.1V to V CC. The converter output noise is deter- mined by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly constant with reference voltage. A decrease in reference voltage will significantly improve the converter’s effective resolution, since the thermal noise (1.45mV) is well below the quan- tization level of the device (75.6mV for a 5V reference). At the minimum reference (100mV) the thermal noise remains constant at 1.45mV RMS (or 8.7mV P-P), while the quantization is reduced to 1.5 mV per LSB. As a result, lowering the reference improves the effective resolution for low level input voltages. Input Voltage Range The analog input is truly differential with an absolute/ common mode range for the IN + and IN – input pins extending from GND – 0.3V to VCC + 0.3V. Outside these limits, the ESD protection devices begin to turn on and the errors due to input leakage current increase rapidly. Within these limits, the LTC2433-1 converts the bipolar differen- tial input signal, V IN = IN+ – IN–, from – FS = – 0.5 • VREF to +FS = 0.5 • VREF where VREF = REF+ – REF–. Outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. Input signals applied to the analog input pins may extend by 300mV below ground and above VCC. In order to limit any fault current, resistors of up to 5k may be added in series with the pins without affecting the performance of the device. In the physical layout, it is important to main- tain the parasitic capacitance of the connection between these series resistors and the corresponding pins as low as possible; therefore, the resistors should be located as close as practical to the pins. The effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the Input Current/Reference Current sections. In addition, series resistors will intro- duce a temperature dependent offset error due to the input leakage current. A 10nA input leakage current will develop a 1LSB offset error on an 8k resistor if V REF = 5V. This error has a very strong temperature dependency. Output Data Format The LTC2433-1 serial output data stream is 19 bits long. The first 3 bits represent status information indicating the conversion state and sign. The next 16 bits are the conver- sion result, MSB first. The third and fourth bit together are also used to indicate an underrange condition (the differ- ential input voltage is below –FS) or an overrange condi- tion (the differential input voltage is above +FS). APPLICATIO S I FOR ATIOWU UU
conversion and sleep states whenever the CS pin is LOW. when the conversion is complete. differential input voltage is below –FS. The function of these bits is summarized in Table 1. Table 1. LTC2433-1 Status Bits Bits 15-0 are the 16-Bit conversion result MSB first. Bit 0 is the least significant bit (LSB). the conversion ends, they will not effect the serial data. corresponding to –FS – 1LSB. Figure 3. Output Data Timing
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60Hz rejection, FO should be connected to GND. Table 2. LTC2433-1 Output Data Format *The differential input voltage VIN = IN+ – IN–. **The differential reference voltage VREF = REF+ – REF–. Figure 4. LTC2433-1 Normal Mode
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frequency deviation from fEOSC/2560 is shown in Figure 5. Figure 5. LTC2433-1 Normal Mode Rejection When
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to read the conversion result. the SDO pin on the falling edge of the serial clock. transition, the converter enters the external SCK mode. described in the previous sections. Table 3. LTC2433-1 State Duration
of operation, see Serial Interface Timing Modes section. control the state of the conversion cycle, see Figure 6. The serial clock mode is selected on the falling edge of CS. (SCK) must be LOW during each CS falling edge. Figure 6. External Serial Clock, Single Cycle Operation Table 4. LTC2433-1 Interface Timing Modes
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pulled LOW in order to monitor the state of the converter. While CS is pulled LOW, EOC is output to the SDO pin. falling edge of SCK, the device begins a new conversion. and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z. order to monitor the conversion status. Typically, CS remains LOW during the data output state. Figure 7. External Serial Clock, Reduced Data Output Length
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Figure 8. External Serial Clock, CS = 0 Operation (2-Wire) interface or isolation barrier. SCK at this time determines if SCK is internal or external. to enter the external serial clock timing mode. external controller indicating the conversion result is ready. (EOC␣ =␣ 1) indicating a new conversion has begun. control the state of the conversion cycle, see Figure 9. matically selected if SCK is not externally driven. pulled LOW in order to monitor the state of the converter. and EOC = 0 if the device is in the sleep state.
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internal static shift register. of the conversion result on the 19th rising edge of SCK. stays HIGH and a new conversion starts. Typically, CS remains LOW during the data output state. driven if the device is in the internal SCK timing mode. Figure 9. Internal Serial Clock, Single Cycle Operation
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the internal SCK timing mode. adding an external 10k pull-up resistor to the SCK pin. Figure 11. CS may be permanently tied to ground, simpli- fying the user interface or isolation barrier. external SCK mode will be selected). Figure 10. Internal Serial Clock, Reduced Data Output Length
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remains HIGH during the conversion. not generally active during the conversion state. Figure 11. Internal Serial Clock, Continuous Operation
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During the conversion period, the undershoot and/or overshoot of a fast digital signal connected to the LTC2433-1 pins may severely disturb the analog to digital conversion process. Undershoot and overshoot can oc- cur because of the impedance mismatch at the converter pin when the transition time of an external control signal is less than twice the propagation delay from the driver to LTC2433-1. For reference, on a regular FR-4 board, signal propagation velocity is approximately 183ps/inch for internal traces and 170ps/inch for surface traces. Thus, a driver generating a control signal with a minimum transi- tion time of 1ns must be connected to the converter pin through a trace shorter than 2.5 inches. This problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. The solution is to carefully terminate all transmission lines close to their characteristic impedance. Parallel termination near the LTC2433-1 pin will eliminate this problem but will increase the driver power dissipation. A series resistor between 27W and 56W placed near the driver will also eliminate this problem without additional power dissipation. The actual resistor value depends upon the trace impedance and connection topology. An alternate solution is to reduce the edge rate of the control signals. It should be noted that using very slow edges will increase the converter power supply current during the transition time. The multiple ground pins used in this package configuration, as well as the differential input and reference architecture, reduce substantially the converter’s sensitivity to ground currents. Particular attention must be given to the connection of the F O signal when the LTC2433-1 is used with an external conversion clock. This clock is active during the conver- sion time and the normal mode rejection provided by the internal digital filter is not very high at this frequency. A normal mode signal of this frequency at the converter reference terminals may result in DC gain and INL errors. A normal mode signal of this frequency at the converter input terminals may result in a DC offset error. Such perturbations may occur due to asymmetric capacitive coupling between the F O signal trace and the converter input and/or reference connection traces. An immediate solution is to maintain maximum possible separation between the F O signal trace and the input/reference sig- nals. When the F O signal is parallel terminated near the converter, substantial AC current is flowing in the loop formed by the F O connection trace, the termination and the ground return path. Thus, perturbation signals may be inductively coupled into the converter input and/or refer- ence. In this situation, the user must reduce to a minimum the loop area for the F O signal as well as the loop area for the differential input and reference connections. Driving the Input and Reference The input and reference pins of the LTC2433-1 converter are directly connected to a network of sampling capaci- tors. Depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four pins transfering small amounts of charge in the process. A simplified equivalent circuit is shown in Figure 12, where IN + and IN– refer to the selected differential channel and the unselected channel is omitted for simplicity. For a simple approximation, the source impedance R S driving an analog input pin (IN+, IN–, REF+ or REF–) can be considered to form, together with R SW and C EQ (see Figure␣ 12), a first order passive network with a time constant t = (RS + RSW) • CEQ. The converter is able to sample the input signal with better than 1LSB accuracy if the sampling period is at least 11 times greater than the input circuit time constant t. The sampling process on the four input analog pins is quasi-independent so each time constant should be considered by itself and, under worst- case circumstances, the errors may add. When using the internal oscillator (F O = LOW), the LTC2433-1’s front-end switched-capacitor network is clocked at 69900Hz corresponding to a 14.3ms sampling APPLICATIO S I FOR ATIOWU UU
for a settling error of less than 1LSB, t £ 0.18/fEOSC. stantial time period (longer than 64 internal clock cycles). Figure 13. An RC Network at IN+ and IN– Figure 14. +FS Error vs RSOURCE at IN+ or IN– (Small CIN)
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Figure 12. LTC2433-1 Equivalent Analog Input Circuit
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- - • () = -• - +
- + • V REF REF V REF REF VI N I N V IN IN R M INTERNAL OSCILLATOR Hz Hz Notch F LOW R f EXTERNAL OSCILLATOR REF REFCM IN INCM EQ O EQ EOSC = +æ Łç ö = -æ Łç ö == () =•() 11 9 50 60 16 7 1 0 12 W RSOURCE (Ω ) 1 10 100 1k 10k 100k +FS ERROR (LSB)
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Figure 16. +FS Error vs RSOURCE at IN+ or IN– (Large CIN) Figure 17. –FS Error vs RSOURCE at IN+ or IN– (Large CIN)
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Figure 15. –FS Error vs RSOURCE at IN+ or IN– (Small CIN)
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will see a quasi constant input differential impedance. for each 180 W of source resistance driving IN + or IN –.
- fEOSCLSB. Figure 18 shows the typical offset error due to input common mode voltage for various values of source resistance imbalance between the IN+ and IN– pins when large CIN values are used. If possible, it is desirable to operate with the input signal common mode voltage very close to the reference signal common mode voltage as is the case in the ratiometric measurement of a symmetric bridge. This configuration eliminates the offset error caused by mismatched source impedances. The magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. The accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. Such a specification can also be easily achieved by an external clock. When relatively stable resistors (50ppm/ °C) are used for the external source impedance seen by IN + and IN–, the expected drift of the dynamic current, offset and gain errors will be insignificant (about 1% of their respec- tive values over the entire temperature and voltage range). Even for the most stringent applications, a one-time calibration operation may be sufficient. In addition to the input sampling charge, the input ESD protection diodes have a temperature dependent leakage current. This current, nominally 1nA (–10nA max), results in a small offset shift. A 15k source resistance will create a 0LSB typical and 1LSB maximum offset voltage. Reference Current In a similar fashion, the LTC2433-1 samples the differen- tial reference pins REF + and REF– transfering small amount of charge to and from the external driving circuits thus producing a dynamic reference current. This current does not change the converter offset, but it may degrade the gain and INL performance. The effect of this current can be analyzed in the same two distinct situations. For relatively small values of the external reference capaci- tors (C REF < 0.01mF), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. Such values for C REF will deteriorate the converter offset and gain performance without significant benefits of reference filtering and the user is advised to avoid them.
Figure 18. Offset Error vs Common Mode Voltage
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be required as reference filters in certain configurations. Figure 19. +FS Error vs RSOURCE at REF+ or REF– (Small CIN) Figure 20. –FS Error vs R SOURCE at REF+ or REF– (Small CIN) Figure 21. +FS Error vs RSOURCE at REF+ and REF– (Large CREF) Figure 22. –FS Error vs R SOURCE at REF+ and REF– (Large CREF)
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mance is degraded by the reference source impedance.
REF– pins rather than to try to match it. operation may be sufficient. differential mode conversion sources in the input circuit. Figure 23. INL vs Differential Input Voltage (VIN = IN+ – IN–)
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Figure 24. Offset Error vs Output Data Rate and Temperature Figure 25. +FS Error vs Output Data Rate and Temperature Figure 26. –FS Error vs Output Data Rate and Temperature Figure 27. Noise Histogram (Output Rate = 100Hz,
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Figure 28. Integral Nonlinearity vs Output Data Rate Figure 29. Offset Error vs Output
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ence voltage may be beneficial. of ADCs that cannot operate with a low reference voltage. scale strain gauge measurements. scale outputs of 50mV to 200mV.
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. UPACKAGE DESCRIPTIO MSOP (MS) 0802 0.53 – 0.01 (.021 – .006) SEATING PLANE 0.18 (.007) 1.10 (.043) MAX 0.17 – 0.27 (.007 – .011) TYP 0.13 – 0.076 (.005 – .003) 0.86 (.034) REF 0.50 (.0197) BSC 12 3 45 4.90 – 0.15 (1.93 – .006) 0.497 – 0.076 (.0196 – .003) REF8910 7 6 3.00 – 0.102 (.118 – .004) (NOTE 3) 3.00 – 0.102 (.118 – .004) NOTE 4 NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.254 (.010) 0° – 6° TYP DETAIL “A” DETAIL “A” GAUGE PLANE 5.23 (.206) MIN 3.2 – 3.45 (.126 – .136) 0.889 – 0.127 (.035 – .005) RECOMMENDED SOLDER PAD LAYOUT 0.305 – 0.038 (.0120 – .0015) TYP 0.50 (.0197) BSC 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661)
Figure 30. Increased Resolution Bridge/Temperature Measurement