LT8710

LT8710 - Synchronous SEPIC/ Inverting/Boost Controller with Output Current Control

Document overview

• Manufacturer or author: Linear Technology Corporation
• PDF pages: 44

Technical content

8710fFor more information www.linear .com/L T8710 Typical applicaTion FeaTures DescripTion Synchronous SEPIC/ Inverting/Boost Contr oller with Output Current Control The LT®8710 is a synchronous PWM DC/DC controller with a rail-to-rail output current monitor and control. The LT8710 is ideal for many types of power supply topologies and can be easily configured for boost, SEPIC, inverting, or flyback configurations. The LT8710’s rail-to-rail output current monitor and control allows the part to be configured in current limited applica- tions such as battery charging. The FLAG pin can be used as a power good indication or C/10 indication allowing for accurate bulk and float battery voltages. The LT8710’s switching frequency range can be set be - tween 100kHz and 750 kHz using an external resistor or synchronized to an external clock. The LT8710 also features innovative EN/FBIN pin cir - cuitry that allows for slowly varying input signals and an adjustable undervoltage lockout function. The pin is also used for input voltage regulation to avoid collapsing a high impedance input supply. Additional features such as frequency foldback and soft-start are integrated. The LT8710 is available in a 20-lead TSSOP package. 300kHz Inverter Generates –5V from a 4.5V to 25V Input

applicaTions

L, LT, LT C, LT M, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, Including 7579816. n Wide Input Range: 4.5V to 80V n Rail-to-Rail Output Current Monitor and Control n Input V oltage Regulation for High Impedance Inputs n C/10 or Power Good Indication Pin n MODE Pin for Forced CCM or Pulse-Skipping Operation n Switching Frequency Up to 750kHz n Easily Configurable as a Boost, SEPIC, Inverting or Flyback Converter with Single Feedback Pin n Can Be Synchronized to External Clock n High Gain EN/FBIN Pin Accepts Slowly Varying Input Signals n 20-Lead TSSOP Package n High Power Local Power Supply n Wide Input Voltage Range SEPIC/Inverting n Lead Acid Battery Charger n Automotive Engine Control Unit (ECU) Power n Solar Panel Power Converter Efficiency and Power Loss IMON SSGND CSP TGCSNBG L T8710

8710 TA01a

–5V VIN 4.5V TO 25V 13.3k 2.2µH 120µF 2.2µF 100µF 10k 10µF 118k 1.5m 2.2µH

• 10µF ×2 60.4k 11.5k 2.2µF INTVCC 330µF+ 47nF 220nF 3.3nF 100pF 499/uni03A9 0.47µF LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W) 100 1 4 5 6

8710 TA01b

VIN = 5V VIN = 12V

8710f For more information www.linear .com/L T8710 pin conFiguraTion absoluTe MaxiMuM raTings (Note 1) FE PACKAGE 20-LEAD PLASTIC TSSOP TOP VIEW FBX V C SS FLAG IMON ISN ISP BIAS INTVEE TG GND SYNC RT MODE EN/FBIN CSP CSN V IN INTVCC BG GND TJMAX = 125°C, θJA = 38°C/W, θJC = 10°C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8710EFE#PBF LT8710EFE#TRPBF LT8710FE 20-Lead Plastic TSSOP –40°C to 125°C LT8710IFE#PBF LT8710IFE#TRPBF LT8710FE 20-Lead Plastic TSSOP –40°C to 125°C Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 0.3V to 80V 0.3V to 80V te 5 te 5 0.3V to 5V 0.3V to 3V V 0.3V to 5.5V 0.3V to 7V MODE 0.3V to 40V 3V to 2V 0.3V to 2V SN – 0.4V to ISN + 2V 3V to 80V 0.3V to 2.5V Operating Junction Temperature Range LT87 40°C to 125°C LT87 65°C to 150°C 0°C

8710fFor more information www.linear .com/L T8710

elecTrical characTerisTics

PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Operating Input Voltage V IN OR VBIAS VIN if VBIAS ≥ 4.5V l 4.25 4.5 V V Quiescent Current, IVIN VBIAS = VISN = 7.5V, Not Switching VBIAS = 6.3V, VINTVEE = VISN = 0V, Not Switching 5.5 5.5 7.5 mA mA Quiescent Current in Shutdown VEN/FBIN = 0V 0 1 µA EN/FBIN Active Mode EN/FBIN Rising l 1.64 1.7 1.76 V EN/FBIN Chip Enable EN/FBIN Rising EN/FBIN Falling l l 1.22 1.18 1.3 1.26 1.38 1.34 V V EN/FBIN Chip Enable Hysteresis 44 mV EN/FBIN Input V oltage Low Shutdown Mode l 0.3 V EN/FBIN Pin Bias Current VEN/FBIN = 3V VEN/FBIN = 1.7V VEN/FBIN = 1.6V VEN/FBIN = 0V 19.5 17.5 22.5 0.1 µA µA µA µA SS Charge Current V SS = 0V, Current Flows Out of SS Pin l 7 10.1 13.8 µA SS Low Detection Voltage Part Exiting Undervoltage Lockout l 18 50 82 mV SS Hi Detection Voltage SS Rising SS Falling 1.5 1.3 1.8 1.7 2.1 2.05 V V SS Hi Detection Hysteresis 100 mV Low Dropout Regulators, INT VCC and INTVEE INTVCC Voltage IINTVCC = 10mA l 6.2 6.3 6.4 V INTVCC Undervoltage Lockout INTV CC Rising INTVCC Falling l l 3.88 3.5 3.73 4.12 3.95 V V INTV CC Undervoltage Lockout Hysteresis 270 mV INTVCC Dropout Voltage VIN – INTVCC, VIN = 6V, VBIAS = 0V, IINTVCC = 10mA VBIAS – VINTVCC, VIN = 0V, VBIAS = 6V, IINTVCC = 10mA 255 280 mV mV INTV CC Load Regulation VIN = 12V, VBIAS = 0V, IINTVCC = 0mA to 80mA VIN = 0V, VBIAS = 12V, IINTVCC = 0mA to 40mA –0.44 –0.34 INTV CC Line Regulation 10V ≤ VIN ≤ 80V, VBIAS = 0V, IINTVCC = 10mA 10V ≤ VBIAS ≤ 80V, VIN = 0V, IINTVCC = 10mA –0.003 –0.006 –0.03 –0.03 %/V %/V INTV CC Maximum External Load Current 5 mA INTVEE Voltage, VBIAS – VINTVEE IINTVEE = 10mA l 6.03 6.18 6.33 V INTVEE Undervoltage Lockout, VBIAS – VINTVEE VBIAS – VINTVEE Rising VBIAS – VINTVEE Falling l l 3.24 2.94 3.42 3.22 3.6 3.48 V V INTV EE Undervoltage Lockout Hysteresis, VBIAS – VINTVEE 200 mV INTVEE Dropout Voltage, VINTVEE VBIAS = 6V, IINTVEE = 10mA 0.75 V Control Loops (Refer to Block Diagram to Locate Amplifiers) Current Limit Voltage, VCSP – VCSN VFBX = 1.1V, Minimum Duty Cycle VFBX = 1.1V, Maximum Duty Cycle l l mV mV V FBX = 1.4V, MODE = 0V, Minimum Duty Cycle VFBX = 1.4V, MODE = 0V, Maximum Duty Cycle l l –23 –38 –32 –51 –41 –65 mV mV FBX Positive Output Regulation V oltage, EA1 l 1.191 1.213 1.237 V FBX Negative Output Regulation Voltage, EA2 l –2 9.6 21 mV The l denotes the specifications which apply over the full operating temperature range, otherwise specifications for each channel are at TA = 25°C. VIN = 12V, VEN/FBIN = 12V, VBIAS = 12V, unless otherwise noted (Note 2).

8710f For more information www.linear .com/L T8710 PARAMETER CONDITIONS MIN TYP MAX UNITS Positive FBX Pin Bias Current VFBX = Positive FBX Reg Voltage, Current into Pin l 81.9 83.7 85.6 µA Negative FBX Pin Bias Current V FBX = Negative FBX Reg Voltage, Current Out of Pin l 81.1 83.1 85.2 µA FBX Amp T ransconductance, EA1 or EA2 ΔI = 2μA 200 µmhos FBX Amp V oltage Gain, EA1 or EA2 70 V/V FBX Line Regulation 4.5V ≤ VIN ≤ 80V, VBIAS = 0V –0.02 –0.001 0.02 %/V Output Current Sense Regulation Voltage, VISP – VISN VISN = 80V, VFBX = 1V VISN = 12V, VFBX = 1V VISN = 0V, VFBX = 1V VISN = 12V, VFBX = 1V, INTVEE in UVLO and VSS > 1.8V l l l l mV mV mV mV IMON Regulation V oltage, EA3 V FBX = 1V VFBX = 1V, INTVEE in UVLO and VSS > 1.8V l l 1.184 0.885 1.213 0.916 1.24 0.947 V V Output Current Sense Amp Transconductance, A6 ΔI = 10μA 1000 µmhos Output Current Sense Amp Voltage Gain, A6

11.9 V/V

Output Current Sense Amp Input Dynamic Range, A6 Negative Input Range, V ISP – VISN Positive Input Range, VISP – VISN 500 –51.8 mV mV IMON Amp T ransconductance, EA3 ΔI = 2μA, V FBX = 1V 165 µmhos IMON Amp Voltage Gain, EA3 VFBX = 1V 65 V/V EN/FBIN Input Regulation Voltage, EA4 V FBX = 1V l 1.55 1.607 1.662 V EN/FBIN Amp T ransconductance, EA4 ΔI = 2µA, V FBX = 1V 140 µmhos EN/FBIN Amp Voltage Gain, EA4 V FBX = 1V 55 V/V MODE Forced CCM Threshold To Exit Forced CCM Mode, MODE Rising To Enter Forced CCM Mode, MODE Falling l l 1.19 1.125 1.224 1.175 1.258 1.23 V V MODE For ced CCM Threshold Hysteresis 49 mV DCM Comparator Threshold in Pulse-Skipping Mode, MODE = 2V V ISN = 80V, To Enter DCM Mode, VISP – VISN Falling VISN = 12V, To Enter DCM Mode, VISP – VISN Falling VISN = 0V, To Enter DCM Mode, VISP – VISN Falling l l l –4.5 –4.5 –7.5 2.8 2.8 2.8 mV mV mV DCM Comparator Threshold in For ced CCM, MODE =0V VISN = 80V, To Enter DCM Mode, VISP – VISN Falling VISN = 12V, To Enter DCM Mode, VISP – VISN Falling VISN = 0V, To Enter DCM Mode, VISP – VISN Falling l l l –220 –220 –220 –300 –300 –300 –380 –380 –380 mV mV mV Oscillator Switching Frequency, f OSC RT = 46.4k RT = 357k l l 640 750 100 860 115 kHz kHz Switching Frequency in Foldback Compared to Normal fOSC 1/5 ratio Switching Frequency Range Free-Running or Synchronizing l 100 750 kHz SYNC High Level for Sync l 1.5 V SYNC Low Level for Sync l 0.4 V SYNC Clock Pulse Duty Cycle VSYNC = 0V to 3V 20 80 % Recommended Min SYNC Ratio fSYNC/fOSC elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications for each channel are at TA = 25°C. VIN = 12V, VEN/FBIN = 12V, VBIAS = 12V, unless otherwise noted (Note 2).

8710fFor more information www.linear .com/L T8710 PARAMETER CONDITIONS MIN TYP MAX UNITS Gate Drivers, BG and TG BG Rise Time CBG = 3300pF (Note 3) 24 ns BG Fall Time CBG = 3300pF (Note 3) 21 ns TG Rise Time CTG = 3300pF (Note 3) 15 ns TG Fall Time CTG = 3300pF (Note 3) 16 ns BG and TG Non-Overlap Time TG Rising to BG Rising, CBG = CTG = 3300pF (Note 3) BG Falling to TG Falling, CBG = CTG = 3300pF (Note 3) 140 220 150 ns ns BG Minimum On-T ime CBG = CTG = 3300pF 150 420 ns BG Minimum Off-Time CBG = CTG = 3300pF 100 480 ns TG Minimum On-Time CBG = CTG = 3300pF 0 150 ns TG Minimum Off-Time CBG = CTG = 3300pF 290 770 ns C/10 and Power Good Indicators, FLAG FLAG C/10 Indicator Threshold V ISP – VISN Falling, VFBX = 1.215V VISP – VISN Rising, VFBX = 1.215V l l mV mV FLAG C/10 Indicator Hysteresis 5 mV FLAG Power Good Threshold for Positive FBX V oltage VFBX Rising, VISP – VISN = 0V VFBX Falling, VISP – VISN = 0V l l 1.127 1.062 1.153 1.095 1.184 1.126 V V FLAG Power Good Threshold for Negative FBX V oltage VFBX Falling, VISP – VISN = 0V VFBX Rising, VISP – VISN = 0V l l 103 68.5 126 152 mV mV FLAG Power Good Hysteresis for Positive or Negative FBX V oltage 58 mV FLAG Anti-Glitch Delay from C/10 or Power Good Threshold T rip to FLAG Toggle 100 µs FLAG Output V oltage Low 100µA into FLAG Pin l 9 50 mV FLAG Leakage Current VFLAG = 7V, FLAG Off 0.01 1 µA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT8710E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LT8710I is guaranteed over the full –40°C to 125°C operating junction temperature range. Note 3: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation over the specified maximum operating junction temperature may impair device reliability. Note 5: Do not apply a positive or negative voltage or current source to the BG, TG, and INTV EE pins, otherwise permanent damage may occur. elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications for each channel are at TA = 25°C. VIN = 12V, VEN/FBIN = 12V, VBIAS = 12V, unless otherwise noted (Note 2).

8710f For more information www.linear .com/L T8710 Positive and Negative Output Voltage Regulation (FBX) Positive and Negative FBX Current at Output Voltage Regulation Input Voltage Regulation (EN/FBIN) Input Voltage Regulation vs FBX (EN/FBIN) Output Current Sense Regulation Voltage (ISP-ISN and IMON) Output Current Sense Regulation Voltage vs FBX (ISP-ISN and IMON) Max Current Limit vs Duty Cycle (CSP - CSN) Max Current Limit vs Temperature at Min DC (CSP - CSN) Max Current Limit vs SS (CSP - CSN) Typical perForMance characTerisTics TA = 25°C, unless otherwise noted. DUTY CYCLE (%) MAX POSITIVE CSP-CSN (mV) MAX NEGATIVE CSP-CSN (mV) –20 –30 –25 –40 –50 –35 –45 –55 –60 5020 70 80 90

8710 G01

fOSC = 300kHz TEMPERATURE (°C) –50 MAX POSITIVE CSP-CSN (mV) MAX NEGATIVE CSP-CSN (mV) –26 –30 –28 –34 –32 –36 –38 50–25 75 100

8710 G02

SS (V) 0.0 CSP-CSN (mV) 0.80.2 1 1.2 1.4

8710 G03

1.60.4 0.6 TEMPERATURE (°C) –50 EN/FBIN VOL TAGE (V) 1.63 1.61 1.62 1.60 1.59 1.58 1.57 –25 50 75 100

8710 G06

FBX (V) 0.6 EN/FBIN (V) 2.0 1.8 1.9 1.7 1.6 1.5 1.4 0.7 1 1.1 1.2

8710 G07

1.30.8 0.9 TEMPERATURE (°C) –50 POSITIVE FBX VOL TAGE (V) NEGATIVE FBX VOL TAGE (mV) 1.2225 1.2175 1.2200 1.2150 1.2125 1.2100 1.2075 15.0 10.0 12.5 7.5 5.0 2.5 –25 50 75 100

8710 G04

TEMPERATURE (°C) –50 POSITIVE FBX CURRENT INTO PIN (µA) NEGATIVE FBX CURRENT OUT OF PIN (µA)86 –25 50 75 100

8710 G05

TEMPERATURE (°C) –50 AVERAGE ISP-ISN (mV) IMON (V) 57.5 52.5 55.0 50.0 47.5 45.0 42.5 1.2175 1.2125 1.2150 1.2100 1.2075 1.2050 1.2025 –25 50 75 100

8710 G08

FBX (V) 0.6 AVERAGE ISP-ISN (mV) IMON (V) 1.30 1.20 1.25 1.15 1.10 1.05 1.00 0.7 1 1.1 1.2

8710 G09

1.30.8 0.9 IMON AVE ISP-ISN

8710fFor more information www.linear .com/L T8710 MODE Forced CCM Thresholds EN/FBIN Chip Enable and Active Mode Thresholds EN/FBIN Pin Current Oscillator Frequency vs Temperature Oscillator Frequency During Soft-Start BG and TG T ransition Time DCM Thresholds (ISP-ISN) Power Good Thresholds (FBX) C/10 Thresholds (ISP-ISN) Typical perForMance characTerisTics TA = 25°C, unless otherwise noted. TEMPERATURE (°C) –50 POSITIVE FBX (V) NEGATIVE FBX (V) 1.16 1.14 1.15 1.13 1.12 1.11 1.10 1.09 1.08 140 120 130 110 100 –25 50 75 100

8710 G11

EN/FBIN VOL TAGE (V) EN/FBIN PIN CURRENT (µA) 0.25 1 1.25 1.5 1.75

8710 G15

20.5 0.75 –40°C 25°C 125°C FBX VOL TAGE (V) NORMALIZED OSCILLATOR FREQUENCY (FSW/FNOM) 0.2 0.8 1 1.2

8710 G17

0.4 0.6 NONINVERTING CONFIGURATIONS INVERTING CONFIGURATIONS TEMPERATURE (°C) –50 fOSC (kHz) 900 800 700 500 400 200 100 600 300 –25 50 75 100 125

8710 G16

RT = 46.4k/uni03A9 RT = 357k/uni03A9 TEMPERATURE (°C) –50 ISP-ISN (mV) ISP-ISN (mV) –280 –300 –290 –310 –320 –330 –340 –25 50 75 100

8710 G10

MODE = 0V , FCM MODE = 2V , DCM TEMPERATURE (°C) –50 AVERAGE ISP-ISN (mV) –25 50 75 100

8710 G12

CAP LOAD (nF) TRANSITION TIME (ns) 2 8 10

8710 G18

TEMPERATURE (°C) –50 MODE (V) 1.24 1.22 1.23 1.21 1.20 1.18 1.17 1.19 1.16 1.15 1.14 –25 50 75 100

8710 G13

FALLING, ENTER FCM RISING, EXIT FCM TEMPERATURE (°C) –50 EN/FBIN CHIP ENABLE (V) EN/FBIN ACTIVE MODE (V) 1.40 1.36 1.38 1.34 1.32 1.28 1.26 1.30 1.24 1.22 1.20 1.75 1.71 1.73 1.69 1.67 1.63 1.61 1.59 1.57 1.65 1.55 –25 50 75 100

8710 G14

8710f For more information www.linear .com/L T8710 INTVCC Current Limit vs VIN or BIAS INTVCC Dropout from VIN or BIAS INTVEE vs Temperature INTVEE UVLO vs Temperature INTVEE Current Limit vs BIAS INTVEE Dropout (BIAS = 6V) Minimum Operating Input Voltage INTV CC vs Temperature INTVCC UVLO vs Temperature Typical perForMance characTerisTics TA = 25°C, unless otherwise noted. TEMPERATURE (°C) –50 VIN OR VBIAS (V) 4.35 4.33 4.29 4.25 4.23 4.21 4.19 4.17 4.31 4.27 4.15 –25 75 100 125

8710 G19

TEMPERATURE (°C) –50 INTVCC (V) 6.40 6.28 6.24 6.36 6.32 6.20 –25 75 100 125

8710 G20

IINTVCC = 10mA TEMPERATURE (°C) –50 INTVCC (V) 4.2 3.9 3.8 3.7 3.6 4.1 4.0 3.5 –25 75 100 125

8710 G21

INPUT VOL TAGE (V) INTVCC CURRENT LIMIT (mA) 150 100 125 20 60 70 80

8710 G22

INTVCC > 3.5V INTVCC > 3.5V INTVCC < 3.5V INTVCC LOAD CURRENT (mA) 10 0 INPUT - INTVCC (V) 500 400 350 300 250 450 200 20 60 70 80

8710 G23

TEMPERATURE (°C) –25 –50 BIAS - INTVEE (V) 3.6 3.4 3.3 3.2 3.1 3.5 3.0 0 100 125

8710 G25

BIAS (V) 20 10 INTVEE CURRENT LIMIT (mA) 30 70 80

8710 G26

BIAS - INTVEE = 5V INTVEE LOAD CURRENT (mA) 10 0 INTVEE (V) 1.2 1.0 0.9 0.7 0.6 0.5 0.8 1.1 0.4 40 50

8710 G27

–40°C 25°C 125°C TEMPERATURE (°C) –25 –50 BIAS - INTVEE (V) 6.28 6.20 6.16 6.12 6.24 6.08 0 100 125

8710 G24

IINTVEE = 10mA

8710fFor more information www.linear .com/L T8710 pin FuncTions FBX (Pin 1): Positive and Negative Feedback Pin. For a boost, SEPIC, or inverting converter, tie a resistor from the FBX pin to VOUT according to the following equations: RFBX = VOUT –1.213V 83.7µA ; Boost or SEPIC Converter RFBX = |VOUT |+9.6mV 83.1µA ; Inverting Converter VC (Pin 2): Error Amplifier Output Pin. Tie external com- pensation network to this pin. SS ( Pin 3): Soft-Start Pin. Place a soft-start capacitor here that is greater than 5x the IMON capacitor. Upon start-up, the SS pin will be charged by a (nominally) 260k resistor to ~2.7V. During a current overload as seen by ISP - ISN, overtemperature, or UVLO condition, the SS pin will be quickly discharged to reset the part. Once those conditions are clear, the part will attempt to restart. FLAG (Pin 4): Power Good or C/10 Indication Pin. The FLAG pin functions as an active high power good pin if C/10 is true. Alternatively, the FLAG pin functions as an active high C/10 indication pin if power is good. Power is good when FBX < 68.5mV or FBX > 1.153V and has 58mV of hysteresis. When FBX = 1.153V, it’s 5% below regulation which corresponds to ~10% below regulation on V OUT (for V OUT > 8V). Active high C/10 indication is when the charge current seen by the ISP and ISN pins is less than 10% of full current (VISP – VISN < 5mV) as the charge current decreases. For increasing charge currents, the C/10 threshold has to reach 20% of full current (VISP – VISN > 10mV). The C/10 indication can be used to set the bulk and float voltage when charging a battery. For either C/10 or power good indicators, there is a 100µs anti-glitch delay. A pull-up resistor or some other form of pull-up network needs to exist on this pin to use these features. See the Block Diagram and Applications section for more information. IMON (Pin 5): Output Current Sense Monitor Output Pin. Outputs a voltage that is proportional to the voltage seen across the ISP and ISN pins. VIMON = 11.9 • (VISP – ISN + 51.8mV) Since the voltage across the ISP and ISN pins is AC, a filtering capacitor is needed on the IMON pin to average out the ISP and ISN voltage. Recommended capacitor value is 10nF to 100nF. A 51.8mV offset is added to the amplifier, so when the average ISP – ISN voltage is 0V, the IMON voltage is 616mV. When the average voltage across the ISP and ISN pins is 50mV, the IMON pin will output 1.213V. Do not resistively load down this pin. ISN, ISP (Pins 6, 7): Output Current Sense Negative and Positive Input Pins Respectively. Kelvin connect ISN and ISP pins to a sense resistor to limit the output current. The commanded NFET current will limit the voltage difference across the sense resistor to 50mV. BIAS (Pin 8): Alternate Input Supply and PFET Bias Pin. Must be locally bypassed. The BIAS pin sets the top rail for the TG gate driver. Must connect to the converter’s V OUT for a positive output voltage or INTV CC for a converter’s negative output voltage. INTVEE (Pin 9): 6.18V-Below-BIAS Regulator Pin. Must be locally bypassed with a minimum capacitance of 2.2µF to BIAS. This pin sets the bottom rail for the TG gate driver. The TG gate driver can begin switching when BIAS – INTV EE exceeds 3.42V (typical). Connect pin to ground for an inverting converter. TG (Pin 10): PFET Gate Drive Pin. Low and high levels are BIAS – INTVEE and BIAS respectively. BG (Pin 11): NFET Gate Drive Pin. Low and high levels are GND and INTVCC respectively. INTVCC (Pin 12): 6.3V Dual Input LDO Regulator Pin. Must be locally bypassed with a minimum capacitance of 2.2µF to GND. Logic will choose to run INTVCC from the VIN or BIAS pins. A maximum 5mA external load can connect to the INTVCC pin. The undervoltage lockout on INTVCC is 4V (typical). The BG gate driver can begin switching when INTVCC exceeds 4V (typical). VIN (Pin 13): Input Supply Pin. Must be locally bypassed. Can run down to 0V as long as BIAS > 4.5V. CSN, CSP (Pins 14, 15): NFET Current Sense Negative and Positive Input Pins Respectively. Kelvin connect these pins to a sense resistor to limit the NFET switch current. The maximum sense voltage at low duty cycle is 50mV. EN/FBIN (Pin 16): Enable and Input Voltage Regulation Pin. In conjunction with the UVLO (undervoltage lockout) circuit, this pin is used to enable/disable the chip and restart the soft-start sequence. The EN/FBIN pin is also

Diagram and Applications section for more information. the part will operate in DCM at light load. ground to set the frequency to a fixed free-running level. the Applications Information section for more information. soldered directly to local ground plane. Figure 1. Block Diagram

• L2 LDO LOGIC LDO UVLO 1.213V REFERENCE EN/FBIN LOGIC IMON 1.38V– DIE TEMP 175°C 1.153V 68.5mV 1.213V 1.224V +1.8V +50mV FBX DCM_EN 260k DRIVER DISABLECSS RIN1 FREQUENCY FOLDBACK SR1 RS Q 14.5k 14.5k 1.213V 11.9k 51.8mV EA4 – EA3 – +A6 +– CIMON CFCC LDO CVEE RFBX COUT VOUT R1 D1

Figure 2. State Diagram

• ALL SWITCHES DISABLED CHIP OFF
• SS PULLED LOW
• INTVCC CHARGES UP INITIALIZE
• SS SLOWLY CHARGES UP
• V C PULLED LOW ACTIVE MODE
• PFET TURNS OFF FOR REMAINDER OF CYCLE IF ISP-ISN VOLTAGE FALLS BELOW 2.8mV (TYP)
• FOR VERY LIGHT LOAD, PART MAY SKIP PULSES DCM AT LIGHT LOAD
• VC COMMANDS PEAK INDUCTOR CURRENT TO MAINTAIN REGULATION REGULATION
• OUTPUT CURRENT LIMITED TO 25mV (TYP) AVERAGE ACROSS THE ISP-ISN PINS OUTPUT CURRENT FOLDBACK
• BG AND TG SWITCH AT CONSTANT FREQUENCY
• INDUCTOR CURRENT CAN REVERSE
• IF ISP-ISN VOLTAGE GOES BELOW –300mV (TYP), PFET TURNS OFF SO INDUCTOR CURRENT GOES MORE POSITIVE FORCED CCM OPERATION
• SS DISCHARGES QUICKLY
• SWITCHER DISABLED EN/FBIN < 1.3V (TYP) OR V IN AND BIAS < 4.5V (MAX) 1.3V < EN/FBIN < 1.7V (TYP) AND VIN OR BIAS > 4.5V EN/FBIN > 1.7V AND VIN OR BIAS > 4.5V AND INTVCC > 4V (TYP) INTVEE REGULATOR IN UVLO AND SS > 1.8V (TYP) MODE < 1.175V (TYP) AND SS > 1.8V (TYP) MODE > 1.224V (TYP) SS < 50mV RESET RESET DETECTED
• NO RESET CONDITIONS DETECTED RESET OVER RESET RESET
• NFET BEGINS SWITCHING
• PFET STARTS SWITCHING WHEN INTV EE REGULATOR IS OUT OF UVLO BEGIN SWITCHING RESET RESET RESET REGULATION = OUTPUT VOLTAGE (FBX) INPUT VOLTAGE (EN/FBIN) OUTPUT CURRENT (ISP-ISN AND IMON) RESET = UVLO ON VIN OR BIAS ( < 4.5V (MAX)) UVLO ON INTVCC ( < 4V (TYP)) EN/FBIN < 1.7V (TYP) AT 1ST POWER-UP EN/FBIN < 1.26V (TYP) AFTER ACTIVE MODE SET OVERCURRENT (ISP – ISN > 63.6mV AVERAGE (TYP)) OVERTEMPERATURE (T J > 175°C (TYP))

illustrates the different EN/FBIN voltage thresholds. section for more information. pin to avoid start-up issues. Figure 3. EN/FBIN Modes of Operation

8710 F03

8710fFor more information www.linear .com/L T8710 Frequency Foldback The frequency foldback circuitry reduces the switching frequency when 175mV < FBX < 1.01V (typical). This feature lowers the minimum duty cycle that the part can achieve, thus allowing better control of the inductor current at start-up. When the FBX voltage is pulled outside of this range, the switching frequency returns to normal. If the part is configured to be in forced continuous conduction mode (MODE pin is driven below 1.175V), then the frequency foldback circuitry is disabled as long as INTV EE is not in UVLO and the SS pin is higher than the SS Hi threshold. Note that the peak inductor current at start-up is a function of many variables including load profile, output capacitance, target VOUT, VIN, switching frequency, etc. OPERATION – REGULATION Use the Block Diagram when stepping through the following description of the LT8710 operating in regulation. Also, assume the converter’s load current is high enough such that the part is operating in synchronous switching. The LT8710 has three modes of regulation: 1. Output V oltage (via FBX pin) 2. Input V oltage (via EN/FBIN pin) 3. Output Current (via ISP, ISN, and IMON pins) All three of these regulation loops control the peak com- manded current through the external NFET, MN. This operation is the same regardless of the regulation mode, so that will be described first. At the start of each oscillator cycle, the SR latch (SR1) is set, which first turns off the external PFET, MP, and then turns on the external NFET, MN. The NFET’s source current flows through an external current sense resistor (RSENSE1) generating a voltage proportional to the NFET switch current. This voltage is then amplified by A5 and added to a stabilizing ramp. The resulting sum is fed into the positive terminal of the PWM comparator A7. When the voltage on the positive input of A7 exceeds the voltage on the negative input (VC pin), the SR latch is reset, turning off the NFET and then turning on the PFET. The voltage on the VC pin is controlled by one of the regulation loops, or a combination of regulation loops. For simplicity, each mode of regulation will be described independently so that only one of the modes of regulation is in command of the LT8710. Output Voltage Regulation A single external resistor is used to set the target output voltage. See the Pin Functions section for selecting the feedback resistor for a desired output voltage. The V C pin voltage (negative input of A7) is set by EA1 (or EA2), which is simply an amplified difference between the FBX pin voltage and the reference voltage (1.213V if the LT8710 is configured as a noninverting converter or 9.6mV if configured as an inverting converter). In this manner, the FBX error amplifier sets the correct peak current level to maintain output voltage regulation. Input Voltage Regulation A single resistor or resistor divider from the EN/FBIN pin to the converter’s input voltage sets the input voltage regulation. It is recommended to use a resistor divider for improved accuracy as described in the Setting the Input Voltage Regulation or Undervoltage Lockout section. The EN/FBIN pin voltage connects to the positive input of amplifier EA4. The VC pin voltage is set by EA4, which is simply an amplified difference between the EN/FBIN pin voltage and a 1.607V reference voltage. In this manner, the EN/FBIN error amplifier sets the correct peak current level to maintain input voltage regulation. Output Current Regulation An external sense resistor connected between the ISP and ISN pins (RSENSE2) sets the maximum output current of the converter when placed in the source of the PFET, MP. A built-in 51.8mV offset is added to the voltage seen across RSENSE2. That voltage is then amplified and outputs to the IMON pin. An external capacitor must be placed from IMON to ground to filter the amplified chopped voltage that’s sensed across RSENSE2. The voltage at the IMON pin is fed to the negative input of the IMON error amplifier, EA3. The VC pin voltage is set by EA3, which is simply an amplified difference between the IMON pin voltage and the 1.213V reference voltage. In this manner, the IMON error amplifier sets the correct peak current level to maintain output current regulation. operaTion

current to about half of its set limit.

• MODE < 1.175V (typical) = For ced CCM or FCM
• MODE > 1.224V (typical) = DCM or Pulse-Skipping The forced continuous mode (FCM) allows the inductor current to reverse directions without any switches being forced off. At very light load currents, the inductor cur - rent will swing positive and negative as the appropriate average current is delivered to the output. There are some exceptions that negate the MODE pin and force the part to operate in DCM at light loads: 1. The INTVEE LDO is in UVLO (BIAS – INTVEE < 3.42V typical). 2. SS < 1.8V (typical). 3. The part is in a reset condition. When the LT8710 is in discontinuous mode (DCM), syn- chronous switch MP is held off whenever MP’s current falls near 0 current (less than 2.8mV (typical) across RSENSE2). This is to prevent current draw from the output and/or feeding current to the input supply. Under very light loads, the current comparator A7, may also remain tripped for several cycles (i.e. skipping pulses). Since MP is held off during the skipped pulses, the inductor current will not reverse. OPERATION – C/10 AND POWER GOOD (FLAG PIN) The FLAG pin is an open-drain pin that functions as an ac- tive high C/10 and power good pin. The FLAG pin changes states 100µs (typical) after the internal comparators tell the FLAG pin to change states to reject glitches or tran - sient events. operaTion

Figure 4. Synchronous Switching

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8710fFor more information www.linear .com/L T8710 C/10 Indication If power is good, then the FLAG pin will function as an active high C/10 indication pin. C/10 is when the charging current (output current) has dropped to 1/10 its maximum and is useful in battery charging applications. The C/10 comparator monitors the voltage at the IMON pin, and when the average ISP-ISN voltage drops below 5mV (typical), the FLAG pin pull-down device is turned off, and the FLAG pin voltage is allowed to pull high. The FLAG pin will pull low again if the average ISP-ISN voltage rises above 10mV (typical). The IMON voltage corresponding to 5mV and 10mV on ISP – ISN is 666.5mV and 727.5mV respectively. Note that if the LT8710 is set to operate in FCM (MODE pin low), then the C/10 comparator is disabled and the FLAG pin operates only as a power good pin. See the Ap- plications section for more information. Power Good Indication If C/10 is detected (average ISP-ISN < 5mV typical), then the FLAG pin functions as an active high power good (PG) pin. Power is good when the FBX voltage is greater than 95% of its regulation target, which corresponds to ~90% of the VOUT regulation target (for VOUT > ~8V). This corresponds to FBX > 1.153V (typical) for noninverting converters and FBX < 68.5mV (typical) for inverting converters. The PG comparators have 58mV of hysteresis to reject glitches. OPERATION – LDO REGULATORS (INTVCC AND INTVEE) The INTVCC LDO regulates at 6.3V (typical) and is used as the top rail for the BG gate driver. The INTVCC LDO can run from V IN or BIAS and will intelligently select to run from the best for minimizing power loss in the chip, but at the same time, select the proper input for maintaining INTVCC as close to 6.3V as possible. The INTVCC regulator also has safety features to limit the power dissipation in the internal pass device and also to prevent it from dam- age if the pin is shorted to ground. The UVLO threshold on INTVCC is 4V (typical), and the LT8710 will be in reset until the LDO comes out of UVLO. The INTVEE regulator regulates to 6.18V (typical) below the BIAS pin voltage. The BIAS and INTV EE voltages are used for the top and bottom rails of the TG gate driver respectively. Just like the INTV CC regulator, the INTV EE regulator has a safety feature to limit the power dissipation in the internal pass device. The TG pin can begin switch- ing after the INTVEE regulator comes out of UVLO (3.42V typical across the BIAS and INTVEE pins) and the part is not in a reset condition. operaTion

Figure 5. Boost Converter – The Component Values Given are Typical Values for a 400kHz, 4.5V to 9V to 12V/6A Boost. Figure 5. This topology generates a positive output voltage where the input voltage is lower than the output voltage. A single feedback resistor sets the output voltage. on the design equations presented in Table 1. Table 1. Boost Design Equations Performance Characteristics to find VCSPN at DCMAX.

• (1– DCMAX ) Step 5: RSENSE2 RSENSE2 ≤ 0.05 1.6 • IOUT Step 6: L LTYP = RSENSE1 •VIN(MIN) 12.5m•f • 1– VIN(MIN) VOUT (1) LMIN = RSENSE1 •VOUT 40m•f • 1– VIN(MIN) VOUT – VIN(MIN) (2) LMAX1 = RSENSE1 •VIN(MIN) 5m•f • 1– VIN(MIN) VOUT (3) LMAX2 = RSENSE1 •VIN(MAX) 5m•f • 1– VIN(MAX) VOUT (4)
• Solve equations 1 to 4 for a range of L values.
• The minimum value of the L range is the higher of LTYP and LMIN. The maximum of the L value range is the lower of LMAX1 and LMAX2. Step 7: COUT COUT ≥ IOUT •DCMAX f •0.005• VOUT Step 8: CIN CIN ≥ DCMAX 8 •L • f2 • 0.005 Step 9: CIMON CIMON ≥ 100µ •DCMAX 0.005• f Step 10: RFBX RFBX = VOUT –1.213V 83.7µA Step 11: RT RT = 35,880 f –1; f in kHz andR T in kΩ NOTE: The final values for COUT and CIN may deviate from the above equations in order to obtain desired load transient performance for a particular application. The COUT and CIN equations assume zero ESR, so increase the capacitance accordingly based on the combined ESR. IMON SSGND CSP TGCSNBG L T8710

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Figure 6. SEPIC Converter – The Component Values Given Are Figure 6. This topology generates a positive output volt- between the input and output due to capacitor C1. on the design equations presented in Table 2. Table 2. SEPIC Design Equations Performance Characteristics to find VCSPN at DCMAX.

• (1–DCMAX ) Step 5: RSENSE2 RSENSE2 ≤ 0.05 1.6 •IOUT Step 6: L LTYP = RSENSE1 •VOUT 12.5m•f • VIN(MIN) VIN(MIN) + VOUT (1) LMIN = RSENSE1 •VOUT 40m•f • 1– VIN(MIN) VOUT    (2) LMAX = RSENSE1 •VOUT 5m•f • VIN(MIN) VIN(MIN) + VOUT (3)
• Solve equations 1, 2, and 3 for a range of L values.
• The minimum value of the L range is the higher of LTYP and LMIN. The maximum of the L value range is LMAX.
• L = L1 = L2 for coupled inductors.
• L = L1 || L2 for uncoupled inductors. Step 7: C1 C1≥10µF TYPICAL( );VRATING> VIN Step 8: COUT COUT ≥ IOUT •DCMAX f •0.005• VOUT Step 9: CIN CIN ≥ DCMAX 8 •L • f2 • 0.005 Step 10: CIMON CIMON ≥ 100µ •DCMAX 0.005• f Step 11: RFBX RFBX = VOUT –1.213V 83.7µA Step 12: RT RT = 35,880 f –1; f in kHz andR T in kΩ NOTE: The final values for COUT and CIN may deviate from the above equations in order to obtain desired load transient performance for a particular application. The COUT and CIN equations assume zero ESR, so increase the capacitance accordingly based on the combined ESR.

Figure 7. Dual Inductor Inverting Converter – The Component –5V/7A Inverting Topology Using Coupled Inductors. inherently built into this topology due to the capacitor C1. information on the design equations presented in Table 3. Table 3. Dual Inductor Inverting Design Equations Performance Characteristics to find VCSPN at DCMAX.

• (1–DCMAX) Step 5: RSENSE2 RSENSE2 ≤ 0.05 1.6 •IOUT Step 6: L LTYP = RSENSE1 •| VOUT | 12.5m•f • VIN(MIN) VIN(MIN)+ |VOUT | (1) LMIN = RSENSE1 •|VOUT | 40m•f • 1– VIN(MIN) VOUT    (2) LMAX = RSENSE1 •|VOUT| 5m•f • VIN(MIN) VIN(MIN)+ |VOUT | (3)
• Solve equations 1, 2, and 3 for a range of L values.
• The minimum value of the L range is the higher of LTYP and LMIN. The maximum of the L value range is LMAX.
• L = L1 = L2 for coupled inductors.
• L = L1 || L2 for uncoupled inductors. Step 7: C1 C1≥10µF TYPICAL( );VRATING> VIN+|VOUT| Step 8: COUT COUT ≥ 1 8 •f2•0.005 • VIN(MAX) VIN(MAX) + |VOUT | Step 9: CIN CIN ≥ DCMAX 8 •L • f2 • 0.005 Step 10: CIMON CIMON ≥ 100µ •DCMAX 0.005• f Step 11: RFBX RFBX = |VOUT |+9. 6mV 83.1µA Step 12: RT RT = 35,880 f –1; f in kHz andR T in kΩ NOTE: The final values for COUT and CIN may deviate from the above equations in order to obtain desired load transient performance for a particular application. The COUT and CIN equations assume zero ESR, so increase the capacitance accordingly based on the combined ESR. IMON SSGND CSP TGCSNBG L T8710

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regulation voltage and current. MODE pin high to prevent reverse current flow. much higher than the EN/FBIN pin current. Figure 8. Configurable UVLO lockout if the LT8710 is NOT in forced continuous mode. will not be accompanied by a soft-start. from the input voltage regulation control loop. be regulated such that the EN/FBIN voltage is at ~1.607V. can be used to monitor and/or limit the output current. The current monitor circuit works as shown in Figure 9. guidelines in the next couple sections.

the output current is limited to about half its set point. Figure 9. Output Current Monitor and Control

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the resistor connected between the FLAG and FBX pins. Figure 10. FLAG Pin Connections and Equations

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• R1• R1+RNTC(T(MAX)) – 1 R1+RNTC(T(MIN))   R1+RNTC(T(MAX)) – 1 R1+RNTC(T(MIN))   1=R RNTC(25) 6.3–1.213V 1.213V 2 = –6.3V ∆VOUT
• RFBX • •RR 1

Specified at two temperatures such as b25/85. appropriate for the application.

• 1–DCMAX( ) • 1– iRIPPLE   where η = Converter efficiency (assume ~90%) VCSPN = Max current limit voltage (see Max Current Limit vs Duty Cycle (CSP-CSN) plot in the Typical Per formance Characteristics) IOUT = Converter load current DCMAX = Switching duty cycle at minimum VIN (see Power Switch Duty Cycle in Appendix) iRIPPLE = Peak-to -peak inductor ripple current percent- age at minimum VIN (recommended to use 25%) REVERSE CURRENT APPLICA TIONS (MODE PIN LOW) When the forced continuous mode is selected (MODE pin low), inductor current is allowed to reverse directions and flow from the VOUT side to the VIN side. This can lead to current sinking from the output and being forced into the input. The reverse current is at a maximum magnitude when VC is lowest. The graph of Max Current Limit vs Duty Cycle (CSP – CSN) in the Typical Performance Character- istics section can help to determine the maximum reverse current capability. The IMON pin voltage will indicate negative inductor cur- rents. Refer to the equation for IMON in the Pin Functions. Note that the IMON voltage is only accurate if the dynamic voltage across RSENSE2 stays within –51.8mV to 500mV. If the valley inductor current goes more negative than –300mV as sensed by RSENSE2, the external PFET will turn off, and the inductor current will start going more positive. applicaTions inForMaTion SWITCH CURRENT LIMIT (RSENSE1 AND CSP-CSN PINS) The external current sense resistor (R SENSE1) sets the maximum peak current though the external NFET switch (MN). The maximum voltage across R SENSE1 is 50mV (typical) at very low switch duty cycles, and then slope compensation decreases the current limit as the duty cycle increases (see the Max Current Limit vs Duty Cycle (CSP- CSN) plot in the Typical Performance Characteristics). The equation below gives the switch current limit for a given duty cycle and current sense resistor (find V CSPN at the operating duty cycle in the plot mentioned). ISW(LIMIT)= VCSPN RSENSE1

Figure 11. Temperature Dependent Output Using an NTC

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VIN to go above the OVP point. Figure 12. Backup Power Converter Figure 13. Input Overvoltage Protection in the linear mode of operation with only 4V of gate drive.

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8710f For more information www.linear .com/L T8710 The RC product should be kept less than 30ns, which is simply the total series R (5.1Ω+5.1Ω in this case) times the equivalent capacitance seen across the sense pins (2.2nF for Figure 14a and 2.35nF for Figure 14b). SWITCHING FREQUENCY The LT8710 uses a constant frequency architecture between 100kHz and 750kHz. The frequency can be set using the internal oscillator or can be synchronized to an external clock source. Selection of the switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. For high power applications, consider operating at lower frequencies to minimize MOSFET heating from switching losses. The switching frequency can be set by placing an appropriate resistor from the RT pin to ground and tying the SYNC pin low. The frequency can also be synchronized to an external clock source driven into the SYNC pin. The following sections provide more details. Oscillator Timing Resistor (RT) The operating frequency of the LT8710 can be set by the internal free-running oscillator. When the SYNC pin is driven low (< 0.4V), the frequency of operation is set by a resistor from the RT pin to ground. The oscillator frequency is calculated using the following formula: f =35,880 RT +1( ) where f is in kHz and RT is in k. Conversely, RT (in k) can be calculated from the desired frequency (in kHz) using: RT = 35,880 f –1 Clock Synchronization An external source can set the operating frequency of the LT8710 by providing a digital clock signal into the SYNC pin (RT resistor still required). The LT8710 will operate at the SYNC clock frequency. The LT8710 will revert to its internal free-running oscillator clock when the SYNC pin is driven below 0.4V for a few free-running clock periods. Driving SYNC high for an extended period of time effec - tively stops the operating clock and prevents latch SR1 from becoming set (see Block Diagram). As a result, the switching operation of the LT8710 will stop. The duty cycle of the SYNC signal must be between 20% and 80% for proper operation. Also, the frequency of the SYNC signal must meet the following two criteria: 1. SYNC may not toggle outside the frequency range of 100kHz to 750kHz unless it is stopped below 0.4V to enable the free-running oscillator. 2. The SYNC frequency can always be higher than the free-running oscillator frequency (as set by the R T resistor), f OSC, but should not be less than 25% below fOSC. After SYNC begins toggling, it is recommended that switch- ing activity is stopped before the SYNC pin stops toggling. Excess negative inductor current can result when SYNC stops toggling as the LT8710 transitions from the external SYNC clock source to the internal free-running oscillator clock. Switching activity can be stopped by driving the EN/FBIN pin low. LDO REGULATORS The LT8710 has two linear regulators to run the BG and TG gate drivers. The INTVCC LDO regulates 6.3V (typical) above ground, and the INTVEE regulator regulates 6.18V (typical) below the BIAS pin. INTVCC LDO Regulator The INTVCC LDO is used as the top rail for the BG gate driver for positive output converters. In the case of a nega- tive output converter, the INTVCC LDO is used as the top rail for both the BG and TG gate drivers (BIAS and INTVEE must tie to INTV CC and GND respectively). An external capacitor greater than 2.2µF must be placed from the INTVCC pin to ground. The UVLO threshold on INTVCC is 4V (typical), and the LT8710 will be in reset until the LDO comes out of UVLO. The INTVCC LDO can run off V IN or BIAS and will intel- ligently select to run off the best for minimizing chip power loss, but at the same time, select the proper input for maintaining INTVCC as close to 6.3V as possible. For applicaTions inForMaTion

switching after the INTVEE regulator comes out of UVLO. the TG gate driver will have levels of 0V and 6.3V. to limit the maximum power in the INTV EE pass device. Performance Characteristics. tor section apply to the INTVEE regulator as well. Figure 15. INTVCC Input Voltage Selection regulating from VIN or BIAS. the current limit of the LDO drops to 0. improve efficiency and prevent overheating of the LT8710. keep the INTVCC current at a minimum.

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the INTVCC LDO is not needed and VIN stays above 4.5V.

• Place bypass capacitors for the VIN and BIAS pins (1µF or greater) as close as possible to the LT8710.
• Place bypass capacitors for the INTV CC and INTV EE (between BIAS and INTVEE) pins (2.2µF or greater) as close as possible to the LT8710.
• The load should connect directly to the positive and negative terminals of the output capacitor for best load regulation. Boost Topology Specific Layout Guidelines
• Keep length of loop (high speed switching path) govern- ing RSENSE1, MN, MP, RSENSE2, COUT, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. applicaTions inForMaTion

Figure 17. Suggested Component Placement for Boost Topology Figure 16. Simplified Schematic of a Non-Synchronous

• To optimize thermal performance, solder the exposed pad of the LT8710 to the ground plane with multiple vias around the pad connecting to additional ground planes.
• High speed switching path (see specific topology below for more information) must be kept as short as possible.
• The FBX, VC, IMON, and RT components should be placed as close to the LT8710 as possible, while being far away as practically possible from switching nodes. The ground for these components should be separated from the switch current path. IMONGND CSP TGCSNBG L T8710

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• Keep length of loop (high speed switching path) govern- ing RSENSE1, MN, C1, MP, RSENSE2, COUT, and ground return as short as possible to minimize parasitic induc- tive spikes at the switch node during switching. MN LT8710 CKT RSENSE1 RSENSE2

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Figure 18. Suggested Component Placement for SEPIC Topology Figure 19. Suggested Component Placement for Dual Inductor Figure 20. Suggested Routing and Connections of CSP/CSN

• Keep length of loop (high speed switching path) govern- ing RSENSE1, MN, C1, MP, RSENSE2, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. Current Sense Resistor Layout Guidelines Route the CSP/CSN and ISP/ISN lines differentially (close together) from the chip to the current sense resistor as shown in Figure 20.
• Place the vias that connect the CSP/CSN and ISP/ISN lines directly at the terminals of the current sense resis- tor as shown in Figure 20.

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8710f For more information www.linear .com/L T8710 applicaTions inForMaTion Power MOSFET Loss and Thermal Calculations The LT8710 requires two external power MOSFETs, an NFET switch for the BG gate driver and a PFET switch for the TG gate driver. Important parameters for estimating the power dissipation in the MOSFETs are: 1. On-resistance (RDSON) 2. Gate-to-drain charge (QGD) 3. PFET body diode forward voltage (VBD) 4. VDS of the FETs during their Off-Time 5. Switch current (ISW) 6. Switching frequency (f) The power loss in each power switch has a DC and AC term. The DC term is when the power switch is fully on, and the AC term is when the power switch is transitioning from on-off or off-on. The following applies for both the NFET and PFET power switches. For a boost application, the average current through the MOSFET (I SW) during its on-time, is the same as the average input current. The magnitude of the drain- to-source voltage, VDS, during its off-time is approximately VOUT. For a SEPIC or dual inductor inverting application, the average current through each MOSFET (I SW) during its on-time, is the sum of the average input current and the output current. The |V DS| voltage during the off-time is approximately VIN + |VOUT|. During the non-overlap time of the gate drivers, the peak and valley inductor current is flowing through the body diode of the PFET. Below are the equations for the power loss in MN and MP. P PMOSFET I 2R PSWI CH T ING PMN= IN2 •RDS N + +VDS •IN •f •tRF PRR – N PMP =IP2 •RDSO O N +VBD• IPK+ IVY 1.6 •f•140ns+PRR – P ISW = IOUT (1–DC); I PK =ISW+ iRIPPLE 2 ; I VY =ISW – iRIPPLE IN= DC • ISW 2 iRIPPLE2 IP = 1–DC( )•   +ISW 2 iRIPPLE2   PRR – N ≈ VDS •IRR •tRR •f P 2RR – P ≈ VDS •IRR •tRR •f where: f = Switching Frequency IN = NFET RMS Current IP = PFET RMS Current tRF = Average of the rise and fall times of the NFET’s drain voltage ISW = Average switch current during its on-time IPK = Peak inductor current IVY = Valley inductor current iRIPPLE = Inductor ripple current DC = Switch duty cycle (see Power Switch Duty Cycle section in Appendix) VBD = PFET body diode forward voltage at ISW VDS = Voltage across the FET when it’s off. VOUT for a boost, V IN + |V OUT| for a dual inductor inverting or SEPIC converter PRR-N = PFET body diode reverse recovery power loss in the NFET PRR-P = PFET body diode reverse recovery power loss in the PFET

8710fFor more information www.linear .com/L T8710 applicaTions inForMaTion IRR = Current needed to remove the PFET body diode charge tRR = Reverse recover y time of PFET body diode Typical values for tRF are 10ns to 40ns depending on the MOSFET capacitance and drain voltage. In general, the lower the QGD of the MOSFET, the faster the rise and fall times of its drain voltage. For best calculations, measure the rise and fall times in the application. PFET body diode reverse recovery power loss is depen - dent on many factors and can be difficult to quantify in an application. In general, this power loss increases with higher VDS and/or higher switching frequency. Chip Power and Thermal Calculations Power dissipation in the LT8710 chip comes from three primary sources: INTV CC and INTVEE LDOs providing gate drive to the BG and TG pins and additional input quiescent current. The average current through each LDO is deter- mined by the gate charge of the power switches, MN and MP, and the switching frequency. Below are the equations for calculating the chip power loss followed by examples. Noninverting Converter: The INTVCC LDO primarily sup- plies voltage for the BG gate driver. The BIAS and INTVEE voltages supply the top and bottom rails of the TG gate driver respectively. The chip Q current comes from the higher of VIN and BIAS. Below are the chip power equa- tions for a noninverting converter: PVCC = 1.04 • QMN • f • VSELECT PVEE1 = QMP • f • VBIAS PVEE2 = 3.1mA • (1 – DC) • VBIAS PQ = 4mA • VMAX where: f = Switching frequency DC = Switch duty cycle (see Power Switch Duty Cycle section in Appendix) QMN = Total gate charge of NFET power switch (MN) at 6.3VGS QMP = Total gate charge of PFET power switch (MP) at 6.18VSG VSELECT = INTVCC LDO selected input voltage, V IN or BIAS (see LDO REGULA TORS section) VMAX = Higher of VIN and BIAS. Inverting Converter: Due to BIAS connecting to INTVCC and INTVEE connecting to ground (see Typical Applica- tions), all the chip power comes from the VIN pin. The INTVCC LDO primarily supplies voltage for both the BG and TG gate drivers. The chip Q current comes from VIN. For consistency, the power that’s needed to run the TG gate driver is still labeled as PVEE even though the power is coming from INTVCC. Below are the chip power equations for an inverting converter: PVCC = 1.04 • QMN • f • VIN PVEE1 = QMP • f • VIN PVEE2 = 3.15mA • (1 – DC) • VIN PQ = 5.5mA • VIN where: f = Switching frequency DC = Switch duty cycle (see Power Switch Duty Cycle section in Appendix) QMN = Total gate charge of NFET power switch (MN) at 6.3VGS QMP = Total gate charge of PFET power switch (MP) at 6.3VSG Chip Power Calculations Example Table 4 calculates the power dissipation of the LT8710 for a 200kHz, 3V – 40V to 5V SEPIC application when VIN is 12V. From PCHIP in Table 4, the die junction temperature can be calculated using the appropriate thermal resistance and worst-case ambient temperature: TJ = TA + QJA • PCHIP where TJ = die junction temperature, T A = ambient tem- perature and θJA is the thermal resistance from the silicon junction to the ambient air. The published θ JA value is 38°C/W for the TSSOP exposed pad package. In practice, lower θJA values are realizable if board layout is performed with appropriate grounding

Table 4. Power Calculations Example for a 200kHz, 3V to 40V to 5V/5A SEPIC (VIN = 12V, MN = FDMS86500L and MP = SUD50P06-15) suggestions in the Layout Guidelines section. reset when the die temperature drops by ~5°C (typical).

• 100% where TP is the clock period and MinOffTime (found in the Electrical Characteristics) is a maximum of 480ns. Conversely, the external power NFET (MN in the Block Diagram) cannot remain off for 100% of each clock cycle, and will turn on for a minimum on time (MinOnTime) when in regulation. This MinOnTime governs the minimum al- lowable duty cycle given by: DCMIN = (MinOnTime) TP
• 100% where TP is the clock period and MinOnTime (found in the Electrical Characteristics) is a maximum of 420ns. The application should be designed such that the operating duty cycle is between DC MIN and DCMAX. Duty cycle equations for several common topologies are given below where VON_MP is the voltage drop across the external power PFET (MP) when it is on, and V ON_MN is the voltage drop across the external power NFET (MN) when it is on. For the boost topology (see Figure 5): DCBOOST ≅ VOUT – VIN+ VON_MP VOUT+ VON_MP – VON_MN For the SEPIC or dual inductor inverting topology (see Figures 6 and 7): VIN+| VOUT|+VON_MP – VON_MN The LT8710 can be used in configurations where the duty cycle is higher than DCMAX, but it must be operated in the discontinuous conduction mode (MODE pin must be high) so that the effective duty cycle is reduced. INDUCTOR SELECTION For high efficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. Also to improve efficiency, choose inductors with more volume for a given inductance. The inductor should have low DCR (copper-wire resistance) to reduce I2R losses, and must be able to handle the peak inductor current without saturat- ing. Note that in some applications, the current handling requirements of the inductor can be lower, such as in the SEPIC topology where each inductor carries a fraction of the total switch current. Molded chokes or chip inductors do not have enough core area to support peak inductor currents in the 5A to 15A range. To minimize radiated noise, use a toroidal or shielded inductor. See Table 5 for a list of inductor manufacturers.

Table 5. Inductor Manufacturers avoid false tripping of the current comparator.

8710f For more information www.linear .com/L T8710 appenDix Adequate Load Current Small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be provided to the load. In order to provide adequate load current, L should be at least: LBOOST ≥ VIN•DC 2•f • VCSPN RSENSE1 – VOUT •IOUT VIN•η or LDUAL ≥ VIN•DC 2•f • VCSPN RSENSE1 – |VOUT|•IOUT VIN•η –IOUT   where: LBOOST = L1 for boost topologies (see Figure 5) LDUAL = L1 = L2 for coupled dual inductor topologies (see Figures 6 and 7) LDUAL = L1 || L2 for uncoupled dual inductor topolo- gies (see Figures 6 and 7) DC = Switch duty cycle (see previous section) VCSPN = Current limit voltage at the operating switch duty cycle (see Max Current Limit vs Duty Cycle ( CSP – CSN) plot in the Typical Per- formance Characteristics) RSENSE1 = Current sense resistor connected across the CSP-CSN pins (see Block Diagram) η = Power conversion efficiency (assume 90%) f = Switching frequency IOUT = Maximum output current Negative values of LBOOST or LDUAL indicate that the out- put load current, I OUT, exceeds the switch current limit capability of the converter. Decrease RSENSE1 to increase the switch current limit. Avoiding Subharmonic Oscillations The LT8710’s internal slope compensation circuit will prevent subharmonic oscillations that can occur when the duty cycle is greater than 50%, provided that the in - ductance exceeds a minimum value. In applications that operate with duty cycles greater than 50%, the inductance must be at least: LMIN ≥ VIN•RSENSE1•(2•DC–1) 40m•DC• f •(1–DC) where LMIN = L1 for boost topologies (see Figure 5) LMIN = L1 = L 2 for coupled dual inductor topologies (see Figures 6 and 7) LMIN = L1 || L2 for uncoupled dual inductor topologies (see Figures 6 and 7) Maximum Inductance Excessive inductance can reduce ripple current to levels that are difficult for the current comparator (A5 in the Block Diagram) to cleanly discriminate, thus causing duty cycle jitter and/or poor regulation. The maximum inductance can be calculated by: LMAX ≤ VIN•RSENSE1•DC 5m• f where: LMAX = L1 for boost topologies (see Figure 5) LMAX = L1 = L 2 for coupled dual inductor topologies (see Figures 6 and 7) LMAX = L1 || L2 for uncoupled dual inductor topologies (see Figures 6 and 7) Inductor Current Rating The inductor(s) must have a rating greater than its (their) peak operating current to prevent inductor saturation, which would result in efficiency losses. The maximum Boost Topology SEPIC or Inverting Topologies

8710fFor more information www.linear .com/L T8710 appenDix inductor current (considering start-up and steady-state conditions) is given by: IL_PEAK = 54mV –16mV •DC2 RSENSE1 + VIN• TMIN_PROP L where IL_PEAK = Peak inductor current in L 1 for a boost topology, or the sum of the peak inductor currents for dual inductor topologies. TMIN_PROP = 100ns (propagation delay through the current feedback loop). For wide input voltage range applications, as the input volt- age increases, the max peak inductor current also increases due to the duty cycle decreasing. It is recommended to utilize the output current limiting feature to reduce the max peak inductor current given by the following equation: IL_PEAK = VISPN RSENSE2•(1–DC) + VIN•DC 2• f •L where…. VISPN = 57mV max for noninverting converters and 60mV max for inverting converters. Note that these equations offer conservative results for the required inductor current ratings. The current ratings could be lower for applications with light loads, and if the SS capacitor is sized appropriately to limit inductor currents at start-up. POWER MOSFET SELECTION The LT8710 requires two external power MOSFETs, an NFET switch for the BG gate driver and a PFET switch for the TG gate driver. It is important to select MOSFETs for optimizing efficiency. For choosing an NFET and PFET, the important device parameters are: 1. Breakdown voltage (BVDSS) 2. Gate threshold voltage (VGSTH) 3. On-resistance (rDSON) 4. Total gate charge (QG) 5. Turn-off delay time (tD(OFF)) 6. Package has exposed paddle The drain-to-source breakdown voltage of the NFET and PFET power MOSFETs must exceed: BVDSS > VOUT for boost converter

• BVDSS > V IN+|VOUT| for SEPIC or dual inductor inverting converter If operating close to the BVDSS rating of the MOSFET, check the leakage specifications on the MOSFET because leakage can decrease the efficiency of the converter. The NFET and PFET gate-to-source drive is approximately 6.3V and 6.18 V respectively, so logic level MOSFETs are required. The BG gate driver can begin switching when the INTVCC voltage exceeds ~4V, so ensure the selected NFET is in the linear mode of operation with 4V of gate- to-source drive to prevent possible damage to the NFET. The TG gate driver can begin switching when the BIAS- INTVEE voltage exceeds ~3.42V, so it is optimal that the PFET be in the linear mode of operation with 3.42V of gate-to-source drive. However, the PFET is less likely to get damaged if it’s not operating in the linear region since the drain-to-source voltage is clamped by its body diode during the NFET’s off-time. Having said that, try to choose a PFET with a low body diode reverse recovery time to minimize stored charge in the PFET. The stored charge in the PFET body diode gets removed when the NFET switch turns on and can lead to efficiency hits especially in ap - plications where the VDS of the PFET (during off-time) is high. For these applications, it may be beneficial to put a Schottky diode across the PFET to reduce the amount of charge in the PFET body diode. In applications where the output voltage is high in magnitude, it may be better to replace the PFET with a Schottky diode since the converter may be more efficient with a Schottky. Power MOSFET on-resistance and total gate charge go hand-in-hand and are typically inversely proportional to each other; the lower the on-resistance, the higher total gate charge. Choose MOSFETs with an on-resistance to give a voltage drop to be less than 300mV at the peak

generally smaller than the LT8710’s non-overlap time. Table 6. Power MOSFET (NFET and PFET) Manufacturers and POSCAP are also available. reduced capacitance at the desired operating voltage.

for a list of ceramic capacitor manufacturers. Table 7. Ceramic Capacitor Manufacturers converter or slow down the converter, respectively. For the circuit in Figure 7, a 3.3nF series cap was used. damped and the compensation procedure is complete.

8705 F21a

8705 F21b

8705 F21c

contribution of the various elements in the loop is critical. to the VC voltage and current sense resistor, RSENSE1. Figure 22. Boost Converter Equivalent Model

• RL 2 • 0.5•R2 RFBX+0.5 •R2 Output Pole:P1= 2 2• π •RL •COUT Error Amp Pole:P2= 1 2• π •(RO+RC)•CC Error Amp Zero: Z1= 1 2• π •RC•CC ESR Zero: Z2= 1 2• π •RESR •COUT RHP Zero: Z3= VIN2 •RL 2• π • VOUT2 •L High Frequency Pole:P3> fS Phase Lead Zero: Z4= 1 2• π •RFBX •CPL Phase LeadPole:P4= 1 2• π • RFBX •0.5•R2 RFBX+0.5 •R2
• CPL Error Amp Filter Pole:P5= 1 2• π • RC •RO RC+RO
• CF ,CF < CC The current mode zero (Z3) is a right half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection.

8710 F22

• IVIN RESR COUT RL

Figure 23. Bode Plot for Example Boost Converter Figure 24. 5V to 12V Boost Converter

8710 F24

8710 F23

8710f For more information www.linear .com/L T8710 Typical applicaTion 300kHz, 4.5V to 25V Input to –5V Output Delivers Up to 7A Output Current Efficiency and Power Loss T ransient Response with 2A to 5.5A to 2A Output Load Step (VIN = 12)

8710 TA02c

200µs/DIV CIN1: 10µF , 50V , 1210, X7S CIN2: OSCON 120µF , 35V , 35SVPF120M COUT1: 100µF , 6.3V , 1812, X5R COUT2: OSCON 330µF , 16V , 16SEQP330M C1: 10µF , 50V , 1210, X7S L1, L2: WÜRTH 2.2µH WE-CFWI 74485540220 MN: FAIRCHILD FDMS8333L MP: FAIRCHILD FDD4141 R SENSE1: 1.5m/uni03A9 2010 RSENSE2: 4m/uni03A9 2512 D1: NXP PMEG2010EA IMON SSGND CSP TGCSNBG L T8710

8710 TA02a

–5V VIN 4.5V TO 25V 13.3k 2.2µH CIN2 120µF 2.2µF COUT1 100µF 10k CIN1 10µF 118k 1.5m MN MP RSENSE1 RSENSE2 2.2µH 10µF ×2 60.4k 11.5k 2.2µF INTVCC COUT2 330µF+ 47nF 220nF 3.3nF 100pF 499/uni03A9 D1 0.47µF LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W) 100 1 4 5 6

8710 TA02b

VIN = 5V VIN = 12V

8710fFor more information www.linear .com/L T8710 Typical applicaTion 300kHz, SuperCap Backup Power

8710 TA03c

8710 TA03d

LOAD CURRENT (A) HOLD-UP TIME (s) 200 150 175 125 100 0.5 1.5 2 2.5

8710 TA03b

VSYSTEM = 10.5V DURING HOLD-UP System Hold-Up Time vs System Load Current SuperCaps Charging When VIN Is Applied SuperCaps Hold-Up System at 10.5V for ~83s When VIN Is Removed (ISYSTEM = 1A) L1, L2: COILCRAFT 10µH MSD1278-103ML MN: FAIRCHILD FDMC8327L MP: VISHAY Si7611DN R SENSE1: 5m/uni03A9 2010 RSENSE2: 50m/uni03A9 2512 DIN: APPROPRIATE SCHOTTKY DIODE OR IDEAL DIODE SUCH AS L TC4358, L TC4352, L TC4412, ETC. CIN1: 22µF , 25V , 1812, X7R COUT: 22µF , 25V , 1812, X7R C1: 10µF , 25V , 1210, X7R C S1-6: POWERSTOR HB1840-2R5606-R D1: CENTRAL SEMI CMDZ5245B-L TZ IMON SSGND CSP TGCSNBG L T8710

8710 TA03a

12V ±5% INPUT POWER SOURCE CAN BE REMOVED D IN 49.9k L1, 10µH CIN2 120µF 2.2µF10k 15V RT 118k MN MP RSENSE1 10µH

• C1, 10µF 165k 14.3k 47nF 220nF 2.2nF 100pF CIN1 22µF COUT 22µF RSENSE2 50m VSYSTEM = VIN WHEN VIN IS PRESENT 10.5V WHEN VIN IS REMOVED 1.2k 1.2k 1.2k 1.2k 1.2k 1.2k CS1 60F CS2 60F CS3 60F CS4 60F CS5 60F CS6 60F 5.1/uni03A9 5.1/uni03A9 4.7nF 4.7nF 2.2µF

8710f For more information www.linear .com/L T8710 Typical applicaTion 400kHz, 12V Boost Converter Delivers Up to 6A from a 4.5V to 9V Input Efficiency and Power Loss T ransient Response with 2A to 5A to 2A Output Load Step (VIN = 5V)

8710 TA04c

200µs/DIV L1: WÜRTH 1.3µH WE-HCI 7443551130 MN: VISHAY SiR802DP MP: VISHAY Si7635DP R SENSE1: 1m/uni03A9 2512 RSENSE2: 5m/uni03A9 2512 CIN1: 22µF , 16V , 1206, X5R CIN2: OSCON 330µF , 16V , 16SEQP330M COUT1: 22µF , 25V , 1812, X7R COUT2: OSCON 330µF , 16V , 16SEQP330M IMON SSGND CSP TGCSNBG L T8710

8710 TA04a

4.5 TO 9V

13.3k 1.3µH COUT2 330µF 2.2µF 10k 88.7k MN MP R SENSE1 130k 18k 2.2µF 47nF 220nF 3.3nF 100pF RSENSE2 COUT1 22µF COUT2 330µF +CIN1 22µF LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W) 100 1 4 5 6

8710 TA04b

VIN = 5V VIN = 8V

8710fFor more information www.linear .com/L T8710 Typical applicaTion Schematic and Equations for Calculating VOUT VOUT Cleanly T ransitions Through 0V with a 1V, 100Hz Sine Wave CNTL Signal (RLOAD = 2Ω) T ransient Response with Stepping VCNTL from 0V to –1V to 0V with 2Ω Output Load 300kHz, –5V to 5V Output Cleanly T ransitions Through 0V with 3A Source and Sink Capability*

8710 TA05c

8710 TA05d

500µs/DIV L1, L2: WÜRTH 4.4µH WE-CFWI 74485540440 MN: FAIRCHILD FDMS8333L MP: FAIRCHILD FDD4141 R SENSE1: 3m/uni03A9 2010 RSENSE2: 10m/uni03A9 2512 * PATENT PENDING CIN1: 22µF , 25V , 1812, X7R CIN2: OSCON 330µF , 16V , 16SEQP330M COUT: 100µF , 6.3V , 1812, X5R C1: 10µF , 25V , 1210, X7R D1: CENTRAL SEMI CMPD1001 IMON SSGND CSP TG TG CSNBG L T8710

8710 TA05a

–5V TO 5V ±3A VIN VCNTL 0V FOR VOUT = –5V –0.5V FOR VOUT = 0V –1V FOR VOUT = 5V VIN 11V TO 13V 4.4µH RSENSE1 MN CIN2 330µF 2.2µF COUT 100µF CIN1 22µF 118k 4.4µH 10µF ×2 60.4k 39.2k 2.2µF 6.04k 10nF 47nF 220nF 2.2nF 100pF RSENSE2 10m FET BVDSS > 2VIN – VOUT CIVRATING > VIN – VOUT DC = VIN – VOUT 2VIN – VOUT FBX ~9.6mV RFBX RCNTL VCNTL VOUT ~83.1µA

8710 TA05b

VOUT = 9.6mV –83.1µA • RFBX – (VCNTL – 9.6mV)RCNTL RFBX

8710f For more information www.linear .com/L T8710 300kHz, 3A Sealed Lead Acid Battery Charger with an Optional Negative Temp-Co Bulk and Float Battery Voltage Efficiency vs Input VoltageBulk and Float Output Voltage with **Optional Components Typical applicaTion TEMPERATURE (°C) –40 OUTPUT VOL TAGE (V) 16.0 15.0 15.5 14.5 14.0 13.5 13.0 12.5 12.0 –20 40 60 80

8710 TA06b

INPUT VOL TAGE (V) EFFICIENCY (%) 10 25 30

8710 TA06c

VOUT = 12V IOUT = 3A L1, L2: WÜRTH 3.5µH WE-CFWI 74485540350 MN: FAIRCHILD FDMS86500L MP1: VISHAY SUD50P06-15 R SENSE1: 1.5m/uni03A9 2010 RSENSE2: 16m/uni03A9 2512 CIN1: 10µF , 50V , 1210, X7S COUT: 22µF , 25V , 1812, X7R C1: 10µF , 50V , 1210, X7S MP2: VISHAY Si2343CDS R NTC: MURATA NCP18XH103F03RB SEE THE BATTERY CHARGING AND C/10 SECTION IN APPLICATIONS INFORMATION FOR MORE INFORMATION ON BATTERY CHARGING * MP2 DISCONNECTS FBX PIN CURRENT DRAW FROM BATTERY WHEN L T8710 IS IN SHUTDOWN ** PLACE 316k/uni03A9 AND 100nF AS CLOSE TO THE FBX PIN AS POSSIBLE. ALSO, CONNECT ALL GROUNDS OF THESE COMPONENTS TO THE L T8710 GROUND IMON SSGND CSP TGCSNBG L T8710

8710 TA06a

14.7V BULK 13.77V FLOAT 3A CHARGE V IN 5V TO 30V 13.3k 3.5µH RSENSE1 MN CIN2 100µF 2.2µF COUT 22µF 10k CIN1 10µF 118k 1.5m 10µF ×2 150k *OPTIONAL MP2 RNTC 10k INTVCC 196k 316k 6.19k 2.2µF SEALED LEAD ACID BATTERY 47nF 220nF 6.8nF 100nF 100pF 3.5µH MP1 2.37k 220nF **OPTIONAL RSENSE2 16m 5.1/uni03A95.1/uni03A9 4.7nF 4.7nF

8710fFor more information www.linear .com/L T8710 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. FE20 (CB) TSSOP REV J 1012 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF RECOMMENDED SOLDER PAD LAYOUT 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 1 3 4 5 6 7 8 9 10 11 12 14 13 6.40 – 6.60* (.252 – .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 2.74 (.108) 0.45 ±0.05

0.65 BSC

4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 3.86 (.152) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev J) Exposed Pad Variation CB package DescripTion Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

8710f For more information www.linear .com/L T8710 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/8710  LINEAR TECHNOLOGY CORPORATION 2014 LT 0114 • PRINTED IN USA relaTeD parTs Typical applicaTion PART NUMBER DESCRIPTION COMMENTS LT3757A Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ V IN ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency, 3mm × 3mm DFN-10 and MSOP-10E Packages LT3758A Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ VIN ≤ 100V, 100kHz to 1MHz Programmable Operating Frequency, 3mm × 3mm DFN-10 and MSOP-10E Packages LT3759 Boost, SEPIC and Inverting Controller 1.6V ≤ VIN ≤ 42V, 100kHz to 1MHz Programmable Operating Frequency, LT3957A Boost, Flyback, SEPIC and Inverting Converter with 5A, 40V Switch 3V ≤ VIN ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency, 5mm × 6mm QFN Package LT3958 Boost, Flyback, SEPIC and Inverting Converter with 3.3A, 84V Switch 5V ≤ V IN ≤ 80V, 100kHz to 1MHz Programmable Operating Frequency, 5mm × 6mm QFN Package LT3959 Boost, SEPIC and Inverting Converter with 6A, 40V Switch 1.6V ≤ V IN ≤ 40V, 100kHz to 1MHz Programmable Operating Frequency, 5mm × 6mm QFN Package LTC3786 Low IQ Synchronous Step-Up Controller 4.5V (Down to 2.5V After Start-Up) ≤ VIN ≤ 38V, VOUT Up to 60V, 55µA Quiescent Current, 3mm × 3mm QFN-16, MSOP-16E 200kHz, Wide Input Range SEPIC Converter Generates a 5V Output with Up to 5A Output Current Efficiency and Power Loss L1, L2: WÜRTH 2.9µH WE-CFWI 74485540290 MN: FAIRCHILD FDMS86500L MP: VISHAY SUD50P06-15 R SENSE1: 1.5m/uni03A9 2010 RSENSE2: 6m/uni03A9 2512 CIN1: 10µF , 50V , 1210, X7S COUT1: 100µF , 6.3V , 1812, X5R COUT2: OSCON 330µF , 16V , 16SEQP330M C1: 10µF , 50V , 1210, X7S IMON SSGND CSP TGCSNBG L T8710

8710 TA07a

3V TO 40V (OPERATING) 4.5V TO 40V (START-UP) 4.02k 2.9µH CIN1 10µF CIN2 220µF 2.2µF 10k 178k 1.5m MN MP RSENSE1 45.3k 8.87k 2.2µF 47nF 220nF 6.8nF 100pF RSENSE2 COUT1 100µF COUT2 330µF 10µF ×2 2.9µH LOAD CURRENT (A) EFFICIENCY (%) POWER LOSS (W) 100 6.00 4.50 5.25 3.75 3.00 2.25 1.50 0.75 3 4 5

8710 TA07b

VIN = 5V VIN = 12V