LT8708

LT8708 (Rev B)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 66

Technical content

Rev. DFor more information www.analog.com Document Feedback CSPOUT CSNOUT EXTVCC VOUTLOMON FBOUT INTVCC GATEVCC IMON_ON IMON_OP ICN ICP IMON_INP IMON_INN CLKOUTSYNCSSRTVCMODE CSNIN TG1 BOOST1 SW1 BG1 CSP CSN L T8708 GND BG2 SW2 BOOST2TG2 CSPIN VINCHIP SHDN FBIN VINHIMON SWEN LDO33 DIR RVSOFF 126kHz FWD (3V)RVS (0V) DB1 DB2 TO BOOST1 TO BOOST2 ILIM TO DIODE DB1 LD033 VBAT2

8708 TA01a

80V Synchronous 4-Switch Buck-Boost DC/DC Controller with Bidirectional Capability The LT®8708 is a high performance buck-boost switching regulator controller that operates from an input voltage that can be above, below or equal to the output voltage. Features are included to simplify bidirectional power con- version in battery/capacitor backup systems and other applications that may need regulation of VOUT, VIN, IOUT, and/or IIN. Forward and reverse current can be monitored and limited for the input and output sides of the converter . All four current limits (forward input, reverse input, for - ward output and reverse output) can be set independently using four resistors on the PCB. The MODE pin can select between discontinuous conduction mode (DCM), continuous conduction mode (CCM), hybrid conduction mode (HCM) and Burst Mode® operation. In combination with the DIR (direction) pin, the chip can be configured to process power only from VIN to VOUT or only from VOUT to VIN. With a wide 2.8V to 80V input and 1.3V to 80V output range, the LT8708 is compatible with most solar , automotive, telecom and battery-powered systems. 12V Bidirectional Dual Battery System with FHCM and RHCM

APPLICATIONS

n Single Inductor Allows VIN Above, Below, or Equal to VOUT n Six Independent Forms of Regulation n VIN Current (Forward and Reverse) n VOUT Current (Forward and Reverse) n VIN and VOUT Voltage n Forward and Reverse Discontinuous Conduction Mode Supported n Supports MODE and DIR Pin Changes While Switching n VINCHIP Range 2.8V (Need EXTVCC > 6.4V) to 80V n VOUT Range: 1.3V to 80V n Synchronous Rectification: Up to 99% Efficiency n Available in 40-Lead (5mm × 8mm) QFN with High Voltage Pin Spacing and 64-Lead (10mm × 10mm) eLQFP n AEC-Q100 Qualified for Automotive Applications n High Voltage Buck-Boost Converters n Bidirectional Charging System n Automotive 48V Systems All registered trademarks and trademarks are the property of their respective owners. Efficiency V BAT2 = 13.5V I OUT = 15A V BAT1 (V) 100 EFFICIENCY (%)

8708 TA01b

Rev. D For more information www.analog.com TABLE OF CONTENTS Inductor Current Sensing and Slope RSENSE Selection: Max RSENSE in the Boost RSENSE Selection: Max RSENSE in the Buck L Selection: Load Current in Buck and Boost Topside MOSFET Driver Supply 12V Bidirectional Dual Battery System with FHCM 48V to 14V Bidirectional Dual Battery System with

Rev. DFor more information www.analog.com PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS VCSP – VCSN, VCSPIN – VCSNIN, IMON_INP, IMON_INN, IMON_OP, IMON_ON, (Note 1) CSNIN, CSPIN, CSPOUT, CSNOUT Voltage –0.3V to 80V Operating Junction Temperature Range 15 16 17 18 TOP VIEW GND UHG PACKAGE 40-LEAD (5mm × 8mm) PLASTIC QFN TJMAX = 150°C, θJA = 36°C/W , θJC = 3.8°C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB 19 20 21 40 39 38 37 36 35 34 1CLKOUT SS SHDN CSN CSP ICN DIR FBIN FBOUT VC IMON_INP IMON_INN RT SYNC CSPIN CSNIN CSNOUT CSPOUT EXTVCC ICP VINHIMON VOUTLOMON RVSOFF BOOST1 TG1 SW1 LDO33 IMON_ON IMON_OP MODE SWEN INTVCC VINCHIP GND BG1 GATEVCC BG2 BOOST2 TG2 SW2 NC SS SHDN CSN CSP ICN DIR FBIN FBOUT VC IMON_INP IMON_INN RT SYNC NC NC NC NC GND BG1 GATEVCC BG2 NC BOOST2 TG2 SW2 NC NC NC NC NC NC NC CLKOUT LDO33 IMON_ON IMON_OP MODE SWEN INTVCC NC VINCHIP NC CSPIN CSNIN NC NC NC NC CSNOUT CSPOUT NC NC NC EXTVCC NC ICP VINHIMON VOUTLOMON RVSOFF NC BOOST1 TG1 SW1 TOP VIEW LWE PACKAGE 64-LEAD (10mm × 10mm) PLASTIC LQFP TJMAX = 150°C, θJA = 17°C/W , θJC = 2.5°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB GND

Rev. D For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VINCHIP = 12V, SHDN = 3V, DIR = 3.3V unless otherwise noted (Note 3). PARAMETER CONDITIONS MIN TYP MAX UNITS Voltage Supplies and Regulators VINCHIP Operating Voltage Range EXTVCC = 0V EXTVCC = 7.5V l l 5.5 2.8 V V VINCHIP Quiescent Current Not Switching, VEXTVCC = 0V SWEN = 3.3V SWEN = 0V 3.9 2.45 6.5 4.5 mA mA VINCHIP Quiescent Current in Shutdown VSHDN = 0V 0 1 μA EXTVCC Switchover Voltage IINTVCC = –20mA, VEXTVCC Rising l 6.15 6.4 6.6 V EXTVCC Switchover Hysteresis 0.2 V INTVCC Current Limit Maximum Current Draw from INTVCC and LDO33 Pins Combined. Regulated from VINCHIP or EXTVCC (12V) INTV CC = 5.25V INTV CC = 4.4V l l 127 165 mA mA INTVCC Voltage Regulated from VINCHIP, IINTVCC = 20mA Regulated from EXTVCC (12V), IINTVCC = 20mA l l 6.1 6.1 6.3 6.3 6.5 6.5 V V INTVCC Load Regulation IINTVCC = 0mA to 50mA –0.5 –1.5 % INTVCC, GATEVCC Undervoltage Lockout INTVCC Falling, GATEVCC Connected to INTVCC l 4.45 4.65 4.85 V ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8708EUHG#PBF LT8708EUHG#TRPBF 8708 40-Lead (5mm × 8mm) Plastic QFN –40°C to 125°C LT8708IUHG#PBF LT8708IUHG#TRPBF 8708 40-Lead (5mm × 8mm) Plastic QFN –40°C to 125°C LT8708HUHG#PBF LT8708HUHG#TRPBF 8708 40-Lead (5mm × 8mm) Plastic QFN –40°C to 150°C AUTOMOTIVE PRODUCTS** LT8708IUHG#WPBF LT8708IUHG#WTRPBF 8708 40-Lead (5mm × 8mm) Plastic QFN –40°C to 125°C LT8708HUHG#WPBF LT8708HUHG#WTRPBF 8708 40-Lead (5mm × 8mm) Plastic QFN –40°C to 150°C TRAY PART MARKING* PACKAGE DESCRIPTION MSL RATING TEMPERATURE RANGE LT8708ELWE#PBF LT8708LWE 64-Lead (10mm × 10mm) Plastic eLQFP 3 –40°C to 125°C LT8708ILWE#PBF LT8708LWE 64-Lead (10mm × 10mm) Plastic eLQFP 3 –40°C to 125°C LT8708HLWE#PBF LT8708LWE 64-Lead (10mm × 10mm) Plastic eLQFP 3 –40°C to 150°C AUTOMOTIVE PRODUCTS** LT8708ELWE#WPBF LT8708LWE 64-Lead (10mm × 10mm) Plastic eLQFP 3 –40°C to 125°C LT8708ILWE#WPBF LT8708LWE 64-Lead (10mm × 10mm) Plastic eLQFP 3 –40°C to 125°C LT8708HLWE#WPBF LT8708LWE 64-Lead (10mm × 10mm) Plastic eLQFP 3 –40°C to 150°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. **Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.

Rev. DFor more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS INTVCC, GATEVCC Undervoltage Lockout Hysteresis GATEVCC Connected to INTVCC 170 mV INTVCC Regulator Dropout Voltage VINCHIP – VINTVCC, IINTVCC = 20mA 220 mV LDO33 Pin Voltage 5mA from LDO33 Pin l 3.23 3.295 3.35 V LDO33 Pin Load Regulation ILDO33 = 0.1mA to 5mA –0.25 –1 % LDO33 Pin Current Limit SYNC = 3V l 12 17.25 22 mA LDO33 Pin Undervoltage Lockout LDO33 Falling 2.96 3.04 3.12 V LDO33 Pin Undervoltage Lockout Hysteresis 35 mV Switching Regulator Control Maximum Current Sense Threshold (VCSP – VCSN) Boost Mode, Minimum M3 Switch Duty Cycle l 76 93 110 mV Maximum Current Sense Threshold (VCSN – VCSP) Buck Mode, Minimum M2 Switch Duty Cycle l 68 82 97 mV Maximum Current Sense Threshold (VCSN – VCSP) Boost Mode, Minimum M3 Switch Duty Cycle l 79 93 108 mV Maximum Current Sense Threshold (VCSP – VCSN) Buck Mode, Minimum M2 Switch Duty Cycle l 72 84 96 mV Gain from VC to Maximum Current Sense Voltage (VCSP – VCSN) (A5 in the Block Diagram) Boost Mode Buck Mode 135 –135 mV/V mV/V SHDN Input Voltage High SHDN Rising to Enable the Device QFN LWE l l 1.175 1.175 1.221 1.221 1.275 1.29 V V SHDN Input Voltage High Hysteresis 40 mV SHDN Input Voltage Low Device Disabled, Low Quiescent Current ( LT8708E, LT8708I) ( LT8708H) l l 0.35 0.3 V V SHDN Pin Bias Current VSHDN = 3V VSHDN = 12V μA μA SWEN Rising Threshold Voltage l 1.156 1.208 1.256 V SWEN Threshold Voltage Hysteresis 22 mV SWEN Output Voltage Low ISWEN = 200μA SHDN = 0V or VINCHIP = 0V SHDN = 3V l l 0.9 0.2 1.1 0.5 V V SWEN Internal Pull-Down Release Voltage SHDN = 3V l 0.75 0.8 V MODE Pin Continuous Conduction Mode (CCM) Threshold l 0.4 V MODE Pin Hybrid DCM/CCM Mode (HCM) Range l 0.8 1.2 V MODE Pin Discontinuous Conduction Mode (DCM) Range l 1.6 2.0 V MODE Pin Burst Mode Operation Threshold l 2.4 V DIR Pin Forward Operation Threshold l 1.6 V DIR Pin Reverse Operation Threshold l 1.2 V RVSOFF Output Voltage Low IRVSOFF = 200μA l 0.08 0.5 V RVSOFF Falling Threshold Voltage l 1.155 1.209 1.275 V RVSOFF Threshold Voltage Hysteresis 165 mV Soft-Start Charging Current VSS = 0V 13 19 25 μA ICN Rising Threshold for FDCM Operation MODE = 1V (HCM), DIR = 3.3V l 235 255 280 mV ICN Falling Threshold for CCM Operation MODE = 1V (HCM), DIR = 3.3V l 185 205 235 mV IMON_INP Rising Threshold for RDCM Operation MODE = 1V (HCM), DIR = 0V l 235 255 280 mV IMON_INP Falling Threshold for CCM Operation MODE = 1V (HCM), DIR = 0V l 185 205 235 mV ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VINCHIP = 12V, SHDN = 3V, DIR = 3.3V unless otherwise noted (Note 3).

Rev. D For more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS Voltage Regulation Loops (Refer to Block Diagram to Locate Amplifiers) Regulation Voltage for FBOUT Regulate VC to 1.2V l 1.193 1.207 1.222 V Regulation Voltage for FBIN Regulate VC to 1.2V l 1.184 1.205 1.226 V Line Regulation for FBOUT and FBIN Error Amp Reference Voltage VINCHIP = 12V to 80V. Not Switching 0.002 0.005 %/V FBOUT Pin Bias Current Current Out of Pin 15 nA FBOUT Error Amp EA4 gm 345 μmho FBOUT Error Amp EA4 Voltage Gain 245 V/V VOUTLOMON Voltage Activation Threshold Falling l 1.185 1.207 1.225 V VOUTLOMON Threshold Voltage Hysteresis 24 mV VOUTLOMON Pin Bias Current VVOUTLOMON =1.24V, Current Into Pin VVOUTLOMON =1.17V, Current Into Pin l 0.8 0.01 1.2 μA μA FBIN Pin Bias Current Current Out of Pin 10 nA FBIN Error Amp EA3 gm 235 μmho FBIN Error Amp EA3 Voltage Gain 150 V/V VINHIMON Voltage Activation Threshold Rising l 1.185 1.207 1.23 V VINHIMON Threshold Voltage Hysteresis 24 mV VINHIMON Pin Bias Current VVINHIMON = 1.17V, Current Out of Pin VVINHIMON = 1.24V, Current Out of Pin l 0.8 0.03 1.2 μA μA Current Regulation Loops (Refer to Block Diagram to Locate Amplifiers) Regulation Voltages for IMON_INP and IMON_OP VC = 1.2V l 1.185 1.209 1.231 V Regulation Voltages for IMON_INN and IMON_ON VC =1.2V l 1.185 1.21 1.24 V Line Regulation for IMON_INP, IMON_INN, IMON_OP and IMON_ON Error Amp Reference Voltage VINCHIP = 12V to 80V 0.002 0.005 %/V CSPIN Bias Current VCSPIN = 12V VCSPIN = 1.5V 0.01 0.01 μA μA CSNIN Bias Current BOOST Capacitor Charge Control Block Not Active V SWEN = 3.3V, VCSPIN = VCSNIN = 12V V SWEN = 3.3V, VCSPIN = VCSNIN = 1.5V V SWEN = 0V 4.25 0.01 μA μA μA CSPIN, CSNIN Common Mode Operating Voltage Range l 0 80 V CSPIN, CSNIN Differential Mode Operating Voltage Range l –100 100 mV IMON_INP Output Current VCSPIN – VCSNIN = 50mV, VCSNIN = 5V VCSPIN – VCSNIN = 50mV, VCSNIN = 5V VCSPIN – VCSNIN = 5mV, VCSNIN = 5V VCSPIN – VCSNIN = 5mV, VCSNIN = 5V l l 64.5 22.5 75.5 27.5 μA μA μA μA IMON_INN Output Current VCSNIN – VCSPIN = 50mV, VCSNIN = 5V VCSNIN – VCSPIN = 50mV, VCSNIN = 5V VCSNIN – VCSPIN = 5mV, VCSNIN = 5V VCSNIN – VCSPIN = 5mV, VCSNIN = 5V l l 30.5 μA μA μA μA IMON_INP and IMON_INN Max Output Current l 120 μA IMON_INP Error Amp EA5 gm 190 μmho IMON_INP Error Amp EA5 Voltage Gain 130 V/V IMON_INN Error Amp EA1 gm FBIN = 0V, FBOUT = 3.3V 190 μmho ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VINCHIP = 12V, SHDN = 3V, DIR = 3.3V unless otherwise noted (Note 3).

Rev. DFor more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS IMON_INN Error Amp EA1 Voltage Gain FBIN = 0V, FBOUT = 3.3V 130 V/V CSPOUT Bias Current VCSPOUT = 12V VCSPOUT = 1.5V 0.01 0.01 μA μA CSNOUT Bias Current BOOST Capacitor Charge Control Block Not Active V SWEN = 3.3V, VCSPOUT = VCSNOUT = 12V V SWEN = 3.3V, VCSPOUT = VCSNOUT = 1.5V V SWEN = 0V 4.25 0.01 μA μA μA CSPOUT , CSNOUT Common Mode Operating Voltage Range l 0 80 V CSPOUT , CSNOUT Differential Mode Operating Voltage Range l –100 100 mV IMON_OP, ICP Output Current VCSPOUT – VCSNOUT = 50mV, VCSNOUT = 5V VCSPOUT – VCSNOUT = 50mV, VCSNOUT = 5V VCSPOUT – VCSNOUT = 5mV, VCSNOUT = 5V VCSPOUT – VCSNOUT = 5mV, VCSNOUT = 5V (QFN) VCSPOUT – VCSNOUT = 5mV, VCSNOUT = 5V (LWE) VCSPOUT – VCSNOUT = –5mV, VCSNOUT = 5V VCSPOUT – VCSNOUT = –5mV, VCSNOUT = 5V l l l l 22.5 20.5 20.5 12.5 10.5 27.5 17.5 19.5 μA μA μA μA μA μA μA IMON_ON, ICN Output Current VCSNOUT – VCSPOUT = 50mV, VCSNOUT = 5V VCSNOUT – VCSPOUT = 50mV, VCSNOUT = 5V VCSNOUT – VCSPOUT = 5mV, VCSNOUT = 5V VCSNOUT – VCSPOUT = 5mV, VCSNOUT = 5V VCSNOUT – VCSPOUT = –5mV, VCSNOUT = 5V VCSNOUT – VCSPOUT = –5mV, VCSNOUT = 5V l l l 22.5 20.5 12.5 10.5 27.5 17.5 19.5 μA μA μA μA μA μA IMON_OP, IMON_ON, ICP and ICN Max Output Current l 120 μA IMON_OP Error Amp EA6 gm 190 μmho IMON_OP Error Amp EA6 Voltage Gain 130 V/V IMON_ON Error Amp EA2 gm FBIN = 0V, FBOUT = 3.3V 190 μmho IMON_ON Error Amp EA2 Voltage Gain FBIN = 0V, FBOUT = 3.3V 130 V/V NMOS Gate Drivers TG1, TG2 Rise Time CLOAD = 3300pF (Note 4) 20 ns TG1, TG2 Fall Time CLOAD = 3300pF (Note 4) 20 ns BG1, BG2 Rise Time CLOAD = 3300pF (Note 4) 20 ns BG1, BG2 Fall Time CLOAD = 3300pF (Note 4) 20 ns TG1 Off to BG1 On Delay CLOAD = 3300pF Each Driver 90 ns BG1 Off to TG1 On Delay CLOAD = 3300pF Each Driver 80 ns TG2 Off to BG2 On Delay CLOAD = 3300pF Each Driver 90 ns BG2 Off to TG2 On Delay CLOAD = 3300pF Each Driver 80 ns Minimum On-Time for Main Switch in Boost Operation (tON(M3,MIN)) Switch M3, CLOAD = 3300pF 200 ns Minimum On-Time for Synchronous Switch in Buck Operation (tON(M2,MIN)) Switch M2, CLOAD = 3300pF 200 ns Minimum Off-Time for Main Switch in Steady-State Boost Operation Switch M3, CLOAD = 3300pF 230 ns Minimum Off-Time for Synchronous Switch in Steady-State Buck Operation Switch M2, CLOAD = 3300pF 230 ns ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VINCHIP = 12V, SHDN = 3V, DIR = 3.3V unless otherwise noted (Note 3).

Rev. D For more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS Oscillator Switch Frequency Range SYNCing or Free Running 100 400 kHz Switching Frequency, FOSC RT = 365k RT = 215k RT = 124k l l l 102 170 310 120 202 350 142 235 400 kHz kHz kHz SYNC High Level for Synchronization l 1.3 V SYNC Low Level for Synchronization l 0.5 V SYNC Clock Pulse Duty Cycle VSYNC = 0V to 2V 20 80 % Recommended Min SYNC Ratio FSYNC/FOSC 3/4 CLKOUT Output Voltage High VLDO33 – VCLKOUT, 1mA Out of CLKOUT Pin, ILDO33 = 0μA 100 250 mV CLKOUT Output Voltage Low 1mA Into CLKOUT Pin 25 100 mV CLKOUT Duty Cycle TJ = –40°C TJ = 25°C TJ = 125°C 22.7 44.1 PARAMETER CONDITIONS MIN TYP MAX UNITS CLKOUT Rise Time CLOAD = 200pF 20 ns CLKOUT Fall Time CLOAD = 200pF 20 ns CLKOUT Phase Delay SYNC Rising to CLKOUT Rising, fOSC = 100kHz l 160 180 200 degrees Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Do not force voltage on the VC pin. Note 3: The LT8708E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8708I is guaranteed over the full –40°C to 125°C junction temperature range. The LT8708H is guaranteed over the full –40°C to 150°C operating junction temperature range. Note 4: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 5: Do not apply a voltage or current source to these pins. They must be connected to capacitive loads only, otherwise permanent damage may occur . Note 6: Negative voltages on the SW1 and SW2 pins are limited, in an application, by the body diodes of the external NMOS devices, M2 and M3, or parallel Schottky diodes when present. The SW1 and SW2 pins are tolerant of these negative voltages in excess of one diode drop below ground, guaranteed by design. Note 7: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 8: Do not force voltage or current into these pins. ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VINCHIP = 12V, SHDN = 3V, DIR = 3.3V unless otherwise noted (Note 3). The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VINCHIP = 12V, SHDN = 3V, DIR = 3V unless otherwise noted (Note 3).

Rev. DFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Output Current (Boost Region – page 59) Efficiency vs Output Current (Buck Region – page 59) Efficiency vs Output Current (Buck–Boost Region – page 59 Feedback Voltages Feedback Voltages (Five Parts) Oscillator Frequency Maximum Inductor Current Sense Voltage vs Duty Cycle Inductor Current Sense Voltage at Minimum Duty Cycle Maximum Inductor Current Sense Voltage at Minimum Duty Cycle LOAD CURRENT (A) 0.01 0.1 100 EFFICIENCY (%)

8708 G01

V IN = 38V V OUT = 47.4V LOAD CURRENT (A) 0.01 0.1 100 EFFICIENCY (%)

8708 G02

V IN = 51.5V V OUT = 47.4V LOAD CURRENT (A) 0.01 0.1 100 EFFICIENCY (%)

8708 G03

V IN = 48V V OUT = 47.4V V C = 1.2V FBOUT FBIN IMON_INP IMON_INN IMON_ON IMON_OP TEMPERATURE (°C) –45 –20 105 130 155 1.17 1.18 1.19 1.20 1.21 1.22 1.23 PIN VOL TAGE (V) Feedback Voltages

8708 G04

V C = 1.2V TEMPERATURE (°C) –45 –20 105 130 155 1.17 1.18 1.19 1.20 1.21 1.22 1.23 PIN VOL TAGE (V)

8708 G05

R T = 124k R T = 215k R T = 365k TEMPERATURE (°C) –45 –20 105 130 155 100 150 200 250 300 350 400 FREQUENCY (kHz) Oscillator Frequency

8708 G06

M2 OR M3 DUTY CYCLE (%) 100 100 120 140 |CSP–CSN| (mV)

8708 G07

V C (V) 0.5 1.5 –100 –80 –60 –40 –20 100 –100 –80 –60 –40 –20 100 CSN-CSP (mV) CSP-CSN (mV)

8708 G08

TEMPERATURE (°C) –45 –20 105 130 155 100 120 |CSP–CSN| (mV) Voltage at Minimum Duty Cycle

8708 G09

Rev. D For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Minimum Inductor Current Sense Voltage vs Duty Cycle INTVCC Line Regulation (EXTVCC = 0V) Minimum Inductor Current Sense Voltage at Minimum Duty Cycle Maximum and Minimum VC vs SS INTVCC Line Regulation (VIN = 12V) IMONx, ICx Output Current CLKOUT Duty Cycle LDO33 Pin Regulation (ILDO33 = 1mA) VIN Supply Current vs Voltage (Not Switching) BUCK REGION BOOST REGION M2 OR M3 DUTY CYCLE (%) 100 –140 –120 –100 –80 –60 –40 –20 –|CSP–CSN| (mV)

8708 G10

V IN (V) 4.0 4.5 5.0 5.5 6.0 6.5 7.0 INTV CC (V)

8708 G11

TEMPERATURE (°C) –45 –20 105 130 155 –120 –100 –80 –60 –40 –20 –|CSP–CSN| (mV)

8708 G12

C MAXIMUM V C T J = 25°C SS (V) 0.3 0.6 0.9 1.2 1.5 0.5 1.0 1.5 2.0 2.5 V C (V) Maximum and Minimum V C vs SS

8708 G13

(V) 5.5 6.0 6.5 7.0 INTV CC (V)

8708 G14

CSPIN–CSNIN (mV) CSPOUT–CSNOUT (mV) –200 –100 100 200 –25.0 25.0 50.0 75.0 100.0 125.0 150.0 175.0 200.0 225.0 250.0 IMONX, ICX CURRENT (µA)

8708 G15

IMON_INN IMON_ON ICN IMON_INP IMON_OP ICP TEMPERATURE (°C) –45 –20 105 130 155 100 DUTY CYCLE (%) CLKOUT Duty Cycle

8708 G16

150°C –45°C 25°C INTV CC (V) 2.5 3.5 4.5 5.5 6.5 1.5 2.0 2.5 3.0 3.5 LDO33 (V)

8708 G17

150°C –45°C 25°C V IN (V) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 I IN (mA)

8708 G18

Rev. DFor more information www.analog.com SHDN Pin Current SHDN and SWEN Pin Thresholds vs Temperature Internal VIN UVLO VINHIMON and VOUTLOMON Pin Thresholds vs Temperature VINHIMON and VOUTLOMON Pin Hysteresis Current vs Temperature TYPICAL PERFORMANCE CHARACTERISTICS SHDN PIN VOL TAGE (V) CURRENT INTO PIN (µA)

8708 G19

TEMPERATURE (°C) –45 –20 105 130 155 1.10 1.12 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 PIN THRESHOLD VOL TAGE (V)

8708 G20

TEMPERATURE (°C) –45 –20 105 130 155 0.5 1.0 1.5 2.0 2.5 3.0 V IN UVLO (V)

8708 G21

TEMPERATURE (°C) –45 –20 105 130 155 1.10 1.12 1.13 1.15 1.16 1.18 1.20 1.21 1.23 1.24 1.26 PIN THRESHOLD VOL TAGE (V)

8708 G22

VINHIMON = 1.24V , OUT OF PIN VOUTLOMON = 1.17V , INTO PIN TEMPERATURE (°C) –45 –20 105 130 155 0.2 0.4 0.7 0.9 1.1 PIN CURRENT (µA)

8708 G23

Rev. D For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Discontinuous Mode (page 59) Continuous Mode (page 59) Continuous Mode (page 59) Load Step (page 59) Load Step (page 59) Load Step (page 59) Continuous Mode (page 59) 5/uni03BCs/DIV 8708 G24 IL 5A/DIV SW1 20V/DIV SW2 20V/DIV VBAT = 38V VLOAD = 47.4V 5/uni03BCs/DIV 8708 G25 IL 5A/DIV SW1 20V/DIV SW2 20V/DIV VBAT = 48V VLOAD = 47.4V 5/uni03BCs/DIV 8708 G26 IL 5A/DIV SW1 20V/DIV SW2 20V/DIV VBAT = 52V VLOAD = 47.4V 5/uni03BCs/DIV 8708 G27 IL 5A/DIV SW1 20V/DIV SW2 20V/DIV VBAT = 38V VLOAD = 47.4V 5ms/DIV 8708 G28 IL 5A/DIV VLOAD 500mV/DIV VBAT = 38V VLOAD = 47.4V LOAD STEP = 2A TO 4A 5ms/DIV 8708 G29 VLOAD 500mV/DIV IL 5A/DIV VBAT = 52V VLOAD = 47.4V LOAD STEP = 2A TO 4A 5ms/DIV 8708 G30 VLOAD 500mV/DIV IL 5A/DIV VBAT = 48V VLOAD = 47.4V LOAD STEP = 2A TO 4A

Rev. DFor more information www.analog.com CLKOUT (Pin 1/Pin 63) : Clock Output Pin. Use this pin to synchronize one or more compatible switching regu - lator ICs to the LT8708. CLKOUT toggles at the same frequency as the internal oscillator or as the SYNC pin, but is approximately 180° out of phase. CLKOUT may also be used as a temperature monitor since the CLKOUT duty cycle varies linearly with the part’s junction temperature. The CLKOUT pin can drive capacitive loads up to 200pF. SS (Pin 2/Pin 2): Soft-Start Pin. Place at least 220nF of capacitance here. Upon start-up, this pin will be charged by an internal resistor to 3.3V. SHDN (Pin 3/Pin 3) : Shutdown Pin. Tie high to enable chip. Ground to shut down and reduce quiescent current to a minimum. Don’t float this pin. CSN (Pin 4/Pin 4): The (–) Input to the Inductor Current Sense and DCM Detect Comparator . CSP (Pin 5/Pin 5): The (+) Input to the Inductor Current Sense and DCM Detect Comparator . The VC pin voltage and built-in offsets between CSP and CSN pins, in con - junction with the RSENSE value, set the inductor current trip threshold. ICN (Pin 6/Pin 6) : Negative V OUT Current Monitor . The current out of this pin is 20μA plus a current proportional to the negative average VOUT current. See the Applications Information section for more information. DIR (Pin 7/Pin 7) : Direction pin when MODE is set for DCM (discontinuous conduction mode) or HCM (hybrid conduction mode) operation. Otherwise this pin is ignored. Connect the pin to GND to process power from the VOUT to VIN. Connect the pin to LDO33 to process power from the VIN to VOUT. FBIN (Pin 8/Pin 8) : VIN Feedback Pin. This pin is con - nected to the input of error amplifier EA3 and is used to detect and/or regulate low VIN voltage. FBOUT (Pin 9/Pin 9): VOUT Feedback Pin. This pin is con- nected to the input of error amplifier EA4 and is used to detect and/or regulate high VOUT voltage. VC (Pin 10/Pin 10): Error Amplifier Output Pin. Tie exter- nal compensation network to this pin. IMON_INP (Pin 11/Pin 11): Positive VIN Current Monitor and Limit Pin. The current out of this pin is 20μA plus a current proportional to the positive average V IN current. IMON_INP also connects to error amplifier EA5 and can be used to limit the maximum positive VIN current. See the Applications Information section for more information. IMON_INN (Pin 12/Pin 12): Negative VIN Current Monitor and Limit Pin. The current out of this pin is 20μA plus a current proportional to the negative average VIN current. IMON_INN also connects to error amplifier EA1 and can be used to limit the maximum negative V IN current. See the Applications Information section for more information. RT (Pin 13/Pin 13) : Timing Resistor Pin. Adjusts the switching frequency. Place a resistor from this pin to ground to set the frequency. Do not float this pin. SYNC (Pin 14/Pin 14): To synchronize the switching fre- quency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock needs to exceed 1.3V, and the low level should be less than 0.5V. Drive this pin to less than 0.5V to revert to the internal free-running clock. See the Applications Information section for more information. BG1, BG2 (Pin 16/Pin 20, Pin 18/Pin 22) : Bottom Gate Drive. Drives the gate of the bottom N-channel MOSFETs between ground and GATEVCC. GATEVCC (Pin 17/Pin 21): Power supply for bottom gate drivers. Must be connected to the INTV CC pin. Do not power from any other supply. Locally bypass to GND. BOOST1, BOOST2 (Pin 24/Pin 35, Pin 19/Pin 24) : Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitor connects here. The BOOST1 pin swings from a diode voltage below GATEVCC up to VIN + GATEVCC. The BOOST2 pin swings from a diode voltage below GATEVCC up to VOUT + GATEVCC. TG1, TG2 (Pin 23/Pin 34, Pin 20/Pin 25): Top Gate Drive. Drives the top N-channel MOSFETs with voltage swings equal to GATEV CC superimposed on the switch node voltages. SW1, SW2 (Pin 22/Pin 33, Pin 21/Pin 26): Switch Nodes. The (–) terminals of the bootstrap capacitors connect here. PIN FUNCTIONS (QFN/eLQFP)

Rev. D For more information www.analog.com RVSOFF (Pin 25/Pin 37) : Reverse Conduction Disable Pin. This is an input/output open-drain pin that requires a pull up resistor . Pulling this pin low disables reverse cur- rent operation. See the Uni and Bidirectional Conduction section for more information. VOUTLOMON (Pin 26/Pin 38): VOUT Low Voltage Monitor Pin. Connect a ±1% resistor divider between V OUT, VOUTLOMON and GND to set an undervoltage level on VOUT. When VOUT is lower than this level, reverse conduc- tion is disabled to prevent drawing current from VOUT. See the Applications Information section for more information. VINHIMON (Pin 27/Pin 39): VIN High Voltage Monitor Pin. Connect a ±1% resistor divider between VIN, VINHIMON and GND in order to set an overvoltage level on VIN. When VIN is higher than this level, reverse conduction is disabled to prevent current flow into V IN. See the Applications Information section for more information. ICP (Pin 28/Pin 40): Positive VOUT Current Monitor Pin. The current out of this pin is 20μA plus a current pro - portional to the positive average V OUT current. See the Applications Information section for more information. EXTVCC (Pin 29/Pin 42): External VCC Input. When EXTVCC exceeds 6.4V (typical), INTVCC will be powered from this pin. When EXTVCC is lower than 6.4V, the INTVCC will be powered from VINCHIP. CSPOUT (Pin 30/Pin 46) : The (+) Input to the V OUT Current Monitor Amplifier . This pin and the CSNOUT pin measure the voltage across the sense resistor , RSENSE2, to provide the VOUT current signals. Connect this pin to VOUT when not in use. See Applications Information section for proper use of this pin. CSNOUT (Pin 31/Pin 47): The (–) Input to the VOUT Current Monitor Amplifier . Connect this pin to VOUT when not in use. See Applications Information section for proper use of this pin. CSNIN (Pin 32/Pin 52): The (–) Input to the VIN Current Monitor Amplifier . This pin and the CSPIN pin measure the voltage across the sense resistor , RSENSE1, to provide the VIN current signals. Connect this pin to VIN when not in use. See Applications Information section for proper use of this pin. CSPIN (Pin 33/Pin 53): The (+) Input to the V IN Current Monitor Amplifier . Connect this pin to V IN when not in use. See Applications Information section for proper use of this pin. VINCHIP (Pin 34/Pin 55) : Main Input Supply Pin for the LT8708. It must be locally bypassed to ground. INTVCC (Pin 35/Pin 57): 6.3V Regulator Output. Must be connected to the GATEVCC pin. INTVCC is powered from EXTVCC when the EXTV CC voltage is higher than 6.4V, otherwise INTVCC is powered from V INCHIP. Bypass this pin to ground with a minimum 4.7μF ceramic capacitor . SWEN (Pin 36/Pin 58) : Switching Regulator Enable Pin. Tie high through a resistor to enable the switching. Ground to disable switching. This pin is pulled down dur- ing shutdown, a thermal lockout or when an internal UVLO (undervoltage lockout) is detected. Don ’t float this pin. See the Start-Up: SWEN Pin section for more details. MODE (Pin 37/Pin 59): Conduction Mode Select Pin. The voltage applied to this pin sets the conduction mode of the controller . Apply less than 0.4V to enable continuous conduction mode (CCM). Apply 0.8V to 1.2V to enable the hybrid conduction mode (HCM). Apply 1.6V to 2.0V to enable the discontinuous conduction mode (DCM). Apply more than 2.4V to enable Burst Mode operation. IMON_OP (Pin 38/Pin 60): Positive VOUT Current Monitor and Limit Pin. The current out of this pin is 20μA plus a current proportional to the positive average VOUT current. IMON_OP also connects to error amplifier EA6 and can be used to limit the maximum positive VOUT current. See the Applications Information section for more information. IMON_ON (Pin 39/Pin 61): Negative VOUT Current Monitor and Limit Pin. The current out of this pin is 20μA plus a current proportional to the negative average VOUT current. IMON_ON also connects to error amplifier EA2 and can be used to limit the maximum negative VOUT current. See the Applications Information section for more information. LDO33 (Pin 40/Pin 62) : 3.3V Regulator Output. Bypass this pin to ground with a minimum 0.1μF ceramic capacitor . GND (Pin 15/Pin 19, Exposed Pad Pin 41/Pin 65) : Ground. Tie directly to local ground plane. PIN FUNCTIONS (QFN/eLQFP)

Figure 1. Block Diagram

8708 F01

Rev. D For more information www.analog.com OPERATION TYPOGRAPHICAL CONVENTIONS The LT8708 is a high performance 4-switch buck-boost con- troller that includes features to facilitate bidirectional cur- rent and power flow. Using the LT8708, an application can command power to be delivered from VIN to VOUT or from VOUT to VIN as needed. Some terms, listed below, are used throughout this data sheet in reference to the direction of current and power flow. In order to clarify these direction- based concepts, these terms are defined as follows: VIN and IIN: The VIN side of circuits drawn in this data sheet will always be on the left. VIN is con- nected to the SW1 side of the buck-boost inductor through M1. IIN is the VIN current. VOUT and IOUT: The VOUT side of circuits drawn in this data sheet will always be on the right. VOUT is con- nected to the SW2 side of the buck-boost inductor through M4. IOUT is the VOUT current. Supply (Input): Power Source. The power source is most commonly applied to V IN. However , VOUT can be a Supply (or Input) when power is being delivered from VOUT to VIN. Load (Output): Devices that are consuming the power . The Load is most commonly connected to VOUT. However , VIN can connect to the Load (or Output) when power is being delivered from VOUT to VIN. Forward Conduction: Current or power flowing from the V IN or SW1 node (or side) to the V OUT or SW2 node (or side) of the circuit. This is gener- ally left to right on schematics. Reverse Conduction: Current or power flowing from the VOUT or SW2 node (or side) to the VIN or SW1 node (or side) of the circuit. This is general right to left on schematics. Positive Current: Current that flows from the SW1 side of the buck-boost inductor to the SW2 side. Also refers to current that flows from V IN and/ or into VOUT. Reverse Current: Current that flows from the SW2 side of the buck-boost inductor to the SW1 side. Also refers to current that flows from VOUT and/ or into VIN. Refer to the Block Diagram (Figure 1) when reading the following sections about the operation of the LT8708. START-UP Figure 2 illustrates the start-up sequence for the LT8708. Start-Up: SHDN Pin The master shutdown pin for the chip is SHDN. When driven below 0.35V (LT8708E, LT8708I) or 0.3V (LT8708H), the chip is disabled (CHIP OFF state) and quiescent current is minimal. Increasing the SHDN voltage can increase qui- escent current but will not enable the chip until SHDN is driven above 1.221V (typical) after which the INTVCC and LDO33 regulators are enabled (SWITCHER OFF 1 state). External devices powered by LDO33 can become active at this time if enough voltage is available on VINCHIP or EXTVCC to raise INTVCC, and thus LDO33, to an adequate voltage. Start-Up: SWEN Pin The SWEN pin is used to enable the switching regulator after the chip has also been enabled by driving SHDN high. SWEN must be pulled high through a resistor to enable the switching regulator . The typical activation threshold is 1.208V as shown in the Electrical Characteristics sec- tion. When the SWEN pin voltage is below the activation threshold, the CSP-CSN, CSPIN-CSNIN and CSPOUT- CSNOUT current sense circuits on the chip are disabled. SWEN has an internal pull-down that is activated when the switching regulator is unable to operate (see CHIP OFF and SWITCHER OFF 1 states in Figure 2). After the chip is able to operate and SWEN is internally pulled down below 0.8V (typical), the internal SWEN pull-down is disabled and start-up can proceed past the SWITCHER OFF1 state. LDO33 or INTVCC are convenient nodes to pull SWEN up to. Choose a pull-up resistor value that limits the current to less than 200μA when SWEN is pulled low. The SWEN pin can also be digitally driven through a current limiting resistor . Note in the Electrical Characteristics section, the SWEN output low voltage is 0.9V (typical) when SHDN is low and/or VINCHIP is unpowered. The SWEN output low is 0.2V when SHDN is 3V and VINCHIP is powered.

Figure 2. Start-Up Sequence (All Values are Typical)

• SS CHARGES UP
• WHEN SS > 0.2V ...
• SWITCHER ENABLED
• V C SOFT-START
• M1, M4 ON-TIME SOFT-START SWITCHER OFF 2
• SWITCHER DISABLED
• INTVCC AND LDO33 OUTPUTS ENABLED
• SS PULLED LOW NORMAL MODE
• NORMAL OPERATION INITIALIZE SS < 50mV SS > 1.8V
• SS PULLED LOW
• VC FORCED TO COMMAND NEAR ZERO CURRENT LIMIT (INTVCC AND GATEVCC > 4.81V) AND LDO33 > 3.075V AND SWEN > 1.208V TJUNCTION < 160°C AND SHDN > 1.221V AND VINCHIP > 2.5V AND ((INTVCC AND GATEVCC < 4.65V) OR LDO33 < 3.04V) SWITCHER OFF 1
• SWITCHER DISABLED
• INTVCC AND LDO33 OUTPUTS ENABLED
• SWEN AND SS PULLED LOW CHIP OFF SHDN < 1.181V OR VINCHIP < 2.5V OR TJUNCTION > 165°C
• SWITCHER OFF
• LDOs OFF
• SWEN PULLED LOW (INTVCC AND GATEVCC > 4.81V) AND LDO33 > 3.075V AND SWEN < 0.8V

8708 F02

low to prepare for soft-starting the switching regulator . the LT8708 exits soft-start and enters normal operation. from 220nF to 2μF. A minimum of 220nF is recommended. regulation capabilities at both the input and the output. combined output of six internal error amplifiers EA1 – EA6.

and limit the maximum current. conduction mode (see Bidirectional Conduction : CCM). discussed later in their respective Conduction sections. so the transfer between modes is continuous. Figure 3. Simplified Diagram of the Buck-Boost Switches Figure 4. Operating Regions vs VOUT − VIN

8708 F03

0 BUCK/BOOST REGION

8708 F04

respective voltages or currents as shown in Table 1. Table 1. Error Amplifiers (EA1 − EA6) commands the most power flow from VOUT to VIN. (EA5 and EA1, respectively).

the switching waveforms in the buck region. output ripple and reduction in maximum output current. clock cycle. Next, switch M4 turns off and M3 turns on. on, the controller first operates as if in the boost region. Figure 5. Buck Region (VIN >> VOUT)

8708 F05

move to the buck-boost region. Electrical Characteristics).

8708 F06a

8708 F06b

and M1 turns on until the end of the cycle. behaving like a typical synchronous boost regulator . part will move to the buck-boost region. ƒ is the switching frequency. Figure 7. Boost Region (VIN << VOUT) regions discussed above (buck, buck-boost and boost). on as long as the normal switching sequence requires. the ongoing switching operations.

8708 F07

allows power flow from VOUT to VIN. Table 2. Conduction Configurations

1. Before transitioning from MODE = Burst Mode opera-
2. Avoid control pulses on the MODE and DIR pins nar -

rower than 15 LT8708 clock cycles. Applications section as an example. provided in the following sub-sections. average current is delivered to the appropriate output. by driving the DIR pin as desired.

VIN. Higher VC voltage reduces or stops the flow. from VOUT (or VIN) and feeding current into VIN (or VOUT). block negative components of the AC inductor current. (or RHCM) direction of average current flow. average current flow opposite to the desired direction. a 17.4k resistor from ground to the IMON_INP pin. inhibited and above which switching activity is re-enabled. when reverse inductor current is detected. ing to Table 3, with the highest priority being at the top. Table 3. Error Amp Priorities row is removed from Table 3.

Table 4. Automatically Disabled Error Amp Conditions amplifiers are listed below. with the FBIN/VIN voltage regulation. ation of the remaining amplifiers. Use Table 5 as a guide. Table 5. Disabling Unused Amplifiers using a resistor divider between VOUT, FBOUT and ground. R FBOUT1 and RFBOUT2 are shown in Figure 1. and power will flow from VOUT to VIN. power will flow from VIN to VOUT. RVSOFF section for more detailed information.

Rev. D For more information www.analog.com VIN REGULATION AND SENSING T wo pins, FBIN and VINHIMON, are provided to sense the VIN voltage and issue the appropriate response to the switching regulator . VIN: Regulation Subject to the priorities in Table 3, a resistor divider between VIN, FBIN and ground can be used to regulate VIN or serve an undervoltage lockout function. A few applica- tion examples are as follows:

• For VIN supplies with high source impedance (i.e., a solar panel), V IN regulation can prevent the supply voltage from dropping too low under high V OUT load conditions.
• For VIN supplies with low source impedance (i.e., bat- teries and voltage supplies), the FBIN pin can be used to stop switching activity when the VIN supply voltage gets too low for proper system operation.
• V IN can also be regulated to a maximum voltage when power is flowing from VOUT to VIN, such as in a battery backup application. When FBIN falls near or below the EA3 reference (1.205V typical), the VC voltage falls and reduces current draw from VIN. The VIN regulation voltage is given by the equation: VIN = 1.205V • 1+ RFBIN1 RFBIN2 where: R FBIN1 and RFBIN2 are shown in Figure 1. VIN: Above Regulation and Overvoltage When the FBIN pin and EA3 detect VIN is above regulation, VC is allowed to rise. If forward conduction is enabled (CCM, FDCM, FHCM and Burst Mode operation), then cur- rent and power can flow from VIN to VOUT. If only reverse conduction is enabled (RDCM and RHCM), then switching will stop and current won ’t be delivered into V IN. NOTE: This above-regulation condition is required to allow for - ward conduction in an application. A resistor divider between V IN, VINHIMON and ground is used to detect VIN overvoltage. This function prevents reverse conduction, from V OUT to V IN, from forcing V IN higher than desired. When overvoltage is detected by VINHIMON, RVSOFF is pulled low to disable reverse cur- rent and power . This function can be used as an OVLO (over voltage lockout), for example, when a battery, connected to V IN, is being charged from V OUT. See the VINHIMON, VOUTLOMON and RVSOFF section for more detailed information. VIN: Below Regulation When the FBIN pin and EA3 detect that VIN is significantly below regulation, VC may fall to its minimum voltage. The LT8708 responds to the minimum VC voltage according to the conduction mode enabled by MODE, DIR and RVSOFF. If only forward conduction is allowed (FDCM, FHCM and Burst Mode operation) then switching will stop and cur- rent won’t be drawn from V OUT. If reverse conduction is allowed (CCM, RDCM and RHCM), then current and power will flow from VOUT to VIN. UVLO functions are available to detect low V IN voltage. These functions are discussed in the Voltage Lockouts section. CURRENT MONITORING AND LIMITING Monitoring and Limiting: IMON Pins The LT8708 can monitor V IN and V OUT current (I IN and IOUT) in both the positive and negative directions. The CSPIN and CSNIN pins connect across a current sense resistor to monitor I IN. External resistors are connected from the IMON_INP and IMON_INN pins to GND. Their resulting voltages are linearly proportional to positive IIN and negative IIN respectively. See amplifier A3 in the Block Diagram. Similarly, an IOUT sense resistor , measured by CSPOUT and CSNOUT , is used to monitor the VOUT current. External resistors are connected from the IMON_OP and IMON_ON pins to GND. Their resulting voltages are linearly propor- tional to positive IOUT and negative IOUT respectively. See amplifier A1 in the Block Diagram. OPERATION

Rev. DFor more information www.analog.com The IIN and IOUT currents can be limited and regulated to independent maximum positive values. When IIN causes IMON_INP to rise near or above 1.209V (typical), EA5 typically causes V C to pull down and limit/regulate the maximum current. Similarly, when I OUT causes IMON_ OP to rise near or above 1.209V (typical), EA6 typically causes VC to pull down and limit/regulate the maximum current. See Table 3 for error amplifier priorities. The IIN and I OUT currents can also be limited and regu - lated to independent maximum negative values. When IIN causes IMON_INN to rise near or above 1.21V (typical), EA1 causes V C to pull up and limit the maximum cur - rent. Similarly, when IOUT causes IMON_ON to rise near or above 1.21V (typical), EA2 causes V C to pull up and limit the maximum current. The IIN and IOUT current limits can provide many benefits. They can be used to prevent overloading the input sup - ply, allow for constant-current battery and supercapacitor charging and can also serve as short-circuit protection for constant-voltage regulators. See the Applications Information section for more information about the cur - rent monitors and the current regulation and limiting. Monitoring: ICP and ICN Pins ICP and ICN are additional current monitor pins with out- put currents typically equal to those of IMON_OP and IMON_ON, respectively. In contrast to IMON_OP, ICP is internally pulled to ~0.6V (typical) when V C is at its minimum and the conduc - tion mode is either RDCM or RHCM. Also, in contrast to IMON_ON, ICN is internally pulled to ~0.6V (typical) when VC is at its maximum and the conduction mode is FDCM, FHCM or Burst Mode operation. Always connect a 17.4k resistor from ICP to ground and from ICN to ground. INTVCC/EXTVCC/GATEVCC/LDO33 POWER Power for the top and bottom MOSFET drivers, the LDO33 pin and most internal circuitry is derived from the INTVCC pin. INTVCC is regulated to 6.3V (typical) from either the VINCHIP or EXTVCC pin. When the EXTVCC pin is left open or tied to a voltage less than 6.2V (typical), an internal low dropout regulator regulates INTV CC from VINCHIP. If EXTVCC is taken above 6.4V (typical), another low drop- out regulator will instead regulate INTV CC from EXTVCC. Regulating INTVCC from EXTVCC allows the power to be derived from the lowest supply voltage (highest effi - ciency) such as the LT8708 switching regulator output (see INTVCC Regulators and EXTV CC Connection in the Applications Information section for more details). The GATEVCC pin directly powers the bottom MOSFET drivers for switches M2 and M3 (see Figure 3). GATEVCC should always be connected to INTVCC and should not be powered or connected to any other source. Undervoltage lockouts (UVLOs) monitoring INTVCC and GATEVCC dis- able the switching regulator when the pins are below 4.65V (typical). The LDO33 pin can provide power to external compo - nents such as a microcontroller and/or can provide an accurate bias voltage. Load current is limited to 17.25mA (typical). As long as SHDN is high, the LDO33 output is linearly regulated from the INTVCC pin and is not affected by the INTVCC or GATEVCC UVLOs or the SWEN pin volt- age. LDO33 remains regulated as long as SHDN is high and sufficient voltage is available on INTV CC (typically > 4.0V). An undervoltage lockout monitoring LDO33 will disable the switching regulator when LDO33 is below 3.04V (typical). CLKOUT AND TEMPERATURE SENSING The CLKOUT pin toggles at the LT8708’s internal clock frequency whether the internal clock is synchronized to an external source or is free-running based on the external RT resistor . The CLKOUT pin can be used to synchronize other devices to the LT8708’s switching frequency. Also, the duty cycle of CLKOUT is proportional to the die tempera- ture and can be used to monitor the die for thermal issues. OPERATION

details for setting up an application using the LT8708. monitoring, PCB layout and efficiency considerations. the use of the various design equations presented here. 6(b) are provided to help with this verification. of Table 6(a) and highlight or circle the applicable cells.

• VIN_FBIN is the VIN voltage when FBIN is at 1.205V (typ)
• VOUT_FBOUT is the V OUT voltage when FBOUT is at 1.207V (typ)
• VIN_VINHIMON is the V IN voltage when V INHIMON at 1.207V (typ)
• VOUT_VOUTLOMON is the VOUT voltage when VOUTLOMON is at 1.207V (typ) If one or more of the FBIN, FBOUT , VINHIMON and VOUTLOMON pins are tied to their inactive states (see Table 5 and the VINHIMON, VOUTLOMON and RVSOFF section), the associated row(s) or column(s) will not apply to the application. For example, if FBIN is tied to LDO33 to deactivate that pin function, then the V IN < VIN_FBIN row of Table 6(a) is not applicable and no cells in that row should be circled. Next, for each cell identified in Table 6(a), check that the operating condition described in Table 6(b) meets the application’s requirements.

Table 6. Power Flow Verification Table pin is not driven low by an external device. and/or capacitance to maintain low output ripple voltage. following sections provide more details.

Rev. DFor more information www.analog.com INTERNAL OSCILLATOR The operating frequency of the LT8708 can be set using the internal free-running oscillator . When the SYNC pin is driven low (< 0.5V), the operating frequency is set by the value of the resistor from the RT pin to ground. An internally trimmed timing capacitor resides inside the IC. The oscil- lator frequency is calculated using the following formula: fOSC = 43,750 RT +1 ⎠⎟kHz where: f OSC is in kHz and RT is in kΩ. Conversely, RT (in kΩ) can be calculated from the desired frequency (in kHz) using: RT = 43,750 fOSC – 1⎛ ⎠⎟kΩ SYNC PIN AND CLOCK SYNCHRONIZATION The operating frequency of the LT8708 can be synchro- nized to an external clock source. To synchronize to the external source, simply provide a digital clock signal into the SYNC pin. The LT8708 will operate at the SYNC clock frequency. The duty cycle of the SYNC signal must be between 20% and 80% for proper operation. Also, the frequency of the SYNC signal must meet the following two criteria: 1. SYNC may not toggle outside the frequency range of 100kHz to 400kHz unless it is stopped low to enable the free-running oscillator . 2. The SYNC pin frequency can always be higher than the free-running oscillator set frequency, fOSC, but should not be less than 25% below fOSC. After SYNC begins toggling, it is recommended that switching activity is stopped before the SYNC pin stops toggling. Excess inductor current can result when SYNC stops toggling as the LT8708 transitions from the external SYNC clock source to the internal free-running oscillator clock. Switching activity can be stopped by driving either the SWEN or SHDN pin low. CLKOUT PIN AND CLOCK SYNCHRONIZATION The CLKOUT pin can drive up to 200pF and toggles at the LT8708’s internal clock frequency whether the internal clock is synchronized to the SYNC pin or is free-running based on the external R T resistor . The rising edge of CLKOUT is approximately 180° out of phase from the internal clock’s rising edge or the SYNC pin’s rising edge if it is toggling. CLKOUT starts toggling when the INITIALIZE state is entered (see Figure 2). The CLKOUT pin can be used to synchronize other devices to the LT8708’s switching frequency. For example, the CLKOUT pin can be tied to the SYNC pin of another LT8708 regulator which will operate approximately 180°out of phase of the master LT8708. The frequency of the master LT8708 can be set by the external RT resistor or by toggling the SYNC pin. Note that the R T pin of the slave LT8708 must have a resistor tied to ground. In general, use the same value RT resistor for all of the synchronized LT8708s. The duty cycle of CLKOUT is proportional to the die tem- perature and can be used to monitor the die for thermal issues. See the Junction Temperature Measurement sec- tion for more information. INDUCTOR CURRENT SENSING AND SLOPE COMPENSATION The LT8708 operates using inductor current mode con - trol. As described previously in the Power Switch Control section, the LT8708 measures the peak of the inductor current waveform in the boost region and the valley of the inductor current waveform in the buck region. The induc- tor current is sensed across the RSENSE resistor with pins CSP and CSN. During any given cycle, the peak (boost region) or valley (buck region) of the inductor current is controlled by the VC pin voltage. Slope compensation provides stability in constant-fre - quency current mode control architectures by preventing subharmonic oscillations at high duty cycles. This is accom- plished internally by adding a compensating ramp to the inductor current signal in the boost region, or subtracting a ramp from the inductor current signal in the buck region. At higher duty cycles, this results in a reduction of maxi- mum inductor current in the boost region, and an increase APPLICATIONS INFORMATION

Rev. D For more information www.analog.com of the maximum inductor current in the buck region. For example, refer to the Maximum Inductor Current Sense Voltage vs Duty Cycle graph in the Typical Performance Characteristics section. The graph shows that, with VC at its maximum voltage, the maximum peak inductor sense voltage VRSENSE is between 47mV and 93mV depending on the duty cycle. It also shows that the maximum induc- tor valley current in the buck region is 82mV increasing to ~130mV at higher duty cycles. RSENSE SELECTION AND MAXIMUM CURRENT The R SENSE resistance must be chosen properly to achieve the desired amount of output current (forward conduction) and input current (reverse conduction). Too much resistance can limit the input/output current below the application requirements. Start by determin - ing the maximum allowed RSENSE resistances in the for- ward and reverse boost regions (R SENSE(MAX,BOOST ,FWD) and RSENSE(MAX,BOOST ,RVS)). Follow this by finding the maximum allowed R SENSE resistances in the forward and reverse buck regions (R SENSE(MAX,BUCK,FWD) and RSENSE(MAX,BUCK,RVS)). The selected R SENSE resistance must be less than all four values. RSENSE Selection: Max RSENSE in the Boost Region Forward Conduction: In this section RSENSE(MAX,BOOST ,FWD) is calculated which is the maximum allowed RSENSE resis- tance when operating in the boost region with forward conduction (VIN to VOUT). Skip this section and assume RSENSE(MAX,BOOST ,FWD) = ∞ when this operating condition does not apply to the application. In the boost region, the maximum positive VOUT current capa- bility is the lowest when VIN is at its minimum and VOUT is at its maximum. Therefore, RSENSE must be chosen to meet the output current requirements under these conditions. Start by finding the maximum boost region duty cycle which occurs when V IN is minimum and V OUT is maxi - mum using: DC(MAX,M3,BOOST) ≅ VIN(MIN,BOOST) VOUT(MAX,BOOST) ⎠⎟ •100% For example, an application with a V IN range of 12V to 48V and VOUT set to 36V will have: DC(MAX,M3,BOOST) ≅ 1– 12V 36V ⎝⎜ ⎞ ⎠⎟ •100% = 67% Referring to the Maximum Inductor Current Sense Voltage graph in the Typical Performance Characteristics section, the maximum RSENSE voltage at 67% duty cycle is 68mV, or: VRSENSE(MAX,BOOST,MAXDC) ≅ 68mV for VIN = 12V, VOUT = 36V. Next, the inductor ripple current in the boost region must be determined. If the main inductor L is not known, the maximum ripple current ∆IL(MAX,BOOST) can be estimated by choosing ∆IL(MAX,BOOST) to be 30% to 50% of the maximum peak inductor current in the boost region as follows: ∆IL(MAX,BOOST) VOUT(MAX,BOOST) •IOUT(MAX,FWD) VIN(MIN,BOOST) • 100% %Ripple – 0.5 A where: I OUT(MAX,FWD) is the maximum V OUT load current required in the boost region. %Ripple is 30% to 50% For example, using V OUT(MAX) = 36V, V IN(MIN) = 12V, IOUT(MAX,FWD) = 2A and %Ripple = 40% we can calculate: IL(MAX,BOOST) 36V •2A 12V • 100% 40% – 0.5 = 3A APPLICATIONS INFORMATION

Rev. DFor more information www.analog.com Otherwise, if the inductance is already known then ∆IL(MAX,BOOST ,FWD) can be more accurately calculated as follows: ∆IL(MAX,BOOST) = DC(MAX,M3,BOOST) 100% ⎠⎟ •VIN(MIN,BOOST) ƒ •L A where: DC (MAX,M3,BOOST) is the maximum duty cycle percent- age in the boost region as calculated previously ƒ is the switching frequency L is the inductance of the main inductor After the maximum ripple current is known, the maximum allowed RSENSE in the boost region while in forward con- duction (VIN to VOUT) can be calculated as follows: RSENSE(MAX,BOOST,FWD) = 2 •VRSENSE(MAX,BOOST,MAXDC) •VIN(MIN,BOOST) 2 •IOUT(MAX,FWD) •VOUT(MAX,BOOST)( ) + ∆IL(MAX,BOOST) •VIN(MIN,BOOST)( ) Ω where: V RSENSE(MAX,BOOST ,MAXDC) is the maximum inductor current sense voltage as discussed in the previous section. Using values from the previous examples: RSENSE(MAX,BOOST,FWD) = 2 •68mV •12V Reverse Conduction: In this section RSENSE(MAX,BOOST ,RVS) is calculated which is the maximum allowed RSENSE resis- tance when operating in the boost region with reverse conduction (VOUT to VIN). Skip this section and assume RSENSE(MAX,BOOST ,RVS) = ∞ when this operating condition does not apply to the application. In the boost region, the maximum reverse V IN current capability is the lowest when operating at the minimum duty cycle. See Switch Control : Boost Region (V IN << VOUT) section for the equation to calculate the minimum duty cycle DC(ABSMIN, M3, BOOST). Before calculating the maximum RSENSE resistance allowed during reverse operation, however , the inductor ripple cur- rent must be determined. If the main inductor L is not known, the ripple current ∆IL(MIN,BOOST) can be estimated by choosing ∆IL(MIN,BOOST) to be 10% of the minimum peak inductor current in the boost region as follows: ∆IL(MIN,BOOST) IIN(MAX,RVS) 100% 10% – 0.5 A≅  where: I IN(MAX,RVS) is the maximum VIN load current required in the boost region in the reverse direction If the inductance is already known then ∆IL(MIN,BOOST) can be calculated as follows: ∆IL MIN,BOOST( ) = DC(ABSMIN,M3,BOOST) 100% ⎠⎟ •VIN(MIN,BOOST) ƒ •L A where: DC (ABSMIN,M3,BOOST) is the minimum duty cycle per - centage in the boost region (see Switch Control: Boost Region (VIN << VOUT) section) ƒ is the switching frequency L is the inductance of the main inductor Now that the inductor ripple current is known, the maxi- mum allowed RSENSE in the boost region while in reverse conduction can be calculated as follows: RSENSE(MAX,BOOST,RVS) = 2•| VRSENSE(MIN,BOOST,MINDC) | 2 •IIN(MAX,RVS)( ) – ∆IL(MIN,BOOST) Ω APPLICATIONS INFORMATION

Rev. D For more information www.analog.com where: V RSENSE(MIN,BOOST ,MINDC) is the minimum inductor cur- rent sense voltage in the boost region at the minimum duty cycle. Typical value is –93mV. Negative result from the above equation indicates that any RSENSE value can meet the requirement. Substitute the calculated result with ∞ and move onto the next section. RSENSE Selection: Max RSENSE in the Buck Region Forward Conduction: In this section RSENSE(MAX,BUCK,FWD) is calculated which is the maximum allowed RSENSE resis- tance when operating in the buck region with forward conduction (VIN to VOUT). In the buck region, the maximum V OUT current capabil- ity is the lowest when operating at the minimum duty cycle. See Switch Control: Boost Region (V IN << VOUT) section for the equation to calculate the minimum duty cycle DC(ABSMIN, M2,BUCK). Before calculating the maximum RSENSE resistance, how- ever , the inductor ripple current must be determined. If the main inductor L is not known, the ripple current ∆IL(MIN,BUCK) can be estimated by choosing ∆IL(MIN,BUCK) to be 10% of the maximum peak inductor current in the buck region as follows: ∆IL(MIN,BUCK) IOUT(MAX,FWD) 100% 10% – 0.5 A≅  where: I OUT(MAX,FWD) is the maximum V OUT load current required in the buck region in the forward direction. If the inductance is already known then ∆IL(MIN,BUCK) can be calculated as follows: ∆IL MIN,BUCK( ) = DC(ABSMIN,M2,BUCK) 100% ⎠⎟ •VOUT(MIN,BUCK) ƒ •L A where: DC (ABSMIN,M2,BUCK) is the minimum duty cycle percent- age in the buck region as calculated previously ƒ is the switching frequency L is the inductance of the main inductor After the inductor ripple current is known, the maximum allowed RSENSE in the buck region while in forward con- duction can be calculated as follows: RSENSE(MAX,BUCK,FWD) = 2 •VRSENSE(MAX,BUCK,MINDC) 2 •IOUT(MAX,FWD)( ) – ∆IL(MIN,BUCK) Ω where: V RSENSE(MAX,BUCK,MINDC) is the maximum inductor cur- rent sense voltage at the minimum duty cycle. Typical value is 82mV. Negative result from the above equation indicates that any RSENSE value can meet the requirement. Substitute the calculated result with ∞ and move onto the next section. Reverse Conduction: In this section R SENSE(MAX, BUCK, RVS) is calculated which is the maximum allowed RSENSE resistance when operating in the buck region with reverse conduction (VOUT to VIN). Skip this section and assume RSENSE(MAX, BUCK, RVS) = ∞ when this operating condition does not apply to the application. In the buck region, the maximum reverse V IN current capability is the least when V IN is at its maximum and VOUT is at its minimum for buck operation. Therefore RSENSE must be chosen to meet the V IN current require- ments under these conditions. Start by finding the buck region duty cycle when V IN is minimum and VOUT is maximum using: DC(MAX,M2,BUCK) ≅ VOUT(MIN,BUCK) VIN(MAX,BUCK) ⎠⎟ •100% APPLICATIONS INFORMATION

reverse direction required in the buck region. current sense voltage at the maximum duty cycle. (Forward Conduction) section. quency = 120kHz, inductance = 10µH, RSENSE = 1mΩ). inductor currents would vary with VIN/VOUT. Figure 8. Currents vs VIN/VOUT Ratio in Forward Conduction

8708 F08

Figure 10. Inductor Current Sense Filter Figure 9. Currents vs VIN/VOUT Ratio in Reverse Conduction an inductor that meets all of the following criteria. network should be placed as close as possible to the IC.

8708 F09

8708 F10

Rev. DFor more information www.analog.com I OUT(MAX,FWD) is the maximum forward V OUT current in boost region To provide adequate reverse IIN current at low VOUT volt- ages in the buck region, L should be at least: L(MIN1,BUCK) VOUT(MIN,BUCK) • DC(MAX,M2,BUCK) 100% 2•ƒ • |VRSENSE(MIN,BUCK,MAXDC) | RSENSE – IIN(MAX,RVS) •VIN(MAX,BUCK) VOUT(MIN,BUCK) /uni03A9 where: DC (MAX,M2,BUCK) is the maximum duty cycle percentage of the M2 switch (see RSENSE Selection: Max RSENSE in the Buck Region section) ƒ is the switching frequency V RSENSE(MIN,BUCK,MAXDC) is the minimum current sense voltage in the buck region at maximum duty cycle (see RSENSE Selection : Max R SENSE in the Buck Region section) I IN(MAX,RVS) is the maximum reverse V IN current in buck region Negative values of L(MIN1,BOOST) or L(MIN1,BUCK) indicate that the load current can’t be delivered because the induc- tor current limit is too low. If L(MIN1,BOOST) or L(MIN1,BUCK) is too large or is negative, consider reducing the RSENSE resistor value to increase the inductor current limit. L Selection: Subharmonic Oscillations The LT8708’s internal slope compensation circuits will prevent subharmonic oscillations that can otherwise occur when VIN/VOUT is less than 0.5 or greater than 2. The slope compensation circuits will prevent these oscil- lations provided that the inductance exceeds a minimum value (see the earlier section Inductor Current Sensing and Slope Compensation for more information). Choose an inductance greater than all of the relevant L(MIN) limits discussed below. Negative calculation results can be inter- preted as zero. In the boost region, if VOUT can be greater than twice VIN, calculate L(MIN2,BOOST) as follows: L(MIN2,BOOST) = VOUT(MAX,BOOST) – VIN(MIN,BOOST) •VOUT(MAX,BOOST) VOUT(MAX,BOOST) – VIN(MIN,BOOST)

• RSENSE 0.08 •f H In the buck region, if VIN can be greater than twice VOUT, calculate L(MIN2,BUCK) as follows: L(MIN2,BUCK) = VIN(MAX,BUCK) • 1– VOUT(MIN,BUCK) VIN(MAX,BUCK) – VOUT(MIN,BUCK)    
• RSENSE 0.08 •ƒ H L Selection: Maximum Current Rating The inductor must have a rating greater than its maximum operating current to prevent inductor saturation resulting in efficiency loss. The maximum forward inductor current in the boost region is: IL(MAX,BOOST,FWD) ≅IOUT(MAX,FWD) • VOUT(MAX,BOOST) VIN(MIN,BOOST) VIN(MIN,BOOST) • DC(MAX,M3,BOOST) 100% 2 •L •ƒ A where: DC (MAX,M3,BOOST) is the maximum duty cycle per - centage of the M3 switch (see RSENSE Selection and Maximum Current section). APPLICATIONS INFORMATION

Rev. D For more information www.analog.com The maximum reverse inductor current in the boost region for applications in which VOUT(MAX) ≥ 2•VIN(MAX) is: IL(MAX,BOOST,RVS) ≅IIN(MAX,RVS) VIN(MAX,BOOST) 4 •L •ƒ ⎠⎟A For applications in which V OUT(MAX) < 2•VIN(MAX), the maximum reverse inductor current is smaller than the value given by the above equation. The following equation can be used to calculate the reverse inductor current for given combinations of VIN and VOUT. IL(MAX,BOOST,RVS) ≅IIN(MAX,RVS) + VIN •(VOUT – VIN) 2 •L •ƒ •VOUT ⎠⎟A where: V OUT > VIN The maximum positive inductor current in the buck region for applications in which VIN(MAX) ≥ 2•VOUT(MAX) is: IL(MAX,BUCK,FWD) ≅IOUT(MAX,FWD) VOUT(MAX,BUCK) 4 •L •ƒ ⎠⎟A For applications with V IN(MAX) < 2•VOUT(MAX), the maxi- mum forward inductor current is smaller than the value given by the above equation. The following equation can be used to calculate the forward inductor current for given combinations of VIN and VOUT. IL(BUCK,FWD) ≅IOUT(MAX,FWD) + VOUT •(VIN – VOUT ) 2 •L •ƒ •VIN ⎠⎟A where: V IN > VOUT The maximum reverse inductor current when operating in the buck region is: IL(MAX,BUCK,RVS) ≅IIN(MAX,RVS) • VIN(MAX,BUCK) VOUT(MIN,BUCK) VOUT(MIN,BUCK) •DC(MAX,M2,BUCK) 100% 2 •L •ƒ A where: DC (MAX,M2,BUCK) is the maximum duty cycle percent - age of the M2 switch in the buck region (see RSENSE Selection: Max RSENSE in the Buck Region section). Note that the inductor current can be higher when there are load transients or the load current exceeds the expected maximum amount. It can also be higher during start-up if inadequate soft-start capacitance is used, or during output shorts. Consider using the IIN and/or IOUT current limiting to help prevent the inductor current from becom- ing excessive. IIN and IOUT current limiting are discussed later in the IIN and IOUT Current Monitoring and Limiting section. Careful board evaluation of the maximum induc- tor current is recommended. POWER MOSFET SELECTION The LT8708 requires four external N-channel power MOSFETs, two for the top switches (switches M1 and M4, shown in Figure 3) and two for the bottom switches (switches M2 and M3, shown in Figure 3 ). Important parameters for the power MOSFETs are the breakdown voltage VBR,DSS, threshold voltage VGS,TH, on-resistance RDS(ON), output capacitance C OSS, and maximum cur - rent IDS(MAX). The gate drive voltage is set by the 6.3V GATEVCC supply. Consequently, logic-level threshold MOSFETs must be used in LT8708 applications. APPLICATIONS INFORMATION

use MOSFETs that dissipate the least amount of power . various regions of operation. Table 7. NMOS Power in Various Operating Regions

• IOUT where necessary. I2R Component Equations: PI2R[M1,BUCK] or PI2R[M4,BOOST] ≅ VOUT VIN
• IOUT 2 •RDS(ON) •ρτ W PI2R[M1,BOOST] ≅ VOUT VIN
• IOUT
• RDS(ON) •ρτ PI2R[M2,BUCK] ≅ VIN – VOUT VIN
• IOUT 2 •RDS(ON) •ρτ W PI2R[M3,BOOST] ≅ VOUT – VIN VIN 2 •VOUT •IOUT 2 •RDS(ON) •ρτ W PI2R[M4,BUCK] ≅IOUT 2 •RDS(ON) •ρτ W

Figure 11. Normalized MOSFET RDS(ON) vs Temperature t RF1 is the average of the SW1 pin rise and fall times. capacitance and VIN voltage. on the MOSFET capacitance and VOUT voltage. 125°C, using a value = 1.5 is reasonable. smallest, VOUT is highest and M1 is always on. is highest, VOUT is lowest and M4 is always on.

8708 F11

Rev. DFor more information www.analog.com Gate Resistors: In some cases it can be beneficial to add 1Ω to 10Ω of resistance between some of the NMOS gate pins and their respective gate driver pins on the LT8708 (i.e., TG1, BG1, TG2, BG2). Due to parasitic inductance and capacitance, ringing can occur on SW1 or SW2 when low capacitance MOSFETs are turned on/off too quickly. The ringing can be of greatest concern when operating the MOSFETs or the LT8708 near the rated voltage lim - its. Additional gate resistance slows the switching speed, minimizing the ringing. Excessive gate resistance can have two negative side effects on performance: 1. Slowing the switch transition times can also increase power dissipation in the switch. This is described above. 2. Capacitive coupling from the SW1 or SW2 pin to the switch gate node can turn it on when it ’s supposed to be off, thus increasing power dissipation. With too much gate resistance, this would happen to the M2 switch when SW1 is rising with positive inductor cur- rent and to the M3 switch when SW2 is rising with negative inductor current. Careful board evaluation should be performed when optimizing the gate resistance values. SW1 and SW2 pin ringing can be affected by the inductor current levels, therefore board evaluation should include measurements at a wide range of load currents, VIN and VOUT. When per- forming PCB measurements of the SW1 and SW2 pins, be sure to use a very short ground post from the PCB ground to the scope probe ground sleeve in order to minimize false inductive voltage readings. CIN AND COUT SELECTION VIN and VOUT capacitance is necessary to suppress volt- age ripple caused by discontinuous current moving in and out of the regulator . A parallel combination of capaci- tors is typically used to achieve high capacitance and low ESR (equivalent series resistance). Dry tantalum, special polymer , aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Capacitors with low ESR and high ripple current ratings, such as OS-CON and POSCAP are also available. Ceramic capacitors should be placed near the regulator input and output to suppress high frequency switching spikes. A ceramic capacitor , of at least 1μF at the maxi - mum VINCHIP operating voltage, should also be placed from V INCHIP to GND as close to the LT8708 pins as possible. Due to their excellent low ESR characteristics ceramic capacitors can significantly reduce input ripple voltage and help reduce power loss in the higher ESR bulk capacitors. X5R or X7R dielectrics are preferred, as these materials retain their capacitance over wide volt - age and temperature ranges. Many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired operating voltage. VIN Capacitance: Discontinuous VIN current is highest in the buck region due to the M1 switch toggling on and off. Make sure that the CIN capacitor network has low enough ESR and is sized to handle the maximum RMS current. For buck operation, the VIN RMS current is given by: I(IN,RMS) ≅IOUT •VOUT VIN

• VIN VOUT – 1 A This formula has a maximum at V IN = 2•VOUT, where I(IN,RMS) = IOUT/2. This simple worst-case condition is commonly used for design because even significant devi- ations do not offer much relief. CIN is necessary to reduce the V IN voltage ripple caused by discontinuities and ripple of IIN. The effects of ESR and the bulk capacitance must be considered when choosing the correct capacitor for a given VIN ripple. The VIN ripple due to the voltage drop across the bulk cap ESRBULK, without having any ceramic capacitance in parallel, is approximately: ∆V(IN,BUCK,BULK) ≅IOUT •ESRBULK V APPLICATIONS INFORMATION

Rev. D For more information www.analog.com When low ESR ceramic capacitance is added in parallel with the bulk capacitor , the VIN ripple is approximately: ∆V(IN,BUCK,CERAM) ≅ IOUT • VOUT VIN

• ESRCERAM • 1– exp – VOUT VIN •ƒ •ESRCERAM •CIN–CERAM ⎠⎟V Add enough ceramic capacitance to make sure ∆V(IN,BUCK,CERAM) is adequate for the application. In a properly designed application, ∆V(IN,BUCK,CERAM) should be much smaller than ∆V(IN,BUCK,BULK) . VOUT Capacitance: Discontinuous VOUT current is highest in the boost region due to the M4 switch toggling on and off. Make sure that the C OUT capacitor network has low enough ESR and is sized to handle the maximum RMS current. For boost operation, the V OUT RMS current is given by: I(OUT,RMS) ≅IOUT • VOUT VIN – 1 A This formula has a maximum when VIN is minimum and VOUT is maximum. COUT is necessary to reduce the V OUT ripple caused by discontinuities and ripple of IOUT. The effects of ESR and the bulk capacitance must be considered when choosing the right capacitor for a given VOUT ripple. The VOUT ripple due to the voltage drop across the bulk cap ESR without having any ceramic caps in parallel is approximately: ∆V(OUT,BOOST,BULK) ≅ VOUT •IOUT VIN
• ESRBULK ∆V(OUT,BUCK,BULK) ≅IRIPPLE •ESRBULK With enough ceramic caps added in parallel, the steady state VOUT ripple due to charging and discharging the ceramic COUT is given by the following equations: ∆V(OUT,BOOST,CERAM) ≅ IOUT •ESRCERAM • 1– exp VIN – VOUT VOUT •ƒ •ESRCERAM •COUT–CERAM ⎠⎟V for VOUT > VIN, and ∆V(OUT,BUCK,CERAM) ≅ VOUT • 1– VOUT VIN 8 •L •ƒ2 •COUT–CERAM V for VOUT < VIN Add enough ceramic caps to make sure ∆V(OUT ,BOOST ,CERAM) and ∆V(OUT ,BUCK,CERAM) are adequate for the application. In a properly designed application, ∆V(OUT ,BOOST ,CERAM) and ∆V(OUT ,BUCK,CERAM) should be much smaller than ∆V(OUT ,BOOST ,BULK) and ∆V(OUT ,BUCK,BULK), respectively. SCHOTTKY DIODE (D1, D2, D3, D4) SELECTION During forward conduction the Schottky diodes, D2 and D4, shown in Figure 1 , conduct during the dead time between the conduction of the power MOSFET switches. They help to prevent the body diodes of synchronous switches M2 and M4 from turning on and storing charge. For example, D4 can significantly reduce reverse-recovery current when M3 turns on, which improves converter effi- ciency, reduces switch M3 power dissipation, and reduces noise in the inductor current sense resistor (R SENSE). Similarly, during reverse conduction, D1 and D3 conduct during the dead time between the conduction of the power MOSFET switches. In order for the diodes to be effective, the inductance between them and the synchronous switch must be as small as possible, mandating that these com- ponents be placed very close to the MOSFETs. APPLICATIONS INFORMATION

Rev. DFor more information www.analog.com For applications with high input or output voltages (typi- cally >40V) avoid Schottky diodes with excessive reverse- leakage currents, particularly at high temperatures. Some ultra-low VF diodes will trade-off increased high tempera- ture leakage current for reduced forward voltage. Diodes D1 and D2 can have reverse voltages in excess of VIN and D3 and D4 can have reverse voltages in excess of V OUT. The combination of high reverse voltage and current can lead to self-heating of the diode. Besides reducing effi - ciency, this can increase leakage current which increases temperatures even further . Choose packages with lower thermal resistance (θJA) to minimize self heating of the diodes. TOPSIDE MOSFET DRIVER SUPPL Y (CB1, DB1, CB2, DB2) The top MOSFET drivers (TG1 and TG2) are driven digi- tally between their respective SW and BOOST pin volt - ages. The BOOST voltages are biased from floating booststrap capacitors CB1 and CB2, which are normally recharged through external silicon diodes DB1 and DB2 when the respective top MOSFET is turned off. The capaci- tors are charged to about 6.3V (about equal to GATEVCC) forcing the VBOOST1-SW1 and VBOOST2-SW2 voltages to be about 6.3V. The boost capacitors CB1 and CB2 need to store about 100 times the gate charge required by the top switches M1 and M4. In most applications, a 0.1μF to 0.47μF, X5R or X7R dielectric capacitor is adequate. The bypass capacitance from GATEVCC to GND should be at least 10 times the CB1 or CB2 capacitance. Top Driver: Boost Cap Charge Control Block When the LT8708 operates exclusively in the boost or buck region, M1 or M4 respectively may be “on” con- tinuously. This prevents the respective bootstrap capaci- tor , CB1 or CB2, from being recharged through the silicon diode, DB1 or DB2. The Boost Cap Charge Control block (see Figure 1) keeps the appropriate bootstrap capacitor charged in these cases. In the boost region, when M1 is always on, current is drawn, as needed, from the CSNOUT and/or BOOST2 pins to charge the CB1 capacitor . In the buck region, when M4 is always on, current is drawn, as needed, from the CSNIN and/or BOOST1 pins to charge the CB2 capacitor . Because of this function, CSPIN and CSNIN should be connected across RSENSE1 in series with the M1 drain. Connect both pins to the M1 drain if they are not being used. Also, CSPOUT and CSNOUT should be connected across RSENSE2 in series with the M4 drain or connect both to the M4 drain if not being used. Top Driver: Boost Diodes DB1 and DB2 Although Schottky diodes have the benefit of low forward voltage drops, they can exhibit high reverse current leak- age and have the potential for thermal runaway under high voltage and temperature conditions. Silicon diodes are thus recommended for diodes DB1 and DB2. Make sure that DB1 and DB2 have reverse breakdown voltage ratings higher than V IN(MAX) and V OUT(MAX) and have less than 1mA of reverse-leakage current at the maximum operating junction temperature. Make sure that the reverse-leakage current at high operating temperatures and voltages won’t cause thermal runaway of the diode. In some cases it is recommended that up to 5Ω of resis- tance is placed in series with DB1 and DB2. The resistors reduce surge currents in the diodes and can reduce ring- ing at the SW and BOOST pins of the IC. Since SW pin ringing is highly dependent on PCB layout, SW pin edge rates and the type of diodes used, careful measurements directly at the SW pins of the IC are recommended. If required, a single resistor can be placed between GATEVCC and the common anodes of DB1 and DB2 (as in the front page application) or by placing separate resistors between the cathodes of each diode and the respective BOOST pins. Excessive resistance in series with DB1 and DB2 can reduce the BOOST-SW capacitor voltage when the M2 or M3 on-times are very short and should be avoided. VINHIMON, VOUTLOMON AND RVSOFF During reverse conduction, current and power are drawn from VOUT and delivered to V IN. This has the potential to draw V OUT lower than desired or drive V IN higher than desired, depending on the supplies and loads. The VINHIMON and VOUTLOMON pins are used to detect either of these conditions and disable reverse conduc - tion by pulling RVSOFF low. APPLICATIONS INFORMATION

Rev. D For more information www.analog.com The purpose of the VINHIMON and VOUTLOMON func - tions becomes clearer when considering the priorities of the error amplifiers (see Table 3). A few important cases should be considered. 1. VIN and VOUT are both above regulation: In this case FBIN is greater than 1.205V while FBOUT is greater than 1.207V. Normally this condition causes V C to fall due to FBOUT being above 1.207V. The LT8708 responds by increasing the reverse current and power being fed into VIN. This can be an undesirable response, for example, if VIN is connected to a battery being charged from VOUT. The solution is to use VINHIMON to detect the maxi - mum VIN and disable reverse conduction by pulling RVSOFF low. 2. VIN and VOUT are both below regulation: In this case FBIN is below 1.205V while FBOUT is below 1.207V. Normally this condition causes V C to fall due to FBIN being below 1.205V. The LT8708 responds by increasing the reverse current and power being drawn from VOUT . This can be an undesirable response, for example, if VOUT is connected to a battery or supercapacitor sup- plying power to VIN. The solution is to use VOUTLOMON to detect the minimum VOUT and disable reverse con- duction by pulling RVSOFF low. If VINHIMON rises above its activation threshold or VOUTLOMON falls below its activation threshold (see RVSOFF pin low and not allow M4 switch to turn on if the inductor current is negative. In addition to the 24mV (typical) voltage hysteresis, the VINHIMON pin will source 1μA (typical) current and the VOUTLOMON pin will sink 1μA (typical) current as current hysteresis. There are two ways to configure the VINHIMON and VOUTLOMON pins. Method (1) uses dedicated resistor dividers for VINHIMON and VOUTLOMON respectively, while method (2) uses common resistor dividers for VINHIMON and FBIN as well as for VOUTLOMON and FBOUT , allowing improved tracking with the FBOUT and FBIN regulation voltages, respectively. 1. Connect a resistor divider between V IN, VINHIMON and GND to configure the V IN overvoltage thresh - old. Connect a resistor divider between V OUT, VOUTLOMON and GND to configure the V OUT under- voltage threshold. (see Figure 12 ). Use the following equations to calculate the resistor values : RHIMON1 = VOVIN+ – 1.207 IFBDIV RHIMON2 = 1.207 IFBDIV RHIMON3 = 1.207 – VHYSMON IHYSMON ⎠⎟ – RHIMON1 •RHIMON2 RHIMON1 +RHIMON2 – VOVIN– •RHIMON2 IHYSMON •(RHIMON1 +RHIMON2) RLOMON1 = VUVOUT– – 1.207 IFBDIV RLOMON2 = 1.207 IFBDIV RLOMON3 = VUVOUT+ •RLOMON2 IHYSMON •(RLOMON1 +RLOMON2) – RLOMON1 •RLOMON2 RLOMON1 +RLOMON2 ⎠⎟ – 1.207 + VHYSMON IHYSMON where: I FBDIV is the desired current through the resistor string. 50μA – 100μA is a good value. V OVIN+ and VOVIN– are the rising and falling V IN over- voltage thresholds. V UVOUT+ and VUVOUT– are the rising and falling V OUT undervoltage thresholds. R HIMON1-3 and RLOMON1-3 are shown in Figure 12. V HYSMON is the VINHIMON and VOUTLOMON hyster - esis voltage. Typical value is 24mV. I HYSMON is the VINHIMON and VOUTLOMON hysteresis current. Typical value is 1μA. APPLICATIONS INFORMATION

• RIN3 RIN4 = [(RIN1 +RIN2) •IHYSMON + VOVIN+ – VOVIN– ]•1.207 VOVIN+ •IHYSMON – VHYSMON IHYSMON ⎠⎟ – (VOVIN+ – 1.207) •RIN3 VOVIN+ ROUT3 = 1.207 IFBDIV ROUT1 = VOUT•ROUT3 • 1 1.207 – 1 VUVOUT– ROUT2 = (VOUT – VUVOUT– ) VUVOUT–
• ROUT3 ROUT4 = (ROUT1 •IHYSMON + VUVOUT + – VUVOUT– ) •1.207 VUVOUT– •IHYSMON – VHYSMON IHYSMON ⎠⎟ – (VUVOUT– – 1.207) •ROUT3 VUVOUT– where: I FBDIV is the desired current through the resistor string. 50μA – 100μA is a good value. V IN and VOUT are the desired regulation voltages. V OVIN+ and VOVIN– are the rising and falling V IN over- voltage thresholds. APPLICATIONS INFORMATION Figure 12.

Figure 13. Single Divider for VINHIMON and FBIN

8708 F13

8708 F14

8708 F12

Figure 14. Single Divider for VOUTLOMON and FBOUT

1. Connect a resistor divider between V IN, FBIN,

voltage thresholds (see Figure 14).

R IN1-4 and ROUT1-4 are shown in Figure 13 and Figure 14. esis voltage. Typical value is 24mV. current. Typical value is 1μA. their maximum, respectively. pin and device names as appropriate. increasing as IIN becomes more negative. Figure 16. IOUT Current Monitor and Limit

8708 F15

8708 F16

Figure 15. IIN Current Monitor and Limit

Rev. DFor more information www.analog.com T ransconductance amplifier A3 performs this monitoring function. A3 converts the current sense voltage, V CSPIN- CSNIN, into two currents: +VCSPIN-CSNIN •1m A V and –VCSPIN-CSNIN •1m A V These currents are added to 20μA offsets and then forced into RIMON_INP and RIMON_INN, respectively. Due to the 20μA offset currents, VIMON_INP and VIMON_ INN are not 0V when I IN is 0A. Instead, VIMON_INP(0) = 20μA•RIMON_INP Volts and VIMON_INN(0) = 20μA•RIMON_INN Volts (typical) when IIN = 0 Amps. As IIN becomes increas- ingly negative, VIMON_INP reduces below VIMON_INP(0) until VIMON_INP = 0V. Similarly, as I IN becomes increasingly positive, VIMON_INN reduces below VIMON_INN(0) until VIMON_INN = 0V. IMON_INP and IMON_INN will not be driven below ground as their output currents can only be posi - tive or zero. The complete transfer functions for IMON_INP and IMON_INN are given in the equations below: VIMON_INP = 1m A V •RSENSE1 •IIN + 20µA⎛ ⎝⎜ ⎞ ⎠⎟ •RIMON_INP VIMON_INN = –1m A V •RSENSE1 •IIN + 20µA⎛ ⎝⎜ ⎞ ⎠⎟ •RIMON_INN The differential voltage V CSPIN-CSNIN should remain between –100mV and 100mV due to the limited current that can be driven out of IMON_INP and IMON_INN. If the instantaneous VCSPIN-CSNIN exceeds these limits but the average VCSPIN-CSNIN is within the limits, consider includ- ing the current sense filter described in the next section. In addition, IMON_INP and IMON_INN should be filtered with capacitors CIMON_INP and CIMON_INN due to IIN ripple and discontinuities that can occur in various regions of operation. A few nF of capacitance is usually sufficient. APPLICATIONS INFORMATION Current Limiting: As shown in Figure 15, IMON_INP volt- age that exceeds 1.209V (typical) causes V C to reduce, thus limiting the forward I IN and inductor currents. IMON_INN voltage that exceeds 1.21V (typical) causes VC to increase, thus limiting the reverse IIN and inductor currents (see the Error Amplifiers section). The forward IIN limit, I(IN,FWD,LIMIT), can be set as needed by choosing the appropriate RSENSE1 and RIMON_INP resis- tors using the following equation: RIMON_INP = 1.209 I(IN,FWD,LIMIT) •1m A V •RSENSE1 + 20µA Ω For example, if RSENSE1 is chosen to be 12.5mΩ and the desired forward IIN current limit is 4A then: RIMON_INP = 1.209 4A •1m A V •12.5mΩ+ 20µA = 17.3kΩ Similarly, the reverse IIN limit, I(IN,RVS,LIMIT), can be set as needed by choosing the appropriate RSENSE1 and RIMON_ INN resistors using the following equation: RIMON_INN = 1.21 I(IN,RVS,LIMIT) •1m A V •RSENSE1 + 20µA Ω CIMON_INP and CIMON_INN capacitors of at least a few nF are necessary to maintain loop stability when IMON_INP and IMON_INN, respectively, are used to operate the LT8708 at constant current limit. Review the Electrical Characteristics and the IMON Output Currents graph in the Typical Performance Characteristics section to understand the operational limits of the IMON_ OP, IMON_ON, IMON_INP and IMON_INN currents. External currents can be summed to the IMON pins to adjust IIN and/or IOUT limit in both directions while switch- ing. When the IMON_OP and IMON_ON pins are used in

Figure 17. CSPIN/CSNIN and CSPOUT/CSNOUT

8708 F17

current when VCSPIN-CSNIN is below –20mV. 100mV while keeping the same average. IMON_ON pins should be grounded when not in use. value of the series capacitor to filter high frequency noise. ation to determine the optimum value.

Rev. DFor more information www.analog.com Also note that CIMON_INP and CIMON_INN capacitors of at least a few nF are necessary to maintain loop stability when IMON_INP and IMON_INN, respectively, are used to operate the LT8708 at constant current limit. INTVCC REGULATORS AND EXTVCC CONNECTION The LT8708 features two PNP LDOs (low dropout regu - lators) that regulate the 6.35V (typical) INTVCC pin from either the V INCHIP or EXTV CC supply pin. INTV CC pow- ers the MOSFET gate drivers via the required GATEV CC connection and also powers the LDO33 pin regulator and much of the LT8708’s internal control circuitry. The INTVCC LDO selection is determined automatically by the EXTVCC pin voltage. When EXTVCC is lower than 6.2V (typ- ical), INTVCC is regulated from the VINCHIP pin LDO. After EXTVCC rises above 6.4V (typical), INTVCC is regulated by the EXTVCC pin LDO instead. Overcurrent protection circuitry typically limits the maxi- mum current draw from either LDO to 127mA. When GATEVCC and INTV CC are below 4.65V, during start-up or during an overload condition, the typical current limit is reduced to 42mA. The INTVCC pin must be bypassed to ground with a minimum 4.7μF ceramic capacitor placed as close as possible to the INTV CC and GND pins. An additional ceramic capacitor should be placed as close as possible to the GATEVCC and GND pins to provide good bypassing to supply the high transient current required by the MOSFET gate drivers. 1μF to 4.7μF is recommended. Power dissipated in the INTVCC LDOs must be minimized to improve efficiency and prevent overheating of the LT8708. Since LDO power dissipation is proportional to the supply voltage and VINCHIP can be as high as 80V in some applica- tions, the EXTVCC pin is available to regulate INTVCC from a lower supply voltage. The EXTVCC pin is connected to VOUT in many applications since VOUT is often regulated to a much lower voltage than the maximum VINCHIP. During start-up, power for the MOSFET drivers, control circuits and the LDO33 pin is usually derived from VINCHIP until VOUT/EXTVCC rises above 6.4V, after which the power is derived from VOUT/ EXTVCC. This works well, for example, in a case where VOUT is regulated to 12V and the maximum VINCHIP voltage is 40V. EXTVCC can be floated or grounded when not in use or can also be connected to an external power supply if available. The following list summarizes the three possible connec- tions for EXTVCC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from VINCHIP through the internal 6.3V regulator at the cost of a small efficiency penalty. 2. EXTVCC connected directly to VOUT (VOUT > 6.4V). This is the normal connection for the regulator and usually provides the highest efficiency. 3. EXTVCC connected to an external supply. If an external supply is available greater than 6.4V (typical) it may be used to power EXTVCC. Powering INTVCC from EXTVCC can also provide enough gate drive when VINCHIP drops as low as 2.8V. This allows the part to operate with a reduced V INCHIP voltage after VOUT gets into regulation. The maximum current drawn through the INTV CC LDO occurs under the following conditions: 1. Large (capacitive) MOSFETs are being driven at high frequencies. 2. VIN and/or VOUT is high, thus requiring more charge to turn the MOSFET gates on and off. 3. The LDO33 pin output current is high. 4. In some applications, LDO current draw is maximum when the part is operating in the buck-boost region where VIN is close to VOUT since all four MOSFETs are switching. To check for overheating find the operating conditions that consume the most power in the LT8708 (PL T8708). This will often be under the same conditions just listed that maximize LDO current. Under these conditions monitor the CLKOUT pin duty cycle to measure the approximate die temperature. See the Junction Temperature Measurement section for more information. LDO33 REGULATOR The LT8708 includes a low dropout regulator (LDO) to regulate the LDO33 pin to 3.3V. This pin can be used to power external circuitry such as a microcontroller or other desired peripherals. The input supply for the LDO33 pin regulator is INTVCC. Therefore INTVCC must have sufficient APPLICATIONS INFORMATION

Rev. D For more information www.analog.com voltage, typically > 4.0V, to properly regulate LDO33. The LDO33 and INTVCC regulators are enabled by the SHDN pin and are not affected by SWEN. The LDO33 pin regu - lator has overcurrent protection circuitry that typically limits the output current to 17.25mA. An undervoltage lockout monitors LDO33 and disables switching activity when LDO33 falls below 3.04V (typical). LDO33 should be bypassed locally with 0.1μF or more. VOL TAGE LOCKOUTS The LT8708 contains several voltage detectors to make sure the chip is under proper operating conditions. Table 8 summarizes the pins that are monitored and also indicates the state that the LT8708 will enter if an under or over voltage condition is detected. Table 8. Voltage Lockout Conditions Information: VINHIMON, VOUTLOMON and RVSOFF VOUTLOMON <1.207V RVSOFF <1.209V FBIN <1.205V Voltage Lockouts The conditions are listed in order of priority from top to bottom. If multiple over/undervoltage conditions are detected, the chip will enter the state listed highest on the table. Due to their accurate thresholds, configurable under - voltage lockouts (UVLOs) can be implemented using the SHDN and SWEN and in some cases, FBIN pin. The UVLO function sets the turn on/off of the LT8708 at a desired minimum voltage. For example, a resistor divider can be connected between VIN, SHDN and GND as shown in Figure 1. From the Electrical Characteristics, SHDN has the Start-Up: SWEN Pin section for additional information. switching activity will not be accompanied by a soft-start.

Rev. DFor more information www.analog.com where DCCLKOUT is the CLKOUT duty cycle in % and T J is the die junction temperature in °C. The actual die tem- perature can deviate from the above equation by ±10°C. THERMAL SHUTDOWN If the die junction temperature reaches approximately 165°C, the part will go into thermal shutdown. The power switches will be turned off and the INTV CC and LDO33 regulators will be turned off (see Figure 2). The part will be re-enabled when the die temperature has dropped by ~5°C (nominal). After re-enabling, the part will start in the SWITCHER OFF 1 state as shown in Figure 2. The part will then INITIALIZE, perform a SOFT-START , then enter NORMAL OPERATION as long as the die tempera - ture remains below approximately 165°C. EFFICIENCY CONSIDERATIONS The efficiency of a switching regulator is equal to the out- put power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, three main sources account for most of the losses in LT8708 circuits. These and a few additional loss components are listed below: 1. Switching losses. These losses arise from the brief amount of time the switches ( M1 – M4) spend in the saturated region during switch node transitions. Power loss depends upon the input voltage, load cur- rent, driver strength and MOSFET capacitance, among other factors. See the Power MOSFET Selection section for more details. 2. DC I2R losses. These arise from the resistances of the MOSFETs (M1 – M4), sensing resistors, inductor and PC board traces and cause the efficiency to drop at high currents. 3. INTVCC current. This is the sum of the MOSFET driver current, LDO33 pin current and control currents. The INTVCC regulator’s input voltage times the current rep- resents lost power . This loss can be reduced by sup- plying INTVCC current through the EXTVCC pin from a APPLICATIONS INFORMATION high efficiency source, such as the output or alternate supply if available. Also, lower capacitance MOSFETs can reduce INTVCC current and power loss. 4. CIN and COUT loss. The C IN capacitor has the difficult job of filtering the large RMS input current to the regu- lator in buck mode. The C OUT capacitor has the more difficult job of filtering the large RMS output current in boost mode. Both C IN and COUT are required to have low ESR to minimize the AC I2R loss and have sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. 5. Other losses. Schottky diodes D1, D2, D3 and D4 are responsible for conduction losses during dead time and light load conduction periods. Inductor core loss occurs predominately at light loads. Hybrid conduction mode (HCM) can be used to improve the efficiency when large inductor current ripples are present in DCM. See the Unidirectional Conduction: HCM section for details. When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If one makes a change and the input current decreases, then the efficiency has increased. If there is no change in input current, then there is no change in efficiency. CIRCUIT BOARD LAYOUT CHECKLIST The basic circuit board layout requires a dedicated ground plane layer . Also, for high current, a multilayer board pro- vides heat sinking for power components.

• The ground plane layer should not have any traces and should be as close as possible to the layer with the power MOSFETs.
• The high di/dt path formed by switch M1, switch M2, D1, RSENSE and the C IN capacitor should be compact with short leads and PC trace lengths. The high di/dt path formed by switch M3, switch M4, D2 and the COUT capacitor also should be compact with short leads and PC trace lengths. T wo layout examples are shown in Figure 18 (a) and (b).

Figure 18. Switches Layout

• Avoid running signal traces parallel to the traces that carry high di/dt current because they can receive induc- tively coupled voltage noise. This includes the SW1, SW2, TG1 and TG2 traces to the controller .
• Use immediate vias to connect the components (includ- ing the LT8708’s GND pins) to the ground plane. Use several vias for each power component.
• Minimize parasitic SW pin capacitance by removing GND, VIN and VOUT copper from underneath the SW1 and SW2 regions.
• Except under the SW pin regions, flood all unused areas on all layers with copper . Flooding with copper will reduce the temperature rise of power components. Connect the copper areas to a DC net (i.e., quiet GND) with many vias. The more vias the board has, the better heat conduction it has.
• Partition the power ground from the signal ground. The small-signal component grounds should not return to the IC GND through the power ground path.
• Place switch M2 and switch M3 as close to the con - troller as possible, keeping the GND, BG and SW traces short.
• Minimize inductance from the sources of M2 and M3 to RSENSE by making the trace short and wide.
• Keep the high dv/dt nodes SW1, SW2, BOOST1, BOOST2, T G1 and T G2 away from sensitive small- signal nodes.
• The output capacitor (–) terminals should be connected as closely as possible to the (–) terminals of the input capacitor .
• Connect the top driver boost capacitor CB1 closely to the BOOST1 and SW1 pins. Connect the top driver boost capacitor CB2 closely to the BOOST2 and SW2 pins.
• Connect the C IN and C OUT capacitors closely to the power MOSFETs. These capacitors carry the MOSFET AC current in the boost and buck regions.
• Connect the FBOUT , FBIN, VINHIMON and VOUTLOMON pin resistor dividers to the (+) terminals of C OUT and CIN, respectively. Small FBOUT/FBIN/VINHIMON/ VOUTLOMON bypass capacitors may be connected closely to the LT8708’s GND pin if needed. The resis- tor connections should not be along the high current or noise paths.
• Route current sense traces (CSP/CSN, CSPIN/CSNIN, CSPOUT/CSNOUT) together with minimum PC trace APPLICATIONS INFORMATION GND VOUT COUT L RSENSE

8708 F18

with Kelvin connections at the RSENSE resistors.

• Connect the VC pin compensation network closely to the IC, between VC and the signal ground pins. The capaci- tor helps to filter the effects of PCB noise and output voltage ripple voltage from the compensation loop.
• Connect the INTVCC and GATEVCC bypass capacitors close to the IC. The capacitors carry the MOSFET driv- ers’ current peaks.
• Run the trace from the LT8708’s SW1/SW2 pin to the drain of M2/M3 in parallel with the trace from the GATEVCC capacitor’s GND to the C IN GND. Route the traces (as much as possible) directly above/below one another on adjacent layers and in such a way that they carry currents in opposite directions.
• Attention is required when making the PCB layout for RSENSE1 and RSENSE2, especially for sense resistor val- ues smaller than 5mΩ. Improper PCB layout can yield significant errors in the sense voltage. HOT PLUGGING CONSIDERATIONS When connecting a battery to an LT8708 application, there can be significant inrush current due to charge equalization between the partially charged battery stack and the charger output capacitors. To a lesser extent a similar effect can occur when connecting a powered DC supply to the input or output. The magnitude of the inrush current depends on (1) the battery or supply voltage, (2) ESR of the input or output capacitors, (3) initial voltage of the capacitors, and (4) cable impedance. Excessive inrush current can lead to sparking that can compromise con - nector integrity and/or voltage overshoot that can cause electrical overstress on LT8708 pins. Excessive inrush current can be mitigated by first con - necting the battery or supply to the charger through a resistive path, followed quickly by a short circuit. This can be accomplished using staggered length pins in a multi-pin connector . Alternatively, consider the use of a APPLICATIONS INFORMATION Hot Swap controller such as the LT1641, LT4256, etc. to make a current limited connection. DESIGN EXAMPLE VIN = 8V to 25V VIN_FBIN = 12V (VIN regulation voltage set by FBIN loop) VOUT_FBOUT = 12V (VOUT regulation voltage set by FBOUT loop) IOUT(MAX,FWD) = 5A IIN(MAX,RVS) = 3A ƒ = 150kHz This design operates in CCM. Maximum ambient temperature = 60°C Power Flow Verification : Determine which conditions in Table 6(a) apply to this application. In this design example, the VINHIMON and VOUTLOMON are disabled, therefore the conditions highlighted in blue in the copy of Table 6(a) apply to this application.

Table 9. A Copy of Table 6(a)

Rev. D For more information www.analog.com Verify expected operation by combining Table 6(a) and Table 6(b):

• When VIN < VIN_FBIN (12V) and VOUT > VOUT_FBOUT (12V) B – power is transferred from VOUT to VIN
• When VIN < VIN_FBIN (12V) and VOUT < VOUT_FBOUT (12V) B – power is transferred from VOUT to VIN
• When VIN > VIN_FBIN (12V) and VOUT > VOUT_FBOUT (12V) C – power is transferred from VOUT to VIN
• When VIN > VIN_FBIN (12V) and VOUT < VOUT_FBOUT (12V) D – power is transferred from VIN to VOUT The results above are as expected for this design example. RT Selection: Choose the RT resistor for the free-running oscillator frequency using: RT = 43,750 fOSC – 1⎛ ⎠⎟kΩ = 43,750 150 – 1⎛ ⎝⎜ ⎞ ⎠⎟ = 290.7kΩ We will choose 294k for RT resistor . RSENSE Selection: Start by calculating the maximum and minimum duty cycle in the boost region: DC(MAX,M3,BOOST) ≅ VIN(MIN,BOOST) VOUT(MAX,BOOST) ⎠⎟ •100% = 1– 8V 12V ⎝⎜ ⎞ ⎠⎟ •100% = 33% DC(ABSMIN,M3,BOOST) ≅ tON(M3,MIN) •ƒ •100% = 200ns •150kHz •100% = 3% Next, from the Maximum Inductor Current Sense Voltage vs Duty Cycle graph in the Typical Performance Characteristics section: V RSENSE(MAX,BOOST ,MAXDC) ≅ 83mV V RSENSE(MIN,BOOST ,MINDC) ≅ 93mV Next, estimate the inductor current ripples at maximum and minimum boost duty cycles: ∆IL(MAX,BOOST) VOUT(MAX,BOOST) •IOUT(MAX,FWD) VIN(MIN,BOOST) • 100% %Ripple – 0.5 A = 12V •5A 8V • 100% 40% – 0.5 =3.75A ∆IL(MIN,BOOST) IIN(MAX,RVS) 100% 10% – 0.5 A = 3A 100% 10% – 0.5 =0.32A Now calculate the maximum R SENSE values in the boost region: APPLICATIONS INFORMATION

Rev. DFor more information www.analog.com RSENSE(MAX,BOOST,FWD) = 2 •VRSENSE(MAX,BOOST,MAXDC) •VIN(MIN,BOOST) 2 •IOUT(MAX,FWD) •VOUT(MAX,BOOST)( ) + ∆IL(MAX,BOOST) •VIN(MIN,BOOST)( ) Ω = 2 •83mV •8V RSENSE(MAX,BOOST,RVS) = 2•| VRSENSE(MIN,BOOST,MINDC) | 2•|IIN(MAX,RVS) |( ) – ∆IL(MIN,BOOST) Ω = 2 •93mV Next, calculate the maximum and minimum duty cycle in the buck region: DC(ABSMIN,M2,BUCK) ≅ tON(M2,MIN) •ƒ •100% = 200ns •150kHz •100% = 3% DC(MAX,M2,BUCK) ≅ VOUT(MIN,BUCK) VIN(MAX,BUCK) ⎠⎟ •100% = 1– 12V 25V ⎝⎜ ⎞ ⎠⎟ •100% = 52% Next, from the Maximum Inductor Current Sense Voltage vs Duty Cycle graph in the Typical Performance Characteristics section: V RSENSE(MAX,BUCK,MINDC) ≅ 100mV V RSENSE(MIN,BUCK,MAXDC) ≅ 82mV Next, estimate the inductor current ripples at maximum and minimum buck duty cycles: ∆IL(MIN,BUCK) IOUT(MAX,FWD) 100% 10% – 0.5 A = 5A 100% 10% – 0.5 =0.526A ∆IL(MAX,BUCK) VIN(MAX,BUCK) •IIN(MAX,RVS) VOUT(MIN,BUCK) • 100% %Ripple – 0.5 A = 25V •3A 12V • 100% 40% – 0.5 =3.125A Now calculate the maximum R SENSE values in the buck region: RSENSE(MAX,BUCK,FWD) = 2 •VRSENSE(MAX,BUCK,MINDC) 2 •IOUT(MAX,FWD)( ) – ∆IL(MIN,BUCK) Ω = 2 •100mV RSENSE(MAX,BUCK,RVS) = 2•| VRSENSE(MIN,BUCK,MAXDC) | •VOUT(MIN,BUCK) 2•|IIN(MAX,RVS) | •VIN(MAX,BUCK)( ) + ∆IL(MAX,BUCK) •VOUT(MIN,BUCK)( ) Ω = 2 •82mV •12V APPLICATIONS INFORMATION

Rev. D For more information www.analog.com Choose the smallest calculated RSENSE and add an addi- tional 30% margin, choose R SENSE to be 10.5mΩ/1.3 = 8.1mΩ Inductor Selection : With R SENSE known, we can now determine the minimum inductor value that will provide adequate load current in the boost region using: L(MIN1,BOOST) ≅ VIN(MIN,BOOST) • DC(MAX,M3,BOOST) 100% 2•ƒ • VRSENSE(MAX,BOOST,MAXDC) RSENSE – IOUT(MAX,BOOST) •VOUT(MAX,BOOST) VIN(MIN,BOOST) H 8V • 33% 100% ⎝⎜ ⎞ 2•150kHz • 83mV 8.1mΩ – 5A •12V ⎝⎜ ⎞ =3.2µH To avoid subharmonic oscillations in the inductor current, choose the minimum inductance according to: L(MIN2,BOOST) = VOUT(MAX,BOOST) – VIN(MIN,BOOST) •VOUT(MAX,BOOST) VOUT(MAX,BOOST) – VIN(MIN,BOOST)

• RSENSE 0.08 •ƒ H 12V – 8V •12V 12V – 8V ⎝⎜ ⎞ ⎦⎥•8.1mΩ 0.08 •150kHz = –8.1µH L(MIN1,BUCK) = VIN(MAX,BUCK) 1– VOUT(MAX,BUCK) VIN(MAX,BUCK) – VOUT(MIN,BUCK)
• RSENSE 0.08 •ƒ H = 25V • 1– 12V 25V –12V ⎝⎜ ⎞ ⎦⎥•8.1mΩ 0.08 •150kHz =1.3µH The inductance must be higher than all of the minimum values calculated above. We will choose a 10μH standard value inductor for improved margin. MOSFET Selection: The MOSFETs are selected based on voltage rating, C OSS and R DS(ON) value. It is important to ensure that the part is specified for operation with the available gate voltage amplitude. In this case, the amplitude is 6.3V and MOSFETs with an R DS(ON) value specified at VGS = 4.5V can be used. Select M1 and M2: With 25V maximum input voltage, MOSFETs with a rating of at least 30V are used. As we do not yet know the actual thermal resistance (circuit board design and airflow have a major impact) we assume that the MOSFET thermal resistance from junction to ambient is 50°C/ W. If we design for a maximum junction temperature, TJ(MAX) = 125°C, the maximum allowable power dissipation can be calculated. First, calculate the maximum power dissipation: PD(MAX) = TJ(MAX) – TA(MAX) RTH(JA) PD(MAX) = 125°C – 60°C 50 °C W = 1.3W Since maximum I2R power in the boost region with posi- tive inductor current happens when VIN is minimum, we can determine the maximum allowable R DS(ON) for the boost region using (see Table 7): PM1= PI2R ≅ VOUT VIN
• IOUT(MAX,FWD)
• RDS(ON) •ρτ W and therefore RDS(ON) < 13W 12V 8V •5
• 1.5 =15.4m/uni03A9 A The Fairchild FDMS7672 meets the specifications with a maximum RDS(ON) of ~6.9mΩ at VGS = 4.5V (~10mΩ at 125°C). The maximum dissipation in M2 occurs at maximum VIN voltage when the circuit is operating in the buck region APPLICATIONS INFORMATION

Rev. DFor more information www.analog.com in the reverse direction. Using the 6.9mΩ Fairchild FDMS7672, the dissipation is (see Table 7): PM2 ≅PI2R +PSWITCHING ≅ VIN – VOUT VIN

• IOUT(MAX,RVS)2 •RDS(ON) •ρτ + VIN •IOUT(MAX,RVS) •ƒ •tRF1( ) + 0.5 •COSS(M1+M2) •VIN 2 •ƒ( ) W P(M2,MAX) ≅ 25V – 12V ⎝⎜ ⎞ + 25V •3A •150kHz •20ns( ) = 0.13W + 0.225W + 0.064W = 0.419W To check the power dissipation in the buck region with VIN maximum and V OUT minimum, choose the equation from Table 7 with positive inductor current in buck mode which yields: PM1 ≅PI2R +PSWITCHING ≅ VOUT VIN
• IOUT(MAX,FWD)
• RDS(ON) •ρτ + VIN •IOUT(MAX,FWD) •ƒ •tRF1( ) + 0.5 •COSS(M1+M2) •VIN 2 •ƒ( ) W P(M1,MAX) ≅ 12V 25V •5A⎛ ⎝⎜ ⎞
• 6.9mΩ •1.5 + 25V •5A •150k •20ns( ) = 0.06W + 0.38W + 0.064W = 0.504W The maximum switching power of 0.38W can be reduced by choosing a slower switching frequency. Since this cal- culation is approximate, measure the actual rise and fall times on the PCB to obtain a better power estimate. Select M3 and M4: With 12V output voltage we need MOSFETs with 20V or higher rating. The highest dissipation of M3 and M4 occurs in the boost region. For switch M3, the max dissipation occurs when the IOUT is highest in the forward direction and V IN is at the minimum 8V (see Table 7): PM3 ≅PI2R +PSWITCHING ≅ (VOUT – VIN) •VOUT VIN 2 •IOUT(MAX,FWD)2 •RDS(ON) •ρτ + VOUT 2 •IOUT(MAX,FWD) •ƒ •tRF2 VIN + 0.5 •COSS(M3+M4) •VOUT 2 •ƒ( ) W For switch M4, the max dissipation occurs when the IIN is highest in the reverse direction and V IN is highest in the boost region (see Table 7): PM4 ≅PI2R +PSWITCHING ≅ VIN VOUT
• IIN(MAX,RVS)2 •RDS(ON) •ρτ + VOUT •IIN(MAX,RVS) •ƒ •tRF2( ) + 0.5 •COSS(M3+M4) •VOUT 2 •ƒ( ) W and VIN(MAX,BOOST) VOUT(MAX,BOOST) = 1– DC(ABSMIN,M3,BOOST) therefore, APPLICATIONS INFORMATION

Rev. D For more information www.analog.com PM4 ≅PI2R +PSWITCHING = (1– DC(ABSMIN,M3,BOOST)) •IIN(MAX,RVS) + VOUT •IIN(MAX,RVS) •ƒ •tRF2( ) + 0.5 •COSS(M3+M4) •VOUT 2 •ƒ( ) W The Fairchild FDMS7672 can also be used for M3 and M4. Assuming 20ns rise and fall times, the calculated power loss is then 0.48W for M3 and 0.21W for M4. Select R SENSE2, RIMON_OP and RIMON_ON : The IOUT(MAX,FWD) = 5A and IIN(MAX,RVS) = 3A, with a 20%mar- gin, the IOUT current limit is set to 6A in the forward and the IIN current limit is set to 3.6A in the reverse directions, respectively. Choose RIMON_OP to be 17.4k, so that the VCSPOUT-CSNOUT limit becomes 50mV, and the RSENSE2 is calculated to be: RSENSE2 = 50mV 6A ≅8mΩ Using the equation given in the I IN and I OUT Current Monitoring and Limiting section, RIMON_ON is calculated to be: RIMON_ON = 1.21 I(OUT,RVS,LIMIT) •1m A V •RSENSE2 + 20µA Ω = 1.21 3.6A •1m A V •8mΩ+ 20µA = 24.9kΩ VOUT Voltage: VOUT voltage is 12V. Select R FBOUT2 as 20k. RFBOUT1 is: RFBOUT1 = VOUT 1.207V – 1⎛ ⎝⎜ ⎞ ⎠⎟ •RFBOUT2 Select RFBOUT1 as 178k. Both RFBOUT1 and RFBOUT2 should have a tolerance of no more than 1%. VIN Voltage: Input voltage is 12V. Select RFBIN2 as 20k. RFBIN1 is: RFBIN1 = VIN 1.207V – 1⎛ ⎝⎜ ⎞ ⎠⎟ •RFBIN2 Select RFBIN1 as 178k. Both R FBIN1 and R FBIN2 should have a tolerance of no more than 1%. Capacitors: A low ESR ( 5mΩ) capacitor network with 30μF ceramic capacitors for CIN is selected. In this mode, the maximum ripple is: ∆V(BUCK,CAP) ≅ IOUT(MAX,FWD) •VOUT VIN

• ESRCERAM • 1– exp – VOUT VIN •ƒ •ESRCERAM •CIN–CERAM ≅5A •12V 24V •5mΩ
• 1– exp –12V 24V •150kHz •5mΩ •30µF = 12.5mV Having 5mΩ of ESR with 66μF ceramic capacitor for the COUT network sets the maximum output voltage ripple at: ∆V(Boost,CAP) ≅ IOUT(MAX,FWD) •ESRCERAM • 1– exp VIN – VOUT VOUT •ƒ •ESRCERAM •COUT–CERAM ≅5A •5mΩ
• 1– exp 8V –12V 12V •150kHz •5mΩ •66µF = 25mV APPLICATIONS INFORMATION

Rev. DFor more information www.analog.com TYPICAL APPLICATIONS12V Bidirectional Dual Battery System with FHCM & RHCM CSPOUT CSNOUT EXTVCC VOUTLOMON FBOUT INTVCC GATEVCC IMON_ON IMON_OP ICN ICP IMON_INP IMON_INN CLKOUTSYNCSSRTVCMODE CSNIN TG1 BOOST1 SW1 BG1 CSP CSN L T8708 GND BG2 SW2 BOOST2TG2 CSPIN VINCHIP SHDN FBIN VINHIMON SWEN LDO33 DIR RVSOFF 120kHz FWD (3V)RVS (0V) DB1 DB2 TO BOOST1 TO BOOST2 TO DIODE DB1 LD033 VBAT2

8708 TA03a

CIN3, COUT3: 220/uni03BCF , 50V CIN1, COUT2: 22µF , 50V , X7R CIN2, COUT1: 10µF , 50V , X7R M5–M6: T2N7002AK, TOSHIBA *SEE UNI AND BIDIRECTIONAL CONDUCTION SECTION FOR MORE DETAILS.DB1, DB2: CENTRAL SEMI CMMR1U-02-L TE L1: 3.3/uni03BCH, WURTH 701014330 XOR: DIODES INC. 74AHC1G86SE-7 M1–M4: INFINEON BSC010N04LS POWER TRANFER DECISION LOGIC 100k 27.4k 12.1k XOR68.1k 220pF 4.7/uni03BCF 127k 100k 54.9k 680pF 10nF 10k 365k 1/uni03BCF 4.7nF 23.7k22nF 17.4k 17.4k 4.7nF 4.7nF 22nF 4.7nF 17.4k 17.4k 23.7k 4.7/uni03BCF 3.3Ω 12.1k 4.7/uni03BCF 133k 100nF 47nF 100Ω 100k 681k 20k 154k 100k COUT3 COUT2COUT1 2mΩ 1Ω0.22/uni03BCF M2 M3 3.3/uni03BCH 1Ω2mΩ 10Ω 10Ω 1nF 1nF1Ω0.22/uni03BCF1Ω CIN3 CIN2 CIN1 2mΩ 1/uni03BCF 100nF 47nF 100Ω 100k 665k 93.1k Reverse Operation (DIR = 0V)Forward Operation (DIR = 3V) VBAT1 10V TO 16V VBAT2 10V TO 16V 12.1k 93.1k 12.1k 133k FBIN PREVENT DISCHARGING VBAT1 BELOW 10.5V CHARGE VBAT2 TO 14.5V FBOUT LIMIT VBAT2 CHARGING CURRENT TO 15A 2mΩ 2mΩ POWER FLOW

8708 TA03b

12.1k 93.1k 20k 154k FBIN PREVENT DISCHARGING VBAT2 BELOW 10.5V CHARGE VBAT1 TO 14.6V VOUTLOMON LIMIT VBAT1 CHARGING CURRENT TO 15A 2mΩ POWER FLOW

8708 TA03c

2mΩ 100k 27.4k LD033 RVS (0V) 100k

Rev. D For more information www.analog.com APPLICATIONS INFORMATION Table of Operation Modes and Power Flow Directions CONDITIONS RESUL TS VBAT1 VBAT2 DIR POWER FLOW CHIP OPERATES IN RVSOFF* <VBAT1_DEAD – No Power Flow Shutdown – <VBAT2_DEAD No Switching <VBAT1_UV >VBAT2_DEAD Hi FHCM >VBAT1_UV >14.5V >VBAT2_DEAD and <14.5V Power Flows from VBAT1 to VBAT2 (VBAT2 Charging) >VBAT1_DEAD >VBAT2_DEAD and <VBAT2_UV Lo No Power Flow RHCM Lo >14.6V >VBAT2_UV Hi >VBAT1_DEAD and <14.6V >VBAT2_UV Power Flows from VBAT2 to VBAT1 (VBAT1 Charging) *For use with LT8708-1(s) VBAT1 Charge Voltage = 14.6V (FBIN in RHCM) VBAT2_UV to Stop Discharging = 10.5V (VOUTLOMON Falling) or 11.7V (VOUTLOMON Rising) VBAT2 Charge Voltage = 14.5V (FBOUT in FHCM) VBAT1 Charging Current Limit = 15A (IMON_INN) VBAT1_DEAD = 9V (Falling) or 9.4V (Rising) VBAT2 Charging Current Limit = 15A (IMON_OP) VBAT2_DEAD = 9.25V (Falling) or 9.4V (Rising) Frequency = 120kHz VBAT1_UV to Stop Discharging = 10.5V (FBIN in FHCM) Direction Change with VBAT1 = 13.5V and VBAT2 = 13.5V Direction Change with VBAT1 = 13.5V and VBAT2 = 16V Direction Change with VBAT1 = 16V and VBAT2 = 13.5V VBAT1 Charging Lead Acid Battery VBAT2 VBAT2 Charging Lead Acid Battery VBAT1 V BAT2 I OUT CHARGING TIME (HOURS) V BAT2 (V) I OUT (A) BAT2

8708 TA03g

V BAT1 I IN CHARGING TIME (HOURS) V BAT1 (V) I IN (A) BAT1

8708 TA03h

12V Bidirectional Dual Battery System with FHCM & RHCM Details

Rev. DFor more information www.analog.com APPLICATIONS INFORMATION 48V to 12V Bidirectional Dual Battery System with FHCM & RHCM Reverse Operation (DIR = 0V)Forward Operation (DIR = 3V) CSPOUT CSNOUT EXTVCC VOUTLOMON FBOUT INTVCC GATEVCC IMON_ON IMON_OP ICN ICP IMON_INP IMON_INN CLKOUTSYNCSSRTVCMODE CSNIN TG1 BOOST1 SW1 BG1 CSP CSN L T8708 GND BG2 SW2 BOOST2TG2 CSPIN VINCHIP SHDN FBIN VINHIMON SWEN LDO33 DIR RVSOFF 120kHz FWD (3V)RVS (0V) DB1 DB2 TO BOOST1 TO BOOST2 TO DIODE DB1 LD033 VBAT2

8708 TA04a

(MAX 36V FOR LOAD DUMP VBAT1 24V TO 55V BATTERY TO DIODE DB2 LD033 IOUTIIN M3–M4: INFINEON BSC010N04LS CIN3: 220/uni03BCF , 100V COUT3: 330/uni03BCF , 40V CIN1, COUT2, CIN2, COUT1: 10µF , 100V , X7R M5–M7: T2N7002AK, TOSHIBA *SEE UNI AND BIDIRECTIONAL CONDUCTION SECTION FOR MORE DETAILS.DB1, DB2: CENTRAL SEMI CMMR1U-02-L TE L1: 10/uni03BCH, SER2918H-103KL XOR: DIODES INC. 74AHC1G86SE-7 M1–M2: INFINEON BSC026N08NS5 POWER TRANFER DECISION LOGIC 100k 16.9k 18.2k XOR68.1k 220pF 4.7/uni03BCF 127k 100k 54.9k 220pF 5.6nF 12.1k 365k 1/uni03BCF 4.7nF 30.1k10nF 17.4k 17.4k 10nF 10nF 4.7nF 4.7nF 17.4k 13.3k 23.7k 4.7/uni03BCF 3.3Ω 12.1k 4.7/uni03BCF 133k 1/uni03BCF 100k 681k 12.1k 93.1k 178k COUT3COUT2COUT1 2mΩ 1Ω0.22/uni03BCF M2 M3 10/uni03BCH 1Ω1.5mΩ 10Ω 10Ω 1nF 1nF 3.3nF 1Ω0.22/uni03BCF1Ω CIN3 CIN2 CIN1 5mΩ 1/uni03BCF 20k 340k 340k VBAT1 24V TO 55V VBAT2 10V TO 16V 18.2k 340k 12.1k 133k FBIN PREVENT DISCHARGING VBAT1 BELOW 24V CHARGE VBAT2 TO 14.5V FBOUT LIMIT VBAT2 CHARGING CURRENT TO 15A 5mΩ 2mΩ POWER FLOW

8708 TA04b

18.2k 340k 12.1k 93.1k FBIN PREVENT DISCHARGING VBAT2 BELOW 10.5V CHARGE VBAT1 TO 48V VOUTLOMON LIMIT VBAT1 CHARGING CURRENT TO 4A 5mΩ POWER FLOW

8708 TA04c

2mΩ 17.8k 16.9k LD033 RVS (0V) 100k

Rev. D For more information www.analog.com APPLICATIONS INFORMATION Direction Change with VBAT1 = 47.5V and VBAT2 = 14V Direction Change with VBAT1 = 55V and VBAT2 = 14V Direction Change with VBAT1 = 47.5V and VBAT2 = 36V Efficiency VBAT1 Charging Lead Acid Battery VBAT2 30ms/DIV 8708 TA04d DIR 5V/DIV IL 20A/DIV IIN 10A/DIV IOUT 20A/DIV 30ms/DIV 8708 TA04e DIR 5V/DIV IL 20A/DIV IOUT 10A/DIV IIN 20A/DIV 30ms/DIV 8708 TA04f DIR 5V/DIV IL 20A/DIV IIN 5A/DIV IOUT 20A/DIV CHARGIN V BAT2 CHARGING V BAT1 VBAT1 (V) VBAT2 (V) 100 EFFICIENCY (%) EFFICIENCY

8708 TA04g

V BAT2 I OUT CHARGING TIME (HOURS) V BAT2 (V) I OUT (A) V BAT2

8708 TA04h

VBAT1 Charge Voltage = 48V (FBIN in RHCM) VBAT2_UV to Stop Discharging = 10.5V (VOUTLOMON Falling) or 12.3V (VOUTLOMON Rising) VBAT2 Charge Voltage = 14.5V (FBOUT in FHCM) VBAT1 Charging Current Limit = 4A (IMON_INN) VBAT1_DEAD = 21.3V (Falling) or 22.2V (Rising) VBAT2 Charging Current Limit = 15A (IMON_OP) VBAT2_DEAD = 9.25V (Falling) or 9.4V (Rising) Frequency = 120kHz Table of Operation Modes and Power Flow Directions CONDITIONS RESUL TS VBAT1 VBAT2 DIR POWER FLOW CHIP OPERATES IN RVSOFF* <VBAT1_DEAD – No Power Flow Shutdown – <VBAT2_DEAD No Switching <VBAT1_UV > VBAT2_DEAD Hi FHCM >VBAT1_UV >14.5V >VBAT2_DEAD and <14.5V Power Flows from VBAT1 to VBAT2 (VBAT2 Charging) >VBAT1_DEAD >VBAT2_DEAD and <VBAT2_UV Lo No Power Flow RHCM Lo >48V >VBAT2_UV Hi >VBAT1_DEAD and <48V >VBAT2_UV Power Flows from VBAT2 to VBAT1 (VBAT1 Charging) *For use with LT8708-1(s) 48V to 14V Bidirectional Dual Battery System with FHCM & RHCM Details

Rev. DFor more information www.analog.com 52V Battery Backup Supply Using FHCM and RHCM When VIN Is Not Applied, VLOAD Is Regulated to 47.4V Until VBAT Drops Below 36VWhen VIN Is Applied, VBAT Is Charged to 52.1V APPLICATIONS INFORMATION CSPOUT CSNOUT VINCHIP SHDN FBOUT INTVCC GATEVCC IMON_ON IMON_OP ICN ICP IMON_INP IMON_INN CLKOUTSYNCSSRTVC MODE CSNIN TG1 BOOST1 SW1 BG1 CSP CSN L T8708 GND BG2 SW2 BOOST2TG2 CSPIN EXTVCC FBIN VINHIMON SWEN LDO33 DIR RVSOFF 150kHz VOUTLOMON DB1 DB2 TO BOOST1 TO BOOST2 TO DIODE DB1 VBAT

8708 TA05a

VOL TAGE: 52.1V VLOAD TO DIODE DB2 L1: 10/uni03BCH, WURTH 701014101 M1–M4: INFINEON BSC039N06NS CIN1: 1200/uni03BCF , 100V COUT3: 220/uni03BCF , 100V CIN2, CIN3h, COUT1, COUT2: 4.7µF , 100V , X7R M5: TOSHIBA T2N7002AK DIN: APPROPRIATE 8A SCHOTTKY DIODE OR IDEAL DIODE SUCH AS L TC4357. DB1, DB2: CENTRAL SEMI CMMR1U-02-L TE VIN 52V DIN TO LOADS (REGULATE TO 47.4V WHEN IN BACKUP) 127k 54.9k 220pF 6.8nF 24.9k 294k 1/uni03BCF 6.8nF 26.7k22nF 17.4k 17.4k 6.8nF 6.8nF 22nF 17.4k 17.4k 4.7/uni03BCF 4Ω 10k 4.7/uni03BCF 422k 1/uni03BCF 10k 294k COUT3COUT2COUT1 10mΩ 2Ω0.22/uni03BCF M2 M3 10/uni03BCH 2Ω5mΩ 10Ω 10Ω 1nF 1nF2Ω0.22/uni03BCF2Ω CIN1 CIN3 CIN2 5mΩ 0.73k 11.3k 464k 84.5k 100k 100k 4.7/uni03BCF 100k VBAT 37.5V TO 52.1V 10k 422k CHARGE VBAT TO 52.1V LIMIT VBAT CHARGING CURRENT TO 5A 10mΩ 10mΩ POWER FLOW

8708 TA05b

TO 52.1V 10k 294k PREVENT DISCHARGING VBAT BELOW 35V LIMIT VLOAD CURRENT TO 5A WHEN POWERED BY VBAT 10mΩ 10mΩ POWER FLOW

8708 TA05c

47.4V LOADS SHDN0.73k 11.3k 464k REGULATE VLOAD TO 47.4V

Rev. D For more information www.analog.com APPLICATIONS INFORMATION T ransient Behavior Upon VIN Dropout, VBAT = 52V T ransient Behavior Upon VIN Dropout, VBAT = 53V T ransient Behavior Upon VIN Dropout, VBAT = 38V 52V Battery Backup Supply Using FHCM and RHCM Detail Table of Operation Modes and Power Flow Directions CONDITIONS RESUL TS VLOAD VBAT POWER FLOW CHIP OPERATES IN RVSOFF DIR – <VBAT_DEAD No Power Flow Shutdown – – >50.2V* >52.1V VBAT_DEAD to 52.1V Power Flows from VIN to VBAT (VBAT Charging) FHCM Lo HiFell Into (47.4V to 50.2V) Range* >52.1V No Power FlowFell Into (45.9V to 47.4V) Range* >VBAT_DEAD Rose Into (47.4V to 50.2V) Range* RHCM Hi LoRose Into (45.9V to 47.4V) Range Power Flows from VBAT to VLOAD (Backup Operation)<45.9V *VLOAD is powered from VIN. VBAT Charge Voltage = 52.1V (FBOUT in FHCM) VLOAD Rising to Activate VBAT Charging = 50.2V (VINHIMON Rising Activating FHCM) VLOAD Regulation Voltage = 47.4V (FBIN in RHCM) VLOAD Falling to Activate Backup Operation = 45.9V (VINHIMON Falling Activating RHCM) VBAT_DEAD = 36V (Falling) or 37.5V (Rising) VBAT Charging Current Limit = 5A (IMON_OP) Frequency = 150kHz VLOAD Current Limit = 5A (IMON_INN) 3ms/DIV 8708 TA05d DIR 5V/DIV VLOAD 5V/DIV VIN 5V/DIV IL 5A/DIV 3ms/DIV 8708 TA05e DIR 5V/DIV VLOAD 5V/DIV VIN 5V/DIV IL 10A/DIV 3ms/DIV 8708 TA05f DIR 5V/DIV VLOAD 5V/DIV VIN 5V/DIV IL 5A/DIV

Rev. DFor more information www.analog.com Supercapacitor Backup Supply Using CCM When VIN Is Not Applied, VLOAD Is Regulated to 11VWhen VIN Is Applied, VOUT Is Charged to 15V APPLICATIONS INFORMATION 10k 115k REGULATE CAPACITOR TO 15V LIMIT CAPACITOR CHARGING CURRENT TO 1A 25mΩ 25mΩ POWER FLOW

8708 TA06b

1.2k CSC CSPOUT CSNOUT EXTVCC FBOUT INTVCC GATEVCC IMON_OP IMON_INP IMON_ON IMON_INN CLKOUTSYNCSSRTVCMODE CSNIN TG1 L T8708 TG2 CSPIN VINCHIP SHDN FBIN VINHIMON VOUTLOMON SWEN LDO33 RVSOFF DIR 350kHz ICN ICP BOOST1 SW1 BG1 CSP CSN GND BG2 SW2 BOOST2 VIN 12V CIN1 CIN2 DIN LD033 COUT1 1.2k COUT2 CSC VOUT 15V

8708 TA06a

5.6nF 124k 1µF 220pF 15k 22nF 6.8nF 17.4k 22nF 26.7k 6.8nF 17.4k 17.4k DB1 DB2 TO BOOST1 TO BOOST2 4Ω4.7µF 10k 4.7µF 100Ω 1µF 47nF 115k 25mΩ TO DIODE DB1 TO DIODE DB2 0.22µF 2Ω5mΩ 10Ω 1nF 1nF 10Ω0.22µF M3M2 2.2/uni03BCH TO LOADS (REGULATE TO 11V WHEN IN BACKUP) 25mΩ 100Ω 1µF 4.7µF 71.5k162k 20k20k 20k 200k 150k 50k 50k M1–M4: INFINEON BSC050NE2LS CIN1, COUT2: 220/uni03BCF , 35V 35HVP220M CIN2, COUT1: 22µF , 25V , TDK C4532X741E226M CSC: 60F , 2.5V COOPER BUSSMAN HB1840-2R5606-R DIN: APPROPRIATE 2A SCHOTTKY DIODE OR IDEAL DIODE SUCH AS L TC4358, L TC4412, L TC4352, ETC. DB1, DB2: CENTRAL SEMI CMMR1U-02-L TE L1: 2.2 /uni03BCH, VISHAY IHLP-5050CE-01-2R2-M-01 25mΩ 25mΩ POWER FLOW

8708 TA06c

1.2k ×6REGULATE LOADS TO 11V PREVENT CHARGING LOADS > 13.3V

Rev. D For more information www.analog.com APPLICATIONS INFORMATION Charging VOUT to 15V with 1A Current T ransient Behavior Upon VIN Dropout (ILOAD = 4A) Supercapacitor Backup Supply Using CCM Detail VOUT Charge Voltage = 15V (FBOUT) VBACKUP Overvoltage Rising Threshold in Backup Operation = 13.3V (VINHIMON Rising) VBACKUP Regulation Voltage = 11V (FBIN) VBACKUP Overvoltage Falling Threshold in Backup Operation = 12.9V (VINHIMON Falling) VIN_MIN = 5.42V (Falling) or 5.65V (Rising) VOUT Charging Current Limit = 1A (IMON_OP) Frequency = 350kHz VIN Current Limit = 2A (IMON_INP) Table of Operation Modes and Power Flow Directions VBACKUP VOUT POWER FLOW CHIP OPERATES IN RVSOFF* <VIN_MIN – NO POWER FLOW Shutdown – >13.3V >15V CCM Lo<15V Power Flows from VIN to VOUT (VOUT Charging)Fell Into (12.9V to 13.3V) Range >15V No Power Flow Rose Into (12.9V to 13.3V) Range <15V Power Flows from VOUT to LOADS (Backup Operation) HiPower Flows from VIN to VOUT (VOUT Charging)>11V and <12.9V >15V Power Flows from VOUT to LOADS (Backup Operation)<11V and >VIN_MIN – *For use with LT8708-1(s) 20s/DIV 8708 TA06d VIN 5V/DIV VOUT 5V/DIV IL 5A/DIV 3s/DIV 8708 TA06e VOUT 5V/DIV VBACKUP 5V/DIV IL 5A/DIV

Rev. DFor more information www.analog.com PACKAGE DESCRIPTION 5.00 ±0.10 PIN 1 TOP MARK 133 2222 2115 BOTTOM VIEW—EXPOSED PAD 3.10 ±0.10 0.675 REF 0.55 REF 5.85 ±0.10

0.75 TYP

× 4 8.00 ±0.10 R = 0.125 TYP (UHG) QFN 0417 REV A

1.00 TYP

0.20 REF

0.40 ±0.05 0.25 ±0.05

0.50 BSC

NOTE: 1. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES IN DEGREES. 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. COPLANARITY SHALL NOT EXCEED 0.08MM. 3. WARPAGE SHALL NOT EXCEED 0.10MM. 4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC(S). 5. REFER JEDEC M0-220. C 0.35 40-Lead Plastic QFN (5mm × 8mm) (Reference LTC DWG # 05-08-1528 Rev A) 4034 TERMINAL THICKNESS DETAIL A 0.00 – 0.05 0.203 ±0.008 DETAIL B DETAIL B

0.08 REF

0.31 REF

3.10 ±0.10 5.85 ±0.10 0.70 ±0.05

6.50 REF

3.50 REF

4.10 ±0.05 5.50 ±0.05 7.10 ±0.05 0.25 ±0.05 8.50 ±0.05 PACKAGE OUTLINE RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

Rev. D For more information www.analog.com PACKAGE DESCRIPTION LWE64 LQFP 0416 REV A 0° – 7° 11° – 13° 0.45 – 0.75

1.00 REF

11° – 13° 1.60 MAX1.35 – 1.45 BSC 0.17 – 0.27 GAUGE PLANE 0.25 NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.25mm (10 MILS) BETWEEN THE LEADS AND MAX 0.50mm (20 MILS) ON ANY SIDE OF THE EXPOSED PAD, MAX 0.77mm (30 MILS) AT CORNER OF EXPOSED PAD, IF PRESENT 3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER 4. DRAWING IS NOT TO SCALE R0.08 – 0.20 10.15 – 10.25

7.50 REF

10.15 – 10.25 RECOMMENDED SOLDER PAD LAYOUT APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA) SIDE VIEW SECTION A – A

1.30 MIN

0.20 – 0.30

12.00 BSC

10.00 BSC

5.74 ±0.10 5.74 ±0.05 5.74 ±0.05 5.74 ±0.10 1732 3316 481 3217 4964 3333 4964 3217 C0.30 – 0.50 64-Lead Plastic Exposed Pad LQFP (10mm × 10mm) (Reference L TC DWG #05-08-1982 Rev A) SEE NOTE: 3

Rev. DFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 01/20 Added eLQFP package option. Added two arrows and corrected the 2nd y-axis of 8708 G08. Corrected the body connection of M1, changed EA7 to A7. Changed RESENSE1 to RSENSE1. Corrected calculations. 1, 3, 4, 6, 13, 14, 64, 65 51, 52 B 10/21 Removed TR from eLQFP package option in the Ordering Information section. The eLQFP package ships in trays. 4 C 05/23 Updated Features and Order Information 1, 4 D 12/24 Updated Order Information 4

Rev. D For more information www.analog.com  ANALOG DEVICES, INC. 2018-2024 www.analog.com RELATED PARTS TYPICAL APPLICATION Supercapacitor Backup Supply Using CCM CSPOUT CSNOUT EXTVCC FBOUT INTVCC GATEVCC IMON_OP IMON_INP IMON_ON IMON_INN CLKOUTSYNCSSRTVCMODE CSNIN TG1 L T8708 TG2 CSPIN VINCHIP SHDN FBIN VINHIMON VOUTLOMON SWEN LDO33 RVSOFF DIR 350kHz ICN ICP BOOST1 SW1 BG1 CSP CSN GND BG2 SW2 BOOST2 VIN 12V CIN1 CIN2 DIN LD033 COUT1 1.2k COUT2 CSC VOUT 15V

8708 TA02

5.6nF 124k 1µF 220pF 15k 22nF 6.8nF 17.4k 22nF 26.7k 6.8nF 17.4k 17.4k DB1 DB2 TO BOOST1 TO BOOST2 4Ω4.7µF 10k 4.7µF 100Ω 1µF 4.7µF 115k 25mΩ TO DIODE DB1 TO DIODE DB2 0.22µF 2Ω5mΩ 10Ω 1nF 1nF 10Ω0.22µF M3M2 2.2/uni03BCH TO LOADS (REGULATE TO 11V WHEN IN BACKUP) 25mΩ 100Ω 1µF 4.7µF 71.5k162k 20k20k 20k 200k 150k 50k 50k M1–M4: INFINEON BSC050NE2LS CIN1, COUT2: 220/uni03BCF , 35V 35HVP220M CIN2, COUT1: 22µF , 25V , TDK C4532X741E226M CSC: 60F , 2.5V COOPER BUSSMAN HB1840-2R5606-R SEE MORE DETAILS OF THIS APPLICATION ON PAGE 61.DIN: APPROPRIATE 2A SCHOTTKY DIODE OR IDEAL DIODE SUCH AS L TC4358, L TC4412, L TC4352, ETC. DB1, DB2: CENTRAL SEMI CMMR1U-02-L TE L1: 2.2/uni03BCH, VISHAY IHLP-5050CE-01-2R2-M-01 PART NUMBER DESCRIPTION COMMENTS LT8708-1 80V Synchronous 4-Switch Buck-Boost DC/DC Slave Controller for LT8708 Multiphase System 2.8V (Need EXTVCC > 6.4V) ≤ VIN ≤ 80V,1.3V ≤ VOUT ≤ 80V, 5mm × 8mm QFN-40 and 10mm × 10mm eLQFP-64 Packages LT8705A 80V VIN and VOUT Synchronous 4-Switch Buck- Boost DC/DC Controller 2.8V ≤ VIN ≤ 80V, Input and Output Current Monitor , 5mm × 7mm QFN-38 and TSSOP-38 Packages LT C 3779 150V VIN and VOUT Synchronous 4-Switch Buck- Boost Controller 4.5V ≤ VIN ≤ 150V, 1.2V ≤ VOUT ≤ 150V, Up to 99% Efficiency Drives Logic-Level or STD Threshold MOSFETs, TSSOP-38 Package LTC7813 60V Low IQ Synchronous Boost+Buck Controller Low EMI and Low Input/Output Ripple 4.5V (Down to 2.2V After Start-Up) ≤ VIN ≤ 60V, Boost VOUT Up to 60V, 0.8V ≤ Buck VOUT ≤ 60V, IQ = 29µA, 5mm × 5mm QFN-32 Package LTC3899 60V, T riple Output, Buck/Buck/Boost Synchronous Controller with 29µA Burst Mode IQ 4.5V (Down to 2.2V after Start-Up) ≤ VIN ≤ 60V, VOUT Up to 60V, Buck VOUT Range: 0.8V to 60V, Boost VOUT Up to 60V LT M 8056 58VIN, Buck-Boost µModule Regulator , Adjustable Input and Output Current Limiting 5V ≤ VIN ≤ 58V, 1.2V ≤ VOUT ≤ 48V, 15mm × 15mm × 4.92mm BGA Package LTC3895/ LTC7801 150V Low IQ, Synchronous Step-Down DC/DC Controller with 100% Duty Cycle 4V ≤ VIN ≤ 140V, 150V ABS Max, PLL Fixed Frequency 50kHz to 900kHz, 0.8V ≤ VOUT ≤ 60V, Adjustable 5V to 10V Gate Drive, IQ = 40μA, 4mm × 5mm QFN-24, TSSOP-24, TSSOP-38(31) Packages LTC3871 Bidirectional Multiphase DC/DC Synchronous Buck or Boost On-Demand Controller VIN/VOUT Up to 100V, Ideal for High Power 48V/12V Automotive Battery LTC7103 105V, 2.3A, Low EMI Synchronous Step-Down Regulator 4.4V ≤ VIN ≤105V, 1V ≤ VOUT ≤ VIN, IQ = 2µA, Fixed Frequency 200kHz, 5mm × 6mm QFN Package