LT8705A

LT8705A - 80V VIN and VOUT Synchronous 4-Switch Buck-Boost DC/DC Controller

Document overview

• Manufacturer or author: Linear Technology Corporation
• PDF pages: 44

Technical content

8705afFor more information www.linear .com/L T8705A Typical applicaTion FeaTures DescripTion 80V VIN and VOUT Synchronous 4-Switch Buck- Boost DC/DC Controller The LT®8705A is a high performance buck-boost switch- ing regulator controller that operates from input voltages above, below or equal to the output voltage. The part has integrated input current, input voltage, output current and output voltage feedback loops. With a wide 2.8V to 80V input and 1.3V to 80V output range, the LT8705A is compatible with most solar, automotive, telecom and battery-powered systems. The LT8705A is an improved pin compatible version of the LT8705 and is recommended for new designs. See LT8705A vs LT8705 in the Applications Information section for more information. The LT8705A includes a MODE pin to select among Burst Mode ® operation, discontinuous or continuous conduc- tion mode at light loads. Additional features include a 3.3V/12mA LDO, a synchronizable fixed operating fre- quency, and onboard gate drivers. L, LT, LT C, LT M, Linear Technology, Burst Mode, µModule and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. n Single Inductor Allows VIN Above, Below, or Equal to Regulated VOUT n VIN Range 2.8V (Need EXTVCC > 6.4V) to 80V n VOUT Range: 1.3V to 80V n Quad N-Channel MOSFET Gate Drivers n Synchronous Rectification: Up to 98% Efficiency n Input and Output Current Monitor Pins n Synchronizable Fixed Frequency: 100kHz to 400kHz n Integrated Input Current, Input Voltage, Output Cur- rent and Output Voltage Feedback Loops n Improved Light Load T ransition from DCM to FCM n Improved IMON_OUT , IMON_IN Offset When Cold n Clock Output Usable To Monitor Die Temperature

applicaTions

n High Voltage Buck-Boost Converters n Input or Output Current Limited Converters Telecom Voltage Stabilizer 8705A TA01 CSPOUT CSNOUT EXTVCC FBOUT INTVCC GATEVCC SRVO_FBIN SRVO_FBOUT SRVO_IIN SRVO_IOUT IMON_IN IMON_OUTSYNCCLKOUTVC 56.2k 202kHz CSNIN TG1 BOOST1 0.22µF 0.22µF TO DIODE TO DIODE ×2 22µH 4.7µF 1nF 1nF SW1 BG1 CSP CSN L T8705A GND BG2 SW2 BOOST2 VOUT 48V VIN 36V TO 80V TG2 CSPIN VIN SHDN SWEN LDO33 MODE FBIN RT SS 3.3nF220pF 215k 71.5k 20k 1µF 1µF 4.7µF 10k 392k 220µF 4.7µF 4/uni03A9 4.7µF TO BOOST1 4.7µF 2/uni03A9 2/uni03A9 10m/uni03A9 + 220µF TO BOOST2 100k 10/uni03A9 10/uni03A9 VIN (V) EFFICIENCY (%) POWER LOSS (W) 8705A TA01b 80 0 40 50 60 80 VOUT = 48V ILOAD = 2A 100 6 Efficiency and Power Loss

8705af For more information www.linear .com/L T8705A pin conFiguraTion absoluTe MaxiMuM raTings VCSP-VCSN, VCSPIN-VCSNIN, 0.3V to 3V 0.3V to 5V 3V to 5V 0.3V to 5.5V 0.3V to 7V 3V to 30V 0.3V to 30V 0.3V to 30V (Note 1) CSNIN, CSPIN, CSPOUT, CSNOUT Voltage ..– 0.3V to 80V te 7) 0.3V to 87V te 6) Operating Junction Temperature Range LT870 40°C to 125°C LT870 40°C to 125°C LT870 40°C to 150°C LT870 55°C to 150°C 65°C to 150°C Lead Temperature (Soldering, 10 sec) FE P 0°C 13 14 15 16 TOP VIEW GND UHF PACKAGE 38-LEAD (5mm × 7mm) PLASTIC QFN 17 18 19 38 37 36 35 34 33 32 1SHDN CSN CSP LDO33 FBIN FBOUT IMON_OUT VC SS CLKOUT SYNC RT CSPOUT CSNOUT EXTV CC SRVO_FBOUT SRVO_IOUT SRVO_IIN SRVO_FBIN NC BOOST1 TG1 SW1 NC IMON_IN MODE SWEN INTV CC VIN CSPIN CSNIN GND BG1 GATEV CC BG2 BOOST2 TG2 SW2 TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB TOP VIEW FE PACKAGE VARIATION: FE38(31) 38-LEAD PLASTIC TSSOP GND INTVCC MODE IMON_IN SHDN CSN CSP LDO33 FBIN FBOUT IMON_OUT VC SS CLKOUT SYNC RT GND BG1 GATEVCC BG2 VIN CSPIN CSNIN CSPOUT CSNOUT EXTVCC BOOST1 TG1 SW1 SW2 TG2 BOOST2 TJMAX = 125°C, θJA = 25°C/W EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB

8705afFor more information www.linear .com/L T8705A

elecTrical characTerisTics

PARAMETER CONDITIONS MIN TYP MAX UNITS Voltage Supplies and Regulators VIN Operating Voltage Range EXTVCC = 0V EXTVCC = 7.5V l l 5.5 2.8 V V V IN Quiescent Current Not Switching, VEXTVCC = 0 2.65 4.2 mA VIN Quiescent Current in Shutdown VSHDN = 0V 0 1 µA EXTVCC Switchover Voltage IINTVCC = 20mA, VEXTVCC Rising l 6.15 6.4 6.6 V EXTVCC Switchover Hysteresis 0.18 V INTVCC Current Limit Maximum Current Draw from INTVCC and LDO33 Pins Combined. Regulated from VIN or EXTVCC (12V) INTVCC = 5.25V INTVCC = 4.5V l l 127 165 mA mA INTV CC Voltage Regulated from VIN, IINTVCC = 20mA Regulated from EXTVCC (12V), IINTVCC = 20mA l l 6.15 6.15 6.35 6.35 6.55 6.55 V V INTV CC Load Regulation IINTVCC = 0mA to 50mA –0.5 –1.5 % INTVCC, GATEVCC Undervoltage Lockout INTVCC Falling, GATEVCC Connected to INTVCC l 4.45 4.65 4.85 V INTVCC, GATEVCC Undervoltage Lockout Hysteresis GATEV CC Connected to INTVCC 160 mV INTVCC Regulator Dropout Voltage VIN-VINTVCC, IINTVCC = 20mA 245 mV LDO33 Pin Voltage 5mA from LDO33 Pin l 3.23 3.295 3.35 V LDO33 Pin Load Regulation ILDO33 = 0.1mA to 5mA –0.25 –1 % LDO33 Pin Current Limit l 12 17.25 22 mA LDO33 Pin Undervoltage Lockout LDO33 Falling 2.96 3.04 3.12 V LDO33 Pin Undervoltage Lockout Hysteresis 35 mV Switching Regulator Control Maximum Current Sense Threshold (VCSP – VCSN) Boost Mode, Minimum M3 Switch Duty Cycle (LT8705AE, LT8705AI) (LT8705AH, LT8705AMP) l l 102 100 117 117 132 134 mV mV Maximum Current Sense Threshold (V CSN – VCSP) Buck Mode, Minimum M2 Switch Duty Cycle (LT8705AE, LT8705AI) (LT8705AH, LT8705AMP) l l 102 104 mV mV The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, SHDN = 3V unless otherwise noted. (Note 3) LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8705AEUHF#PBF LT8705AEUHF#TRPBF 8705A 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C LT8705AIUHF#PBF LT8705AIUHF#TRPBF 8705A 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C LT8705AEFE#PBF LT8705AEFE#TRPBF LT8705AFE 38-Lead Plastic TSSOP –40°C to 125°C LT8705AIFE#PBF LT8705AIFE#TRPBF LT8705AFE 38-Lead Plastic TSSOP –40°C to 125°C LT8705AHFE#PBF LT8705AHFE#TRPBF LT8705AFE 38-Lead Plastic TSSOP –40°C to 150°C LT8705AMPFE#PBF LT8705AMPFE#TRPBF LT8705AFE 38-Lead Plastic TSSOP –55°C to 150°C Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. orDer inForMaTion http://www.linear.com/product/LT8705A#orderinfo

8705af For more information www.linear .com/L T8705A PARAMETER CONDITIONS MIN TYP MAX UNITS Gain from VC to Maximum Current Sense Voltage (VCSP-VCSN) (A5 in the Block Diagram) Boost Mode Buck Mode 150 –150 mV/V mV/V SHDN Input V oltage High SHDN Rising to Enable the Device l 1.184 1.234 1.284 V SHDN Input Voltage High Hysteresis 50 mV SHDN Input Voltage Low Device Disabled, Low Quiescent Current (LT8705AE, LT8705AI) (LT8705AH, LT8705AMP) l l 0.35 0.3 V V SHDN Pin Bias Current VSHDN = 3V VSHDN = 12V µA µA SWEN Rising Threshold V oltage (Note 5) l 1.156 1.206 1.256 V SWEN Threshold Voltage Hysteresis (Note 5) 22 mV MODE Pin Forced Continuous Mode Threshold l 0.4 V MODE Pin Burst Mode Range l 1.0 1.7 V MODE Pin Discontinuous Mode Threshold l 2.3 V Soft-Start Charging Current VSS = 0.5V 13 19 25 µA Soft-Start Discharge Current VSS = 0.5V 9.5 µA Voltage Regulator Loops (Refer to Block Diagram to Locate Amplifiers) Regulation Voltage for FBOUT VC = 1.2V (LT8705AE, LT8705AI) VC = 1.2V (LT8705AH, LT8705AMP) l l 1.193 1.191 1.207 1.207 1.222 1.222 V V Regulation V oltage for FBIN VC = 1.2V (LT8705AE, LT8705AI) VC = 1.2V (LT8705AH, LT8705AMP) l l 1.184 1.182 1.205 1.205 1.226 1.226 V V Line Regulation for FBOUT and FBIN Error Amp Reference Voltage V IN = 12V to 80V; Not Switching 0.002 0.005 %/V FBOUT Pin Bias Current Current Out of Pin 15 nA FBOUT Error Amp EA4 gm 315 µmho FBOUT Error Amp EA4 Voltage Gain 220 V/V FBIN Pin Bias Current Current Out of Pin 10 nA FBIN Error Amp EA3 gm 130 µmho FBIN Error Amp EA3 Voltage Gain 90 V/V SRVO_FBIN Activation Threshold (Note 5) (VFBIN Falling) – (Regulation Voltage for FBIN), VFBOUT = VIMON_IN = VIMON_OUT = 0V 56 72 89 mV SRVO_FBIN Activation Threshold Hysteresis (Note 5) V FBOUT = VIMON_IN = VIMON_OUT = 0V 33 mV SRVO_FBOUT Activation Threshold (Note 5) (VFBOUT Rising) – (Regulation Voltage for FBOUT), VFBIN = 3V, VIMON_IN = VIMON_OUT = 0V –37 –29 –21 mV SRVO_FBOUT Activation Threshold Hysteresis (Note 5) V FBIN = 3V, VIMON_IN = 0V, VIMON_OUT = 0V 15 mV SRVO_FBIN, SRVO_FBOUT Low Voltage (Note 5) I = 100μA l 110 330 mV SRVO_FBIN, SRVO_FBOUT Leakage Current (Note 5) V SRVO_FBIN = VSRVO_FBOUT = 2.5V l 0 1 µA Current Regulation Loops (Refer to Block Diagram to Locate Amplifiers) Regulation Voltages for IMON_IN and IMON_OUT VC = 1.2V l 1.187 1.208 1.229 V Line Regulation for IMON_IN and IMON_OUT Error Amp Reference Voltage VIN = 12V to 80V; Not Switching 0.002 0.005 %/V CSPIN, CSNIN Bias Current BOOST Capacitor Charge Control Block Not Active ICSPIN + ICSNIN, VCSPIN = VCSNIN = 12V µA elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, SHDN = 3V unless otherwise noted. (Note 3)

8705afFor more information www.linear .com/L T8705A PARAMETER CONDITIONS MIN TYP MAX UNITS CSPIN, CSNIN Common Mode Operating Voltage Range l 1.5 80 V CSPIN, CSNIN Differential Operating Voltage Range l –100 100 mV VCSPIN-CSNIN to IMON_IN Amplifier A7 gm VCSPIN – VCSNIN = 50mV, VCSPIN = 5.025V (All Grades) (LT8705AE, LT8705AI) (LT8705AH, LT8705AMP) l l 0.95 0.94 0.93 1.05 1.06 1.07 mmho mmho mmho IMON_IN Maximum Output Current l 100 µA IMON_IN Overvoltage Threshold l 1.55 1.61 1.67 V IMON_IN Error Amp EA2 gm 185 µmho IMON_IN Error Amp EA2 Voltage Gain 130 V/V CSPOUT, CSNOUT Bias Current BOOST Capacitor Charge Control Block Not Active I CSPOUT + ICSNOUT, VCSPOUT = VCSNOUT = 12V ICSPOUT + ICSNOUT, VCSPOUT = VCSNOUT = 1.5V µA µA CSPOUT, CSNOUT Common Mode Operating V oltage Range l 0 80 V CSPOUT, CSNOUT Differential Mode Operating Voltage Range l –100 100 mV VCSPOUT-CSNOUT to IMON_OUT Amplifier A6 gm VCSPOUT – VCSNOUT = 50mV, VCSPOUT = 5.025V (All Grades) (LT8705AE, LT8705AI) (LT8705AH, LT8705AMP) V CSPOUT – VCSNOUT = 5mV, VCSPOUT = 5.0025V (All Grades) (LT8705AE, LT8705AI) (LT8705AH, LT8705AMP) l l l l 0.95 0.94 0.93 0.65 0.55 0.5 1.05 1.085 1.095 1.35 1.6 1.65 mmho mmho mmho mmho mmho mmho IMON_OUT Maximum Output Current l 100 µA IMON_OUT Overvoltage Threshold l 1.55 1.61 1.67 V IMON_OUT Error Amp EA1 gm 185 µmho IMON_OUT Error Amp EA1 Voltage Gain 130 V/V SRVO_IIN Activation Threshold (Note 5) (VIMON_IN Rising) – (Regulation Voltage for IMON_IN), VFBIN = 3V, VFBOUT = 0V, VIMON_OUT = 0V –60 –49 –37 mV SRVO_IIN Activation Threshold Hysteresis (Note 5) V FBIN = 3V, VFBOUT = 0V, VIMON_OUT = 0V 22 mV SRVO_IOUT Activation Threshold (Note 5) (VIMON_OUT Rising) – (Regulation Voltage for IMON_ OUT), VFBIN = 3V, VFBOUT = 0V, VIMON_IN = 0V –62 –51 –39 mV SRVO_IOUT Activation Threshold Hysteresis (Note 5) V FBIN = 3V, VFBOUT = 0V, VIMON_IN = 0V 22 mV SRVO_IIN, SRVO_IOUT Low Voltage (Note 5) I = 100μA l 110 330 mV SRVO_IIN, SRVO_IOUT Leakage Current (Note 5) VSRVO_IIN = VSRVO_IOUT = 2.5V l 0 1 µA NMOS Gate Drivers TG1, TG2 Rise Time CLOAD = 3300pF (Note 4) 20 ns TG1, TG2 Fall Time CLOAD = 3300pF (Note 4) 20 ns BG1, BG2 Rise Time CLOAD = 3300pF (Note 4) 20 ns BG1, BG2 Fall Time CLOAD = 3300pF (Note 4) 20 ns TG1 Off to BG1 On Delay CLOAD = 3300pF Each Driver 100 ns BG1 Off to TG1 On Delay CLOAD = 3300pF Each Driver 80 ns TG2 Off to BG2 On Delay CLOAD = 3300pF Each Driver 100 ns elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, SHDN = 3V unless otherwise noted. (Note 2)

8705af For more information www.linear .com/L T8705A Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Do not force voltage on the V C pin. Note 3: The LT8705AE is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8705AI is guaranteed over the full –40°C to 125°C junction temperature range. The LT8705AH is guaranteed over the full –40°C to 150°C operating junction temperature range. The LT8705AMP is guaranteed over the full –55°C to 150°C operating junction temperature range. Operating lifetime is derated at junction temperatures greater than 125°C. Note 4: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 5: This specification not applicable in the FE38 package. Note 6: Do not apply a voltage or current source to these pins. They must be connected to capacitive loads only, otherwise permanent damage may occur. Note 7: Negative voltages on the SW1 and SW2 pins are limited, in an application, by the body diodes of the external NMOS devices, M2 and M3, or parallel Schottky diodes when present. The SW1 and SW2 pins are tolerant of these negative voltages in excess of one diode drop below ground, guaranteed by design. Note 8: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. PARAMETER CONDITIONS MIN TYP MAX UNITS BG2 Off to TG2 On Delay CLOAD = 3300pF Each Driver 80 ns Minimum On-Time for Main Switch in Boost Operation (tON(M3,MIN)) Switch M3, CLOAD = 3300pF 265 ns Minimum On-Time for Synchronous Switch in Buck Operation (t ON(M2,MIN)) Switch M2, CLOAD = 3300pF 260 ns Minimum Off-Time for Main Switch in Steady-State Boost Operation Switch M3, C LOAD = 3300pF 245 ns Minimum Off-Time for Synchronous Switch in Steady-State Buck Operation Switch M2, CLOAD = 3300pF 245 ns Oscillator Switch Frequency Range SYNCing or Free Running 100 400 kHz Switching Frequency, fOSC RT = 365k RT = 215k RT = 124K l l l 102 170 310 120 202 350 142 235 400 kHz kHz kHz SYNC High Level for Synchronization l 1.3 V SYNC Low Level for Synchronization l 0.5 V SYNC Clock Pulse Duty Cycle VSYNC = 0V to 2V 20 80 % Recommended Minimum SYNC Ratio fSYNC/fOSC 3/4 CLKOUT Output Voltage High 1mA Out of CLKOUT Pin 2.3 2.45 2.55 V CLKOUT Output Voltage Low 1mA Into CLKOUT Pin 25 100 mV CLKOUT Duty Cycle TJ = –40°C TJ = 25°C TJ = 125°C 22.7 44.1 CLKOUT Rise T ime CLOAD = 200pF 30 ns CLKOUT Fall Time CLOAD = 200pF 25 ns CLKOUT Phase Delay SYNC Rising to CLKOUT Rising, fOSC = 100kHz l 160 180 200 Deg elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, SHDN = 3V unless otherwise noted. (Note 3)

8705afFor more information www.linear .com/L T8705A Typical perForMance characTerisTics FBOUT Voltages (Five Parts)Feedback Voltages Oscillator Frequency Maximum Inductor Current Sense Voltage vs Duty Cycle Inductor Current Sense Voltage at Minimum Duty Cycle Efficiency vs Output Current (Boost Region-Figure 15) Efficiency vs Output Current (Buck-Boost Region-Figure 15) Efficiency vs Output Current (Buck Region-Figure 15) Maximum Inductor Current Sense Voltage at Minimum Duty Cycle T A = 25°C unless otherwise specified. LOAD CURRENT (mA) EFFICIENCY (%) 100 1000 8705A G01 100 VIN = 36V VOUT = 48V 10000 BURST FCM DCM LOAD CURRENT (mA) EFFICIENCY (%) 100 1000 8705A G02 100 VIN = 48V VOUT = 48V 10000 BURST FCM DCM LOAD CURRENT (mA) EFFICIENCY (%) 100 1000 8705A G03 100 VIN = 72V VOUT = 48V 10000 BURST FCM DCM TEMPERATURE (°C) –55

1.17 PIN VOLTAGE (V)

1.18 1.19 1.20 1.21 –5 45 95 145 8705A G04 1.22 1.23 –30 20 70 120 IMON_OUT IMON_IN FBOUT FBIN VC = 1.2V TEMPERATURE (°C) –45 FBOUT VOLTAGE (V) 1.21 1.22 1.23 30 80 8705A G05 1.20 1.19 –20 5 55 105 130 1.18 1.17 VC = 1.2V TEMPERATURE (°C) –40 FREQUENCY (kHz) 200 300 120 8705A G06 100 0 40 80–20 20 60 100 400 RT = 124k RT = 215k RT = 365k150 250 350 M2 OR M3 DUTY CYCLE (%) 100 120 140 8705A G07 20 40 60 100 |CSP-CSN| (mV) BUCK REGION BOOST REGION VC (V) 0.5 –80 CSN-CSP (mV) CSP-CSN (mV) –40 –20 1 1.5 8705A G08 100 120 BUCK REGION BOOST REGION –60 –80 –40 –20 100 120 –60 TEMPERATURE (°C) –40 |CSP-CSN| (mV) 100 120 0 40 80–20 20 60 100 120 8705A G09 BOOST REGION BUCK REGION

8705af For more information www.linear .com/L T8705A Typical perForMance characTerisTics IMON Output Currents CLKOUT Duty Cycle LDO33 Pin Regulation (ILDO33 = 1mA) SHDN and SWEN Pin Thresholds vs Temperature INTV CC Line Regulation (EXTVCC = 0V) INTVCC Line Regulation (VIN = 12V) Maximum VC vs SS Minimum Inductor Current Sense Voltage in Forced Continuous Mode V IN Supply Current vs Voltage (Not Switching) TA = 25°C unless otherwise specified. M2 OR M3 DUTY CYCLE (%) –40 –20 8705A G10 –60 –80 20 40 60 100 –100 –120 –140 –|CSP-CSN| (mV) BUCK REGION BOOST REGION VIN (V) 4.0 INTVCC (V) 4.5 5.0 5.5 6.0 8 12 16 20 8705A G11 6.5 7.0 6 10 14 18 EXTVCC (V) 5.5 INTVCC (V) 6.0 6.5 7.0 6 8 8705A G12 10 12 EXTVCC RISING EXTVCC FALLING SS (V) MAXIMUM VC (V) 0.2 0.6 0.8 1.0 2.0 1.4 0.4 0.8 1.0 1.2 8705A G13 0.4 1.6 1.8 1.2 0.2 0.6 1.4 BOOST AND BUCK-BOOST REGIONS BUCK REGION TJ = 25°C VIN (V) IIN (mA) 2.0 2.5 3.0 65 7535 45 55 8705A G14 1.5 1.0 15 25 0.5 3.5 GATEVCC CONNECTED TO INTVCC 125°C 25°C –40°C CSPIN-CSNIN (mV) CSPOUT-CSNOUT (mV) –100 –25 IMON_OUT, IMON_IN (µA) 100 100 200 8705A G15 0–50 15050 200 125 150 175 TEMPERATURE (°C) –50 DUTY CYCLE (%) 100 25 75 150 8705A G16 –25 0 50 100 125 INTVCC (V) 2.5 LDO (V) 2.5 3.0 8705A G17 2.0 1.5 3 43.5 4.5 5 5.5 3.5 125°C 25°C –40°C TEMPERATURE (°C) –55 PIN THRESHOLD VOLTAGE (V) 1.22 1.26 1.30 125 8705A G18 1.18 1.14 1.20 1.24 1.28 1.16 1.12 1.10 –15 25 65 85–35 1455 45 105 RISING FALLING SHDN SWEN

8705afFor more information www.linear .com/L T8705A Typical perForMance characTerisTics Discontinuous Mode (Figure 15) Forced Continuous Mode (Figure 15) Forced Continuous Mode (Figure 14) Forced Continuous Mode (Figure 14) SHDN and MODE Pin Currents Internal V IN UVLO SRVO_xx Pin Activation Thresholds SRVO_xx Pin Activation Threshold Hysteresis SW1 20V/DIV SW2 20V/DIV IL 2A/DIV 5µs/DIVVIN = 48V VOUT = 48V 8705A G25 SW1 50V/DIV SW2 20V/DIV IL 2A/DIV 5µs/DIVVIN = 72V VOUT = 48V 8705A G26 TA = 25°C unless otherwise specified. PIN VOLTAGE (V) CURRENT INTO PIN (µA) 8705A G19 6 3 12 9 18 21 2715 30 MODE SHDN TEMPERATURE (°C) –40 –20 VIN UVLO (V) 0.5 1.0 1.5 2.0 2.5 3.0 0 20 40 60 80 100 120 8705A G20 TEMPERATURE (°C) –50 VPIN-VREGULATION VPIN APPROACHING VREGULATION (mV) 150 8705A G21 –25 –75 0 50 100–25 25 75 125 125 –50 100 FBIN FBOUT IMON_IN IMON_OUT TEMPERATURE (°C) –50 PIN ACTIVATION THRESHOLD HYSTERSIS (mV) 25 75 150 8705A G22 –25 0 50 100 125 FBIN FBOUT IMON_IN IMON_OUT SW1 50V/DIV SW2 50V/DIV IL 2A/DIV 5µs/DIVVIN = 72V VOUT = 48V 8705A G23 SW1 20V/DIV SW2 20V/DIV IL 2A/DIV 5µs/DIVVIN = 36V VOUT = 48V 8705A G24

8705af For more information www.linear .com/L T8705A Typical perForMance characTerisTics Load Step (Figure 14) Load Step (Figure 14) Load Step (Figure 14) Line T ransient (Figure 14) Line T ransient (Figure 14) Burst Mode Operation (Figure 14) Burst Mode Operation (Figure 14) VOUT 100mV/DIV IL 1A/DIV 2ms/DIVVIN = 36V VOUT = 48V 8705A G27 VOUT 100mV/DIV IL 5A/DIV 5ms/DIVVIN = 72V VOUT = 48V 8705A G28 VOUT 500mV/DIV IL 2A/DIV 500µs/DIVVIN = 36V VOUT = 48V LOAD STEP = 1A TO 3A 8705A G29 VOUT 500mV/DIV IL 2A/DIV 500µs/DIVVIN = 48V VOUT = 48V LOAD STEP = 1A TO 3A 8705A G30 VOUT 500mV/DIV IL 2A/DIV 500µs/DIVVIN = 72V VOUT = 48V LOAD STEP = 1A TO 3A 8705A G31 VOUT 0.5V/DIV VC 0.5V/DIV VIN 36V TO 72V IL 2A/DIV 2ms/DIV 8705A G32 VOUT 0.5V/DIV VC 0.5V/DIV VIN 72V TO 36V IL 2A/DIV 2ms/DIV 8705A G33 TA = 25°C unless otherwise specified.

8705afFor more information www.linear .com/L T8705A pin FuncTions SHDN (Pin 1/Pin 4): Shutdown Pin. Tie high to enable device. Ground to shut down and reduce quiescent current to a minimum. Do not float this pin. CSN (Pin 2/Pin 5): The (–) Input to the Inductor Current Sense and Reverse-Current Detect Amplifier. CSP (Pin 3/Pin 6): The (+) Input to the Inductor Current Sense and Reverse-Current Detect Amplifier. The V C pin voltage and built-in offsets between CSP and CSN pins, in conjunction with the RSENSE resistor value, set the current trip threshold. LDO33 (Pin 4/Pin 7): 3.3V Regulator Output. Bypass this pin to ground with a minimum 0.1μF ceramic capacitor. FBIN (Pin 5/Pin 8): Input Feedback Pin. This pin is con - nected to the input error amplifier input. FBOUT ( Pin 6/Pin 9): Output Feedback Pin. This pin connects the error amplifier input to an external resistor divider from the output. IMON_OUT (Pin 7/Pin 10): Output Current Monitor Pin. The current out of this pin is proportional to the output current. See the Operation and Applications Information sections. V C (Pin 8/Pin 11): Error Amplifier Output Pin. Tie external compensation network to this pin. SS (Pin 9/Pin 12): Soft-Start Pin. Place at least 100nF of capacitance here. Upon start-up, this pin will be charged by an internal resistor to 2.5V. CLKOUT (Pin 10/Pin 13): Clock Output Pin. Use this pin to synchronize one or more compatible switching regu - lator ICs to the LT8705A. CLKOUT toggles at the same frequency as the internal oscillator or as the SYNC pin, but is approximately 180° out of phase. CLKOUT may also be used as a temperature monitor since the CLKOUT duty cycle varies linearly with the part’s junction temperature. The CLKOUT pin can drive capacitive loads up to 200pF. SYNC (Pin 11/Pin 14): To synchronize the switching fre- quency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock needs to exceed 1.3V, and the low level should be less than 0.5V. Drive this pin to less than 0.5V to revert to the internal free-running clock. See the Applications Information section for more information. (QFN/TSSOP) RT (Pin 12/Pin 15): Timing Resistor Pin. Adjusts the switch- ing frequency. Place a resistor from this pin to ground to set the free-running frequency. Do not float this pin. BG1, BG2 (Pins 14, 16/Pins 17, 19): Bottom Gate Drive. Drives the gates of the bottom N-channel MOSFET s between ground and GATEVCC. GATEVCC (Pin 15/Pin 18): Power Supply for Gate Drivers. Must be connected to the INTVCC pin. Do not power from any other supply. Locally bypass to GND. BOOST1, BOOST2 (Pins 23, 17/Pins 28, 20): Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitor connects here. The BOOST1 pin swings from a diode voltage below GATEV CC up to VIN + GATEVCC. The BOOST2 pin swings from a diode voltage below GATEVCC up to VOUT + GATEVCC TG1, TG2 (Pins 22, 18/Pins 26, 21): Top Gate Drive. Drives the top N-channel MOSFETs with voltage swings equal to GATEVCC superimposed on the switch node voltages. SW1, SW2 (Pins 21, 19/Pins 24, 22): Switch Nodes. The (–) terminals of the bootstrap capacitors connect here. SRVO_FBIN (Pin 25 QFN Only): Open-Drain Logic Out - put. This pin is pulled to ground when the input voltage feedback loop is active. SRVO_IIN (Pin 26 QFN Only): Open-Drain Logic Output. The pin is pulled to ground when the input current loop is active. SRVO_IOUT (Pin 27 QFN Only): Open-Drain Logic Out - put. The pin is pulled to ground when the output current feedback loop is active. SRVO_FBOUT (Pin 28 QFN Only): Open-Drain Logic Out- put. This pin is pulled to ground when the output voltage feedback loop is active. EXT VCC (Pin 29/Pin 30): External VCC Input. When EXTVCC exceeds 6.4V (typical), INTVCC will be powered from this pin. When EXTVCC is lower than 6.22V (typical), INTV CC will be powered from VIN. CSNOUT (Pin 30/Pin 32): The (–) Input to the Output Cur- rent Monitor Amplifier. Connect this pin to VOUT when not in use. See Applications Information section for proper use of this pin.

8705af For more information www.linear .com/L T8705A CSPOUT (Pin 31/Pin 34): The (+) Input to the Output Current Monitor Amplifier. This pin and the CSNOUT pin measure the voltage across the sense resistor, R SENSE2, to provide the output current signals. Connect this pin to VOUT when not in use. See Applications Information section for proper use of this pin. CSNIN (Pin 32/Pin 36): The (–) Input to the Input Current Monitor Amplifier. This pin and the CSPIN pin measure the voltage across the sense resistor, RSENSE1, to provide the input current signals. Connect this pin to VIN when not in use. See Applications Information section for proper use of this pin. CSPIN (Pin 33/Pin 37): The (+) Input to the Input Cur - rent Monitor Amplifier. Connect this pin to V IN when not in use. See Applications Information section for proper use of this pin. V IN (Pin 34/Pin 38): Main Input Supply Pin. It must be locally bypassed to ground. INTV CC (Pin 35/Pin 1): Internal 6.35V Regulator Output. Must be connected to the GATEVCC pin. INTVCC is powered from EXTVCC when the EXTVCC voltage is higher than 6.4V, otherwise INTVCC is powered from VIN . Bypass this pin to ground with a minimum 4.7μF ceramic capacitor. SWEN (Pin 36 QFN Only ): Switch Enable Pin. Tie high to enable switching. Ground to disable switching. Don’t float this pin. This pin is internally tied to INTV CC in the TSSOP package. IMON_IN (Pin 38/Pin 3): Input Current Monitor Pin. The current out of this pin is proportional to the input current. See the Operation and Applications Information sections. MODE (Pin 37/Pin 2): Mode Pin. The voltage applied to this pin sets the operating mode of the controller. When the applied voltage is less than 0.4V, the forced continu- ous current mode is active. When this pin is allowed to float, Burst Mode operation is active. When the MODE pin voltage is higher than 2.3V, discontinuous mode is active. GND (Pin 13, Exposed Pad Pin 39/Pin 16, Exposed Pad Pin 39): Ground. Tie directly to local ground plane. pin FuncTions (QFN/TSSOP)

Figure 1. Block Diagram

8705af For more information www.linear .com/L T8705A operaTion Refer to the Block Diagram (Figure 1) when reading the following sections about the operation of the LT8705A. Main Control Loop The LT8705A is a current mode controller that provides an output voltage above, equal to or below the input voltage. The LT C® proprietary topology and control architecture employs a current-sensing resistor (R SENSE) in buck or boost modes. The inductor current is controlled by the voltage on the V C pin, which is the diode-AND of error amplifiers EA1-EA4. In the simplest form, where the output is regulated to a constant voltage, the FBOUT pin receives the output voltage feedback signal, which is compared to the internal reference voltage by EA4. Low output voltages would create a higher VC voltage, and thus more current would flow into the output. Conversely, higher output volt- ages would cause VC to drop, thus reducing the current fed into the output. The LT8705A contains four error amplifiers (EA1-EA4) allowing it to regulate or limit the output current (EA1), input current (EA2), input voltage (EA3) and/or output voltage (EA4). In a typical application, the output voltage might be regulated using EA4, while the remaining error amplifiers are monitoring for excessive input or output current or an input undervoltage condition. In other ap- plications, such as a battery charger, the output current regulator (EA1) can facilitate constant current charging until a predetermined voltage is reached where the output voltage (EA4) control would take over. INTVCC/EXTVCC/GATEVCC/LDO33 Power Power for the top and bottom MOSFET drivers, the LDO33 pin and most internal circuitry is derived from the INTVCC pin. INTVCC is regulated to 6.35V (typical) from either the VIN or EXTVCC pin. When the EXTV CC pin is left open or tied to a voltage less than 6.22V (typical), an internal low dropout regulator regulates INTVCC from VIN. If EXTVCC is taken above 6.4V (typical), another low dropout regula- tor will instead regulate INTV CC from EXTVCC. Regulating INTVCC from EXTV CC allows the power to be derived from the lowest supply voltage (highest efficiency) such as the LT8705A switching regulator output (see INTV CC Regulators and EXTV CC Connection in the Applications Information section for more details). The GATEVCC pin directly powers the bottom MOSFET drivers for switches M2 and M3. GATEVCC should always be connected to INTV CC and should not be powered or connected to any other source. Undervoltage lock outs (UVLOs) monitoring INTV CC and GATEV CC disable the switching regulator when the pins are below 4.65V (typical). The LDO33 pin is available to provide power to external components such as a microcontroller and/or to provide an accurate bias voltage. Load current is limited to 17.25mA (typical). As long as SHDN is high the LDO33 output is linearly regulated from the INTVCC pin and is not affected by the INTVCC or GATEVCC UVLOs or the SWEN pin voltage. LDO33 will remain regulated as long as SHDN is high and sufficient voltage is available on INTVCC (typically > 4.0V). An undervoltage lockout, monitoring LDO33, will disable the switching regulator when LDO33 is below 3.04V (typical). Start-Up Figure 2 illustrates the start-up sequence for the LT8705A. The master shutdown pin for the chip is SHDN. When driven below 0.35V (LT8705AE, LT8705AI) or 0.3V (LT8705AH, LT8705AMP) the chip is disabled (chip off state) and qui- escent current is minimal. Increasing the SHDN voltage can increase quiescent current but will not enable the chip until SHDN is driven above 1.234V (typical) after which the INTV CC and LDO33 regulators are enabled (switcher off state). External devices powered by the LDO33 pin can become active at this time if enough voltage is available on VIN or EXTVCC to raise INTVCC, and thus LDO33, to an adequate voltage. Starting up the switching regulator happens after SWEN (switcher enable) is also driven above 1.206V (typical), INTVCC and GATEVCC have risen above 4.81V (typical) and the LDO33 pin has risen above 3.08V (typical) (initialize state). The SWEN pin is not available in the TSSOP pack- age. In this package the SWEN pin is internally connected to INT VCC. Start-Up: Soft-Start of Switch Current In the initialize state, the SS (soft-start) pin is pulled low to prepare for soft starting the regulator. If forced continu- ous mode is selected (MODE pin low), the part is put into discontinuous mode during soft-start to prevent current

soft-start state and restart switching activity. transfer between modes is continuous. like a typical synchronous buck regulator.

0 BUCK/BOOST REGION

Figure 3. Simplified Diagram of the Output Switches Figure 4. Operating Regions vs VOUT-VIN Figure 5. Buck Region (VIN >> VOUT) will move to the buck-boost region. output ripple and reduction in maximum output current.

8705af For more information www.linear .com/L T8705A operaTion When V OUT is much higher than V IN the duty cycle of switch M3 will increase, causing the M3 switch off-time to decrease. The M3 switch off-time should be kept above 245ns (typical, see Electrical Characteristics) to maintain steady-state operation, avoid duty cycle jitter, increased output ripple and reduction in maximum output current. Light Load Current Operation (MODE Pin) Under light current load conditions, the LT8705A can be set to operate in discontinuous mode, forced continuous mode, or Burst Mode operation. To select forced continu- ous mode, tie the MODE pin to a voltage below 0.4V (i.e., ground). To select discontinuous mode, tie MODE to a voltage above 2.3V (i.e., LDO33). To select Burst Mode operation, float the MODE pin or tie it between 1.0V and 1.7V. Discontinuous Mode: When the LT8705A is in discontinu- ous mode, synchronous switch M4 is held off whenever reverse current in the inductor is detected. This is to prevent current draw from the output and/or feeding current to the input supply. Under very light loads, the current compara- tor may also remain tripped for several cycles and force switches M1 and M3 to stay off for the same number of cycles (i.e., skipping pulses). Synchronous switch M2 will remain on during the skipped cycles, but since switch M4 is off, the inductor current will not reverse. Burst Mode Operation: Burst Mode operation sets a V C level, with about 25mV of hysteresis, below which switch- ing activity is inhibited and above which switching activity is re-enabled. A typical example is when, at light output currents, VOUT rises and forces the VC pin below the thresh- old that temporarily inhibits switching. After VOUT drops slightly and V C rises ~25mV the switching is resumed, initially in the buck-boost region. Burst Mode operation can increase efficiency at light load currents by eliminating unnecessary switching activity and related power losses. Burst Mode operation handles reverse-current detection similar to discontinuous mode. The M4 switch is turned off when reverse current is detected. Forced Continuous Mode: The forced continuous mode allows the inductor current to reverse directions without any switches being forced “off” to prevent this from hap- pening. At very light load currents the inductor current will swing positive and negative as the appropriate average current is delivered to the output. During soft-start , when the SS pin is below 1.6V, the part will be forced into discontinuous mode to prevent pulling current from the output to the input. After SS rises above 1.6V, forced continuous mode will be enabled. Voltage Regulation Loops The LT8705A provides two constant-voltage regulation loops, one for output voltage and one for input voltage. A resistor divider between VOUT, FBOUT and GND senses the output voltage. As with traditional voltage regulators, when FBOUT rises near or above the reference voltage of EA4 (1.207V typical, see Block Diagram), the VC voltage is reduced to command the amount of current that keeps VOUT regulated to the desired voltage. The input voltage can also be sensed by connecting a resistor divider between V IN, FBIN and GND. When the FBIN voltage falls near or below the reference voltage of EA3 (1.205V typical, see Block Diagram), the VC voltage is reduced to also reduce the input current. For applications with a high input source impedance (i.e., a solar panel), the input voltage regulation loop can prevent the input voltage from becoming too low under high output load conditions. For applications with a lower input source impedance (i.e., batteries and voltage supplies), the FBIN pin can be used to stop switching activity when the input power supply voltage gets too low for proper system operation. See the Applications Information section for more information about setting up the voltage regulation loops. Current Monitoring and Regulation The LT8705A provides two constant-current regulation loops, one for input current and one for output current. A sensing resistor close to the input capacitor, sensed by CSPIN and CSNIN, monitors the input current. A current, linearly proportional to the sense voltage (VCSPIN-VCSNIN), is forced out of the IMON_IN pin and into an external resistor. The resulting voltage VIMON_IN is therefore linearly proportional to the input current. Similarly, a sensing resistor close to the output capacitor, and sensed by

8705afFor more information www.linear .com/L T8705A operaTion CSPOUT and CSNOUT will monitor the output current and generate a voltage VIMON_OUT that is linearly proportional to the output current. When the input or output current causes the respective IMON_IN or IMON_OUT voltage to rise near or above 1.208V (typical), the VC pin voltage will be pulled down to maintain the desired maximum input and/or output current (see EA1 and EA2 on the Block Diagram). The input current limit function prevents overloading the DC input source, while the output current limit provides a building block for battery charger or LED driver applications. It can also serve as short-circuit protection for a constant-voltage regulator. See the Applications Information section for more information about setting up the current regulation loops. SRVO Pins The QFN package has four open-drain SRVO pins: SRVO_FBIN, SRVO_ FBOUT, SRVO_IIN, SRVO_ IOUT. Place pull-up resistors from the desired SRVO pin(s) to a power supply less than 30V (i.e., the LDO33 pin) to enable reading of their logic states. The SRVO_FBOUT, SRVO_IIN and SRVO_IOUT pins are pulled low when their associated error amp (EA4, EA2, EA1) input voltages are near or greater than their regulation voltages (≅1.2V typical). SRVO_FBIN is pulled low when FBIN is near or lower than its regulation voltage (≅1.2V typical). The SRVO pins can therefore be used as indicators of when their respective feedback loops are active. For example, the SRVO_FBOUT pin pulls low when FBOUT rises to within 29mV (typical, see Electrical Characteristics) of its regulation voltage (1.207V typical). The pull-down turns off after FBOUT falls to more than 44mV (typical) lower than its regulation voltage. As another example, the SRVO_IOUT pin can be read to determine when the output current has nearly reached its predetermined limit. A logic “1” on SRVO_IOUT indicates that the output current has not reached the current limit and a logic “0” indicates that it has. CLKOUT and Temperature Sensing The CLKOUT pin toggles at the LT8705A’s internal clock frequency whether the internal clock is synchronized to an external source or is free-running based on the external R T resistor. The CLKOUT pin can be used to synchronize other devices to the LT8705A’s switching frequency. Also, the duty cycle of CLKOUT is proportional to the die temperature and can be used to monitor the die for thermal issues.

8705afFor more information www.linear .com/L T8705A applicaTions inForMaTion Operating Frequency Selection The LT8705A uses a constant frequency architecture between 100kHz and 400kHz. The frequency can be set using the internal oscillator or can be synchronized to an external clock source. Selection of the switching frequency is a trade-off between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires more inductance and/or capacitance to maintain low output ripple voltage. For high power applications, consider operating at lower frequencies to minimize MOSFET heating from switching losses. The switching frequency can be set by placing an appropriate resistor from the RT pin to ground and tying the SYNC pin low. The frequency can also be synchronized to an external clock source driven into the SYNC pin. The following sections provide more details. Internal Oscillator The operating frequency of the LT8705A can be set using the internal free-running oscillator. When the SYNC pin is driven low (<0.5V), the frequency of operation is set by the value of a resistor from the RT pin to ground. An internally trimmed timing capacitor resides inside the IC. The oscillator frequency is calculated using the following formula: fOSC = 43,750 RT +1 kHz where fOSC is in kHz and RT is in kΩ. Conversely, RT (in kΩ) can be calculated from the desired frequency (in kHz) using: RT = 43,750 fOSC kΩ SYNC Pin and Clock Synchronization The operating frequency of the LT8705A can be syn- chronized to an external clock source. To synchronize to the external source, simply provide a digital clock signal into the SYNC pin. The LT8705A will operate at the SYNC clock frequency. The duty cycle of the SYNC signal must be between 20% and 80% for proper operation. Also, the frequency of the SYNC signal must meet the following two criteria: 1. SYNC may not toggle outside the frequency range of 100kHz to 400kHz unless it is stopped low to enable the free-running oscillator. 2. The SYNC pin frequency can always be higher than the free-running oscillator set frequency, fOSC, but should not be less than 25% below fOSC. After SYNC begins toggling, it is recommended that switching activity is stopped before the SYNC pin stops toggling. Excess inductor current can result when SYNC stops toggling as the LT8705A transitions from the external SYNC clock source to the internal free-running oscillator clock. Switching activity can be stopped by driving either the SWEN or SHDN pin low. CLKOUT Pin and Clock Synchronization The CLKOUT pin can drive up to 200pF and toggles at the LT8705 A’s internal clock frequency whether the internal clock is synchronized to the SYNC pin or is free-running based on the external R T resistor. The rising edge of CLKOUT is approximately 180° out of phase from the internal clock’s rising edge or the SYNC pin’s rising edge if it is toggling. CLKOUT toggles only in normal mode (see Figure 2). The CLKOUT pin can be used to synchronize other devices to the LT8705A’s switching frequency. For example, the CLKOUT pin can be tied to the SYNC pin of another LT8705A regulator which will operate approximately 180° out of phase of the master LT8705A due to the CLKOUT phase shift. The frequency of the master LT8705A can be set by the external RT resistor or by toggling the SYNC pin. CLKOUT will begin oscillating after the master LT8705A enters normal mode (see Figure 2). Note that the RT pin of the slave LT8705A must have a resistor tied to ground. In general, use the same value R T resistor for all of the synchronized LT8705As.

8705af For more information www.linear .com/L T8705A applicaTions inForMaTion The duty cycle of CLKOUT is proportional to the die tem- perature and can be used to monitor the die for thermal issues. See the Junction Temperature Measurement section for more information. Inductor Current Sensing and Slope Compensation The LT8705A operates using inductor current mode con- trol. As described previously in the Power Switch Control section, the LT8705A measures the peak of the inductor current waveform in the boost region and the valley of the inductor current waveform in the buck region. The induc- tor current is sensed across the RSENSE resistor with pins CSP and CSN. During any given cycle, the peak (boost region) or valley (buck region) of the inductor current is controlled by the VC pin voltage. Slope compensation provides stability in constant- frequency current mode control architectures by prevent- ing subharmonic oscillations at high duty cycles. This is accomplished internally by adding a compensating ramp to the inductor current signal in the boost region, or subtracting a ramp from the inductor current signal in the buck region. At higher duty cycles, this results in a reduction of maximum inductor current in the boost region, and an increase of the maximum inductor current in the buck region. For example, refer to the Maximum Inductor Current Sense Voltage vs Duty Cycle graph in the Typical Performance Characteristics section. The graph shows that, with VC at its maximum voltage, the maximum inductor sense voltage V RSENSE is between 78mV and 117mV depending on the duty cycle. It also shows that the maximum inductor valley current in the buck region is 86mV increasing to ~130mV at higher duty cycles. RSENSE Selection and Maximum Current The RSENSE resistance must be chosen properly to achieve the desired amount of output current. Too much resistance can limit the output current below the application require- ments. Start by determining the maximum allowed RSENSE resistance in the boost region, RSENSE(MAX,BOOST). Follow this by finding the maximum allowed RSENSE resistance in the buck region, RSENSE(MAX,BUCK). The selected RSENSE resistance must be smaller than both. Boost Region: In the boost region, the maximum output current capability is the least when VIN is at its minimum and VOUT is at its maximum. Therefore R SENSE must be chosen to meet the output current requirements under these conditions. Start by finding the boost region duty cycle when VIN is minimum and VOUT is maximum using: DC(MAX,M3,BOOST) ≅ 1– VIN(MIN) VOUT(MAX)  •100% For example, an application with a V IN range of 12V to 48V and VOUT set to 36V will have: DC(MAX,M3,BOOST) ≅ 1– 12V 36V    •100%= 67% Referring to the Maximum Inductor Current Sense Volt- age graph in the Typical Performance Characteristics section, the maximum RSENSE voltage at 67% duty cycle is ≅93mV, or: VRSENSE(MAX,BOOST, MAX) ≅93mV for VIN = 12V, VOUT = 36V. Next, the inductor ripple current in the boost region must be determined. If the main inductor L is not known, the maximum ripple current ∆IL(MAX,BOOST) can be estimated by choosing ∆IL(MAX,BOOST) to be 30% to 50% of the maximum inductor current in the boost region as follows: ∆IL(MAX,BOOST) ≅ VOUT(MAX) •IOUT(MAX,BOOST) VIN(MIN) • 100% %Ripple – 0.5 A where: IOUT(MAX,BOOST) is the maximum output load current required in the boost region %Ripple is 30% to 50% For example, using V OUT(MAX) = 36V, V IN(MIN) = 12V, IOUT(MAX,BOOST) = 2A and %Ripple = 40% we can estimate: ∆IL(MAX,BOOST) ≅ 36V •2A 12V • 100% 40% – 0.5   = 3A

8705afFor more information www.linear .com/L T8705A Otherwise, if the inductor value is already known then ∆IL(MAX,BOOST) can be more accurately calculated as follows: ∆IL(MAX,BOOST) = DC(MAX,M3,BOOST) 100%  • V IN(MIN) f •L A where: DC(MAX,M3,BOOST) is the maximum duty cycle percentage in the boost region as calculated previously. f is the switching frequency L is the inductance of the main inductor After the maximum ripple current is known, the maximum allowed R SENSE in the boost region can be calculated as follows: RSENSE(MAX,BOOST) = 2• VRSENSE(MAX,BOOST,MAX) • VIN(MIN) 2•IOUT(MAX,BOOST) • VOUT(MIN)( ) + ∆I L(MAX,BOOST) • VIN(MIN)( ) Ω where VRSENSE(MAX,BOOST,MAX) is the maximum inductor current sense voltage as discussed in the previous section. Using values from the previous examples: RSENSE(MAX,BOOST) = 2•93mV •12 =12.4mΩ Buck Region: In the buck region, the maximum output cur- rent capability is the least when operating at the minimum duty cycle. This is because the slope compensation ramp increases the maximum R SENSE voltage with increasing duty cycle. The minimum duty cycle for buck operation can be calculated using: DC(MIN,M2,BUCK) ≅ tON(M2,MIN) • f • 100% where tON(M2,MIN) is 260ns (typical value, see Electrical Characteristics) Before calculating the maximum R SENSE resistance, however, the inductor ripple current must be determined. If the main inductor L is not known, the ripple current ∆IL(MIN,BUCK) can be estimated by choosing ∆IL(MIN,BUCK) to be 10% of the maximum inductor current in the buck region as follows: ∆IL(MIN,BUCK) ≅ IOUT(MAX,BUCK) 100% 10% – 0.5   A where: IOUT(MAX,BUCK) is the maximum output load current required in the buck region. If the inductor value is already known then ∆IL(MIN,BUCK) can be calculated as follows: ∆IL MIN,BUCK( ) = DC(MIN,M2,BUCK) 100%  • V OUT(MIN) f •L A where: DC(MIN,M2,BUCK) is the minimum duty cycle percentage in the buck region as calculated previously. f is the switching frequency L is the inductance of the main inductor After the inductor ripple current is known, the maximum allowed R SENSE in the buck region can be calculated as follows: RSENSE(MAX,BUCK) = 2•86mV 2•IOUT(MAX,BUCK)( ) – ∆IL(MIN,BUCK) Final R SENSE Value: The final R SENSE value should be lower than both RSENSE(MAX,BOOST) and RSENSE(MAX,BUCK). A margin of 30% or more is recommended. Figure 9 shows approximately how the maximum output current and maximum inductor current would vary with V IN/VOUT while all other operating parameters remain constant (frequency = 350 kHz, inductance = 10μH, RSENSE = 10mΩ). This graph is normalized and accounts for changes in maximum current due to the slope compensation ramps and the effects of changing ripple current. The curve is theoretical, but can be used as a guide to predict relative changes in maximum output and inductor current over a range of V IN/VOUT voltages. applicaTions inForMaTion

Figure 9. Currents vs VIN/VOUT Ratio load (IOUT) while operating in the boost region. resistor value to increase the inductor current limit. below. Negative results can be interpreted as zero.

• RSENSE 0.08 • f H

8705afFor more information www.linear .com/L T8705A applicaTions inForMaTion In the buck region, if VIN can be greater than twice VOUT, calculate L(MIN1,BUCK) as follows: L(MIN1,BUCK) = VIN(MAX) • 1– VOUT(MAX) VIN(MAX) – VOUT(MIN)  •RSENSE 0.08 • f H Inductor Selection: Maximum Current Rating The inductor must have a rating greater than its peak operating current to prevent inductor saturation resulting in efficiency loss. The peak inductor current in the boost region is: IL(MAX,BOOST) ≅IOUT(MAX) • VOUT(MAX) VIN(MIN) VIN(MIN) • DC(MAX,M3,BOOST 100% 2•L • f A where DC(MAX,M3,BOOST) is the maximum duty cycle percentage of the M3 switch (see R SENSE Selection and Maximum Current section). The peak inductor current when operating in the buck region is: IL(MAX,BUCK) ≅IOUT(MAX) VOUT(MIN) • DC(MAX,M2,BUCK 100% 2•L • f A where DC(MAX,M2,BUCK) is the maximum duty cycle percent- age of the M2 switch in the buck region given by: DC MAX,M2,BUCK( ) ≅ 1– VOUT(MIN) VIN(MAX)  •100% Note that the inductor current can be higher during load transients and if the load current exceeds the expected maximum IOUT(MAX). It can also be higher during start- up if inadequate soft-start capacitance is used or during output shorts. Consider using the output current limiting to prevent the inductor current from becoming excessive. Output current limiting is discussed later in the Input/ Output Current Monitoring and Limiting section. Care - ful board evaluation of the maximum inductor current is recommended. Power MOSFET Selection and Efficiency Considerations The LT8705A requires four external N-channel power MOSFETs, two for the top switches (switches M1 and M4, shown in Figure 3) and two for the bottom switches (switches M2 and M3, shown in Figure 3). Important parameters for the power MOSFETs are the breakdown voltage, VBR,DSS, threshold voltage, VGS,TH, on-resistance, RDS(ON), reverse-transfer capacitance, CRSS (gate-to-drain capacitance), and maximum current, I DS(MAX). The gate drive voltage is set by the 6.35V GATEV CC supply. Con- sequently, logic-level threshold MOSFETs must be used in LT8705A applications. It is very important to consider power dissipation when selecting power MOSFETs. The most efficient circuit will use MOSFETs that dissipate the least amount of power. Power dissipation must be limited to avoid overheating that might damage the devices. For most buck-boost ap- plications the M1 and M3 switches will have the highest power dissipation where M2 will have the lowest unless the output becomes shorted. In some cases it can be helpful to use two or more MOSFETs in parallel to reduce power dissipation in each device. This is most helpful when power is dominated by I 2R losses while the MOSFET is “on”. The additional capacitance of connecting MOSFETs in parallel can sometimes slow down switching edge rates and consequently increase total switching power losses. The following sections provide guidelines for calculating power consumption of the individual MOSFETs. From a known power dissipation, the MOSFET junction tempera- ture can be obtained using the following formula: TJ = TA + P • RTH(JA)

• IOUT 2 •RDS(ON) • ρτ + VIN •IOUT • f • tRF1( ) W BUCK REGION( ) ≅ VOUT VIN
• IOUT
• RDS(ON) • ρτ + 0W (BOOST REGION) where: the PSWITCHING term is 0 in the boost region JUNCTION TEMPERATURE (°C) –50 ρτ NORMALIZED ON-RESISTANCE (/uni03A9) 1.0 1.5 150 8705A F10 0.5 0 50 100 2.0

Figure 10. Normalized MOSFET RDS(ON) vs Temperature tRF1 is the average of the SW1 pin rise and fall times. MOSFET capacitance and VIN voltage. 125°C, using a value ρτ = 1.5 is reasonable.

• IOUT(MAX) 2 •RDS(ON) •ρ τ  W Switch M3: Switch M3 operates in the boost and buck-boost regions as a control switch. Similar to the M1 switch, the power dissipation comes from I2R power and switching power. The maximum power dissipation is when V IN is the lowest and VOUT is the highest. The following expres-

8705afFor more information www.linear .com/L T8705A applicaTions inForMaTion sion approximates the power dissipation in the M3 switch under those conditions: PM3 =PI2R +PSWITCHING ≅ VOUT – VIN( ) • VOUT VIN2

• IOUT2 •RDS(ON) •ρ τ + V OUT2 •IOUT • f • tRF2 VIN  W where the total power is 0 in the buck region. tRF2 is the average of the SW2 pin rise and fall times and, similar to tRF1, is typically 20ns to 40ns. As with the M1 switch, the switching power (PSWITCHING) often dominates. Look for MOSFETs with lower C RSS or consider operating at a lower frequency to minimize power loss and increase efficiency. Switch M4: In most cases the switching power dissipa- tion in the M4 switch is quite small and I 2R power losses dominate. I2R power is greatest in the boost region where the switch operates as the synchronous rectifier. Lower VIN and higher VOUT increases the inductor current for a given IOUT, leading to the highest power consumption. The M4 switch power consumption in the boost region can be approximated as: P(M4,BOOST) ≅ VOUT VIN
• IOUT2 •ρτ •RDS(ON)  W Gate Resistors: In some cases it can be beneficial to add 1Ω to 10Ω of resistance between some of the NMOS gate pins and their respective gate driver pins on the LT8705A (i.e., TG1, BG1, TG2, BG2). Due to parasitic inductance and capacitance, ringing can occur on SW1 or SW2 when low capacitance MOSFETs are turned on/off too quickly. The ringing can be of greatest concern when operating the MOSFETs or the LT8705A near the rated voltage limits. Additional gate resistance slows the switching speed, minimizing the ringing. Excessive gate resistance can have two negative side ef- fects on performance: 1. Slowing the switch transition times can also increase power dissipation in the switch. This is described above in the Switch M1 and Switch M3 sections. 2. Capacitive coupling from the SW1 or SW2 pin to the switch gate node can turn it on when it’s supposed to be off, thus increasing power dissipation. With too much gate resistance, this would most commonly happen to the M2 switch when SW1 is rising. Careful board evaluation should be performed when optimizing the gate resistance values. SW1 and SW2 pin ringing can be affected by the inductor current levels, therefore board evaluation should include measurements at a wide range of load currents. When performing PCB measurements of the SW1 and SW2 pins, be sure to use a very short ground post from the PCB ground to the scope probe ground sleeve in order to minimize false inductive voltages readings. C IN and COUT Selection Input and output capacitance is necessary to suppress voltage ripple caused by discontinuous current moving in and out of the regulator. A parallel combination of capaci- tors is typically used to achieve high capacitance and low ESR (equivalent series resistance). Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Capacitors with low ESR and high ripple current ratings, such as OS-CON and POSCAP are also available. Ceramic capacitors should be placed near the regulator input and output to suppress high frequency switching spikes. A ceramic capacitor, of at least 1µF, should also be placed from VIN to GND as close to the LT8705A pins as possible. Due to their excellent low ESR characteristics ceramic capacitors can significantly reduce input ripple voltage and help reduce power loss in the higher ESR bulk capacitors. X5R or X7R dielectrics are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. Many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired operating voltage. Input Capacitance: Discontinuous input current is highest in the buck region due to the M1 switch toggling on and off. Make sure that the CIN capacitor network has low enough ESR and is sized to handle the maximum RMS current. For buck operation, the input RMS current is given by: IRMS ≅IOUT(MAX) • VOUT VIN
• VIN VOUT

8705af For more information www.linear .com/L T8705A applicaTions inForMaTion This formula has a maximum at V IN = 2V OUT, where IRMS = I OUT(MAX)/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. The maximum input ripple due to the voltage drop across the ESR is approximately: ∆V(BUCK,ESR) ≅ VIN(MAX) •IOUT(MAX) VOUT(MIN)

• ESR Output Capacitance: The output capacitance (C OUT) is necessary to reduce the output voltage ripple caused by discontinuities and ripple in the output and load currents. The effects of ESR and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. The steady-state output ripple due to charging and discharging the bulk output capacitance is given by the following equations: ∆V BOOST,CAP( ) ≅ IOUT • VOUT – VIN( ) COUT • VIN • f V for VOUT > VIN ∆V(BUCK,CAP) ≅ VOUT • 1– VOUT VIN 8 •L • f2 •COUT V for VOUT < VIN The maximum output ripple due to the voltage drop across the ESR is approximately: ∆V(BOOST,ESR) ≅ VOUT(MAX) •IOUT(MAX) VIN(MIN)
• ESR As with C IN, multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Schottky Diode (D1, D2) Selection The Schottky diodes, D1 and D2, shown in Figure 1, con- duct during the dead time between the conduction of the power MOSFET switches. They are intended to prevent the body diodes of synchronous switches M2 and M4 from turning on and storing charge. For example, D2 significantly reduces reverse-recovery current between switch M4 turn-off and switch M3 turn-on, which improves converter efficiency, reduces switch M3 power dissipation and reduces noise in the inductor current sense resistor (RSENSE) when M3 turns on. In order for the diode to be effective, the inductance between it and the synchronous switch must be as small as possible, mandating that these components be placed adjacently. For applications with high input or output voltages (typi- cally >40V) avoid Schottky diodes with excessive reverse- leakage currents particularly at high temperatures. Some ultralow VF diodes will trade off increased high temperature leakage current for reduced forward voltage. Diode D1 can have a reverse voltage up to V IN and D2 can have a reverse voltage up to V OUT. The combination of high reverse voltage and current can lead to self heating of the diode. Besides reducing efficiency, this can increase leak- age current which increases temperatures even further. Choose packages with lower thermal resistance (θ JA) to minimize self heating of the diodes. Topside MOSFET Driver Supply (CB1, DB1, CB2, DB2) The top MOSFET drivers (TG1 and TG2) are driven digitally between their respective SW and BOOST pin voltages. The BOOST voltages are biased from floating bootstrap capacitors C B1 and C B2, which are normally recharged through external silicon diodes D B1 and D B2 when the respective top MOSFET is turned off. The capacitors are charged to about 6.3V (about equal to GATEVCC) forcing the VBOOST1-SW1 and VBOOST2-SW2 voltages to be about 6.3V. The boost capacitors CB1 and CB2 need to store about 100 times the gate charge required by the top switches M1 and M4. In most applications, a 0.1μF to 0.47μF, X5R or X7R dielectric capacitor is adequate. The bypass capacitance from GATEV CC to GND should be at least ten times the CB1 or CB2 capacitance. Boost Capacitor Charge Control Block : When the LT8705A operates exclusively in the buck or boost region, one of the top MOSFETs, M1 or M4, can be constantly on. This prevents the respective bootstrap capacitor, C B1 or CB2, from being recharged through the silicon diode, D B1 or DB2. The Boost Capacitor Charge Control block (see Fig- ure 1) keeps the appropriate BOOST pin charged in these cases. When the M1 switch is always on (boost region),

8705afFor more information www.linear .com/L T8705A applicaTions inForMaTion with the internal precision voltage reference (typically 1.207V) by the error amplifier EA4. The output voltage is given by the equation: VOUT =1.207V • 1+RFBOUT1 RFBOUT2 where RFBOUT1 and RFBOUT2 are shown in Figure 1. Input Voltage Regulation or Undervoltage Lockout By connecting a resistor divider between V IN, FBIN and GND, the FBIN pin provides a means to regulate the input voltage or to create an undervoltage lockout function. Referring to error amplifier EA3 in the Block Diagram, when FBIN is lower than the 1.205V reference VC is pulled low. For example, if V IN is provided by a relatively high impedance source (i.e., a solar panel) and the current draw pulls VIN below a preset limit, V C will be reduced, thus reducing current draw from the input supply and limiting the voltage drop. Note that using this function in forced continuous mode (MODE pin low) can result in current being drawn from the output and forced into the input. If this behavior is not desired then use discontinuous or Burst Mode operation. To set the minimum or regulated input voltage use: VIN(MIN) =1.205V • 1+RFBIN1 RFBIN2 where RFBIN1 and R FBIN2 are shown in Figure 1. Make sure to select R FBIN1 and RFBIN2 such that FBIN doesn’t exceed 30V (absolute maximum rating) under maximum VIN conditions. This same technique can be used to create an undervolt- age lockout if the LT8705A is NOT in forced continuous mode. When in Burst Mode operation or discontinuous mode, forcing VC low will stop all switching activity. Note that this does not reset the soft-start function, therefore resumption of switching activity will not be accompanied by a soft-start. current is automatically drawn from the CSPOUT and/or BOOST2 pins to charge the BOOST1 capacitor as needed. When the M4 switch is always on (buck region) current is drawn from the CSNIN and/or BOOST1 pins to charge the BOOST2 capacitor. Because of this function, CSPIN and CSNIN should be connected to a potential close to VIN. Tie both pins to V IN if they are not being used. Also, CSPOUT and CSNOUT should always be tied to a potential close to VOUT, or be tied directly to V OUT if not being used. Boost Diodes D B1 and D B2: Although Schottky diodes have the benefit of low forward voltage drops, they can exhibit high reverse current leakage and have the potential for thermal runaway under high voltage and temperature conditions. Silicon diodes are thus recommended for diodes DB1 and D B2. Make sure that D B1 and D B2 have reverse breakdown voltage ratings higher than V IN(MAX) and VOUT(MAX) and have less than 1mA of reverse leakage current at the maximum operating junction temperature. Make sure that the reverse leakage current at high op - erating temperatures and voltages won’t cause thermal runaway of the diode. In some cases it is recommended that up to 5Ω of resis- tance is placed in series with D B1 and DB2. The resistors reduce surge currents in the diodes and can reduce ring- ing at the SW and BOOST pins of the IC. Since SW pin ringing is highly dependent on PCB layout, SW pin edge rates and the type of diodes used, careful measurements directly at the SW pins of the IC are recommended. If required, a single resistor can be placed between GAT- EVCC and the common anodes of DB1 and DB2 (as in the front page application) or by placing separate resistors between the cathodes of each diode and the respective BOOST pins. Excessive resistance in series with D B1 and D B2 can reduce the BOOST-SW capacitor voltage when the M2 or M3 on-times are very short and should be avoided. Output V oltage The LT8705A output voltage is set by an external feedback resistive divider carefully placed across the output capaci- tor. The resultant feedback signal (FBOUT) is compared

8705afFor more information www.linear .com/L T8705A applicaTions inForMaTion Also, because of their use with the Boost Capacitor Charge Control block, tie the CSPIN and CSNIN pins to VIN and tie the IMON_IN pin to ground when the input current sensing is not in use. Similarly, the CSPOUT and CSNOUT pins should be tied to V OUT and IMON_OUT should be grounded when not in use. The remaining discussion refers to the input current moni- tor circuit. All discussion and equations are applicable to the output current monitor circuit, substituting pin and device names as appropriate. Current Monitoring: For input current monitoring, current flowing through R SENSE1 develops a voltage across CSPIN and CSNIN which is multiplied by 1mA/V (typical), converting it to a current that is forced out of the IMON_IN pin and into resistor R IMON_IN (Note: Negative CSPIN to CSNIN voltages are not multiplied and no current flows out of IMON_IN in that case). The resulting IMON_IN volt- age is then proportional to the input current according to: VIMON_IN =IRSENSE1 • RSENSE1 •1m A V •RIMON_IN   For accurate current monitoring, the CSPIN and CSNIN voltages should be kept above 1.5V (CSPOUT and CSNOUT pins should be kept above 0V). Also, the differential voltage VCSPIN-CSNIN should be kept below 100mV due to the limited amount of current that can be driven out of IMON_IN. Finally, the IMON_IN voltage must be filtered with capacitor CIMON_IN because the input current often has ripple and discontinuities depending on the LT8705A’s region of operation. C IMON_IN should be chosen by the equation: CIMON_IN > 100 f •RIMON_IN where f is the switching frequency, to achieve adequate filtering. Additional capacitance, bringing the C IMON_IN total to 0.1μF to 1μF, may be necessary to maintain loop stability if the IMON_IN pin is used in a constant-current regulation loop. Current Limiting: As shown in Figure 11, IMON_IN voltages exceeding 1.208V (typical) cause the VC voltage to reduce, thus limiting the inductor and input currents. RIMON_IN can be selected for a desired input current limit using: RIMON_IN = 1.208V IRSENSE(LIMIT) •1m A V • RSENSE1 Ω For example, if RSENSE1 is chosen to be 12.5mΩ and the desired input current limit is 4A then: RIMON_IN = 1.208V 4A •1m A V •12.5mΩ = 24.2kΩ Review the Electrical Characteristics and the IMON Output Currents graph in the Typical Performance Characteristics section to understand the operational limits of the IMON_ OUT and IMON_IN currents. Overcurrent Fault: If IMON_IN exceeds 1.61V (typical), a fault will occur and switching activity will stop (see Fault Conditions earlier in the data sheet). The fault current is determined by: IRSENSE1(FAULT) = 1.61V 1.208V •IRSENSE1(LIMIT)    A For example, an input current limit set to 4A would have a fault current limit of 5.3A. Output Overvoltage If the output voltage is higher than the value set by the FBOUT resistor divider, the LT8705A will respond according to the mode and region of operation. In forced continuous mode, the LT8705A will sink current into the input (see the Reverse Current Limit discussion in the Applications Information section for more information). In discontinu- ous mode and Burst Mode operation, switching will stop and the output will be allowed to remain high.

8705af For more information www.linear .com/L T8705A applicaTions inForMaTion INTVCC Regulators and EXTVCC Connection The LT8705A features two PNP LDOs (low dropout regu- lators) that regulate the 6.35V (typical) INTVCC pin from either the VIN or EXTVCC supply pin. INTVCC powers the MOSFET gate drivers via the required GATEV CC connec- tion and also powers the LDO33 pin regulator and much of the LT8705A’s internal control circuitry. The INTV CC LDO selection is determined automatically by the EXTVCC pin voltage. When EXTVCC is lower than 6.22V (typical), INTVCC is regulated from the VIN LDO. After EXTVCC rises above 6.4V (typical), INTVCC is regulated by the EXTVCC LDO instead. Overcurrent protection circuitry typically limits the maximum current draw from either LDO to 127mA. When GATEVCC and INTVCC are below 4.65V, during start-up or during an overload condition, the typical current limit is reduced to 42mA. The INTV CC pin must be bypassed to ground with a minimum 4.7μF ceramic capacitor placed as close as possible to the INTVCC and GND pins. An ad- ditional ceramic capacitor should be placed as close as possible to the GATEVCC and GND pins to provide good bypassing to supply the high transient current required by the MOSFET gate drivers. 1μF to 4.7μF is recommended. Power dissipated in the INTVCC LDOs must be minimized to improve efficiency and prevent overheating of the LT8705A. Since LDO power dissipation is proportional to the input voltage and V IN can be as high as 80V in some applications, the EXTVCC pin is available to regulate INTVCC from a lower input voltage. The EXTVCC pin is con- nected to VOUT in many applications since V OUT is often regulated to a much lower voltage than the maximum VIN. During start-up, power for the MOSFET drivers, control circuits and the LDO33 pin is derived from VIN until VOUT/ EXTVCC rises above 6.4V, after which the power is derived from VOUT/EXTVCC. This works well, for example, in a case where VOUT is regulated to 12V and the maximum V IN voltage is 40V. EXTVCC can be floated or grounded when not in use or can also be connected to an external power supply if available. The maximum current drawn through the INTV CC LDO occurs under the following conditions: Large ( capacitive) MOSFETs are being driven at high frequencies. 2. VIN and/or VOUT is high, thus requiring more charge to turn the MOSFET gates on and off. 3. The LDO33 pin output current is high. 4. In some applications, LDO current draw is maximum when the part is operating in the buck-boost region where VIN is close to VOUT since all four MOSFETs are switching. To check for overheating find the operating conditions that consume the most power in the LT8705A (PLT8705A). This will often be under the same conditions just listed that maximize LDO current. Under these conditions monitor the CLKOUT pin duty cycle to measure the approximate die temperature. See the Junction Temperature Measurement section for more information. Powering INTV CC from V OUT/EXTVCC can also provide enough gate drive when V IN drops as low as 2.8V. This allows the part to operate with a reduced input voltage after the output gets into regulation. The following list summarizes the three possible connec- tions for EXTV CC: 1. EXTVCC left open (or grounded). This will cause INTVCC to be powered from V IN through the internal 6.35V regulator at the cost of a small efficiency penalty. 2. EXTVCC connected directly to VOUT (VOUT > 6.4V). This is the normal connection for the regulator and usually provides the highest efficiency. 3. EXTVCC connected to an external supply. If an external supply is available greater than 6.4V (typical) it may be used to power EXTVCC.

determine the optimum value. voltage condition is detected. Table 1. Voltage Lockout Conditions

Voltage Regulation or Undervoltage Lockout section. network should be placed as close as possible to the IC. as this can increase offset voltages at the CSP/CSN pins. The RC product should be kept to less than 30ns. Considerations section for more details. Figure 13. Inductor Current Sense Filter

1. INTVCC current. This is the sum of the MOSFET driver

can reduce INTVCC current and power loss.

1. CIN and COUT loss. The input capacitor has the difficult

additional upstream losses in fuses or batteries. predominately at light loads. current, then there is no change in efficiency. provides heat sinking for power components.

• The high di/dt path formed by switch M1, switch M2, D1, RSENSE and the C IN capacitor should be compact with short leads and PC trace lengths. The high di/dt path formed by switch M3, switch M4, D2 and the COUT capacitor also should be compact with short leads and PC trace lengths. Tw o layout examples are shown in Figures 14a and 14b. GND VOUT COUT L RSENSE 8705A F14b M3M2 SW1 SW2 VIN CIN LT8705 CKT

Figure 14. Switches Layout

• Avoid running signal traces parallel to the traces that carr y high di/dt current because they can receive inductively coupled voltage noise. This includes the SW1, SW2, TG1 and TG2 traces to the controller.
• Use immediate vias to connect the components (includ- ing the LT8705A’s GND pins) to the ground plane. Use several vias for each power component.
• Minimize parasitic SW pin capacitance by removing GND and V IN copper from underneath the SW1 and SW2 regions.

8705af For more information www.linear .com/L T8705A

• Except under the SW pin regions, flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. Connect the copper areas to a DC net (e.g., quiet GND).
• Partition the power ground from the signal ground. The small-signal component grounds should not return to the IC GND through the power ground path.
• Pla ce switch M2 and switch M3 as close to the controller as possible, keeping the GND, BG and SW traces short.
• Minimize inductance from the sources of M2 and M3 to RSENSE by making the trace short and wide.
• Keep the high dV/dT nodes SW1, SW2, BOOST1, BOOST2, TG1 and TG2 away from sensitive small-signal nodes.
• The output capacitor (–) terminals should be connected as closely as possible to the (–) terminals of the input capacitor.
• Connect the top driver boost capacitor, CB1, closely to the BOOST1 and SW1 pins. Connect the top driver boost capacitor, CB2, closely to the BOOST2 and SW2 pins.
• Connect the input capacitors, CIN, and output capacitors, COUT, closely to the power MOSFETs. These capacitors carry the MOSFET AC current in the boost and buck regions.
• Connect the FBOUT and FBIN pin resistor dividers to the (+) terminals of COUT and CIN respectively. Small FBOUT/ FBIN bypass capacitors may be connected closely to the LT8705A’s GND pin if needed. The resistor connections should not be along the high current or noise paths.
• Route current sense traces (CSP/CSN, CSPIN/CSNIN, CSPOUT/CSNOUT) together with minimum PC trace spacing. Avoid having sense lines pass through noisy areas, such as switch nodes. The optional filter network capacitor between CSP and CSN should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the R SENSE resistors.
• Connect the VC pin compensation network closely to the IC, between VC and the signal ground pins. The capaci- tor helps to filter the effects of PCB noise and output voltage ripple voltage from the compensation loop.
• Connect the INTVCC and GATEVCC bypass capacitors close to the IC. The capacitors carry the MOSFET driv- ers’ current peaks. Design Example VIN = 8V to 25V VOUT = 12V IOUT(MAX) = 5A f = 350kHz Maximum ambient temperature = 60°C RT Selection: Choose the RT resistor for the free-running oscillator frequency using: RT = 43,750 fOSC kΩ = 43,750 350 –1    =124kΩ RSENSE Selection: Start by calculating the maximum duty cycle in the boost region: DC(MAX,M3,BOOST) ≅ 1– VIN(MIN) VOUT(MAX)  •100% = 1– 8V 12V    •100%= 33% Next, from the Maximum Inductor Current Sense Voltage vs Duty Cycle graph in the Typical Performance Charac- teristics section: VRSENSE(MAX,BOOST,MAX) ≅ 107mV Next, estimate the maximum and minimum inductor cur- rent ripple in the boost and buck regions respectively: ∆IL(MAX,BOOST) ≅ VOUT(MAX) •IOUT(MAX,BOOST) VIN(MIN) • 100% %Ripple – 0.5 A = 12V •5A 8V • 100% 40% – 0.5   = 3.75A ∆IL(MIN,BUCK) ≅ IOUT(MAX,BUCK) 100% 10% – 0.5   A = 5A 100% 10% – 0.5   = 0.53A Now calculate the maximum R SENSE values in the boost and buck regions to be: applicaTions inForMaTion

8705afFor more information www.linear .com/L T8705A applicaTions inForMaTion RSENSE(MAX,BOOST) = 2• VRSENSE(MAX,BOOST,MAX) • VIN(MIN) 2•IOUT(MAX,BOOST) • VOUT(MIN)( ) + ∆I L(MAX,BOOST) • VIN(MIN)( ) Ω = 2•107mV •8V =11.4mΩ RSENSE(MAX,BUCK) = 2•86mV 2•IOUT(MAX,BUCK)( ) – ∆IL(MIN,BUCK) Ω = 2•86mV Adding an additional 30% margin, choose R SENSE to be Inductor Selection: With R SENSE known, we can now determine the minimum inductor value that will provide adequate load current in the boost region using: L(MIN1,BOOST) ≅ VIN(MIN) • DC(MAX,M3,BOOST) 100% 2• f • VRSENSE(MAX,BOOST,MAX) RSENSE – IOUT(MAX) • VOUT(MAX) VIN(MIN) H 8V • 33% 100%   2•350kHz • 107mV 8.7mΩ – 5A •12V   = 0.8µH To avoid subharmonic oscillations in the inductor current, choose the minimum inductance according to: L(MIN2,BOOST) = VOUT(MAX) – VIN(MIN) • VOUT(MAX) VOUT(MAX) – VIN(MIN)

• RSENSE 0.08 • f H 12V – 8V •12V 12V – 8V    •8.7mΩ 0.08 •350kHz = –3.7µH L(MIN1,BUCK) = VIN(MAX) • 1– VOUT(MAX) VIN(MAX) – VOUT(MIN)  •RSENSE 0.08 • f 25V • 1– 12V 25V –12V    •8.7mΩ 0.08 •350kHz = 0.6µH The inductance must be higher than all of the minimum values calculated above. We will choose a 10μH standard value inductor for improved margin. MOSFET Selection: The MOSFETs are selected based on voltage rating, CRSS and RDS(ON) value. It is important to ensure that the part is specified for operation with the available gate voltage amplitude. In this case, the amplitude is 6.35V and MOSFETs with an RDS(ON) value specified at VGS = 4.5V can be used. Select M1 and M2: With 25V maximum input voltage, MOSFETs with a rating of at least 30V are used. As we do not yet know the actual thermal resistance (circuit board design and airflow have a major impact) we assume that the MOSFET thermal resistance from junction to ambient is 50°C/W. If we design for a maximum junction temperature, TJ(MAX) = 125°C, the maximum allowable power dissipation can be calculated. First, calculate the maximum power dissipation: PD(MAX) = TJ(MAX) – TA(MAX) RTH(JA) PD(MAX) = 125°C– 60°C 50°C/W =1.3W Since maximum I2R power dissipation in the boost region happens when V IN is minimum, we can determine the maximum allowable RDS(ON) for the boost region using: PM1 =PI2R ≅ VOUT VIN
• IOUT
• RDS(ON) •ρ τ  W 1.3W ≅ 12V 8V •5A  
• RDS(ON) •1.5  Wand therefore RDS(ON) <15.4mΩ The Fairchild FDMS7672 meets the specifications with a maximum RDS(ON) of ~6.9mΩ at VGS = 4.5V (~10mΩ at 125°C). Checking the power dissipation in the buck region with VIN maximum and VOUT minimum yields:

8705af For more information www.linear .com/L T8705A PM1 = PI2R +PSWITCHING ≅ VOUT VIN

• IOUT 2 •RDS(ON) • ρτ  + V IN •IOUT • f • tRF1( ) W PM1 ≅ 12V 25V • 5A2 • 6.9mΩ • 1.5   The maximum switching power of 0.88W can be reduced by choosing a slower switching frequency. Since this calculation is approximate, measure the actual rise and fall times on the PCB to obtain a better power estimate. The maximum dissipation in M2 occurs at maximum input voltage when the circuit is operating in the buck region. Using the 6.9mΩ Fairchild FDMS7672 the dissipation is: P(M2,BUCK) ≅ VIN – VOUT VIN
• IOUT(MAX) 2 •RDS(ON) •ρ τ  W P (M2,BUCK) ≅ 25V –12V 25V • 5A( ) 2 •6.9mΩ •1.5    = 0.13W Select M3 and M4: With 12V output voltage we need MOSFETs with 20V or higher rating. The highest dissipation occurs in the boost region when input voltage is minimum and output current is highest. For switch M3 the dissipation is: PM3 =PI2R +PSWITCHING ≅ VOUT – VIN( ) • VOUT VIN2
• IOUT2 •RDS(ON) •ρ τ + V OUT2 •IOUT • f • tRF2 VIN  W as described in the Power MOSFET Selection and Efficiency Considerations section. The maximum dissipation in switch M4 is: P M4,BOOST( ) ≅ VOUT(MAX) VIN(MIN)
• IOUT2 •ρ τ •RDS(ON)  W The Fairchild FDMS7672 can also be used for M3 and M4. Assuming 20ns rise and fall times, the calculated power loss at the minimum 8V input voltage is then 0.82W for M3 and 0.39W for M4 Output Voltage: Output voltage is 12V. Select RFBOUT2 as 20k. RFBOUT1 is: RFBOUT1 = VOUT 1.207V –1    •R FBOUT2 Select RFBOUT1 as 178k. Both RFBOUT1 and RFBOUT2 should have a tolerance of no more than 1%. Capacitors: A low ESR (5mΩ) capacitor network for CIN is selected. In this mode, the maximum ripple is: ∆V(BUCK,ESR) ≅ VIN(MAX) •IOUT(MAX) VOUT(MIN)
• ESR ∆V(BUCK,ESR) ≅ 25V •5A 12V •5mΩ = 52mV assuming ESR dominates the ripple. Having 5mΩ of ESR for the C OUT network sets the maxi- mum output voltage ripple at: ∆V(BOOST,ESR) ≅ VOUT(MAX) •IOUT(MAX) VIN(MIN)
• ESR ∆V(BOOST,ESR) ≅ 12V •5A 8V •5mΩ = 37.5mV assuming ESR dominates the ripple. applicaTions inForMaTion

Figure 15. Telecom Voltage Stabilizer

8705af For more information www.linear .com/L T8705A Supercapacitor Backup Supply DIN 12V INPUT 25m/uni03A9 POWER FLOW 12V LOADS INPUT CURRENT IN EXCESS OF 2A WILL DRAW FROM SUPER CAPS 25m/uni03A9 LIMIT CAPACITOR CHARGING CURRENT TO 1A 113k 20k 115k REGULATE CAPACITORS TO 15V 1.2kCSC CSC CSC CSC CSC CSC 10k 1.2k 1.2k 1.2k 1.2k 1.2k 8705A TA02b DIN INPUT 25m/uni03A9 POWER FLOW LOADS 25m/uni03A9 113k 20k 115k 1.2k REGULATE LOADS TO 8V CSC CSC CSC CSC CSC CSC 10k 1.2k 1.2k 1.2k 1.2k 1.2k 8705A TA02c VOUT 5V/DIV VIN 5V/DIV IL 5A/DIV 20SEC/DIV 8705A TA02d VOUT 5V/DIV VINP 5V/DIV IL 5A/DIV 3SEC/DIV 15V 8705A TA02e Charging VOUT to 15V with 1A Current Remove VIN. Loads (4A Draw) Regulated to 8V from Supercaps 8705A TA02a CSPOUT CSNOUT EXTVCC FBOUT INTVCC GATEVCC SRVO_FBIN SRVO_FBOUT SRVO_IIN SRVO_IOUT IMON_IN IMON_OUT 47.5k SYNCCLKOUTVC 14.3k 350kHz CSNIN TG1 BOOST1 0.22µF 0.22µF TO DIODE DB1 2.2µH TO LOADS TO DIODE DB2 M125m/uni03A9 M4 SW1 BG1 CSP CSN L T8705A GND BG2 SW2 BOOST2 VOUT 15V VIN 12V TG2 CSPIN VIN SHDN SWEN LDO33 MODE FBIN RT SS 15nF C IN1, COUT2: 100µF , 20V SANYO OS-CON 205A100M CIN2, COUT1: 22µF , 25V , TDK C4532X741E226M CSC: 60F , 2.5V COOPER BUSSMAN HB1840-2R5606-R DIN: APPROPRIATE 2A SCHOTTKY DIODE OR IDEAL DIODE SUCH AS L TC4358, L TC4412, L TC4352, ETC. DB1, DB2: CENTRAL SEMI CMMR1U-02-L TE L1: 2.2µH, VISHAY IHLP-5050CE-01-2R2-M-01 M1-M4: FAIRCHILD FDMS7698 220pF 124k 71.5k 20k1k 1µF 1µF15V 4.7µF 10k 115k CIN1 DIN VINP CIN2 COUT1 CSC 1.2k COUT2 4/uni03A9 DB1 DB2 4.7µF TO BOOST1 100k 4.7µF 113k 2/uni03A9 2/uni03A9 3m/uni03A9 20k + + TO BOOST2 100nF *INPUT SIDE OVERVOL TAGE PROTECTION WHEN CONVERTER IS DRAWING CURRENT FROM THE SUPER CAPACITORS 100nF 25m/uni03A9 2N3904* 24k Typical applicaTions

8705afFor more information www.linear .com/L T8705A Typical applicaTions 12V, 15A Output Converter Accepts 7.5V to 55V Input Efficiency vs Output Current Load Step Input T ransient (8V to 50V) Start-Up Waveforms 8705A TA03a CSPOUT CSNOUT EXTVCC FBOUT INTVCC GATEVCC SRVO_FBIN SRVO_FBOUT SRVO_IIN SRVO_IOUT IMON_IN IMON_OUTSYNCCLKOUT 190kHz VC 10k CSNIN TG1 BOOST1 0.22µF 0.22µF TO DIODE DB1 TO DIODE DB2 M1 M4 SW1 BG1 CSP CSN L T8705A GND BG2 SW2 BOOST2 VOUT 12V 15A VIN 7.5V TO 55V (INCREASED VOUT RIPPLE FOR VIN > 50V) TG2 CSPIN VIN SHDN SWEN LDO33 MODE FBIN RT SS 15nF220pF 226k 86.6k 20k 1µF 1µF 4.7µF 11.3k M1: INFINEON BSC028N06NS M2: INFINEON BSC039N06NS M3, M4: INFINEON BSC015NE2LS5I L1: COILCRAFT SER2915H-682, 6.8µH C IN1: 220µF , 100V CIN2: 4.7µF , 100V , TDK C453X7S2A475M COUT1: 10µF , 25V , TDK C4532X7R1E106M COUT2: 330µF , 25V , PANASONIC 25SEPF330M RSENSE: SUSUMU 3m/uni03A9, KRL6432E-M-R003-F-T1 102k CIN1 220µF C IN2 4.7µF COUT1 10µF 4/uni03A9 DB1 DB2 4.7µF TO BOOST1 100k 4.7µF 2/uni03A9 COUT2 330µF TO BOOST2 L1, 6.8µH RSENSE 1nF 1nF 3m/uni03A98.2/uni03A9 8.2/uni03A9 5.6nF 2/uni03A9 LOAD CURRENT (A) EFFICIENCY (%) 8705A TA03b 3 6 9 15 100 VIN = 7.5V VIN = 20V VIN = 35V VIN = 50V VIN = 12V VOUT = 12V LOAD STEP = 5A TO 10A VOUT 0.5V/DIV IL 5A/DIV 500µs/DIV 8705A TA03c ILOAD = 5A VOUT = 12V VOUT 0.2V/DIV VIN 20V/DIV 20ms/DIV 8705A TA03d VIN = 28V 1.67/uni03A9 LOAD VOUT 5V/DIV IL 5A/DIV 10ms/DIV 8705A TA03e

8705af For more information www.linear .com/L T8705A 5.00 ±0.10 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE M0-220 VARIATION WHKD 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS PIN 1 TOP MARK (SEE NOTE 6) BOTTOM VIEW—EXPOSED PAD

5.50 REF

5.15 ±0.10 7.00 ±0.10 0.75 ±0.05 R = 0.125 TYP R = 0.10 TYP 0.25 ±0.05 (UH) QFN REF C 1107

0.50 BSC

0.200 REF

0.00 – 0.05 RECOMMENDED SOLDER PAD LAYOUT APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

3.00 REF

3.15 ±0.10 0.40 ±0.10 0.70 ±0.05

5.5 REF

3.00 REF 3.15 ±0.05 4.10 ±0.05 6.10 ±0.05 7.50 ±0.05 0.25 ±0.05 PACKAGE OUTLINE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701 Rev C) package DescripTion Please refer to http://www.linear.com/product/LT8705A#packaging for the most recent package drawings.

8705afFor more information www.linear .com/L T8705A Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 4.75 (.187) REF FE38 (AB) TSSOP REV B 0910 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 1 19 PIN NUMBERS 23, 25, 27, 29, 31, 33 AND 35 ARE REMOVED REF 9.60 – 9.80* (.378 – .386) 1.20 (.047) MAX 0.05 – 0.15 (.002 – .006) 0.50 (.0196) BSC 0.17 – 0.27 (.0067 – .0106) TYP RECOMMENDED SOLDER PAD LAYOUT 0.315 ±0.05

4.50 REF

6.60 ±0.10 1.05 ±0.10

4.75 REF

2.74 REF

2.74 (.108) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC 38-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1865 Rev B) Exposed Pad Variation AB package DescripTion Please refer to http://www.linear.com/product/LT8705A#packaging for the most recent package drawings.

8705af For more information www.linear .com/L T8705A  LINEAR TECHNOLOGY CORPORATION 2016 LT 1016 • PRINTED IN USA relaTeD parTs Typical applicaTion PART NUMBER DESCRIPTION COMMENTS LT8390 60V Synchronous 4-Switch Buck-Boost Controller with Spread Spectrum 4V ≤ VIN ≤ 60V, 1V ≤ VOUT ≤ 60V, Regulates Output Voltage, Input or Output Current, TSSOP-28, 4mm × 5mm QFN-28 LTC3789 38V Synchronous 4-Switch Buck-Boost DC/DC Controller 4V ≤ V IN ≤ 38V, 0.8V ≤ VOUT ≤ 38V, SSOP-28, 4mm × 5mm QFN-28 LTC7813 60V, Low IQ Synchronous Boost + Buck Controller with Adjustable Gate Drive Level 5V to 10V 4.5V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 60V 5mm × 5mm QFN-32 LT3758A High Input Voltage, Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ V IN ≤ 100V, Positive or Negative VOUT, 3mm × 3mm DFN-10 and MSOP-10E LTC3115-1 40V, 2A Synchronous Buck-Boost DC/DC Converter 2.7V ≤ V IN ≤ 40V, 2.7V ≤ VOUT ≤ 40V, 4mm × 5mm DFN-16, TSSOP-20 LT M®8056 58V Buck-Boost μModule® Regulator, Adjustable Input and Output Current Limiting 5V ≤ VIN ≤ 58V, 1.2V ≤ VOUT ≤ 48V, 15mm × 15mm × 4.92mm BGA Package 12V Output Converter Accepts 4V to 80V Input (5.5V Minimum to Start) 8705A TA04a CSPOUT CSNOUT EXTVCC FBOUT INTVCC GATEVCC SRVO_FBIN SRVO_FBOUT SRVO_IIN SRVO_IOUT IMON_IN IMON_OUTSYNCCLKOUT 202kHz VC 16.5k CSNIN TG1 BOOST1 0.22µF 0.22µF TO DIODE DB1 TO DIODE DB2 ×2 M4 7m/uni03A9 SW1 BG1 CSP CSN L T8705A GND BG2 SW2 BOOST2 VOUT 12V 5.0A (VIN ≥ 5.5V) 4.5A (VIN ≥ 5.0V) 4.0A (VIN ≥ 4.5V) 3.5A (VIN ≥ 4.0V) VIN 4V TO 80V (INCREASED VOUT RIPPLE FOR VIN > 60V) TG2 CSPIN VIN SHDN SWEN LDO33 MODE FBIN RT SS 10nF220pF 215k 38.3k 20k 1µF 1µF 4.7µF 11.3k C IN1: 220µF , 100V CIN2: 4.7µF , 100V , TDK C4532X7S2A475M COUT1A, COUT1B: 22µF , 25V , TDK C4532X7R1E226M COUT2: 100µF , 16V , SANYO OS-CON 16SA100M COUT3: 470µF , 16V DB1, DB2: CENTRAL SEMI CMMR1U-02-L TE L1: 15µH, WURTH 7443631500 M1, M2: FAIRCHILD FDMS86101 M3, M4: FAIRCHILD FDMS7692 *2/uni03A9 FROM TG1 TO EACH SEPARATE M1 GATE 102k CIN1 CIN2 ×6 COUT1A 4/uni03A9 DB1 DB2 4.7µF 4.7µF 22nF TO BOOST1 100k 4.7µF 2/uni03A9* + COUT1B COUT2 COUT3 TO BOOST2 26.1k 15µH 1nF 1nF 4m/uni03A9 10/uni03A9 10/uni03A9 LOAD CURRENT (A) EFFICIENCY (%) 8705A TA04c 1 2 3 5 100 VIN = 60V VIN = 40V VIN = 20V VIN = 12V VIN = 5V VOUT 200mV/DIV VIN 20V/DIV 10ms/DIVILOAD = 2A 8705A TA04c Efficiency vs Output Current Input T ransient (4V to 80V) Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L T8705A