LT8705

LT8392 AD | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 28

Technical content

Rev. 0For more information www.analog.com Document Feedback TYPICAL APPLICATION FEATURES DESCRIPTION 60V Synchronous 4-Switch Buck-Boost Controller with Spread Spectrum The LT®8392 is a synchronous 4-switch buck-boost DC/ DC controller that regulates output voltage, input or out- put current from input voltage above, below, or equal to the output voltage. The proprietary peak-buck peak-boost current mode control scheme allows adjustable and syn- chronizable 150kHz to 650kHz fixed frequency operation, or internal ±15% triangle spread spectrum operation for low EMI. With 3V to 60V input voltage range, 1V to 60V output voltage capability, and seamless low noise tran - sitions between operation regions, the L T8392 is ideal for voltage regulator , battery and super-capacitor charger applications in automotive, industrial, telecom, and even battery-powered systems. The L T8392 provides input or output current monitor and power good flag. Fault protection function detects output short-circuit condition, during which the L T8392 retries, latches off, or keeps running. 98% Efficient 96W (12V 8A) Buck-Boost Voltage Regulator

APPLICATIONS

n 4-Switch Single Inductor Architecture Allows VIN Above, Below or Equal to VOUT n Up to 98% Efficiency n Proprietary Peak-Buck Peak-Boost Current Mode n Wide VIN Range: 3V (Need EXTVCC ≥ 4.5V) to 60V n ±1.5% Output Voltage Accuracy: 1V ≤ VOUT ≤ 60V n ±4% Input or Output Current Accuracy with Monitor n Spread Spectrum Frequency Modulation for Low EMI n Integrated Bootstrap Diodes n Adjustable and Synchronizable: 150kHz to 650kHz n VOUT Disconnected from VIN During Shutdown n Available in 28-Lead TSSOP with Exposed Pad and 28-Lead QFN (4mm × 5mm) n Automotive, Industrial, Telecom Systems n High Frequency Battery-Powered System All registered trademarks and trademarks are the property of their respective owners. 100k 0.1µF 10µF 1m/uni03A9 0.1µF 3µH 120µF 130k 4.7µF 226k 27nF 12k 110k 10k 5m/uni03A9 22µF 0.1µF 1µF 1µF 1µF 470µF 470µF EN/UVLO INTVCC PGOOD BG2 BST2 TG2 SYNC/SPRD FB V OUT EXTVCC ISP ISN VIN 6V TO 18V CONTINUOUS 3V TO 36V TRANSIENT 200kHz V OUT 12V LSP LSN SW1 SW2 BST1 TG1 CTRL TRIM VREF BG1 V IN L T8392 ISMON GND TEST SS V C RT 100k

8392 TA01a

0.47µF 10k 10k Efficiency vs VIN I OUT = 8A INPUT VOL TAGE (V) 100 EFFICIENCY (%)

8392 TA01b

Rev. 0 For more information www.analog.com ABSOLUTE MAXIMUM RATINGS (Note 1) ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8392EFE#PBF LT8392EFE#TRPBF LT8392FE 28-Lead Plastic TSSOP –40°C to 125°C LT8392JFE#PBF LT8392JFE#TRPBF LT8392FE 28-Lead Plastic TSSOP –40°C to 150°C LT8392HFE#PBF LT8392HFE#TRPBF LT8392FE 28-Lead Plastic TSSOP –40°C to 150°C LT8392EUFD#PBF LT8392EUFD#TRPBF 8392 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LT8392JUFD#PBF LT8392JUFD#TRPBF 8392 28-Lead (4mm × 5mm) Plastic QFN –40°C to 150°C LT8392HUFD#PBF LT8392HUFD#TRPBF 8392 28-Lead (4mm × 5mm) Plastic QFN –40°C to 150°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. TOP VIEW FE PACKAGE 28-LEAD PLASTIC TSSOP θJA = 30°C/W, θJC = 5°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB BG1 BST1 SW1 TG1 LSP LSN VIN INTVCC EN/UVLO TEST TRIM VREF CTRL ISP BG2 BST2 SW2 TG2 VOUT EXTVCC SYNC/SPRD RT VC FB SS PGOOD ISMON ISN GND 9 10 TOP VIEW GND UFD PACKAGE 28-LEAD (4mm × 5mm) PLASTIC QFN θJA = 43°C/W, θJC = 3.4°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB 11 12 13 28 27 26 25 24 1TG1 LSP LSN VIN INTVCC EN/UVLO TEST TRIM TG2 VOUT EXTVCC SYNC/SPRD RT VC FB SS SW1 BST1 BG1 BG2 BST2 SW2 VREF CTRL ISP ISN ISMON PGOOD 8 15 PIN CONFIGURATION Operating Junction Temperature Range (Notes 2, 3)

Rev. 0For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Supply VIN Operating Voltage Range EXTVCC = 0V EXTVCC = 8V l l V V VIN Shutdown Current VEN/UVLO = 0.3V 1 2 µA VIN Active Current (Not Switching) VEN/UVLO = 1.5V, EXTVCC = 0V VEN/UVLO = 1.5V, EXTVCC = 8V 250 500 mA µA EXTVCC Voltage Range l 0 40 V EXTVCC Shutdown Current VEN/UVLO = 0.3V, EXTVCC = 8V 0.1 0.5 µA EXTVCC Active Current (Not Switching) VEN/UVLO = 1.5V, EXTVCC = 8V 1.8 mA VOUT Voltage Range l 0 60 V VOUT Quiescent Current VEN/UVLO = 0.3V, VOUT = 12V VEN/UVLO = 1.5V, VOUT = 12V 0.1 0.5 µA µA Linear Regulators INTVCC Regulation Voltage IINTVCC = 20mA 4.8 5.0 5.2 V INTVCC Current Limit VINTVCC = 4.5V 130 190 250 mA INTVCC Undervoltage Lockout Threshold Falling 3.34 3.54 3.74 V INTVCC Undervoltage Lockout Hysteresis 0.22 V VREF Regulation Voltage IVREF = 100µA l 1.96 2.00 2.04 V VREF Current Limit VREF = 1.8V 2 2.5 3.2 mA Control Inputs EN/UVLO Shutdown Threshold l 0.3 0.6 1.0 V EN/UVLO Enable Threshold Falling l 1.196 1.220 1.244 V EN/UVLO Enable Hysteresis 13 mV EN/UVLO Hysteresis Current VEN/UVLO = 1.1V VEN/UVLO = 1.3V 2.1 –0.1 2.5 2.9 0.1 µA µA Error Amplifier Full-Scale Current Regulation V(ISP-ISN) VCTRL = 2V, VISP = 12V VCTRL = 2V, VISP = 0V l l mV mV 1/10th Current Regulation V(ISP-ISN) VCTRL = 0.35V, VISP = 12V VCTRL = 0.35V, VISP = 0V l l mV mV ISMON Monitor Output VISMON V(ISP–ISN) = 50mV, VISP = 12V/0V V(ISP–ISN) = 5mV, VISP = 12V/0V V(ISP–ISN)) = 0mV, VISP = 12V/0V l l l 1.15 0.30 0.20 1.25 0.35 0.25 1.35 0.40 0.30 V V V ISP/ISN Input Common Mode Range l 0 60 V ISP Input Bias Current VISP = VISN = 12V VISP = VISN = 0V VEN/UVLO = 0V, VISP = VISN = 12V or 0V –10 µA µA µA ISN Input Bias Current VISP = VISN = 12V VISP = VISN = 0V VEN/UVLO = 0V, VISP = VISN = 12V or 0V –10 µA µA µA ISP/ISN Current Regulation Amplifier gm 8000 µs FB Regulation Voltage VC = 1.2V l 0.985 1.00 1.015 V FB Line Regulation VIN = 4V to 60V 0.2 0.5 %

Rev. 0 For more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS FB Load Regulation 0.2 0.8 % FB Voltage Regulation Amplifier gm 660 µs FB Input Bias Current FB in regulation, Current out of Pin 20 40 nA VC Output Impedance 10 MΩ Current Comparator Maximum Current Sense Threshold V(LSP-LSN) Buck, VFB = 0.8V Boost, VFB = 0.8V l l mV mV Fault FB Short Threshold (VFB) Falling 0.23 0.25 0.27 V FB Short Hysteresis 35 50 65 mV PGOOD Upper Threshold Offset from VFB Rising 6 8 10 % PGOOD Lower Threshold Offset from VFB Falling –10 –8 –6 % PGOOD Pull-Down Resistance 100 200 Ω SS Hard Pull-Down Resistance VEN/UVLO = 1.1V 100 200 Ω SS Pull-Up Current VSS = 0V 10 12.5 15 µA SS Pull-Down Current VSS = 2V 1 1.25 1.5 µA SS Fault Latch-Off Threshold 1.7 V SS Fault Reset Threshold 0.2 V Oscillator Switching Frequency VSYNC/SPRD = 0V, RT = 100kΩ l 380 400 420 kHz SYNC Frequency 150 650 kHz SYNC/SPRD Threshold Voltage 0.4 1.5 V Highest Spread Spectrum Above Oscillator Frequency VSYNC/SPRD = 5V 12 15 18 % Lowest Spread Spectrum Below Oscillator Frequency VSYNC/SPRD = 5V –18 –15 –12 % NMOS Drivers TG1, TG2 Gate Driver On-Resistance Gate Pull-Up Gate Pull-Down V(BST–SW) = 5V 2.6 1.4 Ω Ω BG1, BG2 Gate Driver On-Resistance Gate Pull-Up Gate Pull-Down VINTVCC = 5V 3.2 1.2 Ω Ω TG Off to BG On Delay 60 ns BG Off to TG On Delay 60 ns ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT8392E is guaranteed to meet performance specifications from 0°C to 125°C operating junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8392J is guaranteed over the –40°C to 150°C operating junction temperature range. The LT8392H is guaranteed over the –40°C to 150°C operating junction temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125°C. Note 3: The LT8392 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 150°C when overtemperature protection is active. Continuous operation above the specified absolute maximum operating junction temperature may impair device reliability.

Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Load Current (Buck Region) Efficiency vs Load Current (Buck-Boost Region) Efficiency vs Load Current (Boost Region) TA = 25°C, unless otherwise noted. Switching Waveforms (Buck Region) Switching Waveforms (Buck-Boost Region) Switching Waveforms (Boost Region) VOUT vs IOUT (CV/CC) VIN Shutdown Current VIN Operating Current FRONT PAGE APPLICATION V IN = 18V , V OUT = 12V , f SW = 200kHz LOAD CURRENT (A) 100 EFFICIENCY (%)

8392 G01

V IN = 12V , V OUT = 12V , f SW = 200kHz LOAD CURRENT (A) 100 EFFICIENCY (%)

8392 G02

V IN = 5V , V OUT = 12V , f SW = 200kHz LOAD CURRENT (A) 100 EFFICIENCY (%)

8392 G03

VIN = 8V , IOUT = 6A VSW1 10V/DIV VSW2 10V/DIV IL 2A/DIV VOUT 500mV/DIV

8392 G04

VIN = 12V , IOUT = 6A VSW1 10V/DIV VSW2 10V/DIV IL 2A/DIV VOUT 500mV/DIV

8392 G05

VIN = 18V , IOUT = 6A VSW1 10V/DIV VSW2 10V/DIV IL 2A/DIV VOUT 500mV/DIV

8392 G06

LOAD CURRENT (A) OUTPUT VOL TAGE (V)

8392 G07

V IN = 4V V IN = 12V V IN = 60V TEMPERATURE (°C) –50 –25 100 125 150 0.5 1.0 1.5 2.0 2.5 3.0 I Q (µA)

8392 G08

= 0V V IN = 12V V IN = 4V V IN = 60V TEMPERATURE (°C) –50 –25 100 125 150 1.8 2.0 2.2 2.4 2.6 2.8 I Q (mA)

8392 G09

Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. INTVCC Voltage vs Temperature INTVCC Voltage vs VIN INTVCC UVLO Threshold VREF Voltage vs Temperature VREF Voltage vs VIN VREF UVLO Threshold EN/UVLO Enable Threshold EN/UVLO Hysteresis Current V(ISP–ISN) Regulation vs VCTRL V IN = 12V , V EXTVCC = 0V V IN = 3V , V EXTVCC = 12V I INTVCC = 20mA TEMPERATURE (°C) –50 –25 100 125 150 4.97 4.98 4.99 5.00 5.01 5.02 5.03 V INTVCC (V)

8392 G10

I INTVCC = 20mA V IN (V) 4.85 4.90 4.95 5.00 5.05 5.10 5.15 V INTVCC (V)

8392 G11

TEMPERATURE (°C) –50 3.2 VINTVCC (V) 3.8 3.9 3.7 3.5 3.6 3.4 3.3 4.0 125100 150–25 0 25 50

8392 G12

TEMPERATURE (°C) –50 1.96 VREF (V) 2.02 2.03 2.01 1.99 2.00 1.98 1.97 2.04 125100 150–25 0 25 50

8392 G13

IVREF = 0mA IVREF = 1mA VIN (V) 1.96 VREF (V) 2.02 2.03 2.01 1.99 2.00 1.98 1.97 2.04 5040 6010 20

8392 G14

IVREF = 100µA TEMPERATURE (°C) –50 1.70 VREF (V) 1.90 1.95 1.85 1.80 1.75 2.00 125100 150–25 250 50

8392 G15

TEMPERATURE (°C) –50

1.200 VEN/UVLO (V)

1.230 1.235 1.225 1.220 1.215 1.210 1.205 1.240 125100 150–25 250 50

8392 G16

TEMPERATURE (°C) –50 2.0 IHYS (µA) 2.8 2.6 2.4 2.2 3.0 125100 150–25 250 50

8392 G17

V CTRL (V) 0.25 0.50 0.75 1.25 1.50 1.75 V (ISP–ISN) (mV)

8392 G18

Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS V(ISP-ISN) Regulation vs VISP V(ISP-ISN) Regulation vs VISP V(ISP-ISN) Regulation vs VFB TA = 25°C, unless otherwise noted. FB Regulation vs Temperature Maximum Current Sense vs Temperature FB Short Threshold PGOOD Thresholds ISMON Voltage vs V(ISP–ISN) SS Current vs Temperature V ISP (V) V (ISP-ISN) (mV)

8392 G19

ISP = 0V ISP = 12V ISP = 60V TEMPERATURE (°C) –50 –25 100 125 150 47.0 48.0 49.0 50.0 51.0 52.0 53.0 V (ISP–ISN) (mV)

8392 G20

V FB (V) 0.96 0.97 0.98 0.99 1.01 1.02 1.03 1.04 V (ISP–ISN) (mV)

8392 G21

V IN = 4V V IN = 12V V IN = 60V TEMPERATURE (°C) –50 –25 100 125 150 0.97 0.98 0.99 1.00 1.01 1.02 1.03 V FB (V)

8392 G22

TEMPERATURE (°C) –50 –25 100 125 150 30.0 35.0 40.0 45.0 50.0 55.0 60.0 65.0 70.0 CURRENT LIMIT (mV)

8392 G23

TEMPERATURE (°C) –50 –25 0.10 VFB (V) 0.30 0.35 0.25 0.20 0.15 0.40 125100 1500 25

8392 G24

TEMPERATURE (°C) –50 –25 100 125 150 –12.0 –8.0 –4.0 4.0 8.0 12.0 THRESHOLD OFFSET (%)

8392 G25

V (ISP–ISN) (V) 0.25 0.50 0.75 1.00 1.25 1.50 V ISMON (V)

8392 G26

TEMPERATURE (°C) –50 –25 0.0 ISS (µA) 10.0 12.5 7.5 5.0 2.5 15.0 125100 1500 25

8392 G27

Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. Oscillator Frequency vs Temperature TEMPERATURE (°C) –50 –25 100 SWITCHING FREQUENCY (kHz) 500 600 400 300 200 700 125100 1500 25

8392 G28

RT = 59.0k RT = 100k RT = 226k PIN FUNCTIONS BG1: Buck Side Bottom Gate Drive. Drives the gate of buck side bottom N-Channel MOSFET with a voltage swing from ground to INTVCC. BST1: Buck Side Bootstrap Floating Driver Supply. The BST1 pin has an integrated bootstrap Schottky diode from the INTVCC pin and requires an external bootstrap capac- itor to the SW1 pin. SW1: Buck Side Switch Node. TG1: Buck Side Top Gate Drive. Drives the gate of buck side top N-Channel MOSFET with a voltage swing from SW1 to BST1. LSP: Positive Terminal of the Buck Side Inductor Current Sense Resistor (RSENSE). Ensure accurate current sense with Kelvin connection. LSN: Negative Terminal of the Buck Side Inductor Current Sense Resistor (RSENSE). Ensure accurate current sense with Kelvin connection. VIN: Input Supply. The VIN pin must be tied to the power input to determine the buck, buck-boost, or boost oper - ation regions. Locally bypass this pin to ground with a minimum 1µF ceramic capacitor . INTVCC: Internal 5V Linear Regulator Output. The INTVCC linear regulator is supplied from either the VIN pin or the BIAS pin, and powers the internal control circuitry and gate drivers. Locally bypass this pin to ground with a minimum 4.7µF ceramic capacitor . EN/UVLO: Enable and Undervoltage Lockout. Force the pin below 0.3V to shut down the part and reduce VIN qui- escent current below 2µA. Force the pin above 1.233V for normal operation. The accurate 1.220V falling threshold can be used to program an undervoltage lockout (UVLO) threshold with a resistor divider from V IN to ground. An accurate 2.5µA pull-down current allows the program - ming of VIN UVLO hysteresis. If neither function is used, tie this pin directly to VIN. TEST: Factory Test. This pin is used for testing purpose only and must be directly connected to ground for the part to operate properly. TRIM: Factory T rim. This pin is used for trim purposes only and must be directly connected to VREF for the part to operate properly. VREF: Voltage Reference Output. The VREF pin provides an accurate 2V reference capable of supplying 1mA current. Locally bypass this pin to ground with a 0.47µF ceramic capacitor .

Rev. 0For more information www.analog.com CTRL: Control Input for ISP/ISN Current Sense Threshold. The CTRL pin is used to program the ISP/ISN current limit: IIS(MAX) = Min VCTRL −0.25V,1V( ) 20 •RIS The VCTRL can be set by an external voltage reference or a resistor divider from VREF to ground. For 0.25V ≤ VCTRL ≤ 1.15V, the current sense threshold linearly goes up from 0mV to 45mV. For VCTRL ≥ 1.35V, the current sense threshold is constant at 50mV full-scale value. For 1.15V ≤ VCTRL ≤ 1.35V, the current sense threshold smoothly transitions from the linear function of VCTRL to the 50mV constant value. Tie CTRL to VREF for the 50mV full-scale threshold. ISP: Positive Terminal of the ISP/ISN Current Sense Resistor (RIS). Ensure accurate current sense with Kelvin connection. ISN: Negative Terminal of the ISP/ISN Current Sense Resistor (RIS). Ensure accurate current sense with Kelvin connection. ISMON: ISP/ISN Current Sense Monitor Output. The ISMON pin generates a voltage that is equal to twenty times V (ISP-ISN) plus 0.25V offset voltage. For parallel applications, tie the master LT8392 ISMON pin to the slave LT8392 CTRL pin. PGOOD: Power Good Open Drain Output. The PGOOD pin is pulled low when the FB pin is within ±8% of the final regulation voltage. To function, the pin requires an external pull-up resistor . SS: Soft-Start Timer Setting. The SS pin is used to set soft-start timer by connecting a capacitor to ground. An internal 12.5µA pull-up current charging the external SS capacitor gradually ramps up FB regulation voltage. A 0.1µF capacitor is recommended on this pin. Any UVLO or thermal shutdown immediately pulls SS pin to ground and stops switching. Using a single resistor from SS to VREF, the LT8392 can be set in three different fault protection modes during output short-circuit condition: hiccup (no resistor), latch-off (499kΩ), and keep-running (100kΩ). See more details in the Application Information section. PIN FUNCTIONS FB: Voltage Loop Feedback Input. The FB pin is used for constant-voltage regulation and output fault protection. The internal error amplifier with its output VC regulates VFB to 1.00V through the DC/DC converter . During output short-cir- cuit (VFB < 0.25V) condition, the part gets into one fault mode per customer setting. During an overvoltage (VFB > 1.08V) condition, the part turns off all TG1, BG1, TG2, and BG2. VC: Error Amplifier Output to Set Inductor Current Comparator Threshold. The VC pin is used to compensate the control loop with an external RC network. RT: Switching Frequency Setting. Connect a resistor from this pin to ground to set the internal oscillator frequency from 150kHz to 650kHz. SYNC/SPRD: Switching Frequency Synchronization or Spread Spectrum. Ground this pin for switching at inter- nal oscillator frequency. Apply a clock signal for external frequency synchronization. Tie to INTVCC for ±15% trian- gle spread spectrum around internal oscillator frequency. EXTVCC: Second Input Supply for Powering INTVCC. The part intelligently chooses either VIN or EXTVCC for INTVCC LDO to improve efficiency. See EXTVCC Connection in the Applications Information Section. Tie this pin ground if not used. VOUT: Output Supply. The V OUT pin must be tied to the power output to determine the buck, buck-boost, or boost operation regions. Locally bypass this pin to ground with a minimum 1µF ceramic capacitor . TG2: Boost Side Top Gate Drive. Drives the gate of boost side top N-Channel MOSFET with a voltage swing from SW2 to BST2. SW2: Boost Side Switch Node. BST2: Boost Side Bootstrap Floating Driver Supply. The BST2 pin has an integrated bootstrap Schottky diode from the INTVCC pin and requires an external bootstrap capac- itor to the SW2 pin. BG2: Boost Side Bottom Gate Drive. Drives the gate of boost side bottom N-Channel MOSFET with a voltage swing from ground to INTVCC. GND (Exposed Pad): Ground. Solder the exposed pad directly to the ground plane.

Rev. 0 For more information www.analog.com BLOCK DIAGRAM EA2 EA1 A2=10 5V LDO 2V REF INTVCC VREF RT SYNC/SPRD CTRL 0.3V FBOV ISOC FB OSC VOS 1.1V VISP-ISN 0.75V PEAK_BOOST LOADON MODE VOUT/BST2 VIN/BST1 ISMON TRIM SS GND ISN 8392 BD ISP 0.25V CTRL 1.25V 1V FB BST2 TG2 SW2 BG2 BG1 SW1 TG1 BST1 VC VIS LOADON 1.25µA 12.5µA 10µA 0.25V FB INHIBIT SWITCH PGOOD TEST VOUT VREF EN/UVLO 1.220V 2.5µA VIN EXTVCC LSN LSP INTVCC INTVCC INTVCC FAUL T LOGIC SHORT INTVCC LOADON PEAK_BUCK 1.1V 0.9V FB FB 1X VIS BOOST LOGIC BUCK LOGIC CHARGE CONTROL

understood by referring to the Block Diagram. to smoothly transition between modes and regions. Figure 1. Simplified Diagram of the Power Switches Figure 2. Current Mode vs VIN/VOUT Ratio Figure 3. Operation Region vs VIN/VOUT Ratio

8392 F01

8392 F03

peak-buck current mode control in buck region (Figure 4). behaving like a typical synchronous buck regulator . Figure 4. Peak-Buck in Buck Region (VIN >> VOUT) Figure 5. Peak-Buck in Buck-Boost Region (VIN ~> VOUT)

8392 F04

switch B is turned on for the rest of the cycle.

8392 F05

B is turned on for the rest of the cycle. Figure 6. Peak-Boost in Buck-Boost Region (VIN <~ VOUT) Figure 7. Peak-Boost in Boost Region (VIN << VOUT)

8392 F06

boost current mode control in boost region (Figure 7). behaving like a typical synchronous boost regulator .

8392 F07

Rev. 0 For more information www.analog.com OPERATION Main Control Loop The LT8392 is a fixed frequency current mode control - ler . The inductor current is sensed through the inductor sense resistor between the LSP and LSN pins. The current sense voltage is gained up by amplifier A1 and added to a slope compensation ramp signal from the internal oscillator . The summing signal is then fed into the positive terminals of the buck current comparator A3 and boost current comparator A4. The negative terminals of A3 and A4 are controlled by the voltage on the V C pin, which is the diode-OR of error amplifiers EA1 and EA2. Depending on the state of the peak-buck peak-boost cur- rent mode control, either the buck logic or the boost logic is controlling the four power switches so that either the FB voltage is regulated to 1V or the current sense voltage between the ISP and ISN pins is regulated by the CTRL pin during normal operation. The gains of EA1 and EA2 have been balanced to ensure smooth transition between constant-voltage and constant-current operation with the same compensation network. Light Load Current Operation At light load, the LT8392 runs either at full switching fre- quency discontinuous conduction mode or pulse-skip - ping mode, where the switches are held off for multiple cycles (i.e., skipping pulses) to maintain the regulation and improve the efficiency. In the buck region, switch B is turned off whenever the buck reverse current threshold is triggered during (B+D) phase. In the boost region, switch D is turned off when - ever the boost reverse current threshold is triggered during (A+D) phase. In the buck-boost region, switch D is turned off whenever the boost reverse current thresh- old is triggered during (A+D) phase, and both switches B and D are turned off whenever the buck reverse current threshold is triggered during (B+D) phase. Internal Charge Path Each of the two top MOSFET drivers is biased from its floating bootstrap capacitor , which is normally re-charged by INTVCC through both the external and internal boot - strap diodes when the top MOSFET is turned off. When the LT8392 operates exclusively in the buck or boost regions, one of the top MOSFETs is constantly on. An internal charge path, from VOUT and BST2 to BST1 or from VIN and BST1 to BST2, charges the bootstrap capacitor to 4.6V so that the top MOSFET can be kept on. Shutdown and Power-On-Reset The LT8392 enters shutdown mode and drains less than 2µA quiescent current when the EN/UVLO pin is below its shutdown threshold (0.3V minimum). Once the EN/ UVLO pin is above its shutdown threshold (1V maximum), the LT8392 wakes up startup circuitry, generates band - gap reference, and powers up the internal INTV CC LDO. The INTVCC LDO supplies the internal control circuitry and gate drivers. Now the LT8392 enters undervoltage lockout (UVLO) mode with a hysteresis current ( 2.5µA typical) pulled into the EN/UVLO pin. When the INTVCC pin is charged above its rising UVLO threshold (3.76V typi - cal), the EN/UVLO pin passes its rising enable threshold (1.233V typical), and the junction temperature is less than its thermal shutdown (165°C typical), the LT8392 enters enable mode, in which the EN/UVLO hysteresis current is turned off and the voltage reference VREF is being charged up from ground. From the time of entering enable mode to the time of VREF passing its rising UVLO threshold (1.89V typical), the LT8392 is going through a power-on-reset (POR), waking up the entire internal control circuitry and settling to the right initial conditions. After the POR, the LT8392 starts switching.

12.5µA pull-up current while the switching is disabled. the LT8392 enters the UP/RUN state. Figure 8. Start-Up and Fault Sequence smoothly to its final regulation voltage. DOWN/STOP states until the fault condition is cleared. will keep running regardless of the fault.

SS hard pull down
Switching disabled
No short detection INIT
SS hard pull down
Switching disabled
No short detection POR = HI or ISOC = HI SS < 0.2V UP/TRY
SS 12.5µA pull up
Switching disabled
No short detection UP/PRE
SS 12.5µA pull up
Switching disabled
No short detection Wait 10µs SS > 0.25V UP/RUN
SS 12.5µA pull up
Switching enabled
No short detection OK/RUN
SS 12.5µA pull up
Switching enabled
Short detection Wait 10µs SS > 1.75V DOWN/STOP
SS 1.25µA pull down
Switching disabled
No short detection FAUL T/RUN
SS 1.25µA pull down
Switching enabled
Short detection SS < 0.2V and LOADON = HI SHORT SS < 1.7V

8392 F08

The front page shows a typical LT8392 application circuit. of selecting external components for typical applications. tinuous conduction mode unless otherwise specified. minimize the total solution size. keep the switching noise out of a sensitive frequency band. for common switching frequencies. Table 1. Switching Frequency vs RT Value (1% Resistor) application when spread spectrum enabled. Figure 9. Average Conducted EMI Figure 10. Peak Conducted EMI

8392 F09

8392 F10

nization frequency and the internal oscillator frequency.

Rev. 0For more information www.analog.com APPLICATIONS INFORMATION Inductor Selection The switching frequency and inductor selection are inter- related in that higher switching frequencies allow the use of smaller inductor and capacitor values. The inductor value has a direct effect on ripple current. The highest cur- rent ripple ∆IL% happens in the buck region at VIN(MAX), and the lowest current ripple ∆IL% happens in the boost region at VIN(MIN). For any given ripple allowance set by customers, the minimum inductance can be calculated as: LBUCK > VOUT • VIN(MAX) −VOUT( ) f •IOUT(MAX) •ΔIL% •VIN(MAX) LBOOST > VIN(MIN) 2 • VOUT −VIN(MIN)( ) f •IOUT(MAX) •ΔIL% •VOUT where: ΔIL% = ΔIL IL(AVG) f is switching frequency V IN(MIN) is minimum input voltage V IN(MAX) is maximum input voltage V OUT is output voltage I OUT(MAX) is maximum output current Slope compensation provides stability in constant fre - quency current mode control by preventing subharmonic oscillations at certain duty cycles. The minimum induc - tance required for stability when duty cycles are larger than 50% can be calculated as: L > 10 •VOUT •RSENSE f For high efficiency, choose an inductor with low core loss, such as ferrite. Also, the inductor should have low DC resistance to reduce the I2R losses, and must be able to handle the peak inductor current without saturating. To minimize radiated noise, use a shielded inductor . RSENSE Selection and Maximum Output Current RSENSE is chosen based on the required output current. The duty cycle independent maximum current sense thresholds (50mV in peak-buck and 50mV in peak-boost) set the maximum inductor peak current in buck region, buck-boost region, and boost region. In boost region, the lowest maximum average load cur - rent happens at VIN(MIN) and can be calculated as: IOUT(MAX _BOOST) = 50mV RSENSE ΔIL(BOOST) ⎠⎟ • VIN(MIN) VOUT where ∆IL(BOOST) is peak-to-peak inductor ripple current in boost region and can be calculated as: ΔIL(BOOST) = VIN(MIN) • VOUT −VIN(MIN)( ) f •L •VOUT In buck region, the lowest maximum average load current happens at VIN(MAX) and can be calculated as: IOUT(MAX _BUCK) = 50mV RSENSE ΔIL(BUCK) where ∆IL(BUCK) is peak-to-peak inductor ripple current in buck region and can be calculated as: ΔIL(BUCK) = VOUT • VIN(MAX) −VOUT( ) f •L •VIN(MAX) The maximum current sense RSENSE in boost region is: RSENSE(BOOST) = 2 •50mV •VIN(MIN) 2 •IOUT(MAX) •VOUT + ΔIL(BOOST) •VIN(MIN) The maximum current sense RSENSE in buck region is RSENSE(BUCK) = 2 •50mV 2 •IOUT(MAX) + ΔIL(BUCK) The final RSENSE value should be lower than the calculated RSENSE in both buck and boost regions. A 20% to 30% margin is usually recommended. Always choose a low ESL current sense resistor .

the INTVCC current limit in the data sheet. Figure 11. Normalized RDS(ON) vs Temperature included in the calculation above.

ρT •RDS(ON) where ρT is a normalization factor (unity at 25°C) account- ing for the significant variation in on-resistance with tem- perature, typically 0.4%/°C as shown in Figure 11. For a maximum junction temperature of 125°C, using a value of ρT = 1.5 is reasonable. Switch B operates in buck region as the synchronous rectifier . Its power dissipation at maximum output cur- rent is given by: PB(BUCK) = VIN −VOUT VIN
IOUT(MAX) 2 •ρT •RDS(ON) JUNCTION TEMPERATURE (°C) –50 ρT NORMALIZED ON-RESISTANCE (/uni03A9) 1.0 1.5 150

8392 F11

Rev. 0For more information www.analog.com APPLICATIONS INFORMATION Switch C operates in boost region as the control switch. Its power dissipation at maximum current is given by: PC(BOOST) = VOUT −VIN( ) •VOUT VIN 2 •IOUT(MAX) 2 •ρT

RDS(ON) + k •VOUT 3 • IOUT(MAX) VIN
CRSS •f where CRSS is usually specified by the MOSFET manufac- turers. The constant k, which accounts for the loss caused by reverse recovery current, is inversely proportional to the gate drive current and has an empirical value of 1.7. For switch D, the maximum power dissipation happens in boost region, when its duty cycle is higher than 50%. Its maximum power dissipation at maximum output current is given by: PD(BOOST) = VOUT VIN
IOUT(MAX) 2 •ρT •RDS(ON) For the same output voltage and current, switch A has the highest power dissipation and switch B has the lowest power dissipation unless a short occurs at the output. From a known power dissipated in the power MOSFET , its junction temperature can be obtained using the following formula: T J = TA + P • RTH(JA) The junction-to-ambient thermal resistance R TH(JA) includes the junction-to-case thermal resistance R TH(JC) and the case-to-ambient thermal resistance RTH(CA). This value of TJ can then be compared to the original, assumed value used in the iterative calculation process. Optional Schottky Diode (DB, DD) Selection The optional Schottky diodes D B (in parallel with switch B) and DD (in parallel with switch D) conduct during the dead time between the conduction of the power MOSFET switches. They are intended to prevent the body diode of synchronous switches B and D from turning on and storing charge during the dead time. In particular , D B significantly reduces reverse recovery current between switch B turn-off and switch A turn-on, and D D signifi- cantly reduces reverse recovery current between switch D turn-off and switch C turn-on. They improve converter efficiency and reduce switch voltage stress. In order for the diode to be effective, the inductance between it and the synchronous switch must be as small as possible, mandating that these components be placed adjacently. CIN and COUT Selection Input and output capacitance is necessary to suppress voltage ripple caused by discontinuous current moving in and out the regulator . A parallel combination of capac- itors is typically used to achieve high capacitance and low equivalent series resistance (ESR). Dry tantalum, special polymer , aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Capacitors with low ESR and high ripple current ratings, such as OS-CON and POSCAP are also available. Ceramic capacitors should be placed near the regulator input and output to suppress high frequency switching spikes. Ceramic capacitors, of at least 1µF, should also be placed from VIN to GND and VOUT to GND as close to the LT8392 pins as possible. Due to their excellent low ESR characteristics, ceramic capacitors can significantly reduce input ripple voltage and help reduce power loss in the higher ESR bulk capacitors. X5R or X7R dielec - trics are preferred, as these materials retain their capac- itance over wide voltage and temperature ranges. Many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired operating voltage. Input Capacitance C IN: Discontinuous input current is highest in the buck region due to the switch A toggling on and off. Make sure that the CIN capacitor network has low enough ESR and is sized to handle the maximum RMS current. In buck region, the input RMS current is given by: IRMS ≈IOUT(MAX) •VOUT VIN
VIN VOUT The formula has a maximum at VIN = 2VOUT, where IRMS = IOUT(MAX)/2. This simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief.

Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION Output Capacitance C OUT: Discontinuous current shifts from the input to the output in the boost region. Make sure that the COUT capacitor network is capable of reduc- ing the output voltage ripple. The effects of ESR and the bulk capacitance must be considered when choosing the right capacitor for a given output ripple voltage. The max- imum steady state ripple due to charging and discharging the bulk capacitance is given by: ΔVCAP(BOOST) = IOUT(MAX) • VOUT −VIN(MIN)( ) COUT •VOUT •f ΔVCAP(BUCK) = VOUT • 1− VOUT VIN(MAX) 8 •L •f2 •COUT The maximum steady ripple due to the voltage drop across the ESR is given by: ΔVESR(BOOST) = VOUT •IOUT(MAX) VIN(MIN)

ESR ΔVESR(BUCK) = VOUT • 1− VOUT VIN(MAX) L •f •ESR INTVCC Regulator An internal P-channel low dropout regulator produces 5V at the INTVCC pin from the VIN supply pin. The INTVCC powers internal circuitry and gate drivers in the LT8392. The INTVCC regulator can supply a peak current of 145mA and must be bypassed to ground with a minimum of 4.7µF ceramic capacitor . Good local bypass is necessary to supply the high transient current required by MOSFET gate drivers. Higher input voltage applications with large MOSFETs being driven at higher switching frequencies may cause the maximum junction temperature rating for the LT8392 to be exceeded. The system supply current is normally dominated by the gate charge current. Additional external loading of the INTVCC also needs to be taken into account for the power dissipation calculation. The total LT8392 power dissipation in this case is VIN • IINTVCC, and overall efficiency is lowered. The junction temperature can be estimated by using the equation: T J = TA + PD • θJA where θJA (in °C/W) is the package thermal resistance. To prevent maximum junction temperature from being exceeded, the input supply current must be checked oper- ating in continuous mode at maximum VIN. Top Gate MOSFET Driver Supply (CBST1, CBST2) The top MOSFET drivers, TG1 and TG2, are driven between their respective SW and BST pin voltages. The boost volt- ages are biased from floating bootstrap capacitors CBST1 and CBST2, which are normally recharged through both the external and internal bootstrap diodes when the respec - tive top MOSFET is turned off. External bootstrap diodes are recommended because the internal bootstrap diodes are not always strong enough to refresh top MOSFETs at 2MHz. Both capacitors are charged to the same voltage as the INTV CC voltage. The bootstrap capacitors C BST1 and CBST2, need to store about 100 times the gate charge required by the top switches A and D. In most applica - tions, a 0.1µF to 0.47µF, X5R or X7R dielectric capacitor is adequate. Programming VIN UVLO A resistor divider from V IN to the EN/UVLO pin imple - ments VIN undervoltage lockout (UVLO). The EN/UVLO enable falling threshold is set at 1.220V with 13mV hyster- esis. In addition, the EN/UVLO pin sinks 2.5µA when the voltage on the pin is below 1.220V. This current provides user programmable hysteresis based on the value of R1. The programmable UVLO thresholds are: VIN(UVLO+) = 1.233V •R1+R2 R2 + 2.5µA •R1 VIN(UVLO−) = 1.220V •R1+R2

Figure 13. Programming Input Current Limit

8392 F13a

8392 F13b

output power and switching current when VIN is low. Figure 12. VIN Undervoltage Lockout (UVLO)

8392 F12

Table 2. V(ISP-ISN) Threshold vs VCTRL

Figure 14. Programming Output Current Limit

8392 F14a

8392 F14b

pins should be shorted to VIN, VOUT, or ground.

20 + 0.25V. Since the ISMON pin has the same 0.25V offset as the CTRL pin, the master LT8392 ISMON pin can be directly tied to the slave LT8392 CTRL pin for equal current sharing in parallel applications. Programming Output Voltage and Thresholds The LT8392 has a voltage feedback pin FB that can be used to program a constant-voltage output. The output voltage can be set by selecting the values of R3 and R4 (Figure 15) according to the following equation: L T8392 VOUT

8392 F15

Figure 15. Feedback Resistor Connection

Rev. 0For more information www.analog.com APPLICATIONS INFORMATION SS pin. As the SS pin voltage rises linearly from 0.25V to 1V (and beyond), the output voltage rises smoothly into its final voltage regulation. The soft-start time can be calculated as: tSS = 1V • CSS 12.5µA Make sure the CSS is at least five to ten times larger than the compensation capacitor on the VC pin for a well-con- trolled output voltage soft-start. A 22nF ceramic capacitor is a good starting point. The SS pin is also used as a fault timer . Once an output short-circuit fault is detected, a 1.25µA pull-down current source is activated. Using a single resistor from the SS pin to the VREF pin, the LT8392 can be set to three differ- ent fault protection modes: hiccup (no resistor), latch-off (499k), and keep-running (100k). With a 100k resistor in keep-running mode, the LT8392 continues switching normally and regulates the current into ground. With a 499k resistor in latch-off mode, the LT8392 stops switching until the EN/UVLO pin is pulled low and high to restart. With no resistor in hiccup mode, the LT8392 enters low duty cycle auto-retry operation. The 1.25µA pull-down current discharges the SS pin to 0.2V and then 12.5µA pull-up current charges the SS pin up. If the output short-circuit condition has not been removed when the SS pin reaches 1.75V, the 1.25µA pull- down current turns on again, initiating a new hiccup cycle. This will continue until the fault is removed. Once the output short-circuit condition is removed, the output will have a smooth short-circuit recovery due to soft-start. Loop Compensation The LT8392 uses an internal transconductance error amplifier , the output of which, VC, compensates the con- trol loop. The external inductor , output capacitor , and the compensation resistor and capacitor determine the loop stability. The inductor and output capacitor are chosen based on performance, size and cost. The compensation resistor and capacitor on the V C pin are set to optimize control loop response and stability. For a typical voltage regulator application, a 2.2nF compensation capacitor on the VC pin is adequate, and a series resistor should always be used to increase the slew rate on the VC pin to maintain tighter output voltage regulation during fast transients on the input supply of the converter . Efficiency Considerations The power efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in circuits produce losses, four main sources account for most of the losses in LT8392 circuits: 1. DC I2R losses. These arise from the resistances of the MOSFETs, sensing resistor , inductor and PC board traces and cause the efficiency to drop at high output currents. 2. T ransition loss. This loss arises from the brief amount of time switch A or switch C spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. 3. INTVCC current. This is the sum of the MOSFET driver and control currents. 4. CIN and C OUT loss. The input capacitor has the diffi- cult job of filtering the large RMS input current to the regulator in buck region. The output capacitor has the difficult job of filtering the large RMS output current in boost region. Both CIN and COUT are required to have low ESR to minimize the AC I 2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. 5. Other losses. Schottky diode DB and DD are responsi- ble for conduction losses during dead time and light load conduction periods. Inductor core loss occurs predominately at light loads. Switch A causes reverse

Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION recovery current loss in buck region, and switch C causes reverse recovery current loss in boost region. When making adjustments to improve efficiency, the input current is the best indicator of changes in effi - ciency. If you make a change and the input current decreases, then the efficiency has increased. If there is no change in the input current, then there is no change in efficiency. PC Board Layout Checklist The basic PC board layout requires a dedicated ground plane layer . Also, for high current, a multilayer board pro- vides heat sinking for power components. n The ground plane layer should not have any traces and it should be as close as possible to the layer with power MOSFETs. n Place CIN, switch A, switch B and D B in one compact area. Place C OUT, switch C, switch D and D D in one compact area. n Use immediate vias to connect the components to the ground plane. Use several large vias for each power component. n Use planes for VIN and VOUT to maintain good voltage filtering and to keep power losses low. n Flood all unused areas on all layers with copper . Flooding with copper will reduce the temperature rise of power components. Connect the copper areas to any DC net (VIN or GND). n Separate the signal and power grounds. All small-sig- nal components should return to the exposed GND pad from the bottom, which is then tied to the power GND close to the sources of switch B and switch C. n Place switch A and switch C as close to the controller as possible, keeping the PGND, BG and SW traces short. n Keep the high dV/dT SW1, SW2, BST1, BST2, TG1 and TG2 nodes away from sensitive small-signal nodes. n The path formed by switch A, switch B, D B and the CIN capacitor should have short leads and PCB trace lengths. The path formed by switch C, switch D, DD and the COUT capacitor also should have short leads and PCB trace lengths. n The output capacitor (–) terminals should be connected as close as possible to the (–) terminals of the input capacitor . n Connect the top driver bootstrap capacitor C BST1 closely to the BST1 and SW1 pins. Connect the top driver bootstrap capacitor C BST2 closely to the BST2 and SW2 pins. n Connect the input capacitors CIN and output capacitors COUT closely to the power MOSFETs. These capacitors carry the MOSFET AC current. n Route LSP and LSN traces together with minimum PCB trace spacing. Avoid sense lines pass through noisy areas, such as switch nodes. The filter capacitor between LSP and LSN should be as close as possible to the IC. Ensure accurate current sensing with Kelvin connections at the R SENSE resistor . Low ESL sense resistor is recommended. n Connect the V C pin compensation network close to the IC, between VC and the signal ground. The capac- itor helps to filter the effects of PCB noise and output voltage ripple voltage from the compensation loop. n Connect the INTVCC bypass capacitor , CINTVCC, close to the IC, between the INTVCC and the power ground. This capacitor carries the MOSFET drivers’ current peaks.

Rev. 0For more information www.analog.com TYPICAL APPLICATIONS 165k 0.1µF 4m/uni03A9 0.1µF 22µF 63V 4.7µF 100V 10µF 25V 120µF 16V 120µF 16V VOUT 12V 383k 4.7µF 100k 0.47µF 100k 400kHz 4.7nF 27k 100k

8392 TA02a

9.09k 10m/uni03A9 0.1µF 1µF 1µF 100pF 6µH EN/UVLO V REF CTRL PGOOD BG2 BST2 TG2 INTV CC TRIM FB V OUT EXTVCC ISP ISN SYNC/SPRD TEST V IN 3V TO 56V ISMON PGOOD LSP LSN SW1 SW2 BST1 TG1 BG1 V IN L T8392 ISMON SS V C RT GND SSFM OFF SSFM ON I OUT LIMIT 5A L1: WURTH 7443551600 6µH M1, M2: INFINEON BSZ100N06LS3 M3, M4: INFINEON BSZ033NE2LS5 98% Efficient 48W (12V 4A) Buck-Boost Voltage Regulator

Rev. 0 For more information www.analog.com PACKAGE DESCRIPTION FE28 (EB) TSSOP REV L 0117 0.09 – 0.20 (.0035 – .0079) 0° – 8° 0.25 REF 0.50 – 0.75 (.020 – .030) 4.30 – 4.50* (.169 – .177) 1 3 4 5 6 7 8 9 10 11 12 13 14 192022 21 151618 17 9.60 – 9.80* (.378 – .386) 4.75 (.187) 2.74 (.108) 28 27 26 2524 23 1.20 (.047) MAX 0.05 – 0.15 (.002 – .006) 0.65 (.0256) BSC 0.195 – 0.30 (.0077 – .0118) TYP 2RECOMMENDED SOLDER PAD LAYOUT EXPOSED PAD HEAT SINK ON BOTTOM OF PACKAGE0.45 ±0.05

0.65 BSC

4.50 ±0.10 6.60 ±0.10 1.05 ±0.10 4.75 (.187) 2.74 (.108) MILLIMETERS (INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE SEE NOTE 4 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT 6.40 (.252) BSC 28-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev L) Exposed Pad Variation EB

Rev. 0For more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION 4.00 ±0.10 (2 SIDES)

2.50 REF

5.00 ±0.10 (2 SIDES) NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT , SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONL Y A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ±0.10 27 28 BOTTOM VIEW—EXPOSED PAD

3.50 REF

0.75 ±0.05 R = 0.115 TYP R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 × 45° CHAMFER 0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UFD28) QFN 0816 REV C RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 0.25 ±0.05 4.10 ±0.05 5.50 ±0.05 2.65 ±0.05 3.10 ±0.05 4.50 ±0.05 PACKAGE OUTLINE 2.65 ±0.10 3.65 ±0.10 3.65 ±0.05 28-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1712 Rev C)

Rev. 0 For more information www.analog.com  ANALOG DEVICES, INC. 2020 www.analog.com RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LT8390/LT8390A 60V Synchronous 4-Switch Buck-Boost Controller with Spread Spectrum VIN: 4V to 60V, VOUT: 0V to 60V, ±1.5% Voltage Accuracy, ±3% Current Accuracy, TSSOP-28 and 4mm × 5mm QFN-28 LT3790 60V Synchronous 4-Switch Buck-Boost Controller VIN: 4.7V to 60V, VOUT: 1.2V to 60V, Regulates VOUT, IOUT, IIN, TSSOP-38 LT8705 80V VIN and VOUT Synchronous 4-Switch Buck-Boost DC/DC Controller VIN: 2.8V to 80V, VOUT: 1.3V to 80V, Regulates VOUT, IOUT, VIN, IIN, 5mm × 7mm QFN-38 and Modified TSSOP-38 for High Voltage LT C

3789 High Efficiency Synchronous 4-Switch Buck-Boost

VIN: 4V to 38V, VOUT: 0.8V to 38V, Regulates VOUT, IOUT or IIN, 5mm × 5mm QFN-32 and SSOP-24 LTC3780 High Efficiency Synchronous 4-Switch Buck-Boost Controller VIN: 4V to 36V, VOUT: 0.8V to 30V, Regulates VOUT, 4mm × 5mm QFN-28 and SSOP-28 LT3757/LT3757A Boost, Flyback, SEPIC and Inverting Controller VIN: 2.9V to 40V, Positive or Negative VOUT, 3mm × 3mm DFN-10, MSOP-10 LT3758 High Input Voltage, Boost, Flyback, SEPIC and Inverting Controller VIN: 5.5V to 100V, Positive or Negative VOUT, 3mm × 3mm DFN-10, MSOP-10 LT8710 Synchronous SEPIC/Inverting/Boost Controller with Output Current Control VIN: 4.5V to 80V, Rail-to-Rail Output Current Monitor and Control, TSSOP-28 125W (25V 5A) Solar Panel to 12V Battery Charger 121k 0.1µF 2.5m/uni03A9 0.1µF 47µF 80V 47µF 80V 4.7µF 100V 10µF 50V 82µF 50V 475k 4.7µF

8392 TA03

0.47µF 174k 27nF 750k 49.9k 8m/uni03A9 301k 0.1µF 1µF 1µF 2.2µF 10/uni03A9 10/uni03A9 100k 301k 4.7µH EN/UVLO V REF CTRL PGOOD BG2 BST2 TG2 INTV CC TRIM FB V OUT ISN ISP SYNC/SPRD TEST 250kHz ISMON VOUT VIN 0V TO 48V LSP LSN SW1 SW2 BST1 TG1 BG1 V IN L T8392 EXTVCC ISMON SS V C RT GND INPUT CURRENT CONTROL 0.25V TO 1V FOR 0A TO 5A 6V V IN UVLO L1: WURTH 7443640470 4.7uH M1: INFINEON BSC067N06LS3 M2: INFINEON BSC028N06LS3 M3, M4: INFINEON BSC010N04LS TO 12V BATTERYFROM SOLAR PANEL

Summary

60V Synchronous 4-Switch Buck-Boost Controller with Spread Spectrum

Description