LT8609

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Rev. 0For more information www.analog.com Document Feedback TYPICAL APPLICATION FEATURES DESCRIPTION Dual Channel 2A, 42V, Synchronous Step-Down Silent Switcher with 6.2µA Quiescent Current The LT®8653S is a dual step-down regulator that delivers up to 2A of continuous current from both channels and supports loads up to 3A from each channel. The LT8653 S features the second generation Silent Switcher architecture to minimize EMI emissions while delivering high efficiency at high switching frequencies. This includes integration of bypass capacitors to optimize high frequency current loops and make it easy to achieve advertised EMI performance by eliminating layout sensitivity. The fast, clean, low overshoot switching edges enable high efficiency operation even at high switching frequencies, leading to a small solution size with wide control loop bandwidth for fast transient response. Burst Mode operation enables ultralow standby current consumption or forced continuous mode can be used to control frequency harmonics across the entire output load range. The LT8653S is a full featured, customizable voltage regulator, but also has several pin strap options to select internal 2MHz switching frequency, internal compensation and internal feedback resistor divider options to create a simple, compact two output voltage regulator with only five external components. 5V/2A, 3.3V/2A 2MHz Step-Down Converter Efficiency

APPLICATIONS

n Silent Switcher®2 Architecture: n Ultralow EMI on Any PCB n Eliminates PCB Layout Sensitivity n Internal Bypass Capacitors Reduce Radiated EMI n Optional Spread Spectrum Modulation n 2A DC from Each Channel Simultaneously n Up to 3A on Either Channel n Ultralow Quiescent Current Burst Mode® Operation: n 6.2μA IQ Regulating 12VIN to 5VOUT1 and 3.3VOUT2 n Output Ripple < 10mVP–P n Optional External VC Pin: Fast T ransient Response n Forced Continuous Mode n High Efficiency at High Frequency n 94.1% Efficiency at 1A, 5VOUT from 12VIN at 2MHz n Pin-Selectable Fixed Output Voltages: 5V, 3.3V, 1.8V n Fast Minimum Switch-On Time: 30ns n Wide Input Voltage Range: 3.0V to 42V n Adjustable and Synchronizable: 300kHz to 3MHz n Fixed Output Pin Strap Options n Internal 2MHz fSW with Fast Internal Compensation n Small 4mm × 3mm 20-Pin LQFN Package n AEC-Q100 Automotive Qualification in Progress n General Purpose Step-Down n Automotive and Industrial Supplies All registered trademarks and trademarks are the property of their respective owners. VIN = 12V fSW = 2MHz 5VOUT 3.3VOUT LOAD CURRENT (A) 0.5 1.5 2.5 100 EFFICIENCY (%) 8653S TA01b L T8653S 8653S TA01a RT VIN EN/UV SW1 FB1 VC1 VC2 SW2 FB2 BIAS VCC GND SYNC 47µF 100µF 4.7µF 2.2µH 2.2µHVOUT1 VOUT2 3.3V V IN 5.6V TO 42V fSW = 2MHz

Rev. 0 For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS BIAS FB1, FB2, SYNC. Operating Junction Temperature Range (Note 2) LT 8653SE LT 8653SI Storage Temperature Range Maximum Reflow (Package Body) Temperature ...260°C (Note 1) LQFN PACKAGE 20-LEAD (4mm × 3mm × 0.94mm) TJMAX/uni00A0=/uni00A0125°C, θJA/uni00A0=/uni00A028°C/W EXPOSED PAD (PIN 21 IS GND, MUST BE SOLDERED TO PCB GND TOP VIEW VC2 FB2 SS2 SS1 FB1 VC1 PG2 PG1 SYNC CLKOUT BIAS V CC SW2 SW1 RT EN/UV VIN VIN 16 15 14 13 12 11 1 2 3 4 5 6 ORDER INFORMATION

ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Input Voltage l 2.6 3 V VIN Quiescent Current in Shutdown V EN/UV = 0V, VSYNC = 0V l 1.7 4 µA µA VIN + VCC Quiescent Current in Sleep with Internal Compensation VEN/UV = 2V, VFB1 = VFB2 > 0.8V, VVC1 = VVC2 = VCC, VSYNC = 0V l 3.7 8 µA µA VIN + VCC Quiescent Current in Sleep with External Compensation VEN/UV = 2V, VFB1 = VFB2 > 0.8V, VVC1 = VVC2 = Float, VSYNC = 0V l 95 160 180 µA µA VIN + VCC Quiescent Current when Active VEN/UV = 2V, VFB1 = VFB2 > 0.8V, VVC1 = VVC2 = VCC, VSYNC = 3.4V 7 9 mA VIN Current In Regulation VIN = 6V, VOUT = 0.8V, Output Load = 100µA VIN = 6V, VOUT = 0.8V, Output Load = 1mA 350 500 µA µA The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE** TYPE MSL RATING TEMPERA TURE RANGE (SEE NOTE 2)DEVICE FINISH CODE LT8653SEV#PBF Au (RoHS) 8653SV e4 LQFN (Laminate Package with QFN Footprint) 3 – 40°C to 125°C LT8653SIV#PBF 3 –40°C to 125°C AUTOMOTIVE PRODUCTS* LT8653SEV#WPBF Au (RoHS) 8653SV e4 LQFN (Laminate Package with QFN Footprint) 3 – 40°C to 125°C LT8653SIV#WPBF 3 –40°C to 125°C Consult Marketing for parts specified with wider operating temperature ranges. *Pad or ball finish code is per IPC/JEDEC J-STD-609. Recommended LGA and BGA PCB Assembly and Manufacturing Procedures LGA and BGA Package and Tray Drawings **The LT8653S package has the same dimensions as a standard 4mm × 3mm QFN package

Rev. 0For more information www.analog.com Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT8653SE is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8653SI is guaranteed over the full –40°C to 125°C operating junction temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater PARAMETER CONDITIONS MIN TYP MAX UNITS Feedback Reference Voltage l 0.794 0.790 0.8 0.8 0.806 0.810 V V 5.0V Reference Voltage l 4.925 5.0 5.075 V 3.3V Reference Voltage l 3.25 3.3 3.35 V 1.8V Reference Voltage l 1.773 1.8 1.827 V Feedback Voltage Line Regulation 0.004 0.02 %/V Feedback Pin Input Current –20 20 nA Minimum On-Time ILOAD = 1.5A, SYNC = 0V ILOAD = 1.5A, SYNC = 3.4V l l ns ns Oscillator Frequency RT = 133k RT = 35.7k RT = 15k RT = VCC l l l l 270 0.94 1.85 1.8 300 330 1.06 2.15 2.2 kHz MHz MHz MHz Top Power NMOS Current Limit V CC = 3.4V l 4.5 5.1 6.2 A Bottom Power NMOS Current Limit V CC = 3.4V 3 4 5 A SW Leakage Current VIN = 42V, VSW = 0V, 42V –1.5 1.5 µA EN/UV Pin Threshold EN/UV Falling l 0.7 0.74 0.78 V EN/UV Pin Hysteresis 30 mV EN/UV Pin Current VEN/UV = 2V –20 20 nA PG Upper Threshold Offset from VFB VFB Falling l 5.2 7 8.8 % PG Lower Threshold Offset from VFB VFB Rising l –9.3 –7.5 –5.7 % PG Hysteresis 0.3 % PG Leakage VPG = 3.3V –40 40 nA PG Pull-Down Resistance VPG = 0.1V l 600 1200 Ω SYNC Threshold SYNC DC and Clock Low Level Voltage SYNC Clock High Level Voltage SYNC DC High Level Voltage 0.4 1.5 2.8 V V V SYNC Pin Current V SYNC = 6V 120 µA SS Source Current l 1 2 3 µA SS Pull-Down Resistance Fault Condition, SS = 0.1V 160 Ω Error Amplifier Transconductance VC = 1.25V 1.3 mS VC Source Current VFB = 0.6V, VVC = 1.25V 170 µA VC Sink Current VFB = 1.0V, VVC = 1.25V 170 µA VC Pin to Switch Current Gain 4.8 A/V The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. than 125°C. The junction temperature (TJ, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation in the IC (PD, in watts) according to the formula: TJ = TA + (PD • θJA), where θJA (in °C/W) is the package thermal impedance. Note 3 This IC includes overtemperature protection that is intended to protect the device during overload conditions. Junction temperature will exceed 150°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature will reduce lifetime.

Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS 5VOUT Efficiency 5VOUT Efficiency 3.3VOUT Efficiency 3.3VOUT Efficiency Efficiency at Different fSW Efficiency vs fSW Load Regulation Line Regulation 0.8V Reference Voltage L = XFL4020-222ME, 2.2µH fSW = 2MHz, FCM LOAD CURRENT (A) 0.5 1.5 2.5 100 EFFICIENCY (%) 8653S G01 12V 24V L = XFL4020-222, 2.2µH fSW = 2MHz, Burst Mode OPERATION 12V 24V LOAD CURRENT (mA) 0.1 100 10k 100 EFFICIENCY (%) 8653S G02 L = XFL4020-222ME, 2.2µH fSW = 2MHz, FCM 12V 24V LOAD CURRENT (A) 0.5 1.5 2.5 100 EFFICIENCY (%) 8653S G03 L = XFL4020-222, 2.2µH fSW = 2MHz, Burst Mode OPERATION 12V 24V LOAD CURRENT (mA) 0.1 100 10k 100 EFFICIENCY (%) 8653S G04 3.3V OUT 12V IN 0.5MHz, XEL4030 4.7µH 1MHz, XFL4020 2.2µH 2MHz, XFL4020 2.2µH 3MHz, XFL4020 2.2µH LOAD CURRENT (A) 0.5 1.5 2.5 100 EFFICIENCY (%) 8653S G05 12V IN 3.3V OUT 0.9A LOAD L = XFL4020, 2.2µH SWITCHING FREQUENCY (MHZ) 0.5 1.5 2.5 100 EFFICIENCY (%) 8653S G06 CH1 CH2 OUTPUT CURRENT (A) 0.5 1.5 2.5 –0.40 –0.30 –0.20 –0.10 0.00 0.10 0.20 0.30 0.40 CHANGE IN V OUT (%) 8653S G07 VIN = 12V VOUT1 = 5V , VOUT2 = 3.3V FCM, fSW = 2MHz I OUT = 0.5A FCM, f SW = 2MHz INPUT VOL TAGE (V) –0.4 –0.3 –0.2 –0.1 0.0 0.1 0.2 0.3 0.4 CHANGE IN V OUT (%) 8653S G08 CH1 CH2 TEMPERATURE (°C) –55 –25 125 155 0.790 0.792 0.794 0.796 0.798 0.800 0.802 0.804 0.806 0.808 0.810 REFERENCE VOL TAGE (V) 8653S G09

Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS 5V Output Voltage 3.3V Output Voltage 1.8V Output Voltage No Load Supply Current with Internal Compensation No Load Supply Current with External Compensation No Load Supply Current Top FET Current Limit Top FET Current Limit V OUT1 = 5V , V OUT2 = 3.3V SYNC = 0V , BIAS = V OUT1 BOTH CHANNELS IN REGULATION INTERNAL COMPENSATION INPUT VOL TAGE (V) INPUT CURRENT (µA) 8653S G13 INTERNAL FB DIVIDER (D0 = D1 = OPEN) EXTERNAL FB DIVIDER (D0 = D1 = 0V) V OUT1 = 5V , V OUT2 = 3.3V SYNC = 0V BOTH CHANNELS IN REGULATION EXTERNAL COMPENSATION INPUT VOL TAGE (V) 100 120 140 160 INPUT CURRENT (µA) 8653S G14 BIAS = VOUT1 BIAS = FLOAT TEMPERATURE (°C) –55 –25 125 155 100 120 INPUT CURRENT (µA) 8653S G15 INTERNAL COMPENSATION EXTERNAL COMPENSATION VIN = 12V VOUT1 = 5V , VOUT2 = 3.3V D0/D1 = OPEN/OPEN VBIAS = VOUT1, SYNC = 0V BOTH CHANNELS IN REGULATION TEMPERATURE (°C) –55 –25 125 155 4.900 4.920 4.940 4.960 4.980 5.000 5.020 5.040 5.060 5.080 5.100 REFERENCE VOL TAGE (V) 5V Output Voltage 8653S G10 TEMPERATURE (°C) –55 –25 125 155 3.240 3.255 3.270 3.285 3.300 3.315 3.330 3.345 3.360 REFERENCE VOL TAGE (V) 3.3V Output Voltage 8653S G11 TEMPERATURE (°C) –55 –25 125 155 1.760 1.770 1.780 1.790 1.800 1.810 1.820 1.830 1.840 REFERENCE VOL TAGE (V) 1.8V Output Voltage 8653S G12 DUTY CYCLE 0.2 0.4 0.6 0.8 CURRENT LIMIT (A) Top FET Current Limit 8653S G16 30% DC TEMPERATURE (°C) –55 –25 125 155 CURRENT LIMIT (A) Top FET Current Limit 8653S G17

Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Switch VDS Minimum On-Time Minimum Off-Time Dropout Voltage Switching Frequency Burst Frequency Soft-Start T racking Soft-Start Current EN Pin Thresholds I DS (A) 0.5 1.5 100 200 300 400 500 600 SWITCH V DS (mV) 8653S G18 TOP FET BOT FET FCM, 1A LOAD TEMPERATURE (°C) –55 –25 125 155 MINIMUM ON-TIME (ns) 8653S G19 FCM, 0.5A LOAD TEMPERATURE (°C) –55 –25 125 155 MINIMUM OFF-TIME (ns) 8653S G20 LOAD CURRENT (A) 0.5 1.5 100 200 300 400 500 600 700 800 900 1000 DROPOUT VOL TAGE (mV) 8653S G21 FCM Burst Mode OPERATION VOUT = 3V fSW = 2MHz TEMPERATURE (°C) –55 –25 125 155 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 SWITCHING FREQUENCY (MHz) 8653S G22 RT = 15k/uni03A9 RT = VCC V IN = 12V , V OUT = 5V SYNC = 0V R T = 15kΩ L = 2.2µH LOAD CURRENT (A) 0.1 0.2 0.3 0.4 0.5 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 SWITCHING FREQUENCY (MHz) 8653S G23 SS VOL TAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 0.2 0.4 0.6 0.8 1.0 FB VOL TAGE (V) 8653S G24 INTERNAL COMPENSATION EXTERNAL COMPENSATION V SS = 0.4V TEMPERATURE (°C) –55 –25 125 155 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 SS PIN CURRENT (µA) 8653S G25 TEMPERATURE (°C) –55 –25 125 155 0.70 0.71 0.72 0.73 0.74 0.75 0.76 0.77 0.78 EN THRESHOLD (V) 8653S G26 EN RISING EN FALLING

Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS PG High Thresholds PG Low Thresholds RT Programmed Switching Frequency Minimum Input Voltage Bias Pin Current per Channel Bias Pin Current per Channel T ransient Response: Internal Compensation T ransient Response: External Compensation RISING TEMPERATURE (°C) –55 –25 125 155 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 PG THRESHOLD OFFSET FROM V REF (%) 8653S G27 FALLING TEMPERATURE (°C) –55 –25 125 155 –10.0 –9.5 –9.0 –8.5 –8.0 –7.5 –7.0 –6.5 –6.0 –5.5 –5.0 PG THRESHOLD OFFSET FROM V REF (%) 8653S G28 SWITCHING FREQUENCY (MHZ) 0.5 1.5 2.5 105 120 135 150 RT PIN RESISTOR (kΩ) 8653S G31 TEMPERATURE (°C) –55 –25 125 155 2.0 2.2 2.4 2.6 2.8 3.0 INPUT VOL TAGE (V) 8653S G32 INPUT VOL TAGE (V) 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 BIAS PIN CURRENT (mA) 8653S G31 fSW = 2MHz LOAD = 2A SWITCHING FREQUENCY (MHZ) 0.5 1.5 2.5 BIAS PIN CURRENT (mA) 8653S G32 VIN = 12V LOAD = 2A T ransient Response: Internal Compensation with Internal 2MHz f SW 40ms/DIV IL 1A/DIV VOUT 100mV/DIV 8653S G33 0A TO 1A TRANSIENT 3.3VOUT, D0 = D1 = 0V COUT = 100µF FCM, fSW = 2MHz (RT = 15k/uni03A9) 40ms/DIV IL 1A/DIV VOUT 100mV/DIV 8653S G34 0A TO 1A TRANSIENT 3.3V OUT, D0 = D1 = 0V COUT = 100µF FCM, fSW = 2MHz (RT = VCC) 40ms/DIV IL 1A/DIV VOUT 100mV/DIV 8653S G35 0A TO 1A TRANSIENT 3.3V OUT, D0 = D1 = 0V COUT = 100µF FCM, fSW = 2MHz (RT = 15k/uni03A9) CC = 470pF, RC = 34.8k/uni03A9

Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Switch Rising Edge CH1, CH2 and CLKOUT Forced Continuous Mode (FCM) Burst Mode Operation Case Temperature Rise Case Temperature Rise 1ns/DIV V SW 2V/DIV 8653S G36 V IN = 12V CH1 = 5V OUT AT 0A CH2 = 3.3V OUT AT 0A SYNC = FLOAT 500ns/DIV SW1 10V/DIV SW2 10V/DIV CLKOUT 2V/DIV 8653S G37 12V IN to 5V OUT AT 100mA SYNC = FLOAT 2µs/DIV SW 5V/DIV I L 500mA/DIV 8653S G38 12V IN to 5V OUT AT 100mA SYNC = 0V 2µs/DIV SW 5V/DIV I L 500mA/DIV 8653S G39 LOAD1 CURRENT (A) 0.5 1.5 2.5 100 110 120 CASE TEMPERATURE RISE (°C) 8653S G40 12VIN, LOAD2 = LOAD 1 24VIN, LOAD2 = LOAD 1 12VIN, LOAD2 = 0A 12VIN, LOAD2 = 2A DC2535A DEMO BOARD VOUT1 = 5V , VOUT2 = 3.3V fSW = 2MHz DUTY CYCLE OF PULSED LOAD 0.2 0.4 0.6 0.8 100 CASE TEMPERATURE RISE (°C) 8653S G41 CH1 = CH2 = 0.5A STANDBY, 3A PULSED CH1 = 0.5A STANDBY, 3A PULSED; CH2 = 0A CH1 = 0.5A STANDBY, 3A PULSED; CH2 = 2A DC2535A DEMO BOARD VIN = 12V VOUT1 = 5V , VOUT2 = 3.3V fSW = 2MHz

Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Conducted EMI Performance Radiated EMI Performance (CISPR25 Radiated Emission Test with Class 5 Peak) Radiated EMI Performance (CISPR25 Radiated Emission Test with Class 5 Average Limits) DC2535A DEMO BOARD (WITH EMI FIL TER INSTALLED) 14V INPUT TO 5V OUTPUT1 AT 2A AND 3.3V OUTPUT2 AT 2A, f SW = 2MHz SPREAD SPECTRUM MODE FIXED FREQUENCY MODE FREQUENCY (MHz) –40 –30 –20 –10 AMPLITUDE (dBµV/m) 8653S G42 DC2535A DEMO BOARD (WITH EMI FIL TER INSTALLED) 14V INPUT TO 5V OUTPUT1 AT 2A AND 3.3V OUTPUT2 AT 2A, f SW = 2MHz VERTICAL POLARIZATION PEAK DETECTOR CLASS 5 PEAK LIMIT SPREAD SPECTRUM MODE FIXED FREQUENCY MODE FREQUENCY (MHz) 100 200 300 400 500 600 700 800 900 1000 AMPLITUDE (dBµV/m) 8653S G43 DC2535A DEMO BOARD (WITH EMI FIL TER INSTALLED) 14V INPUT TO 5V OUTPUT1 AT 2A AND 3.3V OUTPUT2 AT 2A, f SW = 2MHz VERTICAL POLARIZATION AVERAGE DETECTOR CLASS 5 AVERAGE LIMIT SPREAD SPECTRUM MODE FIXED FREQUENCY MODE FREQUENCY (MHz) 100 200 300 400 500 600 700 800 900 1000 –15 –10 AMPLITUDE (dBµV/m) 8653S G44

Rev. 0 For more information www.analog.com PIN FUNCTIONS D0 (Pin 1): Output Voltage Select Bit. D0 should be tied high to VCC, low to GND or left open to select the desired FB regulation voltage (see Table 1). D1 (Pin 2): Output Voltage Select Bit. D1 should be tied high to VCC, low to GND or left open to select the desired FB regulation voltage (see Table 1). PG2 (Pin 3): The PG2 pin is the open-drain output of an internal comparator . PG2 remains low until the FB2 pin is within ±7.5% of the final regulation voltage and there are no fault conditions. PG2 is pulled low during V IN UVLO, VCC UVLO, thermal shutdown or when the EN/UV pin is low. PG1 (Pin 4): The PG1 pin is the open-drain output of an internal comparator . PG1 remains low until the FB1 pin is within ±7.5% of the final regulation voltage and there are no fault conditions. PG1 is pulled low during V IN UVLO, VCC UVLO, thermal shutdown or when the EN/UV pin is low. SYNC (Pin 5) : External Clock Synchronization Input. Ground this pin for low ripple Burst Mode operation at low output loads. Apply a DC voltage of 2.8V or higher or tie to V CC for forced continuous mode with spread spectrum modulation. Float the SYNC pin for forced continuous mode without spread spectrum modulation. When in forced continuous mode, the I Q will increase to several mA. Apply a clock source to the SYNC pin for synchronization to an external frequency. The LT8653S will be in forced continuous mode when an external fre - quency is applied. CLKOUT (Pin 6): In forced continuous mode, the CLKOUT pin provides a 50% duty cycle square wave 90 degrees out of phase with Channel 1. This allows synchronization with other regulators with up to four phases. When an external clock is applied to the SYNC pin, the CLKOUT pin will output a waveform with the same phase, duty cycle and frequency as the SYNC waveform. In Burst Mode operation, the CLKOUT pin will be grounded. Float this pin if the CLKOUT function is not used. SW1 (Pin 7): The SW1 pin is the output of the Channel 1 internal power switches. Connect this pin to the induc - tor . This node should be kept small on the PCB for good per formance. SW2 (Pin 8): The SW2 pin is the output of the Channel 2 internal power switches. Connect this pin to the induc - tor . This node should be kept small on the PCB for good per formance. VCC (Pin 9): Internal Regulator Bypass Pin. The inter - nal power drivers and control circuits are powered from this voltage. V CC current will be supplied from BIAS if VBIAS > 3.1V, otherwise current will be drawn from V IN. Voltage on V CC will vary between 2.8V and 3.3V when VBIAS is between 3.0V and 3.5V. Do not load the VCC pin with external circuitry. BIAS (Pin 10): The internal regulator will draw current from BIAS instead of V IN when BIAS is tied to a voltage higher than 3.1V. For output voltages of 3.3V and above this pin should be tied to V OUT. If this pin is tied to a sup- ply other than VOUT, use a 1µF local bypass capacitor on this pin. VC1 (Pin 11): Channel 1 Error Amplifier Output and Switching Regulator Compensation Pin. Connect this pin to appropriate external components to compensate the regulator loop frequency response. Connect this pin to VCC to use the default internal compensation. If internal compensation is used, the burst mode quiescent current is only 2.5µA for Channel 1. If external compensation is used, the burst mode quiescent current is increased to about 50µA for Channel 1. FB1 (Pin 12): The LT8653S regulates the FB1 pin to 800mV, 1.8V, 3.3V, or 5.0V depending on the state of the D0 and D1 pins. If set to 800mV, connect the feedback resistor divider tap to this pin. If set to 1.8V, 3.3V or 5.0V, connect this pin directly to the output.

Rev. 0For more information www.analog.com PIN FUNCTIONS SS1 (Pin 13): Channel 1 Output T racking and Soft-Start Pin. This pin allows user control of output voltage ramp rate during startup. A SS1 voltage below 0.8V forces the LT8653S to regulate the FB1 pin to equal the SS1 pin voltage. When SS1 is above 0.8V, the tracking function is disabled and the internal reference resumes control of the error amplifier . An internal 2μA pull-up current from VCC on this pin allows a capacitor to program output volt- age slew rate. This pin is pulled to ground with a 360Ω MOSFET during shutdown and fault conditions; use a series resistor if driving from a low impedance output. This pin may be left floating if the soft-start feature is not being used. SS2 (Pin 14): Channel 2 Output Tracking and Soft-Start Pin. This pin allows user control of output voltage ramp rate during startup. A SS2 voltage below 0.8V forces the LT8653S to regulate the FB2 pin to equal the S S2 pin voltage. When S S2 is above 0.8V, the tracking function is disabled and the internal reference resumes control of the error amplifier. An internal 2μA pull-up current from VCC on this pin allows a capacitor to program output voltage slew rate. This pin is pulled to ground with a 360Ω MOSFET during shutdown and fault conditions ; use a series resistor if driving from a low impedance output. This pin may be left floating if the soft-start feature is not being used. FB2 (Pin 15): The LT8653S regulates the FB2 pin to 800mV, 1.8V, 3.3V, or 5.0V depending on the state of the D0 and D1 pins. If set to 800mV, connect the feedback resistor divider tap to this pin. If set to 1.8V, 3.3V or 5.0V, connect this pin directly to the output. VC2 (Pin 16): Channel 2 Error Amplifier Output and Switching Regulator Compensation Pin. Connect this pin to appropriate external components to compensate the regulator loop frequency response. Connect this pin to VCC to use the default internal compensation. If internal compensation is used, the burst mode quiescent current is only 2.5µA for Channel 2. If external compensation is used, the burst mode quiescent current is increased to about 50µA for Channel 2. RT (Pin 17): A resistor is tied between RT and ground to set the switching frequency. The RT pin can be tied to V CC to set the switching frequency to 2MHz with a fast internal compensation. EN/UV (Pin 18): Both channels of the LT8653S are shut- down when this pin is low and active when this pin is high. The hysteretic threshold voltage is 0.77V going up and 0.74V going down. Tie to V IN if shutdown feature is not used. An external resistor divider from V IN can be used to program a VIN threshold below which the LT8653S will shut down. Do not float this pin. VIN (Pin 19, 20) : The V IN pins supply current to the LT8653S internal circuitry and to the internal top side power switch of Channel 1 and 2. This pin must be locally bypassed. Be sure to place the positive terminal of the input capacitor as close as possible to the V IN pin, and the negative capacitor terminal as close as possible to the GND pad. GND (Exposed Pad Pin 21): LT8653S System Ground. Connect the exposed pad to the system ground and the board ground plane. Place the negative terminal of the input capacitors as close to the GND pad as possible. The exposed pad must be soldered to the PCB in order to lower the thermal resistance.

Rev. 0 For more information www.analog.com BLOCK DIAGRAM 8653S BD 0.1µF ERROR AMP SHDN THERMAL SHUTDOWN V IN UVLO SHDN THERMAL SHUTDOWN V IN UVLO VCC UVLO SHDN THERMAL SHUTDOWN V IN UVLO SHDN THERMAL SHUTDOWN V IN UVLO VCC UVLO ±7.5% OSCILLATOR 300kHz TO 3MHz DRIVER BURST LOGIC BURST LOGIC ERROR AMP ±7.5% SLOPE COMP SLOPE COMP INTERNAL REFERENCE AND 3.4V REGULATOR 0.8V 0.74V SHDN VCC VCC VCC VCC VC1 VC2 0.8V 2µA 2µA VCC – 0.2V VCC – 0.2V VC1 INTERNAL FEEDBACK RESISTOR DIVIDER INTERNAL FEEDBACK RESISTOR DIVIDER EN/UV BIAS VIN VCC BST1 SW1 VIN BST2 SW2 SS2 FB2 PG2 RT SYNC VC2 SS1 FB1 PG1 GND VOUT1 VOUT2 VIN GND VIN VOUT1 VOUT2 RT CSS1 CSS2 COUT2 COUT1 0.22µF 0.22µF 0.22µF CIN CLKOUT RC2 CC2 RC1 CC1 CFF1 CFF2 SWITCH LOGIC AND ANTI- SHOOT- THROUGH DRIVER SWITCH LOGIC AND ANTI- SHOOT- THROUGH GND

Rev. 0For more information www.analog.com OPERATION Foreword The LT8653S is a dual monolithic step-down regula - tor . The two channels are the same in terms of current capability and power switch size. The following sections describe the operation of channel 1 and common circuits. They will highlight channel 2 differences and interactions only when relevant. Operation The LT8653S is a dual monolithic, constant frequency, peak current mode step-down DC/DC converter . An oscil- lator , with frequency set using a resistor on the RT pin, turns on the internal top power switch at the beginning of each clock cycle. Current in the inductor then increases until the top switch current comparator trips and turns off the top power switch. The peak inductor current at which the top switch turns off is controlled by the voltage on the VC node. The error amplifier servos the V C node by comparing the voltage on the VFB pin with an internal 0.8V reference. When the load current increases, it causes a reduction in the feedback voltage relative to the reference, leading the error amplifier to raise the VC voltage until the average inductor current matches the new load current. When the top power switch turns off, the synchronous power switch turns on until the next clock cycle begins or inductor current falls to zero when not in forced continu- ous mode (FCM). If overload conditions result in more than the bottom NMOS current limit flowing through the bottom switch, the next clock cycle will be delayed until switch current returns to a safe level. The “S” in LT8653S refers to the second generation Silent Switcher technology. This technology allows fast switching edges for high efficiency at high switching fre- quencies, while simultaneously achieving good EMI/EMC performance. This includes the integration of ceramic capacitors into the package for VIN, VCC, BST1 and BST2 (C1–C4 in the block diagram). These caps keep all the fast AC current loops small, which improves EMI/EMC performance. If the EN/UV pin is low, both channels are shut down and the LT8653S draws 1.7µA from the input supply. When the EN/UV pin is above 0.74V, both switching regulators will become active. 6.2μA is supplied by V IN to common bias circuits for both channels. Each channel can independently enter Burst Mode opera- tion to optimize efficiency at light load. Between bursts, all circuitry associated with controlling the output switch is shut down, reducing the channel’s contribution to input supply current. In a typical application, 6.2μA will be consumed from input supply when regulating one chan- nel with no load. Ground the SYNC pin for Burst Mode o peration, float it for forced continuous mode (FCM) or apply a DC voltage higher than 1.8V to use FCM with spread spectrum modulation (SSM). If a clock is applied to the SYNC pin both channels will synchronize to the external clock frequency and operate in FCM. While in FCM, the oscillator operates continuously and rising SW transitions are aligned to the clock. During light loads, the inductor current is allowed to go negative to maintain the programmed switching frequency. Minimum current limits for both power switches are enforced to prevent large negative inductor current from flowing back to the input. SSM dithers the switching frequency from the pro- grammed value set by the RT pin up to 20% higher than the programmed value to spread out the switching energy in the frequency domain. The CLKOUT pin has no output in Burst Mode operation, but outputs a square wave 90 degrees phase shifted from channel 1 when in FCM. If a clock is applied to the SYNC pin, the CLKOUT pin has the same phase and duty cycle as the external clock. To improve efficiency across all loads, supply current to internal circuitry can be sourced from the BIAS pin when biased at 3.3V or above. Otherwise, the internal circuitry will draw current exclusively from VIN. The BIAS

Rev. 0 For more information www.analog.com OPERATION pin should be connected to the lowest VOUT programmed at 3.3V or above. The VC pin allows the loop compensation of the switch - ing regulator to be optimized based on the programmed switching frequency. Internal compensation can be selected by connecting the VC pin to VCC, which simplifies the application circuit. External compensation improves the transient response at the expense of about 50µA more quiescent current per channel. Comparators monitoring the FB pin voltage will pull the corresponding PG pin low if the output voltage varies more than ±7.5% (typical) from the regulation voltage or if a fault condition is present. T racking soft-start is implemented by providing constant current via the SS pin to an external soft-start capacitor to generate a voltage ramp. FB voltage is regulated to the voltage at the SS pin until it exceeds 0.8V; FB is then regulated to the reference 0.8V. When the SS pin is below 40mV, the corresponding switching regulator will stop switching. The SS capacitor is reset during shutdown, VIN undervoltage, or thermal shutdown. Both channels are designed for output currents up to 3A, but thermal considerations practically limit the output currents to 2A of continuous current from each channel simultaneously.

in the Typical Performance Characteristics section. rent resulting in a total of 6.8µA w ith both channels on. lead capacitor should be connected from VOUT to FB. using an external resistor divider . Table 1. D0 and D1 Fixed Output Voltage Configurations by using a resistor tied from the RT pin to ground.

Table 2. SW Frequency vs. RT Value control of inductor current to assure safe operation. VOUT dropout is limited by the RDS(ON) of the top switch. age will be larger due to the smaller maximum duty cycle.

Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION For applications that cannot allow deviation from the pro- grammed switching frequency at low VIN/VOUT ratios use the following formula to set switching frequency: VIN MIN( ) = VOUT +VSW BOT( ) 1– fSW • tOFF MIN( ) – VSW BOT( ) +VSW TOP( ) where V IN(MIN) is the minimum input voltage without skipped cycles, VOUT is the output voltage, VSW(TOP) and VSW(BOT) are the internal switch drops (~ 0.6V, ~0.33V, respectively at maximum load), fSW is the switching fre- quency (set by RT) and tOFF(MIN) is the minimum switch off-time. Note that higher switching frequency will increase the minimum input voltage below which cycles will be dropped to achieve higher duty cycle. Inductor Selection and Maximum Output Current The LT8653S is designed to minimize solution size by allowing the inductor to be chosen based on the output load requirements of the application. During overload or short-circuit conditions, the LT8653S safely tolerates operation with a saturated inductor through the use of a high speed peak-current mode architecture. A good first choice for the inductor value is: L1 ,2= VOUT1 ,2+VSW(BOT) fSW where fSW is the switching frequency in MHz, V OUT is the output voltage, V SW(BOT) is the bottom switch drop (~0.33V) and L is the inductor value in μH. To avoid over- heating and poor efficiency, an inductor must be chosen with an RMS current rating that is greater than the maxi- mum expected output load of the application. In addition, the saturation current (typically labeled I SAT) rating of the inductor must be higher than the load current plus 1/2 of in inductor ripple current: IL PEAK( ) =ILOAD MAX( ) + 1 ∆IL (1) where ∆ IL is the inductor ripple current as calculated in Equation 1 and I LOAD(MAX) is the maximum output load for a given application. As a quick example, an application requiring 1A output should use an inductor with an RMS rating of greater than 1A and an ISAT of greater than 1.3A. During long duration overload or short-circuit conditions, the inductor RMS rating requirement must be greater to avoid overheating of the inductor . To keep the efficiency high, the series resistance (DCR) should be low and the core material should be intended for high frequency applications. The LT8653S limits the peak switch current in order to protect the switches and the system from overload faults. The top switch current limit (ILIM) is at least 6A at low duty cycles and decreases linearly to 4A at DC = 0.8. The induc- tor value must then be sufficient to supply the desired maximum output current (IOUT(MAX)), which is a function of the switch current limit (ILIM) and the ripple current. IOUT MAX( ) =ILIM – ∆IL The peak-to-peak ripple current in the inductor can be calculated as follows: ∆IL = VOUT L • fSW

1– VOUT VIN MAX( ) where fSW is the switching frequency of the LT8653S and L is the value of the inductor . Therefore, the maximum output current that the LT8653S will deliver depends on the switch current limit, the inductor value and the input and output voltages. Each channel has a secondary bottom switch current limit. After the top switch has turned off, the bottom switch carries the inductor current. If for any reason the inductor current is too high, the bottom switch will remain on, delaying the top switch turning on until the inductor current returns to a safe level. This level is specified as the bottom NMOS current limit and is independent of duty cycle. Maximum output current in the application circuit is limited to this valley current plus one half of the inductor ripple current. In most cases current limit is enforced by the top switch. The bottom switch limit controls the inductor current

input voltage, high frequency or saturated inductor). mum rated current of the LT8653S. oscillation. See Application Note 19. Table 3. Inductor Manufacturers with a low performance electrolytic capacitor . Devices Application Note 88). values, see the Typical Applications section. for suggested capacitor values. with a higher voltage rating may be required.

capacitor at audio frequencies, generating audible noise. ceramic capacitors are also available. Table 4. Ceramic Capacitor Manufacturers be large to minimize their effect on efficiency at low loads. 3.0V, the internal LDO will consume current from VIN.

Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION Synchronization To select low ripple Burst Mode operation, tie the SYNC pin below 0.4V (this can be ground or a logic low out - put). To select forced continuous mode (FCM), float the SYNC pin. T o select FCM with spread spectrum modula- tion (SSM), tie the SYNC pin above 2.8V (SYNC can be tied to V CC). To synchronize the LT8653S oscillator to an external frequency, connect a square wave (with 20% to 80% duty cycle) to the SYNC pin. The square wave amplitude should have valleys that are below 0.4V and peaks above 1.5V (up to 6V). When synchronized to an external clock the LT8653S will use FCM. Channel 1 will synchronize its positive switch edge transi- tions to the positive edge of the SYNC signal and chan - nel 2 will synchronize to the negative edge of the SYNC signal. The LT8653 S may be synchronized over a 300kHz to 3MHz range. The R T resistor should be chosen to set the LT8653S switching frequency equal to or below the lowest synchronization input. For example, if the synchro- nization signal will be 500kHz and higher , the RT should be selected for nominal 500kHz. The slope compensation is set by the RT value, while the minimum slope compensation required to avoid subhar- monic oscillations is established by the inductor size, input voltage and output voltage. Since the synchroniza- tion frequency will not change the slopes of the inductor current waveform, if the inductor is large enough to avoid subharmonic oscillations at the frequency set by RT, then the slope compensation will be sufficient for all synchro- nization frequencies. A synchronizing signal that incorporates spread spectrum may reduce EMI. The duty cycle of the SYNC signal can be used to set the relative phasing of the two channels for minimizing input ripple. Forced Continuous Mode Forced continuous mode (FCM) is activated by either floating the SYNC pin, tying the SYNC pin to VCC, apply- ing a DC voltage above 2.8V to the SYNC pin or applying an external clock to the SYNC pin. While in FCM, discontinuous mode operation is disabled and the inductor current is allowed to go negative so that the regulator can switch at the programmed frequency all the way down to zero output current. This has the advan- tage of maintaining the programmed switching frequency across the entire load range so that the switch harmonics and EMI are consistent and predictable. The disadvantage of FCM is that the light load efficiency will be low com - pared to Burst Mode operation. At low input voltages when the part enters dropout, the programmed switching frequency will be maintained and off time skipping will not be allowed. This keeps the switching frequency controlled, but the dropout voltage will be higher than in burst mode, due to maximum duty cycle constraints. The negative inductor current is limited to a maximum of about –2.5A, so the LT8653 S can only sink a maxi - mum of about –1.3A. This prevents boosting an excessive amount of current back from the output to the input. FCM is disabled if the input voltage is greater than 37V to pre- vent overvoltaging the LT8653 S i f the input capacitor is charged when sinking current from the output. Additional safety features include disabling FCM when the SS pin voltage is below 1.8V to prevent discharging the output when starting up into a pre-biased output, and a bottom FET current limit to prevent over charging the output if the minimum on time is violated.

side. See Figure 9 for example PCB layout. Figure 9. Recommended Layout

Rev. 0 For more information www.analog.com TYPICAL APPLICATIONS 5V, 3.3V, 2MHz Step-Down Converter with FCM and External Compensation T wo Phase, 3.3V, 4A, 2MHz Step-Down Converter L T8653S 8653S TA02 RT VIN EN/UV PG1 CLKOUT PG2 BIAS SW1 FB1 SW2 FB2 VC2 SS2 VCC GND SYNC 47µF 1210 X5R VC1 SS1 470pF 470pF 10nF 10nF 100µF 1210 X5R 4.7µF 2.2µH 2.2µH VOUT1 V OUT2 3.3V VIN 6.1V TO 42V fSW = 2MHz 22.1k 34.8k 100k 4.7pF 100k 4.7pF 15k 4.7pF 4.7pF 191k 316k L1, L2: XFL4020-222ME 1µF VCC L T8653S 8653S TA03 RT VIN EN/UV CLKOUT SW1 SW2 VC1 VC2 SS1 SS2 FB1 FB2D0 V CC GND SYNC 1000pF 10pF 100µF 1210 X5R 4.7µF ×2 2.2µH 2.2µH V OUT2 3.3V VIN 3.8V TO 42V fSW = 2MHz 24.9k 22nF PG1 PG2 BIAS 100k 15k L1, L2: XFL4020-222ME 1µF

Rev. 0For more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION 20-Lead (4mm × 3mm × 0.94mm) (Reference L TC DWG # 05-08-1524 Rev B) DETAIL B A PACKAGE TOP VIEW PAD “A1” CORNER Y X aaa Z2× 20b PACKAGE BOTTOM VIEW

6 SEE NOTES

E D b e e b DETAIL B SUBSTRATE MOLD CAP // bbb Z Z DETAIL A DETAIL C SUGGESTED PCB LAYOUT TOP VIEW 0.0000 0.0000 0.7500 1.2500 0.2500 0.2500 0.7500 1.2500 0.7500 0.2500 0.2500 0.7500 DETAIL A PIN 1 NOTCH 0.25 × 45° 17 20 0.375 0.375 aaa Z 2× M X Y Z ccc MXY Z ccc M X Y Z eee M Zfff PACKAGE OUTLINE 0.25 ±0.05 0.70 ±0.05 0.375 0.375 4.50 ±0.05 3.50 ±0.05 LGA 20 0417 REV BPACKAGE IN TRAY LOADING ORIENTATION 0.40 2.40 1.40 TRAY PIN 1 BEVEL COMPONENT PIN “A1” L TXXXXXX ddd Z 20× e SYMBOL A L b D E e aaa bbb ccc ddd eee fff MIN 0.85 0.01 0.30 0.22 NOM 0.94 0.02 0.40 0.25 3.00 4.00 1.40 2.40 0.50 0.24 0.70 MAX 1.03 0.03 0.50 0.28 0.10 0.10 0.10 0.10 0.15 0.08 NOTES DIMENSIONSZ DETAIL C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. PRIMARY DATUM -Z- IS SEATING PLANE METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN SO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE

6 THE EXPOSED HEAT FEATURE MAY HAVE OPTIONAL CORNER RADII

7 CORNER SUPPORT PAD CHAMFER IS OPTIONAL

L e/2

Rev. 0 For more information www.analog.com  ANALOG DEVICES, INC. 2019 www.analog.com RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LT8650S 42V, Dual 4A, 95% Efficiency, 2.2MHz Synchronous Silent Switcher 2 Step Down DC/DC Converter with IQ = 6.2µA VIN = 3V to 42V, VOUT(MIN) = 0.8V, IQ = 6.2µA, ISD < 1µA, 4mm × 6mm QFN LT8640S 42V, 5A, 95% Efficiency, 2.2MHz Synchronous Silent Switcher 2 Step Down DC/DC Converter with IQ = 2.5µA VIN = 3.4V to 42V, VOUT(MIN) = 0.97V, IQ = 2.5µA, ISD < 1µA, 4mm × 4mm QFN LT8609S 42V, 2A, 95% Efficiency, 2.2MHz Synchronous Silent Switcher 2 Step Down DC/DC Converter with IQ = 2.5µA VIN = 3V to 42V, VOUT(MIN) = 0.8V, IQ = 2.5µA, ISD < 1µA, 3mm × 3mm QFN LT8609/ LT8609A 42V, 2A, 94% Efficiency, 2.2MHz Synchronous MicroPower Step Down DC/DC Converter with IQ = 2.5µA VIN = 3V to 42V, VOUT(MIN) = 0.8V, IQ = 2.5µA, ISD < 1µA, MSOP 10E, 3mm × 3mm DFN Packages LT8610A/ LT8610AB 42V, 3.5A, 96% Efficiency, 2.2MHz Synchronous MicroPower Step Down DC/DC Converter with IQ = 2.5µA VIN = 3.4V to 42V, VOUT(MIN) = 0.97V, IQ = 2.5µA, ISD < 1µA, MSOP LT8612 42V, 6A, 96% Efficiency, 2.2MHz Synchronous MicroPower Step Down DC/DC Converter with IQ = 2.5µA VIN = 3.4V to 42V, VOUT(MIN) = 0.97V, IQ = 3.0µA, ISD < 1µA, 3mm × 6mm QFN Synchronous MicroPower Step Down DC/DC Converter with IQ = 25µA VIN = 3V to 42V, VOUT(MIN) = 0.8V, IQ = 25µA, ISD < 1µA, 6mm × 6mm QFN 5V, 1.8V, 2MHz Step-Down Converter L T8653S 8653S TA04 RT VIN EN/UV SW1 FB1 BIAS VC1 V CC SW2 FB2 VC2V CC VCC VCC GND SYNC 47µF 1210 X5R 47µF 1210 X5R 4.7µF 2.2µH 1.0µH VOUT1 V OUT2 1.8V V IN 5.6V TO 42V fSW = 2MHz L1: XFL4020-222ME L2: XFL4020-102ME

Summary

Dual Channel 2A, 42V, Synchronous Step-Down Silent Switcher 2 with 6.2關A Quiescent Current

Description

Dual Channel 2A, 42V, Synchronous Step-Down Silent Switcher 2 with 6.2關A Quiescent Current

Source title LT8609 Datasheet(PDF) - Analog Devices

Read LT8609 online.