LT8603

LT8603 DS (Rev. C)

Document overview

• Manufacturer or author: Analog Devices Inc.
• PDF pages: 38

Technical content

Rev. CFor more information www.analog.com TYPICAL APPLICATION FEATURES DESCRIPTION 42V, Low IQ, Quad Output Triple Monolithic Buck Converter and Boost Controller The LT®8603 is a highly flexible, quad output regulator combining two high input voltage capable monolithic step-down switching regulators, one low input voltage capable monolithic step-down regulator , and a boost controller to satisfy a wide range of applications while occupying minimal board space. With the boost controller configured to supply the chip VIN supply, the LT8603 produces three precisely regulated outputs even when the boost input voltage falls signifi - cantly below the regulated output voltages, such as dur- ing an automotive cold crank scenario. Alternatively, with the boost controller driven from one of the step-down regulator outputs or configured as a SEPIC, the LT8603 provides four precisely regulated outputs over a wide input voltage range. The LT8603 provides robust regulation by including a cycle-by-cycle current limit for all step-down regulators, thermal shutdown, and a boost controller that can tolerate reverse battery connections and negative transient input voltages down to –42V. Cold Crank Tolerant Automotive T riple Output Supply

APPLICATIONS

n Flexible Power Supply System Capable of Four Regulated Outputs with VBATT << VOUT n Two High Voltage Synchronous Buck Regulators n 3V to 42V Input Voltage Range n Output Currents Up to 2.5A and 1.5A n One Low Voltage Synchronous Buck Regulator n 2.6V to 5.5V Input Voltage Range n Output Currents Up to 1.8A n One Boost Controller Allows Buck Converters to Regulate with VBATT << VOUT n Selectable Burst Mode® Operation Allows Low 28µA IQ with High Voltage Channels Active n Programmable Power-On Reset n Individual Channel Power Good Indicators n Step-Down Switching Frequency: 250kHz to 2.2MHz n Available in 40-Lead QFN (6mm × 6mm) Package n AEC-Q100 Qualified for Automotive Applications n Automotive Stop-Start and Cold Crank Ride Through n Last-Gasp CPU Power Hold-Up n Industrial Controls and Power Supplies All registered trademarks and trademarks are the property of their respective owners. LT8603 Response to a Cold Crank Automotive Input Waveform

8603 TA01a

2V < VBATT < 8.5V GND PORENPOREN VBATT 2V TO 42V (BOOST START-UP ABOVE 4.3V) L T8603 FB4 GATE4 ISN4 PG1-4 BIAS RST PG1-4 OUT2 RESET ISP4PVIN1VINEN/UVLO PVIN2 BST2 OUT3 1.2V , 1.8A SW3 FB3 OUT2 3.3V , 2.5A – IPVIN3 SW2 FB2 PVIN3 BST1 OUT1 5V , 1.5A SW1 FB1TRKSS1-2 CPOR RT SYNC FSEL4B FSEL4A INTVCC INTVCC4 RUN3 TIME (10ms/DIV) VOL TAGE 2V/DIV

8603 TA01b

Rev. C For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS Supply Voltages Operating Junction Temperature (Notes 2, 5) (Note 1) 3940 38 37 36 35 34 33 32 31 11 2012 13 14 15 TOP VIEW GND UJ PACKAGE 40-LEAD (6mm × 6mm) PLASTIC QFN 16 17 18 19 PG1 GND SW1 BST1 BST2 SW2 SW2 GND BIAS PG2 RUN3 RT INTVCC FB3 FB1 FB2 FB4 VIN EN/UVLO TRKSS1 PG3 POREN GND PVIN1 SW3 GND PVIN3 SYNC RST CPOR PG4 FSEL4A GND PVIN2 GATE4 INTVCC4 FSEL4B ISN4 ISP4 TRKSS2 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8603EUJ#PBF LT8603EUJ#TRPBF LT8603UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C LT8603IUJ#PBF LT8603IUJ#TRPBF LT8603UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C LT8603JUJ#PBF LT8603JUJ#TRPBF LT8603UJ 40-Lead (6mm x 6mm) Plastic QFN –40°C to 150°C AUTOMOTIVE PRODUCTS** LT8603EUJ#WPBF LT8603EUJ#WTRPBF LT8603UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C LT8603IUJ#WPBF LT8603IUJ#WTRPBF LT8603UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 125°C LT8603JUJ#WPBF LT8603JUJ#WTRPBF LT8603UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 150°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. **Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.

Rev. CFor more information www.analog.com

ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS Bias and Internal Regulators Minimum Operating VIN for Channels 1, 2 and 3 l 2.7 3.0 V Minimum VIN to Start for Channels 1, 2 and 3 l 3.1 3.3 V Minimum Operating VIN for Channel 4 l 3.0 3.2 V Minimum VIN to Start for Channel 4 l 4.0 4.15 V VIN Quiescent Current, Shutdown VBIAS = 0V, EN/UVLO = 0.4V 0.1 1 μA Total Operating Current VBATT VBATT = 12V, Channels 1 and 2 Active, No-Load (Note 4) VBATT = 12V, All Channels Active, No-Load (Note 4) μA μA EN/UVLO Threshold EN/UVLO Rising l 1.15 1.2 1.25 V EN/UVLO Falling l 1.1 1.15 1.2 V EN/UVLO Input Current EN/UVLO = 1.2V –50 50 nA INTVCC4 Regulated Voltage VBIAS = 0V VBIAS = 6V l l 4.4 4.7 4.6 4.8 5.2 V V INTVCC4 Regulator Load Regulation INTVCC4 at 1mA – INTVCC4 at 40mA 70 mV Oscillator Switching Frequency RT = 28.7kΩ, E, I-Grade RT = 28.7kΩ, J-Grade RT = 243kΩ, E, I ,J-Grade l l l 1.8 1.75 0.224 0.25 2.2 2.2 0.284 MHz MHz MHz SYNC Input Frequency Range l 0.25 2.2 MHz SYNC Input Voltage Low l 0.3 V SYNC Input Voltage High l 1.2 V SYNC Input Current –100 100 nA FSEL4A, FSEL4B Input Voltage Low l 0.4 V FSEL4A, FSEL4B Input Voltage High l 2 V FSEL4A, FSEL4B Input Current l –100 100 nA Channel 1 Feedback Voltage FB1 E-, I-Grade J-Grade l l 0.985 0.98 1.015 1.015 V V Input Current FB1 l –100 100 nA FB1 Line Regulation VIN = 3V to 42V 0.002 0.01 %/V SW1 Peak Current Limit (Note 3) 2.0 2.7 3.7 A SW1 Leakage Current 0.1 1 μA SW1 Top On-Resistance ISW1 = 1A 240 mΩ SW1 Bottom On-Resistance ISW1 = 1A 170 mΩ Lower FB1 Power Good Threshold Percentage of VFB1, VFB1 Falling l 89 92 95 % Upper FB1 Power Good Threshold Percentage of VFB1, VFB1 Rising l 104 107 110 % Power Good Threshold Hysteresis 0.8 % PG1 Output Voltage Low IPG1 = 350μA l 0.13 0.3 V PG1 Leakage Current PG1 = 5V, FB1 = 1V l 6 μA TRKSS1 Pull-Up Current TRKSS1 = 0.2V 1.5 2.4 3.1 μA The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, EN/UVLO = 3V unless otherwise noted. (Note 2)

Rev. C For more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS Channel 2 Feedback Voltage FB2 E-, I-Grade J-Grade l l 0.985 0.98 1.015 1.015 V V Input Current FB2 l –100 100 nA FB2 Line Regulation VIN = 3V to 42V 0.002 0.01 %/V SW2 Peak Current Limit (Note 3) 3.2 4.0 5.3 A SW2 Leakage Current 0.1 1 μA SW2 Top On-Resistance ISW2 = 1A 150 mΩ SW2 Bottom On-Resistance ISW2 = 1A 100 mΩ Lower FB2 Power Good Threshold Percentage of VFB2, VFB2 Falling l 89 92 95 % Upper FB2 Power Good Threshold Percentage of VFB2, VFB2 Rising l 104 107 110 % Power Good Threshold Hysteresis 0.8 % PG2 Output Voltage Low IPG2 = 350μA l 0.13 0.3 V PG2 Leakage Current PG2 = 5V, FB2 = 1V l 6 μA TRKSS2 Pull-Up Current TRKSS2 = 0.2V 1.5 2.4 3.1 μA Channel 3 PVIN3 Operating Voltage PVIN3 Falling l 2.6 5.5 V PVIN3 Undervoltage Lockout PVIN3 Falling l 2.35 2.6 V Feedback Voltage FB3 E-, I-Grade J-Grade l l 788 784 800 800 812 812 mV mV FB3 Line Regulation VIN = 3V to 42V 0.002 0.01 %/V Input Current FB3 l –100 100 nA SW3 Leakage Current 0.1 1 μA SW3 Peak Current Limit (Note 3) 2.6 3.2 3.8 A SW3 PMOS On-Resistance ISW3 = 1A 150 mΩ SW3 NMOS On-Resistance ISW3 = 1A 100 mΩ Lower FB3 Power Good Threshold Percentage of VFB3, VFB3 Falling l 89 92 95 % Upper FB3 Power Good Threshold Percentage of VFB3, VFB3 Rising l 104 107 110 % Power Good Threshold Hysteresis 0.2 % PG3 Output Voltage Low IPG3 = 350μA l 0.13 0.3 V PG3 Leakage Current PG3 = 5V, FB3 = 0.8V l 6 μA RUN3 Threshold Voltage l 1.15 1.20 1.25 V RUN3 Input Current –100 100 nA Soft-Start Time 0.7 1 1.3 ms The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, EN/UVLO = 3V unless otherwise noted. (Note 2)

Rev. CFor more information www.analog.com Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT8603E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8603I is guaranteed to meet performance specifications from –40°C to 125°C junction temperature. The LT8603J is guaranteed over the full –40°C to 150°C operating junction temperature range. High junction PARAMETER CONDITIONS MIN TYP MAX UNITS Channel 4 Feedback Voltage FB4 E-, I-Grade J-Grade l l 788 784 800 800 812 812 mV mV FB4 Line Regulation VIN = 3.2V to 42V 0.002 0.01 %/V Input Current FB4 l –100 100 nA Soft-Start Time 1 ms Current Comparator Limit Threshold VISP4 to VISN4, VCM = 2V to 42V, E, I-Grade VISP4 to VISN4, VCM = 2V to 42V, J-Grade l l mV mV Current Comparator Input Common Mode Range 2 42 V ISP4, ISN4 Input Currents, Sleep VISP4 = VISN4 = 2V to 42V, FB4 = 1V, SYNC = 0V 200 nA ISP4, ISN4 Input Currents, Active VISP4 = VISN4 = 2V to 42V, FB4 = 0V, SYNC = 0V 34 44 μA ISP4, ISN4 Input Currents VISP4 = VISN4 = –42V 7 10 mA GATE4 High Side PMOS On-Resistance 2.5 Ω GATE4 Low Side NMOS On-Resistance 1.25 Ω FB4 Power Good Threshold Percentage of VFB4, VFB4 Falling l 89 92 95 % Power Good Threshold Hysteresis 0.2 % PG4 Output Voltage Low IPG4 = 350μA l 0.13 0.3 V PG4 Leakage Current PG4 = 5V, FB4 = 0.8V l 6 μA Power-On Reset POR Delay Time CPOR = 1000pF l 31 35.2 39.4 ms RST Output Voltage Low IRST = 100μA l 0.1 0.2 V RST Pull-Up Current POR Timed Out, RST = 0V 20 μA RST Leakage Current POR Timed Out, RST = 6V –100 100 nA POREN Threshold l 1.15 1.2 1.25 V POREN Pull-Up Current POREN = 0V 0.6 1.0 1.4 μA The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, EN/UVLO = 3V unless otherwise noted. (Note 2) temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures above 125°C. Note 3: Current limit is assured by design and/or correlation to static test. Slope compensation reduces current limit at higher duty cycles. Note 4: Measurement made using the circuit titled, “Details of Front Page Application” in the Typical Applications section. Note 5: This IC includes overtemperature protection that is intended to protect the device during overload conditions. Junction temperature will exceed 150°C when overtemperature protection is active. Continuous operation above the specified maximum junction temperature will reduce lifetime.

Rev. C For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Channel 1 Efficiency vs Load VOUT1 = 5V, fSW = 2MHz Channel 2 Efficiency vs Load VOUT2 = 3.3V, fSW = 2MHz Channel 3 Efficiency vs Load VOUT3 = 1.2V, fSW = 2MHz Channel 4 Efficiency vs Load VOUT4 = 8V, fSW = 1MHz Channel 4 Efficiency vs Load VOUT4 = 8V, fSW = 1.0MHz No-Load I (VIN) vs VIN All Channels Enabled (Note 4) Channel 1 Efficiency vs Load VOUT1 = 5V, fSW = 1MHz Channel 2 Efficiency vs Load VOUT2 = 3.3V, fSW = 1MHz Channel 3 Efficiency vs Load VOUT3 = 1.2V, fSW = 1MHz TA = 25°C, VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V and PVIN3 = 3.3V unless otherwise noted. LOAD CURRENT (A) 0.001 0.01 0.1 100 EFFICIENCY (%) OUT1 SW

8603 G01

= 12V PV IN1 = 24V PV IN1 = 36V Burst Mode OPERATION LOAD CURRENT (A) 0.001 0.01 0.1 100 EFFICIENCY (%) OUT2 SW

8603 G02

= 12V PV IN2 = 24V PV IN2 = 36V Burst Mode OPERATION LOAD CURRENT (A) 0.001 0.01 0.1 100 EFFICIENCY (%) OUT3 SW

8603 G03

= 2.6V PV IN3 = 3.3V PV IN3 = 5.5V Burst Mode OPERATION LOAD CURRENT (A) 0.001 0.01 0.1 100 EFFICIENCY (%) OUT1 SW

8603 G04

= 12V PV IN1 = 24V PV IN1 = 36V Burst Mode OPERATION LOAD CURRENT (A) 0.001 0.01 0.1 100 EFFICIENCY (%) V OUT2 = 3.3V , f SW = 2MHz

8603 G05

= 12V PV IN2 = 24V Burst Mode OPERATION LOAD CURRENT (A) 0.001 0.01 0.1 100 EFFICIENCY (%) OUT3 SW

8603 G06

= 2.6V PV IN3 = 3.3V PV IN3 = 5.5V Burst Mode OPERATION LIGHT LOAD BURST R SENSE = 4.0mΩ L4 = 1.5/uni03BCH VBATT = 6V VBATT = 4.5V VBATT = 3V LOAD CURRENT (A) 0.001 0.01 0.1 100 EFFICIENCY (%) OUT4 SW

8603 G07

R SENSE = 4.0mΩ L4 = 1.5/uni03BCH LOAD CURRENT (A) 0.0 0.8 1.5 2.3 3.0 100 EFFICIENCY (%) V OUT4 = 8V , f SW = 400KHz

8603 G08

VBATT = 6V VBATT = 4.5V VBATT = 3V V BATT (V) 100 150 200 250 300 350 400 I(VBATT) (/uni03BCA)

8603 G09

Rev. CFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V and PVIN3 = 3.3V unless otherwise noted. Channel 1 Peak Current Limit vs Duty Cycle Channel 2 Peak Current Limit vs Duty Cycle Channel 3 Peak Current Limit vs Duty Cycle Channels 1, 2 Minimum On-Time vs Temperature Channels 1, 2 Minimum Off-Time vs Temperature Channel 3 Minimum Off-Time vs ISW Channels 1, 2 Minimum On-Time vs ISW Channels 1, 2 Minimum Off-Time vs ISW Channel 3 Minimum On-Time vs ISW DUTY CYCLE (%) 100 1.5 1.8 2.1 2.4 2.7 3.0 TOP FET CURRENT LIMIT (A)

8603 G10

DUTY CYCLE (%) 100 2.5 3.0 3.5 4.0 4.5 5.0 TOP FET CURRENT LIMIT (A) Peak Current Limit vs. Duty Cycle

8603 G11

SWITCH CURRENT (A) 0.5 1.5 2.5 100 MINIMUM ON-TIME (ns) Minimum On Time vs I SW

8603 G13

SWITCH CURRENT (A) 0.5 1.5 2.5 100 MINIMUM OFF-TIME (ns) Minimum Off-Time vs I SW

8603 G14

= 2.6V PV IN3 = 3.3V PV IN3 = 5.5V I SW (A) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 108 126 144 162 180 MINIMUM ON-TIME (ns) Minimum On-Time vs I SW

8603 G15

I SW (A) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 100 MINIMUM OFF-TIME (ns) Minimum Off-Time vs I SW

8603 G18

DUTY CYCLE (%) 100 1.5 2.0 2.5 3.0 3.5 4.0 TOP FET CURRENT LIMIT (A) Duty Cycle

8601 G12

I SW = 1A CH 1 CH 2 TEMPERATURE (°C) –50 –25 100 125 150 MIN ON-TIME (ns) Minimum On Time vs Temperature

8603 G16

I SW = 1A CH 1 CH 2 TEMPERATURE (°C) –50 –25 100 125 150 100 MIN OFF-TIME (ns) Minimum Off Time vs Temperature

8603 G17

Rev. C For more information www.analog.com TA = 25°C, VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V and PVIN3 = 3.3V unless otherwise noted. POR Delay Time vs Temperature Feedback Voltage vs Temperature Switching Frequency vs RT Switching Frequency vs Temperature POR Delay vs CPOR TYPICAL PERFORMANCE CHARACTERISTICS Channel 4 ILIM Threshold vs Common Mode Channel 4 ILIM Threshold vs Temperature TEMPERATURE (°C) –50 –25 100 125 150 0.990 0.995 1.000 1.005 1.010 0.790 0.795 0.800 0.805 0.810 CH 1 AND CH 2 V FB (V) CH 3 AND CH 4 V FB (V)

8603 G19

R T (kΩ) 100 125 150 175 200 225 250 275 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 FREQUENCY (MHz) T

8603 G20

R T = 30kΩ R T = 60kΩ R T = 250kΩ TEMPERATURE (°C) –50 –25 100 125 150 –10 FREQUENCY CHANGE (%)

8603 G21

C POR (pF) 100 1000 10000 100 600 POR DELAY (ms) POR

8603 G22

TEMPERATURE (°C) –50 –25 100 125 150 –10 DELAY TIME CHANGE (%)

8603 G23

V ISP , V ISN (V) V ISP – V ISN (mV) vs Common Mode

8603 G24

TEMPERATURE (°C) –50 –25 100 125 150 40.0 42.0 44.0 46.0 48.0 50.0 52.0 54.0 56.0 58.0 60.0

8603 G25

V ISP – V ISN (mV) VBATT = 2V VBATT = 42V

Rev. CFor more information www.analog.com Channels 3 RDS(ON) vs Temperature TA = 25°C, VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V and PVIN3 = 3.3V unless otherwise noted. TYPICAL PERFORMANCE CHARACTERISTICS Channel 1 RDS(ON) vs Temperature Channel 4 Minimum On-Time vs VISP – VISN Channel 4 Minimum Off-Time vs VISP – VISN Channel 4 ISP , ISN Input Current vs VISP, VISN BOTTOM FET TOP FET TEMPERATURE (°C) –50 –25 100 125 150 100 200 300 400 500 R DS(ON) (mΩ) DSON

8603 G29

Channel 2 RDS(ON) vs Temperature Channel 1 Full Frequency VIN vs Load Current Channel 2 Full Frequency VIN vs Load Current Channel 3 Full Frequency VIN vs Load Current TEMPERATURE (°C) –50 –25 100 125 150 100 200 300 400 R DS(ON) (mΩ)

8603 G30

ISW2 = 1A BOTTOM FET TOP FET TEMPERATURE (°C) –50 –25 100 125 150 100 150 200 250 300 R DS(ON) (mΩ)

8603 G31

ISW = 1A BOTTOM FET TOP FET RT = 28.7k FULL FREQUENCY REGION (2MHz) VOUT = 3.3V VOUT = 5V I OUT (A) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 V IN (V)

8603 G32

I OUT (A) 0.3 0.7 1.3 1.6 1.9 2.3 2.6 V IN (V)

8603 G33

R T = 28.7k FULL FREQUENCY REGION (2MHz) V OUT = 3.3V V OUT = 5V I OUT (A) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 V IN (V)

8603 G34

RT = 28.7k FULL FREQUENCY REGION (2MHz) VOUT = 1.8V VOUT = 1.2V CH4 FSW = 2MHz TA = 135°C TA = 25°C TA = –45°C V ISP – V ISN (mV) 100 120 140 160 180 200 MIN ON-TIME (ns) ISP – ISN

8603 G26

2V , 34/uni03BCA TYPICAL ACTIVE < 200nA IN SLEEP V ISP , V ISN (V) –50 –40 –30 –20 –10 ISP , ISN INPUT CURRENT(mA) ISP , ISN

8603 G28

TA = 150°C TA = 100°C TA = 25°C TA = –45°C CH4 SWITCHING FREQUENCY (MHz) 0.5 1.5 2.5 100 140 180 220 260 300 MINIMUM OFF-TIME (ns)

8603 G27

Rev. C For more information www.analog.com T A = 25°C, VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V and PVIN3 = 3.3V, unless otherwise noted. TYPICAL PERFORMANCE CHARACTERISTICS Radiated EMI Performance, CISPR 25 Radiated Emission Tests with Class 5 Peak Limits TRKSS Pull-Up Current vs Voltage RST Pull-Up Current vs Voltage TRKSS VOL TAGE (V) 0.5 1.5 2.5 3.5 TRKSS CURRENT (µA)

8603 G37

VOL TAGE (V) 0.5 1.5 2.5 3.5 –30 –20 –10 RST CURRENT (µA)

8603 G38

Dropout, RL = 2Ω Channel 1 Start-Up and Dropout, RL = 20Ω 100ms/DIV 2V/DIV

8603 G39

8602 G40

Shutdown IQ from the Battery Overvoltage/Temperature EN/UVLO Current vs Voltage V EN/UVLO (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 I EN/UVLO (µA)

8603 G36

V BATT (V) I(V BATT (µA) Q

8603 G35

TA = 150°C TA = 125°C TA = 25°C TA = –50°C AMPLITUDE (dBµV/m) –15 –10 FREQUENCY (MHz) 30 930130 230 330 530430 630 730 830 1030

8603 EMI 01a

CISPR 25 CLASS 5 PEAK LIMIT DATA DC2114A DEMO BOARD (WITH EMI FIL TER INSTALLED) VBATT = 14V , VOUT1 = 5V , VOUT2 = 3.3V , VOUT3 = 1.8V , IOUT1,2,3 = 1A fSW = 2MHz, FSELA = INTVCC , FSELB = Ground

Rev. CFor more information www.analog.com PIN FUNCTIONS PG1, PG2, PG3 (Pins 1, 10, 40): Power Good Indicators for Channels 1, 2 and 3, respectively. These pins are open- drain outputs that pull down until the associated FB pin is within ±8% of the target regulation voltage. GND (Pins 2, 8, 13, 35, 38, Exposed Pad 41) : Ground. All ground pins and the exposed pad must be soldered to PCB ground. See the Applications Information section for PCB layout recommendations. SW1 (Pin 3): High Voltage Converter 1 Switch Node. This is the output of the internal power switches for Channel 1. BST1, BST2 (Pins 4, 5): Boost Voltage for High Voltage Converters. These pins provide the drive voltage required by the internal power MOSFETs. A capacitor should be connected from BST to the associated SW pin. SW2 (Pins 6, 7): High Voltage Converter 2 Switch Node. This is the output of the internal power switches for Channel 2. These pins should be soldered to the same PCB trace for even current distribution. BIAS (Pin 9) : Alternate Power Source for INTV CC and INTVCC4 Regulators. If BIAS > 3.1V for INTVCC or > 4.6V for INTVCC4 the internal regulators will draw their power from BIAS. This will reduce the on-chip power dissipation during full frequency operation and reduce the effective no-load sleep current at the input. PG4 (Pin 11): Power Good Indicator Channel 4. This pin is an open-drain output that pulls low until the Channel 4 feedback voltage is greater than 92% of its reference voltage. FSEL4A, FSE L4B (Pins 12, 17) : Boost Converter Frequency Select and RUN Control. These pins are logic inputs. When both pins are low, the boost controller is shut down. The boost controller switching frequency is controlled using these pins according to Table 2 in the Applications Information section. GATE4 (Pin 15) : External MOSFET Gate Drive Output. This pin switches from GND to V INTVCC4 to turn on the low side power MOSFET in the BOOST converter . See the Applications Information section for information on MOSFET selection. INTVCC4 (Pin 16) : Internal Boost Regulator Output. Do not load the INTVCC4 pin with external circuitry. INTVCC4 is 4.6V when BIAS < 4.6V, 5V when BIAS > 5V, and equal to BIAS when BIAS is between 4.6V and 5V. Decouple to ground with a low ESR 4.7µF capacitor . ISP4, ISN4 (Pins 19, 18): Boost Controller Current Sense Inputs. Connect a current sense resistor of appropriate value between these pins with IS P4 connected to the input supply and IS N4 to the application inductor . See the Applications Information section for sense resistor selection details. TRKSS1, TRKSS2 (Pins 21, 20): T rack/Soft-Start Inputs for the High Voltage Converters. When this pin is below 1V, the converter regulates the FB pin to the TRKSS volt- age instead of the internal reference. The TRKSS pin has a 2.4μA pull-up current. Connect a capacitor between either of these pins to ground to program a soft-start time for the associated channel. EN/UVLO (Pin 22): Enable/Undervoltage Lockout Input. The LT8603 is in low power shutdown when this pin is below 0.4V. Between 0.4V and 1.1V, the part will turn on the internal reference. A precision threshold at 1.2V (ris- ing) enables the switching regulators. The precision threshold allows the EN/UVLO pin to be used as an input undervoltage lockout by connecting to resistor divider between V IN and GND. When the EN/UVLO voltage is between 0.4V and 1.2V, the LT8603 input current will depend on the mode selected, the V IN voltage and EN/ UVLO voltage. VIN (Pin 23) : Power Supply to Internal Functions. This pin provides power to the LT8603 internal circuitry. This pin must reach 4V for the boost converter to complete its internal soft-start delay of 1ms. FB4 (Pin 24): Feedback Input Pin for the Boost Converter . The converter regulates FB4 to 0.8V. FB1, FB2 (Pins 26, 25) : Feedback Input Pins for the High Voltage Converters. The converters regulate the

Rev. C For more information www.analog.com corresponding feedback pin to the lesser of 1V or the voltage on the associated TRKSS pin. FB3 (Pin 27) : Feedback Input Pin for the Low Voltage Converter . The converter regulates FB3 to 0.8V. INTVCC (Pin 28): Internal Regulator Bypass. Do not load the INTVCC pin with external circuitry. INTV CC is 3.1V when BIAS < 3.1V, 3.4V when BIAS > 3.4V, and equal to BIAS when BIAS is between 3.1V and 3.4V. Decouple to ground with a low ESR 4.7µF capacitor . RT (Pin 29): Frequency Programming Resistor . Connect a resistor between this pin and ground to set the internal oscillator frequency. This pin should not be left open. RUN3 (Pin 30): Enable Input For Low Voltage Channel 3. Channel 3 is enabled when the voltage on this pin exceeds 1.2V. The RUN3 pin has a precise threshold so it can be used to create a UVLO function or be sequenced from another channel. There is an internal soft-start timer which ramps the output up in approximately 1ms. CPOR (Pin 31) : Power-On Reset Timing Capacitor . A capacitor from this pin to ground sets the period of the power-on reset oscillator timer . See the Applications Information Section for details. RST (Pin 32) : Active Low Reset Output. This pin is the output of the power-on reset function. This pin is an open- drain output with a weak pull-up to approximately 2V. This pin is held low until the power on reset timer times out. SYNC (Pin 33): Clock Synchronization and Mode Select Input. This pin allows the LT8603 to synchronize its switching frequency to an external clock. When an external clock is applied, the LT8603 will operate in pulse-skipping mode. If clock synchronization is not used, connect this pin to ground to enable low ripple Burst Mode operation or connect high to enable pulse-skipping operation. PVIN3 (Pin 34) : Input Supply Voltage to Low Voltage Channel 3. This pin will normally be connected to the output of one of the high voltage converters but can be supplied from any voltage in the specified range. It should be bypassed locally with a low ESR ceramic capaci - tor to ground with a low inductance connection to the exposed pad. SW3 (Pin 36): Low Voltage Converter Switch Node. This is the output of the internal power switches for Channel 3. PVIN1, PVIN2 (Pins 37, 14): Input Supply to High Voltage Channels 1 and 2, respectively. These pins can be pow - ered from the boost converter output or any voltage in the specified range. Each pin should be bypassed locally with a low ESR ceramic capacitor to ground with a low inductance connection to the exposed pad. POREN (Pin 39): Power-On Reset Enable. This is a logic input that starts the ramp on the POR timing capacitor . This input has a weak pull-up to allow direct connection to open-drain outputs. PIN FUNCTIONS

Rev. CFor more information www.analog.com BLOCK DIAGRAM 8603 BD 2.4µA FB2 GATE4 ILIM2 ERROR AMPLIFIER BST1 BST2 RST LOOP COMPENSATION LOGIC 4 1.08V 0.92V TRKSS2 PG2 ISN4 DRIVER GND RUN3 ISP4 SW2 PVIN2 ILIM2 ILIM3 ILIM1 LOGIC 2 CLK4 CLK2 CLK1 CLK1 INTVCC GND DRIVER DRIVER DRIVER CURRENT SENSE COMPARATOR CURRENT SENSE COMPARATOR REVERSE CURRENT COMPARATOR CURRENT SENSE COMPARATOR REVERSE CURRENT COMPARATOR REVERSE CURRENT COMPARATOR SLOPE4 CLK4 CLK2 CLK1 SS4 2.4µA SS3 0.8V 0.8V FB4 FB1 SW3 PVIN3 TRKSS1 PG1 GND SW1 PVIN1 GND FB3 ILIM4 ITRIP ILIM1 ILIM3 ERROR AMPLIFIER ERROR AMPLIFIER LOOP COMPENSATION + 0.736V 1.08V 0.92V 0.864V 0.736V PG4PG3 CPOR POREN LOOP COMPENSATION LOOP COMPENSATION BIAS VIN POWER-ON RESET FSEL4B FSEL4A BOOST DIVIDER AND SLOPE GEN SYNC RT OSCILLATOR REFERENCE STANDBY/BIAS INTVCC4 REGULATOR INTVCC REGULATOR EN/UVLO LOGIC 3 LOGIC 1 INTVCC INTVCC4 INTVCC4 INTVCC4 3.4V 0.8V 1.2V CURRENT COMPARATOR ERROR AMPLIFIER

Rev. C For more information www.analog.com OPERATION The LT8603 combines two 42V input step-down convert- ers (Channels 1 and 2), one 5.5V input step-down con - verter (Channel 3) and a boost controller (Channel 4) to provide a flexible system that can be configured to gener- ate up to four regulated outputs. For example, the boost controller may be used to guarantee a supply to the high voltage converters above their minimum dropout voltage even during the cold crank cycle in an automobile. Start-Up When enabled by setting the EN/UVLO voltage above its threshold, the LT8603 INTVCC regulator charges its output capacitor to supply the internal chip circuitry. If BIAS is higher than 3.1V, BIAS supplies current to the INTV CC regulator to reduce VIN quiescent current. The boost controller is enabled with a logic high on either one or both of the FSEL4A and FSEL4B pins. Once enabled, the INTVCC4 regulator charges its output capaci- tor bringing the INTV CC4 supply into regulation. When the voltage at INTVCC4 exceeds 4.0V, the boost controller gate driver will begin supplying gate drive pules to the external MOSFET . Like the INTVCC regulator , the INTVCC4 regulator can also draw power from the BIAS pin when BIAS exceeds 4.6V. High Voltage Buck Regulators (Channels 1 and 2) Each high voltage channel is a synchronous buck regu - lator that operates from an independent PV IN pin. The internal top power MOSFET is turned on at the beginning of each oscillator cycle, and turned off when the current flowing through the top MOSFET reaches a level deter - mined by the error amplifier . The error amplifier measures the output voltage through an external resistor divider tied to the FB pin to control the peak current in the top switch. The reference of the error amplifier is determined by the lower of the internal 1V reference and the voltage at its TRKSS pin. While the top MOSFET is off, the bottom MOSFET is turned on for the remainder of the oscillator cycle or until the inductor current starts to reverse. If overload conditions result in more than 2A for Channel 1 or 3.3A for Channel 2 flowing through the bottom switch, the next clock cycle will be delayed until switch current returns to a safe level. The TRKSS pins can be used for controlled start-up or tracking of another supply. Low Voltage Buck Regulator (Channel 3) The low voltage channel is a synchronous buck regulator that operates from an independent PVIN pin. The PVIN pin has an undervoltage lockout set at 2.35V. The top power MOSFET is turned on at the beginning of each oscillator cycle, and turned off when the current flowing through the top MOSFET reaches a level determined by the error amplifier . The error amplifier measures the output voltage through an external resistor divider tied to the FB3 pin to control the peak current in the top switch. The reference of the error amplifier is an internal 800mV reference. While the top MOSFET is off, the bottom MOSFET is turned on for the remainder of the oscillator cycle or until the induc- tor current starts to reverse. If overload conditions result in more than 2.4A flowing through the bottom switch, the next clock cycle will be delayed until switch current returns to a safe level. The low voltage channel has a RU N3 pin to allow power sequencing, plus an internal soft-start circuit that ramps the output voltage up in 1ms. Boost Controller (Channel 4) The boost controller includes an error amplifier , loop compensation, current comparator , switch control logic, and a gate driver . The controller is enabled and its clock frequency selected by control of the FSEL4A and FSEL4B pins as described in the Applications Information section. The required external N-channel MOSFET is turned on by the internal clock and turned off when the inductor current sensed by the current comparator exceeds its threshold. The error amplifier adjusts the current com - parator threshold by comparing the FB4 voltage to an internal 0.8V reference voltage. The output voltage is set by a resistor divider from the output to the FB4 pin. The internal INTVCC4 regulator provides the gate drive for the external MOSFET .

Rev. CFor more information www.analog.com OPERATION Multiphase Switching The oscillator generates two clock signals 180° out of phase with each other . Channels 1 and 3 operate from CLK1, while Channels 2 and 4 operate from CL K2. The clock for Channel 4 may be selected as either a ÷1, ÷2 or ÷5 version of CLK2 using the FSEL4A and FSEL4B pins. Regardless of the divide ratio chosen, the Channel 4 clock edges remain aligned to the CLK2 edges. Since a buck regulator only draws input current during the top switch on cycle, multiphase operation reduces peak input current and doubles the input current frequency. These effects reduce input current ripple and reduce the input capacitance required. Undervoltage Lockout The EN/UVLO pin is used to put the LT8603 in shutdown, reducing the input current to less than 1μA. The accurate 1.2V threshold of the EN/UVLO pin provides a program - mable VIN undervoltage lockout through an external resis- tor divider tied to the EN/UVLO pin. A 50mV hysteresis voltage on the EN/UVLO pin prevents switching noise from inadvertently shutting down the LT8603. Power Good Comparators Channels 1, 2 and 3 have power good comparators that trip when the feedback pin is more than 8% above or below its reference voltage. Channel 4 has a power good comparator that indicates when the output voltage is more than 8% below its reference. The PG output pins are open- drain and pulled low when the corresponding output is out of regulation. The PG outputs are not valid until INTV CC rises to 2.7V. Power-On Reset Timer The LT8603 includes a power-on reset timer . The power-on reset timeout period is adjustable using an external capacitor on the CPOR pin as described in the Applications Information section. The timer is initiated when the POREN pin is higher than 1.2V. The output of the POR timer , the RST pin, is an open-drain output with a weak internal pull-up of 100k to approximately 2V. RST is held low until the expiration of the POR timer . The RST pin is only valid when the LT8603 is enabled and INTVCC is above 2.7V.

be configured to generate up to four regulated outputs. troller can go lower than 3V. hysteresis. The UVLO divider circuit is shown in Figure 1.

• 1.2V Switching Frequency All 4 channels share a single oscillator . The buck chan - nels switch at the oscillator frequency. The boost chan - nel can switch at f OSC, fOSC/2 or f OSC/5. The switching frequency range of all 4 channels should be determined before selecting the oscillator frequency. A low frequency usually provides better efficiency and a wider operating range due to lower switching losses and less sensitivity to timing constraints such as minimum on- and off-times. A high switching frequency uses smaller components and moves the switching noise away from sensitive frequency bands, such as the AM radio band, but does so at the cost of lower efficiency. A high switching frequency also decreases the duty cycle range because of finite mini - mum on- and off-times which are independent of the switching frequency. The oscillator frequency can be programmed from 250kHz to 2.2MHz by tying a resistor from the RT pin to ground. Table 1 shows the necessary value of RT for some com- mon switching frequencies.

Table 1. Oscillator Frequency (fOSC) vs RT Value placed close to the LT8603 and away from noise sources. Figure 1. UVLO Divider

8603 F01

avoid unexpected interactions. nected to external components to form a boost converter . how they are connected internally. goes to the current comparator to set the peak current. width is 120ns for a high pulse and 90ns for a low pulse. frequency close to the synchronization input. pin. Do not leave the SYNC pin floating. Figure 2. Boost Controller Block Diagram

8603 F02

a single diode in series with external MOSFET drain. comparator , or when maximum duty cycle is reached. Table 2. Boost Frequency Selection BIAS. Do not use the INTVCC4 output for external circuitry. Figure 3. Feedback Resistor Divider that it is not influenced by anticipated leakage or noise. ler will be inactive consuming minimal quiescent current. must reach 4V plus the diode forward voltage to start.

8603 F03

is required the SEPIC configuration should be considered. where VD is the forward voltage drop of the diode. Figure 4. Channel 4 in Boost Configuration

8603 F04

*SD2 IS FOR REVERSE INPUT PROTECTION. SHORT IF NOT NEEDED.

Rev. C For more information www.analog.com APPLICATIONS INFORMATION From this the ripple current can be specified using: ∆IL = χ•IL(MAX) = χ•IOUT(MAX) • 1 1 – DMAX where χ in the above equation represents the percent - age peak-to-peak ripple current in the inductor relative to IL(MAX). Choosing the inductor ripple current, ∆IL, has a direct impact on the choice of the inductor value and the converter’s maximum output current capability. Choosing smaller values of ∆IL increases the converter’s output cur- rent capability but requires larger inductors. Choosing larger values of ∆IL provides faster transient response and allows the use of smaller inductors but results in higher input current ripple, greater core losses, and lower output current capability. In addition, larger values of ∆IL at high duty cycle may result in sub-harmonic oscillation. The typical range for χ is 20% to 40% though careful evaluation of system stability should be made to ensure adequate design margin. The peak inductor current will be the average inductor current plus half the ripple current. The LT8603 current sense comparator has a built-in cur- rent limit threshold of 50mV across ISP4 and ISN4 so the peak voltage across the sense resistor should be kept to no more than 80% of this or 40mV. Therefore, the value of RSENSE should be: RSENSE = 0.04 IL(PEAK) IL(PEAK) can be calculated from: IL(PEAK) = 1+ χ ⎝⎜ ⎞ ⎠⎟• IOUT(MAX) 1 – DMAX The inductor value to achieve the required ripple is given by following equation: L = VBATT MIN( ) ∆IL • fSW

• DMAX The inductor should have a saturation current exceeding the current limit value of: ILIM = 0.05 RSENSE Finally, the ESR and magnetic loss of the inductor con - tribute to overall system power loss. For best efficiency, an inductor with low ESR and a core rated for the desired operating frequency should be chosen. The sense resis- tor should be chosen to have adequate power handling capability. The maximum power dissipation is given by: PRSENSE = 0.052 RSENSE For example, a 4mΩ could dissipate up to 0.625W. Boost: MOSFET Selection For the boost configuration, the selected external MOSFET should have a BVDSS rating exceeding, with margin, the larger of either the maximum input voltage or the boost output voltage plus a diode forward voltage. The maxi - mum input voltage should include careful consideration of possible transient conditions. In addition, the chosen MOSFET should be compatible with the LT8603’s nomi- nal gate drive of 4.6V and have a low value of R DS(ON) for best efficiency. The current rating for the MOSFET must be greater than the peak inductor current. Finally, the maximum gate drive current required by the external MOSFET should not exceed the 40mA capability of the LT8603. The current drawn by the gate driver is given by: IDRIVE =Qg • fsw where Q g is the MOSFET gate charge and f SW is pro - grammed switching frequency. For example, if Q g is 20nC and f SW is 1MHz, the drive requirement is 20mA. Boost: Diode Selection In the boost converter , the rectifier diode, SD1, only con- ducts when the switch is off. The average diode current is equal to the output current. The peak current is equal to the peak inductor current and is given by: ID PEAK( ) = 1+ χ ⎝⎜ ⎞ ⎠⎟• IOUT MAX( ) 1 – DMAX

and a reverse breakdown voltage greater than VOUT4(MAX). desired reverse polarity protection. load conditions and stabilize the LT8603’s control loop. cant inductance to the load due to long wire or cables. be made to ensure adequate design margin. Figure 5. Switching Waveforms for a Boost Converter

8603 F05

withstand any voltage transients that may be applied. cation must be made to ensure adequate design margin. provides reverse battery protection. Figure 6. Channel 4 in SEPIC Configuration

8603 F06

*SD2 IS FOR REVERSE INPUT PROTECTION. SHORT IF NOT NEEDED.

frequency for the SEPIC converter . duty cycle may result in sub-harmonic oscillation. should be made to ensure adequate design margin. culated at the minimum input voltage and full load current. Figure 7. SEPIC Topology and Current Flow

8603 F07

Figure 8. SEPIC Converter Switching Waveforms

8603 F08

Rev. CFor more information www.analog.com APPLICATIONS INFORMATION The power dissipated by the diode is: PD =IOUT(MAX) • VD If the reverse protection diode, SD2, is needed, the peak reverse voltage must be greater than the maximum reverse polarity input expected. The average forward cur- rent is equal to the input current and the peak forward current is the same as for the rectifier diode above. The start-up diodes, SD3 and SD4, have modest current requirements; the forward current will be less than 50mA under all input conditions. The peak reverse voltage on SD3 is the maximum reverse polarity input expected and the peak reverse voltage on SD4 is the maximum input voltage. SEPIC: DC-Coupling Capacitor The DC-coupling capacitor CC (C5 in Figure 6) sees a nearly rectangular current waveform as shown in Figure 8c. During the switch “off” time, the current through CC is approximately I IN, and approximately –IOUT during the switch “on” time. This current ripple creates a triangular ripple voltage on CC: ΔVCC(P−P) = IOUT(MAX) CC•fsw

• VOUT VBATT + VOUT + VD The maximum voltage on CC is then: VCC(MAX) = VBATT(MAX) + ΔVCC(P−P) which is typically close to VBATT(MAX). The ripple current through CC is: IRMS(CC) =IOUT(MAX) • VOUT +VD VBATT(MIN) The capacitance value should be chosen large enough that ∆VCC(P-P) is less than 10% of V BATT(MIN). If ∆VCC(P-P) is small then the voltage rating is close to VBATT(MAX). SEPIC: Output Capacitor The output capacitor has two essential functions. First, the output capacitor filters the LT8603’s discontinuous output current to produce the DC output current. In this role, the capacitor determines the output ripple, thus low imped - ance at the switching frequency is important. Second, the output capacitor stores energy in order to satisfy transient load conditions and stabilize the LT8603’s control loop. Typically, the low equivalent series resistance of X5R and X7R ceramic capacitors provide low output ripple and good transient response. For some applications, transient performance can be improved with higher output capacitance and/or the addition of a feedforward capacitor placed between the output voltage and the feedback pin. Note that larger out- put capacitance may be required when lower switching frequencies are used or when there is significant induc - tance to the load due to long wire or cables. Increasing the output capacitance will also decrease the output ripple. When choosing a capacitor , special attention should be given to the capacitor ’s data sheet to understand the effective capacitance under the relevant operating condi- tions of voltage bias and temperature. For good starting values, refer to the Typical Applications section. For all applications, careful evaluation of system stability should be made to ensure adequate design margin. SEPIC: Input Capacitor The input capacitor is in series with the inductor so the input current waveform is continuous and the d i/dt is limited. An input capacitor should be chosen to handle the RMS input capacitor ripple current as given by: IRMS CIN( ) =0.3 • VBATT MIN( ) L • fsw
• DMAX Ensure that capacitors present at the input are rated to withstand any voltage transients that may be applied.

where fSW is the programmed operating frequency. longer maintain the programmed operating frequency. series resistance (DCR) and magnetic loss. Figure 9. Feedback Resistor Divider

8603 F09

cation must be made to ensure adequate design margin. made to ensure adequate design margin.

Rev. CFor more information www.analog.com APPLICATIONS INFORMATION where VOUTx is the output voltage for the corresponding channel, VBOTx is the voltage across the bottom switch for the corresponding channel, fSW is the switching frequency in MHz, and L is in μH. Once the inductance is selected, the inductor current ripple and peak current can be calculated as: ∆ILx = VOUTx Lx •fSW

• 1– VOUTx PVINx(MAX) ILx(PEAK) = IOUTx(MAX) + ∆ILx where PVINx(MAX) is the maximum input voltage for each channel in a given application and IOUTx(MAX) is the maxi- mum output current for each channel in a given applica- tion. To avoid overheating and poor efficiency, an induc- tor must be chosen with an RMS current rating that is greater than the maximum expected output load of the application. In addition, the saturation current rating of the inductor must be higher than the load plus half the ripple current. Finally, for best efficiency the inductor series resistance should be as small as possible, and the core material should be intended for the application switching frequency. The optimum inductor for a given application may differ from the one indicated by this design guide. Careful evalu- ation of the application circuit should be completed with the chosen inductor to ensure adequate design margin. Buck: Shorted Output Protection If the bottom MOSFET current exceeds the valley current limit at the start of a clock cycle, the top MOSFET is kept off until the overcurrent situation clears. This prevents the buildup of inductor current during a shorted output condi- tion. Further , during overload or short-circuit conditions, the LT8603 safely tolerates operation with a saturated inductor . Buck: Input Capacitor Selection Step-down converters draw current from the input sup - ply in pulses with very fast rise and fall times. An input capacitor is required to reduce the resultant voltage ripple at the input and minimize EMI. For this function, a ceramic X7R or X5R bypass capacitor should be placed between each buck channel ’s PVIN pin and ground. To be most effective, the input capacitor must have low impedance at the switching frequency and an adequate ripple current rating. The worst case ripple current occurs when V OUT is one- half PVIN. Under this condition, the ripple current is: ICIN(RMS) = IOUT Reasonable starting values for the input capacitor are: 4.7μF for Channels 1 and 3 10μF for Channel 2 A word of caution is in order regarding the use of ceramic capacitors at the input. A ceramic input capacitor can combine with stray inductance to form a resonant tank circuit back to the supply. If power is applied quickly (for example by plugging the circuit into a live power source), this tank can ring, as much as doubling the input volt - age. The solution is to either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor in parallel with the ceramic capacitor . For details see Analog Devices Application Note 88. Buck: Output Capacitor Selection The output capacitor performs two functions. First, it fil- ters the inductor current to generate an output with low voltage ripple. Second, it stores energy to minimize droop and overshoot during transient loads. Because the LT8603 buck converters are able to operate at a high frequency, minimal output capacitance is necessary. The internally compensated current mode control loops are stable with- out requiring a minimum series resistance (ESR) in the output capacitor . Therefore ceramic capacitors may be used and will result in very low output ripple. You can estimate output ripple with the following equa - tions as appropriate: VRIPPLE = ∆IL 8 • fSW •COUT ,for ceramic

Rev. C For more information www.analog.com APPLICATIONS INFORMATION VRIPPLE =∆IL • ESR, for aluminum or tantalum where VRIPPLE is the peak-to-peak output ripple, f SW is the switching frequency, ∆IL is the peak-to-peak ripple current in the inductor , COUT is the output capacitor value in µF and ESR is the output capacitor series resistance. The low ESR and small size of ceramic capacitors make them the preferred type for LT8603 applications. However , not all ceramic capacitors are the same. Many of the higher value capacitors use dielectrics with high temperature and voltage coefficients. In particular Y5V and Z5U types lose a large fraction of their capacitance with applied voltage and at temperature extremes. Because loop stability, tran- sient response ripple and EMI depend on the value of the input and output capacitors it is best to use X5R (max 85°C), X7R (max 125°C), or X8R (max 150°C) capacitors depending on the operating temperature range. Electrolytic capacitors are also an option. The ESRs of most aluminum electrolytic capacitors are too large to deliver low output ripple. Tantalum, as well as newer , lower ESR organic electrolytic capacitors intended for power supply use are suitable. Choose a capacitor with a low enough ESR for the required output ripple. Because the volume of the capacitor determines its ESR, both the size and value will be larger than a ceramic capacitor that would give similar ripple performance. One benefit is that larger capacitance may give better transient response for large changes in load current. The Typical Applications section provides a reason - able starting point for output capacitor values. Note, for applications that intend to operate near minimum on- time, larger output capacitance values may be required to minimize output voltage ripple. Careful evaluation of each application must be made to ensure adequate design margin. Buck: Boost Capacitor Selection The high voltage channels require a voltage above PV IN to drive the gates of the top NFET switches. Connecting a capacitor between each channel’s BST and SW pins cre- ates this voltage with an approximate value of 3.3V. For most applications, a 0.1μF ceramic capacitor is a good choice. Buck: RUN, Soft-Start, T racking In addition to the global EN/UVLO pin that controls the entire chip, each channel has its own independent control pin or pins. The low voltage channel has a RUN pin with a fixed inter- nal threshold of 1.2V. When the RUN pin exceeds 1.2V, a soft start is initiated which brings the low voltage channel into regulation in approximately 1.0ms. Channel 1 and Channel 2 have dual purpose TRKSSx control pins which can be used to ramp each output in a controlled way. Each channel’s feedback pin voltage will regulate to the lower of the corresponding TRKSS pin and the internal 1V reference. These pins can therefore provide output voltage tracking. In addition, there is an internal constant current pull-up of 2.4μA at each TRKSS pin that can be used to charge an external capacitor to provide a programmable output soft-start function. The soft-start ramp time can be calculated from: tSS =CTRKSS • 1V 2.4µA The TRKSSx pin is pulled down through approximately 330Ω. It will be pulled down if temperature protection is activated. To achieve coincident tracking, connect a resistor divider from the controlling output to the TRKSS pin of the slave output. Figure 10 shows the divider required for Channel 2 to track VOUT1. With this circuit, R1 and R2 values should be chosen to minimize the offset from the 2.4µA pull- up current. To achieve ratiometric tracking, connect both TRKSS1 and TRKS S2 to a single capacitor to ground. Figure 10 shows the output waveforms for both coinci - dent and ratiometric tracking. Note: Pulling TRKSS1 and TRKSS2 to ground does not guarantee the respective channel will never display a switching cycle.

an internal clock counter that terminates after 64 cycles. Figure 10. T racking Output Waveforms

8603 F10

and their connections made on that layer . should be kept as small as possible. planes and thermal vias under and near the part. Figure 11. Power-On Reset Timing

8601 F11

sequencing example is shown in Figure 12. OUT3 is in regulation, then the POR timer is started. Figure 12. Sequencing the Outputs and POR

8603 F12

DC routing, ground plane fill. Layer 2 (Internal): Unbroken ground plane. maximum junction temperature. set of curves is representative of typical applications. measurements in the final application and environment. Figure 13. Thermal Derating, E-, I-, and J-Grade

8603 F13a

8603 F13b

Rev. C For more information www.analog.com 1.0/uni03BCH C9, 22pF R10, 187k R11, 374k C15 47/uni03BCF OUT3 1.2V C12 0.1/uni03BCF 1.5/uni03BCH C13, 15pF R8, 1M R9, 432k C14 47/uni03BCF OUT2 3.3V R12 28.7k C10, 4.7/uni03BCF C11, 4.7/uni03BCF C8, 2.2nF C7, 2.2nF 100/uni03BCFM1 SD2* SD1L4 1.5/uni03BCH 4m/uni03A9 4.7/uni03BCF CVIN1 4.7/uni03BCF CVIN2 4.7/uni03BCF VBATT 2V TO 20V TRANSIENTS TO 42V (4.3V TO START) 0.1/uni03BCFL1, 3.3/uni03BCH C8, 3.3pF R6, 1M R7, 249k 22/uni03BCF OUT1 5.0V

8603 TA03a

ISN4 GATE4 VIN PVIN1 PVIN2 BST1 SW1 FB1 BST2 SW2 FB2 BIAS PVIN3 SW3 FB3 PG1 PG2 PG3 PG4 RST L T8603 RT GND *SD2 OPTIONALL Y PROVIDES REVERSE BATTERY PROTECTION. REPLACE WITH SHORT IF REQUIRED. CVIN1, CVIN2, AND CVIN3 SHOULD BE PLACED AS CLOSE AS POSSIBLE TO THEIR RESPECTIVE PVIN PINS. * M2 IS RECOMMENDED FOR LOWEST QUIESCENT CURRENT WHEN CHANNEL 4 IS INACTIVE C16, 1000pF CVIN3 4.7/uni03BCF M2* 110k BOOST ON/OFF L1: WURTH 74437336033 L2: WURTH 74437336015 L3: WURTH 74437324010 L4: WURTH 7443736015 SD1: PMEG060V050EPD M1: RJK0651DPB-00 M2: FK3306010L INTVCC4 OUT4 8V FOR VBATT < 8.4V VBATT – 0.4V FOR VBATT > 8.4 Details of Front Page Application TYPICAL APPLICATIONS VIN VOUT4 VOUT3 VOUT2 VOUT1 4ms/DIV 2V/DIV

8603 TA03b

Rev. CFor more information www.analog.com L3, 1.0/uni03BCH C15, 22pF R10, 499k R11, 1M C16 47/uni03BCF 1.2V C12 0.1/uni03BCFL2, 1.5/uni03BCH C13, 15pF R8, 825k R9, 357k C14 47/uni03BCF 3.3V R12 28.7k C10, 4.7/uni03BCF C11, 4.7/uni03BCF C9, 2.2nF C7, 2.2nF 2.2/uni03BCH SD2* SD1 SD4SD3 2.2/uni03BCH 4m/uni03A9 20/uni03BCF CVIN1 4.7/uni03BCF CVIN2 4.7/uni03BCF VBATT 3V TO 42V (4.3V TO START) 0.1/uni03BCFL1, 3.3/uni03BCH C8, 3.3pF R6, 1M R7, 249k C17 22/uni03BCF OUT1 5.0V

8603 TA04a

ISN4 GATE4 VIN PVIN1 PVIN2 BST1 SW1 FB1 BST2 SW2 FB2 BIAS PVIN3 SW3 FB3 L T8603 RT GND *SD2 OPTIONALL Y PROVIDES REVERSE BATTERY PROTECTION. REPLACE WITH SHORT IF NOT REQUIRED. SD3 ENSURE START-UP . SD4 MAINAINS VIN AT VBATT < 4V . CVIN1, CVIN2, AND CVIN3 SHOULD BE PLACED AS CLOSE AS POSSIBLE TO THEIR RESPECTIVE PVIN PINS. 20/uni03BCF 100/uni03BCF OUT4 806k UNUSED PINS NOT SHOWN: PG1-4, POR, CPOR, RST VOUT 4 =0.8 •(R4 +R5) 110k CVIN3 4.7/uni03BCF L1: WURTH 74437336033 L2: WURTH 74437336015 L3: WURTH 74437324010 L4: WURTH 74485540220 SD1: PMEG060V050EPD M1: BSZ067N06LS3 Four Regulated Outputs with Channel 4 Configured as a SEPIC TYPICAL APPLICATIONS Start-Up Sequence VOUT3 VOUT2 VOUT1 VOUT4 VIN AT 10V/DIV 20ms/DIV 2V/DIV 10V/DIV

8603 TA04b

Rev. C For more information www.analog.com TYPICAL APPLICATIONS 0.1/uni03BCFL1, 2.2/uni03BCH C16, 10pF R12, 1M R13, 665k 47/uni03BCF 2.5V L3, 1.0/uni03BCH C15, 22pF R6, 499k R9, 1M 47/uni03BCF 1.2V 0.1/uni03BCFL2, 2.2/uni03BCH C14, 15pF R10, 825k R11, 357k C13 47/uni03BCF 3.3V 28.7k C10, 4.7/uni03BCF C11, 4.7/uni03BCF C9, 2.2nF C8, 2.2nF C3, 4.7/uni03BCF 5.6/uni03BCH 887k SD1 C12 22/uni03BCF VBATT 4V TO 20V 887k

8603 TA05a

R2, 422k BST1 SW1 FB1 10k C2, 4.7/uni03BCF C1, 4.7/uni03BCF 40m R5, 169k UNUSED PINS NOT SHOWN: PG1-4, POR, CPOR, RST L1: WURTH 74437324022 L2: WURTH 74437324022 L3: WURTH 74437321010 L4: Wurth 74437324056 SD1: PMEG6030ETP M1: RJK0651DPB-00 Four Regulated Outputs with Channel 4 Driven from Channel 2 VOUT3 VOUT1 VOUT2 VOUT4 VIN AT 5V/DIV 10ms/DIV 2V/DIV 5V/DIV

8603 TA05b

Rev. CFor more information www.analog.com TYPICAL APPLICATIONS L3, 1.0/uni03BCH C15, 22pF R10, 499k R11, 1M 47/uni03BCF OUT3 1.2V 1.5/uni03BCH C13, 15pF R8, 825k R9, 357k C14 47/uni03BCF OUT2 3.3V 0.1/uni03BCF C12 0.1/uni03BCF 2.2/uni03BCH C5, 3.3pF R6, 1M R7, 249k 22/uni03BCF OUT1 5.0V 28.7k C10, 4.7/uni03BCF C11, 4.7/uni03BCF C9, 2.2nF C8, 2.2nF SD1 22/uni03BCF 4.7/uni03BCF VBATT 6V TO 16V

8603 TA06a

15.4k 909k BEL – 0ZCJ0016FF2E ISP4 ISN4PVIN1 PVIN2 10m/uni03A9 22/uni03BCH 280k 10pF UNUSED PINS NOT SHOWN: PG1-4, POR, CPOR, RST L1: WURTH 74437336022 L2: WURTH 74437336015 L3: WURTH 74437324010 L4: WURTH 74437346220 SD1: PMEG060V05EPD M1: BUK9Y58-75, 115 Four Regulated Outputs with Channel 4 Providing 48V Output V OUT4 V IN V OUT1 V OUT2 V OUT3 AT 5V/DIV AT 2V/DIV AT 2V/DIV AT 2V/DIV 100ms/DIV 2V/DIV 10V/DIV 5V/DIV

8603 TA06b

Rev. C For more information www.analog.com PACKAGE DESCRIPTION 6.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (SEE NOTE 6) PIN 1 NOTCH R = 0.45 OR 0.35 × 45° CHAMFER 0.40 ±0.10 4039 BOTTOM VIEW—EXPOSED PAD

4.50 REF

(4-SIDES) 4.42 ±0.10 4.42 ±0.10 4.42 ±0.05 4.42 ±0.05 0.75 ±0.05 R = 0.115 TYP 0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UJ40) QFN REV Ø 0406 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 4.50 ±0.05 (4 SIDES) 5.10 ±0.05 6.50 ±0.05 0.25 ±0.05 R = 0.10 TYP 40-Lead Plastic QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1728 Rev Ø)

Rev. CFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 09/19 Added AECQ-100 under Features. Added LT8603J under Absolute Maximum Ratings section. Added LT8603JUJ#PBF & LT8603JUJ3TRPBF to the order table. Added LT8603EUJ#WPBF/TRPBF and LT8603JUJ#WPBF/WTRPBF to the order table. Added statements regarding #W under order table. Added switching frequency specs for E, I- and J-Grade on EC table. Updated Feedback voltage FB1 for E-, I- and J-Grade on EC table. Updated Feedback voltage FB2 for E-, I- and J-Grade on EC table. Updated Feedback voltage FB3 for E-, I- and J-Grade on EC table. Updated Feedback voltage FB4 for E-, I- and J-Grade on EC table. Edit and add additional information for current comparator input common mode range conditions for W-, I- and J-Grade. Added LT8603J grade temperature statement to Note 2 under EC table. Replaced FBref with VFB in R1 equation. Replaced VIN with PVIN. Added X8R information under Applications Information. Corrected di/dt typo. Added title for Figure 13 and Figure and second curve for thermal derating for J-Grade. Removed http info link. B 04/20 Add LT8603IUJ#WPBF to the order information. 2 C 06/25 Updated Typical Applications diagram 32

Rev. C www.analog.com © ANALOG DEVICES, INC. 2017-2025 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS Synchronous Micropower Step-Down DC/DC Converter with IQ = 25µA VIN = 3V to 42V, VOUT(MIN)= 0.8V, IQ = 25µA, ISD < 1µA, 6mm × 6mm QFN-40 Package LT8601 42V, 94% Efficiency, 2.2MHz T riple Output (1.5A+2.5A+1.8A) Synchronous Micropower Step-Down DC/DC Converter with IQ = 30μA VIN = 3V to 42V, VOUT(MIN)= 0.8V, IQ = 30µA, ISD < 1µA, 6mm × 6mm QFN-40 Package LT8640 42V, 5A/7A Peak, 96% Efficiency, 3MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 2.5µA VIN = 3.4V to 42V, VOUT(MIN) = 0.97V, IQ = 2.5µA, ISD < 1µA, 3mm × 4mm QFN-18 Package LT8614 42V, 4A, 96% Efficiency, 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 2.5µA VIN = 3.4V to 42V, VOUT(MIN) = 0.97V, IQ = 2.5µA, ISD < 1µA, 3mm × 4mm QFN-18 Package LT8616 42V, Dual 2.5A + 1.5A, 95% Efficiency, 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 5µA VIN = 3.4V to 42V, VOUT(MIN) = 0.8V, IQ = 5µA, ISD < 1µA, TSSOP-28E, 3mm × 6mm QFN-28 Packages LT8612 42V, 6A, 96% Efficiency, 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 2.5µA VIN = 3.4V to 42V, VOUT(MIN) = 0.97V, IQ = 3.0µA, ISD < 1µA, 3mm × 6mm QFN-28 Package LT8609/LT8609A 42V, 2A/3A Peak, 93% Efficiency, 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 2.5µA VIN = 3.2V to 42V, VOUT(MIN) = 0.8V, IQ = 2.5µA, ISD < 1µA, LT8610 42V, 2.5A, 96% Efficiency, 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 2.5µA VIN = 3.4V to 42V, VOUT(MIN) = 0.97V, IQ = 2.5µA, ISD < 1µA, LT8611 42V, 2.5A, 96% Efficiency, 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 2.5µA and Input/Output Current Limit/Monitor VIN = 3.4V to 42V, VOUT(MIN) = 0.97V, IQ = 2.5µA, ISD < 1µA, 3mm × 5mm QFN-24 Package LT8610A/8610AB 42V, 3.5A, 96% Efficiency, 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 2.5µA VIN = 3.4V to 42V, VOUT(MIN) = 0.97V, IQ = 2.5µA, ISD < 1µA, LT8610AC 42V, 3.5A, 96% Efficiency, 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 2.5µA VIN = 3V to 42V, VOUT(MIN) = 0.8V, IQ = 2.5µA, ISD < 1µA,