LT8602

LT8602 (Rev. C)

Document overview

• Manufacturer or author: Analog Devices Inc.
• PDF pages: 30

Technical content

Rev. CFor more information www.analog.comDocument Feedback TYPICAL APPLICATION FEATURES DESCRIPTION 42V Quad Monolithic Synchronous Step-Down Regulator The LT®8602 is a quad channel, current mode, monolithic buck switching regulator with a programmable power-on reset. All regulators are synchronized to a single oscillator with an adjustable frequency from 250kHz to 2.2MHz. The LT8602 can be configured for micropower Burst Mode operation or pulse-skipping operation at light load. Mi - cropower operation results in quiescent current of 30µA with all four regulators operating in the application below. The high voltage channels are synchronous buck regula- tors that operate from an input of 3V to 42V. The output currents are up to 1.5A (OUT1) and 2.5A (OUT2). The low voltage channels operate from an input of 2.6V to 5.5V. Internal synchronous power switches provide high efficiency with output currents up to 1.8A. The LT8602 uses a 2-phase clock with channels 1 and 3 operating 180° from channels 2 and 4 to reduce input ripple current on both HV and LV inputs. All channels have cycle-by-cycle current limit, providing protection against shorted outputs. Thermal shutdown provides additional protection. The LT8602 is available in either a 40-lead 6mm × 6mm QFN or a 48-Lead 7mm × 7mm LQFP package. 5V, 3.3V, 1.8V and 1.2V Step-Down Regulators

APPLICATIONS

n Flexible Power Supply System Providing Four Outputs with a Wide Input Range n Tw o High Voltage Synchronous Buck Regulators: 3V to 42V Input Voltage Range Output Currents Up to 2.5A and 1.5A High Efficiency Up to 93% n Tw o Low Voltage Synchronous Buck Regulators: 2.6V to 5.5V Input Voltage Range Output Currents Up to 1.8A and 94% Efficiency n Resistor Programmable and Synchronizable 250kHz to 2.2MHz Switching Frequency n Low Ripple Burst Mode® Operation: 30µA I Q at 12VIN Output Ripple < 15mV n Programmable Power-On Reset n Power Good Indicators n 2-Phase Clock Reduces Input Current Ripple n Available in Thermally Enhanced 40-Lead QFN (6mm × 6mm) or 48-Lead (7mm × 7mm) LQFP Packages n AEC-Q100 Qualified for Automotive Applications n Automotive Systems n Distributed Supply Regulation n Industrial Controls and Power Supplies HV Channel Efficiency, VIN = 12V, VOUT1 = 5V EFFICIENCY POWER LOSS F SW = 1MHz F SW = 2MHz LOAD CURRENT (A) 0.3 0.6 0.9 1.2 1.5 1.8 100 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 EFFICIENCY (%) POWER LOSS (W)

8602 TA01c

LV Channel Efficiency, VOUT3 = 1.8V

8602 TA01a

*IOUT2 = 2.5A – IPVIN3 – IPVIN4 VIN IN 6V TO 42V L T8602 POREN PVIN1 PVIN2 EN/UVLO OUT2 OUT3 1.8V , 1.7ASW3 FB3 OUT4 1.2V , 1.8ASW4 FB4 BST1 OUT1 5V , 1.5ASW1 FB1 BST2 OUT2 3.3V*SW2 FB2 BIAS PVIN4 PVIN3 INTVCC CPOR TRKSS1, 2 RT SYNC RST PG1-4 RUN3-4 EFFICIENCY POWER LOSS F SW = 1MHz F SW = 2MHz LOAD CURRENT (A) 0.3 0.6 0.9 1.2 1.5 100 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 EFFICIENCY (%) POWER LOSS (W)

8602 TA01b

All registered trademarks and trademarks are the property of their respective owners.

Rev. C For more information www.analog.com PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Supply Voltages (Note 1) 3940 38 37 36 35 34 33 32 31 11 2012 13 14 15 TOP VIEW GND UJ PACKAGE 40-LEAD (6mm × 6mm) PLASTIC QFN θJC = 2°C/W , θJA = 33°C/W EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB 16 17 18 19 PG1 GND SW1 BST1 BST2 SW2 SW2 GND GND BIAS RUN3 RT INTVCC FB3 FB1 FB2 FB4 VIN EN/UVLO TRKSS1 PG3 POREN GND PVIN1 SW3 GND PVIN3 SYNC RST CPOR PG2 PG4 GND PVIN2 SW4 GND PVIN4 RUN4 NC TRKSS2 PG1 GND GND SW1 SW1 BST1 BST2 SW2 SW2 GND GND BIAS PG2 PG4 GND PVIN2 PVIN2 GND SW4 GND PVIN4 GND RUN4 TRKSS2 PG3 POREN GND PVIN1 PVIN1 GND SW3 GND PVIN3 GND SYNC RSTB CPOR RUN3 RT INTVCC FB3 FB1 GND FB2 FB4 VIN EN/UVLO TRKSS1 TOP VIEW LXE PACKAGE 48-LEAD (7mm × 7mm) PLASTIC LQFP θJA = 20°C/W EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB GND ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL (QFN)/ TRAY (LXE) PART MARKING* PACKAGE DESCRIPTION MSL RATING TEMPERATURE RANGE LT8602EUJ#PBF LT8602EUJ#TRPBF LT8602UJ 40-Lead (6mm × 6mm) Plastic QFN 1 –40°C to 125°C LT8602IUJ#PBF LT8602IUJ#TRPBF LT8602UJ 40-Lead (6mm × 6mm) Plastic QFN 1 –40°C to 125°C LT8602JUJ#PBF LT8602JUJ#TRPBF LT8602UJ 40-Lead (6mm × 6mm) Plastic QFN 1 –40°C to 150°C LT8602ELXE#PBF LT8602ELXE#TRPBF LT8602LXE 48-Lead (7mm × 7mm) Plastic eLQFP 3 –40°C to 125°C LT8602ILXE#PBF LT8602ILXE#TRPBF LT8602LXE 48-Lead (7mm × 7mm) Plastic eLQFP 3 –40°C to 125°C Operating Junction Temperature (Notes 2, 3)

Rev. CFor more information www.analog.com

ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS Minimum Operating Voltage l 2.7 3 V Minimum Operating Voltage, to Start l 3.1 3.5 V VIN Quiescent Current, Shutdown EN/UVLO = 0.4V 0.1 1 µA VIN Quiescent Current, Operating No Load (Note 4) 100µA on VOUT2 (Note 4) µA µA EN/UVLO Threshold EN/UVLO Rising 1.15 1.2 1.25 V EN/UVLO Hysteresis 50 mV EN/UVLO Input Current EN/UVLO = 2V –40 40 nA Oscillator Switching Frequency RT = 28.9k, E-, I-Grade RT = 28.9k, J-Grade RT = 254k, E-, I-Grade RT = 254k, J-Grade l l l l 1.8 1.75 0.225 0.224 0.25 0.25 2.2 2.2 0.275 0.284 MHz MHz MHz MHz SYNC Input Frequency Range l 0.25 2.2 MHz SYNC Input Voltage Low l 0.3 V SYNC Input Voltage High l 1.2 V SYNC Input Current –100 100 nA Channel 1 Feedback Voltage FB1 E-, I-Grade J-Grade l l 0.988 0.98 1.012 1.015 V V FB Voltage Line Regulation VIN = 3V to 42V 0.002 0.01 %/V Input Current FB1 l –100 100 nA SW1 Peak Current Limit VIN = PVIN1 = 6V 2.3 2.7 3.0 A SW1 Leakage Current 0.1 1 µA SW1 Top On Resistance ISW1 = 1A 240 mΩ SW1 Bottom On Resistance ISW1 = 1A 170 mΩ Lower FB1 Power Good Threshold Percentage of VFB1 l 89 92 95 % Upper FB1 Power Good Threshold Percentage of VFB1 l 105 108 111 % PG1 Output Voltage Low IPG1 = –100μA l 0.1 0.2 V The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V, PVIN3 = PVIN4 = 3.3V unless otherwise noted. (Note 2) ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL (QFN)/ TRAY (LXE) PART MARKING* PACKAGE DESCRIPTION MSL RATING TEMPERATURE RANGE AUTOMOTIVE PRODUCTS** LT8602EUJ#WPBF LT8602EUJ#WTRPBF LT8602UJ 40-Lead (6mm × 6mm) Plastic QFN 1 –40°C to 125°C LT8602IUJ#WPBF LT8602IUJ#WTRPBF LT8602UJ 40-Lead (6mm × 6mm) Plastic QFN 1 –40°C to 125°C LT8602JUJ#WPBF LT8602JUJ#WTRPBF LT8602UJ 40-Lead (6mm × 6mm) Plastic QFN 1 –40°C to 150°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. **Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.

Rev. C For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V, PVIN3 = PVIN4 = 3.3V unless otherwise noted. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS PG1 Leakage Current PG1 = 5V, FB1 = 1V l 30 µA TRKSS1 Pull-Up Current SS1 = 0.2V 1.5 2.4 3.1 μA Minimum Switch-On Time ISW1 = 1A 60 ns Minimum Switch-Off Time ISW1 = 1A 70 ns Channel 2 Feedback Voltage FB2 E-, I-Grade J-Grade l l 0.988 0.98 1.012 1.015 V V FB Voltage Line Regulation VIN = 3V to 42V 0.002 0.01 %/V Input Current FB2 l –100 100 nA SW2 Peak Current Limit VIN = PVIN2 = 6V 3.5 4.0 4.5 A SW2 Leakage Current 0.1 1 µA SW2 Top On Resistance ISW2 = 1A 150 mΩ SW2 Bottom On Resistance ISW2 = 1A 100 mΩ Lower FB2 Power Good Threshold Percentage of VFB2 l 89 92 95 % Upper FB2 Power Good Threshold Percentage of VFB2 l 105 108 111 % PG2 Output Voltage Low IPG2 = –100μA l 0.1 0.2 V PG2 Leakage Current PG2 = 5V, FB2 = 1V l 30 µA TRKSS2 Pull-Up Current SS2 = 0.2V 1.5 2.4 3.1 µA Minimum Switch-On Time ISW2 = 2A 60 ns Minimum Switch-Off Time ISW2 = 2A 70 ns Channel 3 Operating Voltage l 2.6 5.5 V Feedback Voltage FB3 E-, I-Grade J-Grade l l 790 784 800 800 810 812 mV mV FB Voltage Line Regulation VIN = 3V to 42V 0.002 0.01 %/V Input Current FB3 l –100 100 nA SW3 Average Current Limit 1.8 3.1 3.5 A SW3 Leakage PVIN3 = 5.5V 0.1 1 µA SW3 PMOS On Resistance ISW3 = 1A 150 mΩ SW3 NMOS On Resistance ISW3 = 1A 120 mΩ Lower FB3 Power Good Threshold Percentage of VFB3 l 89 92 95 % Upper FB3 Power Good Threshold Percentage of VFB3 l 105 108 111 % PG3 Output Voltage Low IPG3 = –100μA l 0.1 0.2 V PG3 Leakage Current PG3 = 5V, FB3 = 0.8V l 30 µA RUN3 Threshold Voltage 200mV/ms Falling Ramp l 0.695 0.72 0.75 V RUN3 Input Current RUN3 = 3.3V l –100 100 nA Soft-Start Time l 0.7 1 1.3 ms Minimum Switch-On Time ISW3 = 1A 70 ns Minimum Switch-Off Time ISW3 = 1A 70 ns PVIN3 UVLO 2.35 2.6 V

Rev. CFor more information www.analog.com The l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V, PVIN3 = PVIN4 = 3.3V unless otherwise noted. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS Channel 4 Operating Voltage l 2.6 5.5 V Feedback Voltage FB4 E-, I-Grade J-Grade l l 790 784 800 800 810 812 mV mV FB Voltage Line Regulation VIN = 3V to 42V 0.002 0.01 %/V Input Current FB4 l –100 100 nA SW4 Average Current Limit 1.8 3.1 3.5 A SW4 Leakage PVIN4 = 5.5V 0.1 1 µA SW4 PMOS On Resistance ISW4 = 1A 150 mΩ SW4 NMOS On Resistance ISW4 = 1A 120 mΩ Lower FB4 Power Good Threshold Percentage of VFB4 l 89 92 95 % Upper FB4 Power Good Threshold Percentage of VFB4 l 105 108 111 % PG4 Output Voltage Low IPG4 = –100μA l 0.1 0.2 V PG4 Leakage Current PG4 = 5V, FB4 = 0.8V l 30 µA RUN4 Threshold Voltage 200mV/ms Falling Ramp l 0.695 0.72 0.75 V RUN4 Input Current RUN4 = 3.3V l –100 100 nA Soft-Start Time l 0.7 1 1.3 ms Minimum Switch-On Time ISW4 = 1A 70 ns Minimum Switch-Off Time ISW4 = 1A 70 ns PVIN4 UVLO 2.35 2.6 V Power-On Reset CPOR Pull-Up Current CPOR = 0V 2 μA POR Delay Time CPOR = 1000pF 31 35.2 39.4 ms RST Output Voltage Low IRST = –100μA l 0.1 0.2 V RST Pull-Up Current POR Timed Out, RST = 0V 20 μA RST Leakage Current RST = 6V, EN/UVLO = 0V –40 40 nA POREN Threshold l 1.15 1.2 1.25 V POREN Pull-Up Current POREN = 0V 0.8 1.2 1.6 μA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT8602E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8602I is guaranteed to meet performance specifications from –40°C to 125°C junction temperature. The LT8602J is guaranteed over the full –40°C to 150°C operating junction temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures above 125°C. Note 3: This IC includes overtemperature protection that is intended to protect the device during overload conditions. Junction temperature will exceed 150°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature will reduce lifetime. Note 4: All four channels enabled as shown in the application circuit details of front page application (using the 1MHz component values) found in the Typical Application section.

Rev. C For more information www.analog.com Channel 2 Peak Current Limit vs Duty Cycle Channel 3/4 Peak Current Limit vs Duty Cycle TYPICAL PERFORMANCE CHARACTERISTICS Channel 1 Peak Current Limit vs Duty Cycle Channel 1 Efficiency vs Load VOUT1 = 8V, fSW = 2MHz Channel 2 Efficiency vs Load VOUT2 = 3.3V, fSW = 2MHz Channel 2 Efficiency vs Load VOUT2 = 3.3V, fSW = 1MHz LV Channel Efficiency vs Load VOUT3 = 1.8V, fSW = 1MHz LV Channel Efficiency vs Load VOUT4 = 1.2V, fSW = 2MHz T A = 25°C, VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V and PVIN3 = PVIN4 = 3.3V, unless otherwise noted. LOAD CURRENT (A) 0.0001 0.001 0.01 0.1 100 EFFICIENCY (%)

8602 G01

= 12V PV IN = 28V PV IN = 42V LOAD CURRENT (A) 0.0001 0.001 0.01 0.1 100 EFFICIENCY (%)

8602 G03

= 5.5V PV IN2 = 12V PV IN2 = 28V LOAD CURRENT (A) 0.0001 0.001 0.01 0.1 100 EFFICIENCY (%)

8602 G05

P VIN4 = 2.6V P VIN4 = 3.3V P VIN4 = 5.5V PVIN3 = 2.6V PVIN3 = 3.3V PVIN3 = 5.5V LOAD CURRENT (A) 0.0001 0.001 0.01 0.1 100 EFFICIENCY (%)

8602 G04

DUTY CYCLE (%) 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 TOP FET CURRENT LIMIT (A)

8602 G06

DUTY CYCLE (%) 100 1.5 2.5 2.0 3.0 3.5 4.0 TOP FET CURRENT LIMIT (A)

8602 G08

DUTY CYCLE (%) 100 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 MAX OUTPUT CURRENT (A)

8602 G09

Channel 3/Channel 4 Maximum Output Current vs Duty Cycle DUTY CYCLE (%) 100 2.5 3.0 3.5 4.0 4.5 5.0 TOP FET CURRENT LIMIT (A)

8602 G07

= 5.5V PV IN2 = 12V PV IN2 = 24V LOAD CURRENT (A) 0.0 0.5 1.0 1.5 2.0 2.5 100 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 EFFICIENCY (%) POWER LOSS (W)

8602 G02

Rev. CFor more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS TRKSS Pull-Up Current vs Voltage RST Pull-Up Current vs Voltage Power-On Reset Time vs CPOR Switching Frequency vs RT T A = 25°C, VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V and PVIN3 = PVIN4 = 3.3V, unless otherwise noted. Switching Frequency vs Temperature Quiescent Current vs VIN Minimum On-Time vs ISW Minimum Off-Time vs ISW TEMPERATURE (°C) –10 –30 –50 110 130 150 FREQUENCY CHANGE (%)

8602 G10

RT = 30k RT = 60k RT = 250k RST VOL TAGE (V) 0.5 1.5 2.5 3.5 –30 –20 –10 RST CURRENT (µA)

8602 G12

CPOR (pF) 2000 4000 6000 8000 10000 100 150 200 250 350 300 400 POR DELAY TIME (ms)

8602 G13

R T (kΩ) 100 125 150 175 200 225 250 275 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 FREQUENCY (MHz)

8602 G14

TRKSS VOL TAGE (V) 0.5 1.5 2.5 3.5 TRKSS CURRENT (µA)

8602 G11

V IN (V) IQ (µA)

8602 G15

SWITCH CURRENT (A) 0.5 1.5 2.5 100 MINIMUM ON-TIME (ns)

8602 G16

SWITCH CURRENT (A) 0.5 1.5 2.5 100 MINIMUM OFF-TIME (ns)

8602 G17

ISW = 1A CHANNEL 1 CHANNEL 2 TEMPERATURE (°C) –50 –25 100 125 150 MINIMUM ON-TIME (ns)

8602 G18

Rev. C For more information www.analog.com T A = 25°C, VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V and PVIN3 = PVIN4 = 3.3V, unless otherwise noted. Channel 3/Channel 4 RDSON vs Temperature Channel 3/Channel 4 Minimum Off-Time vs ISW Channel 1 RDSON vs Temperature Channel 2 RDSON vs Temperature TYPICAL PERFORMANCE CHARACTERISTICS Channel 3/Channel 4 Minimum On-Time vs ISW Minimum Off-Time vs Temperature TEMPERATURE (°C) –50 –25 100 125 150 100 MINIMUM OFF-TIME (ns)

8602 G19

I SW = 1A ISW (A) 0.3 0.6 0.9 1.2 1.5 100 120 140 160 180 MINIMUM ON-TIME (ns)

8602 G20

PVIN = 2.6V PVIN = 3.3V PVIN = 5.5V ISW (A) 0.3 0.6 0.9 1.2 1.5 100 MINIMUM OFF-TIME (ns)

8602 G21

TEMPERATURE (°C) –50 –25 100 125 150 100 200 300 400 500 R DSON (mΩ)

8602 G22

ISW1 = 1A TEMPERATURE (°C) –50 –25 100 125 150 100 200 300 400 R DSON (mΩ)

8602 G23

ISW2 = 1A TEMPERATURE (°C) –50 –25 100 125 150 100 150 200 250 300 R DSON (mΩ)

8602 G24

ISW = 1A CHANNELS 1, 2 CHANNELS 3, 4 TEMPERATURE (°C) –50 –25 100 125 150 0.990 0.995 1.000 1.005 1.010 0.790 0.795 0.800 0.805 0.810 CHANNELS 1, 2 V FB (V) CHANNELS 3, 4 V FB (V)

8602 G25

V EN/UVLO (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 I EN/UVLO (µA)

8602 G26

Feedback Voltage vs Temperature EN/UVLO Current vs Voltage Channel 1 Full Frequency VIN vs Load Current RT = 28.9k FULL FREQUENCY REGION (2MHz) VOUT = 3.3V VOUT = 5V I OUT (A) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 V IN (V)

8602 G27

Rev. CFor more information www.analog.com T A = 25°C, VIN = PVIN1 = PVIN2 = 12V, EN/UVLO = 3V and PVIN3 = PVIN4 = 3.3V, unless otherwise noted. TYPICAL PERFORMANCE CHARACTERISTICS Channel 2 Start-Up and Dropout, RL = 20Ω Channel 2 Start-Up and Dropout, RL = 2Ω Channel 1 Start-Up and Dropout, RL = 3.3Ω Full Frequency Waveforms Light Load Waveforms 100ms/DIV 2V/DIV

8602 G29

Channel 3, 4 Full Frequency VIN vs Load Current Channel 1 Start-Up and Dropout, RL = 20Ω 100ms/DIV 2V/DIV

8602 G33

8602 G30

8602 G32

VOUT1 = 5V VOUT2 = 3.3V VOUT3 = 1.8V VOUT4 = 1.2V VSW4 2V/DIV

8602 G34

5µs/DIV VOUT 20mV/DIV VSW 5V/DIV CHANNEL 1 12VIN TO 5VOUT AT 10mA VSYNC = 0V IL 0.5A/DIV

8602 G35

I OUT (A) 0.3 0.7 1.3 1.6 1.9 2.3 2.6 V IN (V)

8602 G28

R T = 28.9k FULL FREQUENCY REGION (2MHz) V OUT = 3.3V V OUT = 5V I OUT (A) 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 V IN (V) RT = 28.9k FULL FREQUENCY REGION (2MHz) VOUT = 1.8V VOUT = 1.2V

Rev. C For more information www.analog.com T A = 25°CTYPICAL PERFORMANCE CHARACTERISTICS Radiated EMI Performance, (CISPR25 Radiated Emission Tests with Class 5 Peak Limit) Vertical Polarization Horizontal Polarization DC1949A Demo Board with EMI Filter Installed 14VIN, 1A at All Outputs, FSW = 2MHz

Rev. CFor more information www.analog.com PIN FUNCTIONS INTVCC (Pin 28/Pin 33): Internal Regulator Bypass. Do not load the INTVCC pin with external circuitry. INTVCC is 3.1V when BIAS < 3.1V; 3.4V when BIAS > 3.4V; and equal to BIAS when BIAS is between 3.1V and 3.4V. Decouple to ground with a low ESR 4.7μF capacitor . PG1, PG2 (Pins 1, 11/Pins 1, 13): Power Good Indica - tors for Channels 1 and 2. Open drain logic output pulls down until the corresponding FB pin rises above 0.92V but remains below 1.08V. PG3, PG4 (Pins 40, 12/Pins 48, 14): Power Good Indica- tors for Channels 3 and 4. Open drain logic output pulls down until the corresponding FB pin rises above 0.736V but remains below 0.864V. POREN (Pin 39/Pin 47): Power On Reset Enable. This is a logic input that starts the ramp on the POR timing capacitor . This input has a weak pull-up. PVIN1, PVIN2 (Pins 37, 14/Pins 44, 45, 16, 17): Input Supply Voltage to HV Channels 1 and 2, respectively. These pins are independent and can be powered from different sources if necessary. Bypass each input with a low ESR capacitor to the adjacent GND pin. PVIN3, PVIN4 (Pins 34, 17/Pins 40, 21): Input Supply Voltage to low voltage Channels 3 and 4. These pins are typically connected to one of the high voltage converter outputs and should be locally bypassed with a low ESR capacitor . PVIN3 and PV IN4 are independent and do not need to be connected to the same supply voltage. RST (Pin 32/Pin 37): Power-On Reset Output. CMOS output with weak pull-up, this pin is held low until the POR times out. RT (Pin 29/Pin 34): Frequency Programming Resistor . Connect a resistor from this pin to ground to set the internal oscillator frequency. BIAS (Pin 10/Pin 12): Power to the internal INTVCC regu- lator . Connect to an output ≥3.1V when such a supply is available. Leaving BIAS unconnected will result in a decrease in efficiency at light load. Decouple to ground with a low ESR capacitor . BST1, BST2 (Pins 4, 5/Pins 6, 7): Boost Voltage for HV Channels. The Boost Voltage provides a drive voltage higher than PVIN to the gate of the NMOS top switch. CPOR (Pin 31/Pin 36): Power-On Reset Timer . Connect a capacitor from this pin to ground to program the power-on reset timer . CPOR has a 2μA pull-up current. EN/UVLO (Pin 22/Pin 26): Enable/Undervoltage Lockout Input. The LT8602 is in low power shutdown when this pin is below 0.4V. Between 0.4V and 1.1V, the part will turn on the internal reference. A precision threshold at 1.2V (rising) enables the switching regulators. This allows the EN/UVLO pin to be used as an input undervoltage lockout by connecting to a resistor divider between VIN and GND. When the EN/UVLO voltage is between 0.4V and 1.2V, the LT8602 input current will depend on the mode selected, the VIN voltage and the EN/UVLO voltage. Connect to VIN if the UVLO function is not needed. FB1, FB2 (Pins 26, 25/Pins 31, 29): Feedback Input Pins for the High Voltage Converters. The converters regulate the corresponding feedback pin to the lesser of 1V or the voltage on the associated TRKSS pin. FB3, FB4 (Pins 27, 24/Pins 32, 28): Feedback Input Pins for the Low Voltage Converters. The converters regulate the corresponding feedback pin to 800mV. GND (Pins 2, 8, 9, 13, 16, 35, 38, 41/Pins 2, 3, 10, 11, 15, 18, 20, 22, 30, 39, 41, 43, 46): Ground. These pins must be soldered to PCB ground. The exposed pad (pin 41) must also be soldered to PCB ground. (QFN/LXE)

Rev. C For more information www.analog.com PIN FUNCTIONS RUN3, RUN4 (Pins 30, 18/Pin 35, 23): Run Inputs for the low voltage converters. SW1 (Pin 3/Pins 4, 5): Channel 1 Switch Node. This is the output of the internal power switches for Channel 1. SW2 (Pins 6, 7/Pins 8, 9): Channel 2 Switch Node. This is the output of the internal power switches for Channel 2. These pins must be connected together . SW3, SW4 (Pins 36, 15/Pins 42, 19): Switch Nodes for low voltage converters. These are the outputs of the internal power switches for Channels 3 and 4. SYNC (Pin 33/Pin 38): Clock Synchronization Input. A digi- tal input to allow the LT8602 to synchronize its switching frequency to an external clock. If clock synchronization is not used, connect this pin to ground to enable low ripple burst mode or connect high to enable pulse skip operation of the synchronous converters. Do not allow SYNC to float. TRKSS1, TRKSS2 (Pins 21, 20/Pins 25, 24): T rack/Soft- Start Inputs for the High Voltage Converters. When this pin is below 1V, the converter regulates the FB pin to the TRKSS voltage instead of the internal reference. The TRKSS pin has a 2.4μA pull-up current. TRKSS may be left floating VIN (Pin 23/Pin 27): Input Supply Voltage to Internal Func- tions. This pin is independent from any PVIN pin and can be powered from different sources if necessary. VIN must be above 3V for the part to operate. (QFN/LXE)

Rev. CFor more information www.analog.com BLOCK DIAGRAM 8602 BD 2.4µA FB2 SW4 PVIN4 ILIM4 ILIM2 ERROR AMPLIFIER BST1 BST2 LOOP COMPENSATION LOGIC 1.08V 0.92V TRKSS2 PG2 SYNC RT GND DRIVER CURRENT SENSE COMPARATOR REVERSE CURRENT COMPARATOR GND RUN4RUN3 SW2 PVIN2 ILIM2 ILIM3 ILIM1 LOGIC CLK2 CLK2 CLK1 CLK1 GND DRIVER DRIVER DRIVER CURRENT SENSE COMPARATOR CURRENT SENSE COMPARATOR REVERSE CURRENT COMPARATOR CURRENT SENSE COMPARATOR REVERSE CURRENT COMPARATOR REVERSE CURRENT COMPARATOR 0.8V INTVCC CLK2CLK1SS4SS3 SS4 2.4µA SS3 0.8V 0.8V FB4 FB1 SW3 PVIN3 TRKSS1 PG1 GND SW1 PVIN1 GND FB3 ILIM4 ILIM1 ILIM3 ERROR AMPLIFIER ERROR AMPLIFIER ERROR AMPLIFIER LOOP COMPENSATION + 0.86V 0.74V 1.08V 0.92V 0.86V 0.74V PG4PG3 CPOR BIAS LOOP COMPENSATION LOOP COMPENSATION OSCILLATOR INTVCC VIN REGULATOR RST POREN POWER-ON RESET EN/UVLO ENABLE REFERENCE LOGIC LOGIC

Rev. C For more information www.analog.com OPERATION The LT8602 is a quad channel, constant frequency, current mode, monolithic buck switching regulator with power-on reset. All channels are synchronized to a single oscillator . T wo of the channels are high voltage (up to 42V input) while the other two are low voltage (up to 5.5V input) and are typically powered from the high voltage buck outputs. Start-Up When enabled by setting the EN/UVLO voltage above its threshold, the LT8602 starts charging the INTVCC capacitor from VIN. If BIAS is higher than 3.1V, BIAS supplies current to the INTVCC regulator to reduce VIN quiescent current. High Voltage Buck Regulators Each high voltage channel is a synchronous buck regulator that operates from an independent PVIN pin. The internal top power MOSFET is turned on at the beginning of each oscillator cycle, and turned off when the current flowing through the top MOSFET reaches a level determined by the error amplifier . The error amplifier measures the output voltage through an external resistor divider tied to the FB pin to control the peak current in the top switch. The refer- ence of the error amplifier is determined by the lower of the internal 1V reference and the voltage at its TRKSS pin. While the top MOSFET is off, the bottom MOSFET is turned on for the remainder of the oscillator cycle or until the inductor current starts to reverse. If overload conditions result in more than 2A (Ch 1) or 3.3A (Ch 2) flowing through the bottom switch, the next clock cycle will be delayed until switch current returns to a safe level. Low Voltage Buck Regulators Each low voltage channel is a synchronous buck regulator that operates from an independent PVIN pin. The PVIN pins have an undervoltage lockout set at 2.35V. Each internal top power MOSFET is turned on at the beginning of each oscillator cycle, and turned off when the current flowing through the top MOSFET reaches a level determined by the error amplifier . The error amplifier measures the output voltage through an external resistor divider tied to the FB pin to control the peak current in the top switch. The reference of the error amplifier is an internal 800mV reference. Each LV channel has a RUN pin to allow power sequencing and an internal soft-start circuit ramps the output voltage up in 1ms. While the top MOSFET is off, the bottom MOSFET is turned on for the remainder of the oscillator cycle or until the inductor current starts to reverse. If overload conditions result in more than 2.4A flowing through the bottom switch, the next clock cycle will be delayed until switch current returns to a safe level. Multiphase Switching The oscillator generates two clock signals 180° out of phase. Channels 1 and 3 operate on CLK1, while channels 2 and 4 operate on CLK2. Since a buck regulator only draws input current during the top switch on cycle, multiphase operation reduces peak input current and doubles the input current frequency. These effects reduce input current ripple and reduce the input capacitance required. Light Load Operation At light load, the regulators operate in low ripple burst mode. Low ripple burst mode shuts down most internal circuitry between switch on cycles to conserve power while still retaining low ripple at the output. Undervoltage Lockout The EN/UVLO pin is used to put the LT8602 in shutdown, reducing the input current to less than 1μA. The accurate 1.2V threshold of the EN/UVLO pin allows a programmable VIN undervoltage lockout through an external resistor divider tied to the EN/UVLO pin. A 50mV (typ) hysteresis voltage on the EN/UVLO pin prevents switching noise from inadvertently shutting down the LT8602.

Rev. CFor more information www.analog.com OPERATION Power Good Comparators Each channel has a power good comparator that trips when the feedback pin is above or below its reference voltage by more than 8%. The PG output pins are open drain. The PG pin for each channel is pulled low when the corresponding output is out of regulation. The PG outputs are not valid until INTVCC rises to 2.7V Power-On Reset Timer The LT8602 includes a power-on reset timer . The power- on reset time is adjustable using an external capacitor on the CPOR pin. The timer is enabled by the POREN pin. The RST pin is the output of the POR timer and is an open-drain output with a weak internal pull-up. The RST pin is valid when the LT8602 is enabled and INTV CC is above 2.7V.

should be 200k or less to avoid noise problems. noise sources, such as the inductor or a SW line. value of RT for common switching frequencies. Table 1. Switching Frequency vs RT Value where RT is in kΩ and fS is in MHz. quency operation is higher efficiency. increases when the switching frequency decreases. an external 250kHz to 2.2MHz clock signal on the SYNC pin. Figure 1. Feedback Resistor Divider

8602 F01

• 1.2V PVIN Voltage Range Each switching regulator channel operates from its own PVIN pin (PVIN1 to PVIN4). The PVIN pin can be connected to either an independent voltage supply or a high voltage channel output. The PVIN1 and PVIN2 voltage range is 3.0V to 42V. The PVIN3 and PVIN4 voltage range is 2.6V to 5.5V. The minimum PVIN voltage to regulate output voltage at full frequency is: PVINx(MIN) = VOUTx DCMAX Where DCMAX is the maximum duty cycle (refer to Switch- ing Frequency section) for that channel. If PVIN is below the calculated minimum voltage, the channel starts to skip switch off cycles. At low input voltages the part will turn on the top switch for longer than a full switch cycle in order to extend the effective duty cycle. When the part is extending the effective duty cycle the switching frequency will drop to one half (or less) of the programmed frequency. The maximum PVIN voltage to regulate output voltage at full frequency is: PVINx(MAX) = VOUTx DCMIN Where DCMIN is the minimum duty cycle (refer to Switching Frequency section) for that channel. If PVIN is above the calculated maximum voltage, the channel starts to skip switch on cycles (pulse-skipping). In this case, the channel switching frequency will no longer be the programmed frequency. The output will continue to regulate, but the peak inductor current and output ripple will increase significantly. Inductor Selection Inductor selection involves inductance, saturation current, series resistance (DCR) and magnetic loss. A good starting point for the inductance values are: Lx =Kx • VOUTx PVINx
• PVINx – VOUTx fS where fS is the switching frequency in MHz, Lx is in µH, VOUTx is the channel output voltage and K1 = 1.6, K2 = 1.0 and K3 and K4 = 1.3. Once the inductance is selected, the inductor current ripple and peak current can be calculated: ΔILx = VOUTx Lx •fS
• 1– VOUTx PVINx(MAX) ILx(PEAK) =IOUTx(MAX) + ΔILx To guarantee sufficient output current, peak inductor cur- rent must be lower than the switch current limit (ILIM). To keep the efficiency high, the inductor series resistance (DCR) should be as small as possible (must be <0.1Ω for channels 1, 3 and 4; <0.06Ω for channel 2), and the core material should be intended for the chosen switch - ing frequency. Table 2 lists several vendors and suitable inductor series.

Table 2. Inductor Vendors

Rev. C For more information www.analog.com APPLICATIONS INFORMATION Of course, such a simple design guide will not always result in the optimum inductors for the applications. A larger value inductor provides a slightly higher maximum load current and will reduce the output voltage ripple. A larger value inductor can result in higher efficiency if the DCR and magnetic losses are the same. However , for inductors of the same dimensions, the larger value inductor has higher DCR. The trade-off between inductance and DCR is not always obvious. Use experiments to find optimum inductors. Low inductance may result in discontinuous mode operation, which is acceptable, but reduces maximum load current. For details of maximum output current and discontinuous mode operation, see the Linear Technol - ogy Application Note 44. For duty cycles greater than 50%, there is a minimum inductance required to avoid subharmonic oscillations. LMINx = 1.05 • VOUTx +VBOTx( ) fS , chs 1, 3 and 4 LMINx = 0.70 • VOUTx +VBOTx( ) fS , ch 2 where VOUTx is the output voltage; V BOTx is the voltage across the bottom switch; fS is the switching frequency in MHz and LMINx is in µH. If the frequency is synchronized over a range, use the lowest frequency to determine LMINx. Shorted Output Protection The LT8602 will tolerate a shorted output. If the bottom MOSFET current exceeds the valley current limit at the start of a clock cycle, the top MOSFET is kept off until the overcurrent situation clears. This prevents the buildup of inductor current during a shorted output. Input Capacitor Selection Bypass each PVIN pin of the LT8602 with a ceramic capaci- tor of X5R (max 85°C), X7R (max 125°C), or X8R (max 150°C) type as appropriate. Step-down converters draw current from the input sup - ply in pulses with very fast rise and fall times. The input capacitor is required to reduce the resulting voltage ripple at the LT8602 input and to force this switching current into a tight local loop, minimizing EMI. The input capaci- tor must have low impedance at the switching frequency to do this effectively and it must have an adequate ripple current rating. The worst case ripple current is when VOUT is one half of PVIN. In this case, the ripple current is: ICIN(RMS) =IOUT A reasonable value for the input capacitor is: CIN = 4.7µF (for Chs 1, 3, 4) or 10µF ( for Ch 2) fS where fS is the switching frequency in MHz. Careful placement of C IN is essential to get the lowest ripple and EMI. CIN should be placed as close to the PVIN pin as possible and on the same side of the PC board. The layer immediately below the component traces should be an unbroken ground plane. The ground side of CIN should have at least 2 vias to the ground plane as close to C IN as possible. This provides a high frequency return path directly under the PVIN to CIN trace. This minimizes loop area of the high frequency, high current path from PV IN to CIN and back to the GND exposed pad. See Figure 8, Recommended PCB Layout. A word of caution is in order regarding the use of ceramic capacitors at the input. A ceramic input capacitor can combine with stray inductance to form a resonant tank circuit back to the supply. If power is applied quickly (for example by plugging the circuit into a live power source), this tank can ring, as much as doubling the input voltage. The solution is to either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor in parallel with the ceramic capacitor . For details, see Linear Technology Application Note 88.

the presence of output capacitor series resistance (ESR). and small circuit size, are therefore an option. V RIPPLE = ∆IL • ESR, for aluminum or tantalum. in µF and ESR is the output capacitor series resistance. where ILIM is the maximum switch current limit. types as appropriate considering operating temperature. Table 3. Low ESR Capacitor Vendors 0.1μF capacitor will work well. nel and internal soft-start for each low voltage channel. The low voltage channel soft-start is set to 1ms.

the capacitance on the TRKSS pin in F . ground does not guarantee the channel will stop switching. for coincident and ratiometric tracking. Figure 2. T racking Circuit

8602 F02

Figure 5. Burst Mode SW Waveforms with Figure 3. In this case, both OUT1 and OUT3 are held high PVIN3 if it is connected to an external supply. frequencies when in Burst Mode operation. Figure 3. Reverse Protection Diodes Figure 4. Burst Mode SW Waveforms with Oscillator Running

8602 F03

8602 F04

8602 F05

pin below 0.3V (this can be ground or a logic low output). lock range is ±20% of the RT set frequency.

Figure 6. Power-On Reset Timing CPOR = 230pF reached at lower output load than in Burst Mode operation. Do not leave the SYNC pin floating. resistance value of 20k or less. allows wired-OR connections of the RST pin. CPOR pin, such as probe capacitance, can affect t RST. above 10nF are not recommended. Figure 7. Sequencing the Outputs and POR sequencing example is shown in Figure 7.

8602 F06

8602 F07

until the voltage reaches the RUN threshold. at least 1.25V and a VOL less than 0.4V. Figure 9. Recommended QFN Package PCB LayoutFigure 8. EN/UVLO Thresholds

8602 F09

8602 F10a

8602 F10b

the circuit board and on the bottom side. stop switching if the internal temperature rises too high. temperature and is intended as a failsafe only. with a range of frequencies and input voltages. Figure 10. Thermal Derating, E-, I-, and J-Grade

Rev. CFor more information www.analog.com TYPICAL APPLICATIONS Details of Front Page Application

8602 TA02a

5V , 1.5AC1 22µF C12 4.7µF 453k 6.2µH 113k GND SW1 EN/UVLO VIN VIN 6V TO 42V BST1 L T8602 RST FB1 0.1µFPVIN1 C11 10µF PVIN2 OUT2 3.3V , 0.8A THE MAX CURRENT ON OUT2 IS A FUNCTION OF THE CURRENTS ON OUT3 AND OUT4: I(OUT2) = 2.5A – 0.6 • I(OUT3) – 0.4 • I(OUT4) 47µF 316k 2.2µH 137k SW2 BST2 FB2 0.1µF INTVCC RTSWITCHING FREQUENCY = 1MHz 4.7µF 4.7pF 22pF OUT3 1.8V , 1.7AC3 22µF 249k 200k 2.2µH SW3 FB3 OUT4 1.2V , 1.8AC4 47µF 100k 200k 1.8µH SW4 FB4 PVIN3 BIAS 4.7µF PVIN4 C6 4.7µF TRKSS1 C13 2200pF TRKSS2 RUN3 RUN4 PG1 OUT2 PG2 PG3 PG4 SYNC POREN CPOR 10pF 22pF R10 20k 60.4k Start-Up Sequence 200µs/DIV THE VALUES SHOWN ARE FOR 1MHz OPERATION. FOR 2MHz OPERATION, MAKE THE FOLLOWING CHANGES: L1 = 3.3µH L2 = 1.2µH L3 = 1.2µH L4 = 1µH R9 = 28.9k THE INPUT VOL TAGE RANGE AT 2MHz IS 6V TO 24V . ABOVE 24V , THE HV CHANNELS WILL REGULATE BUT WITH HIGH RIPPLE DUE TO MISSED PULSES. V OUT1 5V/DIV V OUT2 5V/DIV V OUT3 2V/DIV V OUT4 2V/DIV

8602 TA02b

Rev. C For more information www.analog.com TYPICAL APPLICATIONS Automotive Input Steps Down to 5V, 3.3V, 1.8V and 1.2V Start-Up Sequence

8602 TA03a

5V , 1.5AC1 22µF C12 4.7µF R12 499k 453k 4.7µH 113k GND SW1 EN/UVLOUVLO = 6V VIN VIN 6V TO 42V BST1 L T8602 RST FB1 0.1µFPVIN1 uP_START C11 10µFR11 PVIN2 OUT2 3.3V , 0.8A THE MAX CURRENT ON OUT2 IS A FUNCTION OF THE CURRENTS ON OUT3 AND OUT4: I(OUT2) = 2.5A – 0.6 • I(OUT3) – 0.4 • I(OUT4) 47µF 316k 2.2µH 137k SW2 BST2 FB2 0.1µF INTVCC RTSWITCHING FREQUENCY = 1.25MHz POR TIME = 7.7ms 4.7µF OUT3 1.8V , 1.7AC3 22µF 249k 200k 1.5µH SW3 FB3 OUT4 1.2V , 1.8AC4 47µF 100k 200k 1.2µH SW4 FB4 C10 220pF PVIN3 BIAS 4.7µF PVIN4 C6 4.7µF TRKSS1 C13 2700pF TRKSS2 RUN3 RUN4 PG1 OUT2 SYNC INPUT PG2 PG3 PG4 SYNC POREN CPOR R10 20k 47.5k 4.7pF 22pF 22pF 22pF OUT2 10k START-UP SEQUENCE: CH1 AND CH2 SOFT-START RATIOMETRICALL Y; THEN CH3 AND CH4 TURN ON; THEN POR TIMER STARTS. 1ms/DIV VOUT1 5V/DIV VOUT2 5V/DIV VOUT3 2V/DIV RST 2V/DIV

8602 TA03b

Rev. CFor more information www.analog.com PACKAGE DESCRIPTION 6.00 ±0.10 (4 SIDES) NOTE: 1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (SEE NOTE 6) PIN 1 NOTCH R = 0.45 OR 0.35 × 45° CHAMFER 0.40 ±0.10 4039 BOTTOM VIEW—EXPOSED PAD

4.50 REF

(4-SIDES) 4.42 ±0.10 4.42 ±0.10 4.42 ±0.05 4.42 ±0.05 0.75 ±0.05 R = 0.115 TYP 0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05 (UJ40) QFN REV Ø 0406 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 4.50 ±0.05 (4 SIDES) 5.10 ±0.05 6.50 ±0.05 0.25 ±0.05 R = 0.10 TYP 40-Lead Plastic QFN (6mm × 6mm) (Reference LTC DWG # 05-08-1728 Rev Ø)

Rev. C For more information www.analog.com PACKAGE DESCRIPTION LXE48 LQFP 0318 REV E 0° – 7° 11° – 13° 0.45 – 0.75

1.00 REF

11° – 13° 1.60 MAX1.35 – 1.45 BSC 0.17 – 0.27 GAUGE PLANE 0.25 NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.25mm (10 MILS) BETWEEN THE LEADS AND ON ANY SIDE OF EXPOSED PAD, MAX 0.50mm (20 MILS) AT CORNER OF EXPOSED PAD, IF PRESENT 3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION 4. DRAWING IS NOT TO SCALE R0.08 – 0.20 BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA) SIDE VIEW SECTION A – A

9.00 BSC

7.00 BSC

7.00 BSC 3.60 ±0.10 3.60 ±0.10 SEE NOTE: 3 C0.30 – 0.50 48-Lead Plastic Exposed Pad LQFP (7mm × 7mm) (Reference L TC DWG #05-08-1832 Rev E) Exposed Pad Variation BB 7.15 – 7.25

5.50 REF

7.15 – 7.25 13 24 PACKAGE OUTLINE RECOMMENDED SOLDER PAD LAYOUT APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.20 – 0.30

1.30 MIN

3.60 ±0.05 3.60 ±0.05 L TCXXXX XXYY TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN “A1”

Rev. CFor more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER A 09/16 Revised Electrical Characteristics tables and temperature dotted soft-start. Replaced G06 and G07 curves. Revised Pin Functions for BIAS, EN/UVLO INTVCC. Changed Figure 7. 4, 5 B 06/17 Added LQFP package option. Added Pin Functions for LQFP package option. Clarified Figure 9 for QFN package. Added clarified drawing for front page application. Typical Application moved from page 25 to 26. Clarified QFN package drawing. Added LQFP package option. 1,2 11,12 C 12/20 Added AEC-Q100 Qualified statement. Add J-Grade and Automotive products to Order Information table. Add J-Grade spec to Electrical Characteristics table, clarified condition. Clarified Note 2 J-Grade. Clarified Input/Output Capacitor Selection for J-Grade. Add Thermal Derating graph for J-Grade. 3, 4, 5 18, 19

Rev. C For more information www.analog.com  ANALOG DEVICES, INC. 2015-2020 www.analog.com PART NUMBER DESCRIPTION COMMENTS LT3507/ LT3507A 36V, 2.7A + 1.8A + 1.8A + LDO Controller , 2.5MHz, High Efficiency, T riple Output Step-Down DC/DC Converter VIN = 4V to 36V, VOUT(MIN) = 0.8V, IQ = 7mA, ISD < 1µA, 5mm × 7mm QFN LT8640 42V, 6A, 96% Efficiency, 2.2MHz Synchronous MicroPower Step-Down DC/DC Converter with IQ = 2.5µA VIN = 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5µA, ISD < 1µA, 3mm × 4mm QFN LT8616 42V Dual (2.5A + 1.5A), 95% Efficiency 3MHz Synchronous MicroPower Step-Down DC/DC Converter with IQ = 6.5µA VIN = 3.4V to 42V, VOUT(MIN) = 0.8V, IQ = 6.5µA, ISD < 1µA, LT8614 42V, 4A, 96% Efficiency, 2.2MHz Synchronous MicroPower Step-Down DC/DC Converter with IQ = 2.5µA VIN = 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5µA, ISD < 1µA, 3mm × 4mm QFN LT8612 42V, 6A, 96% Efficiency, 2.2MHz Synchronous MicroPower Step-Down DC/DC Converter with IQ = 2.5µA VIN = 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5µA, ISD < 1µA, 3mm × 6mm QFN LT8610 42V, 2.5A, 96% Efficiency, 2.2MHz Synchronous MicroPower Step-Down DC/DC Converter with IQ = 2.5µA VIN = 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5µA, ISD < 1µA, MSOP-16E LT8611 42V, 2.5A, 96% Efficiency, 2.2MHz Synchronous MicroPower Step-Down DC/DC Converter with IQ = 2.5µA and Input/Output Current Limit/Monitor VIN = 3.4V to 42V, VOUT(MIN) = 0.985V , IQ = 2.5µA, ISD < 1µA, 3mm × 5mm QFN-24 LT8610A/ LT8610AB 42V, 3.5A, 96% Efficiency, 2.2MHz Synchronous MicroPower Step-Down DC/DC Converter with IQ = 2.5µA VIN = 3.4V to 42V, VOUT(MIN) = 0.985V, IQ = 2.5µA, ISD < 1µA, MSOP-16E RELATED PARTS TYPICAL APPLICATION 10V to 42V Input Steps Down to 5V, 2.5V, 1.8V and 8V (Delayed)

8602 TA04a

8V , 1.5AC1 47µF C12 4.7µF R12 287k 1000k 4.7µH 143k GND SW1 EN/UVLOUVLO = 9.6V VIN VIN 10V TO 42V BST1 L T8602 RST FB1 0.1µFPVIN1 10pF C11 10µFR11 PVIN2 OUT2 5V , 0.8A THE MAX CURRENT ON OUT2 IS A FUNCTION OF THE CURRENTS ON OUT3 AND OUT4: I(OUT2) = 2.5A – 0.56 • I(OUT3) – 0.4 • I(OUT4) 47µF 549k 2.2µH 137k SW2 BST2 FB2 0.1µF INTVCC RT SWITCHING FREQUENCY = 2.2MHz 4.7µF OUT3 2.5V , 1.7AC3 47µF 243k 115k 1µH SW3 FB3 OUT4 1.8V , 1.8AC4 47µF 215k 174k 1µH SW4 FB4 C10 330pF PVIN3 BIAS 4.7µF PVIN4 C6 4.7µF TRKSS1 C13 2700pF C14 2.2nF TRKSS2 RUN3 RUN4 PG1 INTVCC PG2 PG3 PG4 SYNC POREN CPOR 10pF R10 20k 10k 26.1k 10pF 10pF 2ms/DIV V CPOR 1V/DIV V OUT3 2V/DIV V OUT4 2V/DIV V OUT1 10V/DIV V OUT2 5V/DIV

8602 TA04b

IN THIS APPLICATION, THE POR IS USED AS A DELAY FOR THE 8V SUPPL Y. THE 8V SUPPL Y WILL START RAMPING UP 12ms AFTER ALL OTHER SUPPLIES HAVE REACHED REGULATION. START-UP SEQUENCE: CH2 SOFT-STARTS; THEN CH3 AND CH4 TURN ON; THEN POR TIMER STARTS; AFTER POR TIMES OUT , THEN CH1 SOFT-STARTS. Start-Up Sequence