LT8601

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Rev. 0For more information www.analog.com Document Feedback TYPICAL APPLICATION FEATURES DESCRIPTION 42V Quad, Gangable, Synchronous, Monolithic Step-Down Regulator The LT®8685S is a highly flexible, four channel, current mode, monolithic regulator able to power a wide range of automotive and industrial applications while occupying minimal board space. The LT8685S combines two 42V capable 2.5A buck reg- ulators with two 8V capable 4A buck regulators. The two 42V regulators may be combined to provide up to 5A of output current using a single inductor . Similarly, the two 8V regulators may be combined to provide up to 8A of output current using a single inductor . Individual channel enable, track/soft-start and power good pins provide flex- ible power supply sequencing and control. The LT8685S features a Silent Switcher 2 architecture, plus selectable spread spectrum mode, to provide ultralow EMI/EMC emissions while delivering high efficiency at high switch- ing frequencies. The LT8685S incorporates thermal shutdown and individ- ual channel cycle-by-cycle current limit for short circuit protection and robust operation. 42V Input, Quad Output 2MHz Step-Down Regulator Efficiency and Loss

APPLICATIONS

n Silent Switcher®2 Architecture n Ultralow EMI Emissions n Optional Spread Spectrum Modulation n T wo High Voltage Synchronous Buck Regulators n 3V to 42V Input Voltage Range n Output Currents Up to 2.5A per Channel n Channels May Be Connected in Parallel Using a Single Inductor n T wo Low Voltage Synchronous Buck Regulators n 3V to 8V Input Voltage Range n Output Currents Up to 4A per Channel n Channels May Be Connected in Parallel Using a Single Inductor n 12µA IQ All Channels Active and No-Load n Flexible Supply Sequencing and Control n Adjustable and Synchronizable: 350kHz to 3MHz n Available in 36-Lead LQFN (5mm × 6mm) n AEC-Q100 Qualified for Automotive Applications n Automotive Systems n Industrial Controls and Power Supplies All registered trademarks and trademarks are the property of their respective owners. BST3 SW3 FB3 BST4 SW4 FB4 BIAS BST1 SW1 FB1 BST2 SW2 FB2 EN/UVLO EN2 V IN1 V IN2 EN3 EN4 V IN3 V IN4 6V TO 42V PG1-4 TRK/SS1-4 RT SYNC/MODE OUT1 5V , 2.5A* INTVCC OUT4 1.2V , 4A VIN OUT3 1.8V , 4A GND OUT2 3.3V , 2.5A L T8685S OUT1 *CURRENT AVAILABLE FROM OUT1: 2.5A – IVIN3 – IVIN4 – IBIAS 8685S TA01a HV CHANNEL EFFICIENCY 12V → 5V LV CHANNEL EFFICIENCY 5V → 1.8V HV CHANNEL LOSS LV CHANNEL LOSS LOAD CURRENT (A) 0.001 0.01 0.1 100 0.5 1.0 1.5 2.0 2.5 3.0 EFFICIENCY (%) POWER LOSS (W) 8685S TA01b

Rev. 0 For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS V B 3V to 14V T O perating Junction Temperature (Notes 2, 3) C to 150°C Maximum Reflow (Package Body) 0°C (Note 1) VIN1 VIN2 TRK/SS2 SYNC/MODE RT TRK/SS4 VIN3 VIN3 VIN4 VIN4 SW2 BST2 PG2 BIAS INTV CC TRK/SS3 PG3 BST3 SW3 SW3 TOP VIEW FB2 EN2 FB1 EN/UVLO TRK/SS1 PG1 BST1 SW1 FB3 EN3 FB4 EN4 PG4 BST4 SW4 SW4 LQFN PACKAGE 36-LEAD (5mm × 6mm × 0.95mm) TJMAX = 150°C, θJA = 19°C/W , θJC_top = 18.3°C/W , θJC_bottom = 5.4°C/W EXPOSED PAD (PINS 37 TO 40) MUST BE SOLDERED TO PCB GND NOTE: 1) θ VALUES ARE DETERMINED BY SIMULATION PER JESD51 CONDITIONS; 2) θJA VALUE IS OBTAINED WITH DEMO BOARD. 13 12 1114 15 16 17 18 34 35 3633 32 31 30 29 GND GND GND GND ORDER INFORMATION PART NUMBER TAPE AND REEL PAD OR BALL FINISH PART MARKING PACKAGE TYPE* MSL RATING TEMPERATURE RANGE (SEE NOTE 2)DEVICE FINISH CODE LT8685SRV#PBF LT8685SRV#TRPBF Au (RoHS) 8685S e4 LQFN (Laminate Package with QFN Footprint) 3 –40°C to 150°C AUTOMOTIVE PRODUCTS** LT8685SRV#WPBF LT8685SRV#WTRPBF Au (RoHS) 8685S e4 LQFN (Laminate Package with QFN Footprint) 3 –40°C to 150°C

• Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Tape and reel specifications.
• Parts ending with PBF and RoHS are WEEE compliant.
• Recommended LGA and BGA PCB Assembly and Manufacturing Procedures
• LGA and BGA Package and Tray Drawings *The LT8685S package has the same dimensions as a standard 5mm × 6mm QFN package. **V ersions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.

Rev. 0For more information www.analog.com

ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS Quiescent Current, Shutdown 0.5 1.5 µA Total Operating Input Current, Burst VOUT1 = VBIAS = 5V, VOUT2 = 3.3V, VOUT3 = 1.8V, VOUT4 = 1.2V, VSYNC/MODE = 0V, No Load 12 µA Total Operating Input Current, Pulse-Skipping V OUT1 = 5V, VOUT2 = 3.3V, VOUT3 = 1.8V, VOUT4 = 1.2V, VSYNC/MODE = Floating, No Load 1100 µA Switching Frequency RRT = 154k RRT = 22.6k RRT = 13.7k l l l 0.28 1.8 2.65 0.35 0.45 2.25 3.4 MHz MHz MHz SYNC Threshold Voltage V IL VIH l l 1.5 0.4 V V SYNC/MODE Pin Input Current VSYNC/MODE = 6V 75 µA Internal VCC Regulator 3.4 V Internal VCC Undervoltage Lockout Falling 2.3 2.4 2.5 V BIAS Pin Threshold 4.5 V Channels 1 to 2 Minimum Input Voltage (CH1 Only) l 2.8 3 V Feedback Reference Voltage l 0.786 0.8 0.812 V Feedback Input Current l –100 0 100 nA VFB1, VFB2 Line Regulation VVIN1 = 3V to 42V 0.01 %/V Peak Current Limit 4.2 4.8 5.4 A Power FET On-resistance Main Switch (Top) Synchronous Switch (Bottom) ISW1, ISW2 = 0.1A ISW1, ISW2 = 0.1A 210 110 mΩ mΩ EN/UVLO Threshold EN/UVLO Falling l 0.78 0.8 0.82 V EN/UVLO Hysteresis 100 mV EN/UVLO Input Current VEN/UVLO = 42V –250 0 250 nA EN2 Threshold EN2 Falling l 0.78 0.81 0.84 V EN2 Hysteresis 50 mV EN2 Input Current VEN2 = 42V –250 0 250 nA Pgood Upper Threshold Offset from VFB1, VFB2 VFB1, VFB2 Rising l 4.5 7.5 10 % Pgood Lower Threshold Offset from VFB1, VFB2 VFB1, VFB2 Falling l –10 –7.5 –4.5 % Pgood Hysteresis 1.2 % Pgood Leakage VPG1, VPG2 = 6V –250 0 250 nA Pgood Pull-Down Resistance VPG1, VPG2 = 0.1V 500 1200 Ω TRK/SS1, TRK/SS2 Pull-Up Current VTRK/SS1, VTRK/SS2 = 0V 2 µA Channels 3 to 4 Feedback Reference Voltage l 0.688 0.7 0.712 V Feedback Input Current l –100 0 100 nA VFB3, VFB4 Line Regulation VVIN1 = 3V to 42V 0.01 %/V Peak Current Limit 7 8.2 9.4 A The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN1 = VIN2 = 12V, VIN3 = VIN4 = 5V, fSW = 2MHz unless otherwise specified.

Rev. 0 For more information www.analog.com Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT8685SR is specified over the –40°C to 150°C operating junction temperature range. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125°C. Note the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. Note 3: This IC includes overtemperature protection that is intended to protect the device during overload conditions. Junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature will reduce lifetime. PARAMETER CONDITIONS MIN TYP MAX UNITS Power FET On-resistance Main Switch (Top) Synchronous Switch (Bottom) ISW3, ISW4 = 0.1A ISW3, ISW4 = 0.1A mΩ mΩ EN3, EN4 Threshold EN3, EN4 Falling l 0.78 0.81 0.84 V EN3, EN4 Hysteresis 50 mV EN3, EN4 Input Current VEN3, VEN4 = 42V –250 0 250 nA Pgood Upper Threshold Offset from VFB3, VFB4 VFB3, VFB4 Rising l 4.5 7.5 10 % Pgood Lower Threshold Offset from VFB3, VFB4 VFB3, VFB4 Falling l –10 –7.5 –4.5 % Pgood Hysteresis 1.2 % Pgood Leakage VPG3, VPG4 = 6V –250 0 250 nA Pgood Pull-Down Resistance VPG3, VPG4 = 0.1V 500 1200 Ω TRK/SS3, TRK/SS4 Pull-Up Current VTRK/SS3, VTRK/SS4 = 0V 2 µA The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN1 = VIN2 = 12V, VIN3 = VIN4 = 5V, fSW = 2MHz unless otherwise specified.

Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS HV Channel Efficiency vs Load VOUT = 5V, Burst Mode® Operation HV Channel Efficiency vs Load V OUT = 5V, Pulse Skip Mode LV Channel Efficiency vs Load V OUT = 1.8V, Burst Mode Operation LV Channel Efficiency vs Load V OUT = 1.8V, Pulse Skip Mode HV Channel Efficiency vs Frequency V OUT = 5V, Burst Mode Operation LV Channel Efficiency vs Frequency V OUT = 1.8V, Burst Mode Operation HV Channel Efficiency vs Load CH1 and CH2 Shared V OUT = 5V, Burst Mode Operation LV Channel Efficiency vs Load CH3 and CH4 Shared V OUT = 1.8V, Burst Mode Operation No-Load Supply Current vs Temperature, Burst Mode Operation TA = 25°C. VIN1 = VIN2 = 12V, VIN3 = VIN4 = 3.3V, fSW = 2MHz unless otherwise noted. PVIN = 12V PVIN = 24V LOAD CURRENT (A) 0.001 0.01 0.1 100 EFFICIENCY (%) 8685S G01 LOAD CURRENT (A) 0.0 0.5 1.0 1.5 2.0 2.5 100 EFFICIENCY (%) 8685S G02 PVIN = 12V PVIN = 24V LOAD CURRENT (A) 0.001 0.01 0.1 100 EFFICIENCY (%) 8685S G03 PVIN = 3.3V PVIN = 5V LOAD CURRENT (A) 0.0 1.0 2.0 3.0 100 EFFICIENCY (%) 8685S G04 PVIN = 3.3V PVIN = 5V I LOAD = 1.25A SWITCHING FREQUENCY (MHz) 0.5 1.5 2.5 100 EFFICIENCY (%) 8685S G05 SWITCHING FREQUENCY (MHz) 0.5 1.5 2.5 100 EFFICIENCY (%) 8685S G06 I LOAD = 2A LOAD CURRENT (A) 0.001 0.01 0.1 100 EFFICIENCY (%) 8685S G07 PVIN = 12V PVIN = 24V LOAD CURRENT (A) 0.001 0.01 0.1 100 EFFICIENCY (%) 8685S G08 PVIN = 3.3V PVIN = 5V V OUT1 = 5V V OUT2 = 3.3V V OUT3 = 1.8V V OUT4 = 1.2V TEMPERATURE (°C) –50 100 150 SUPPL Y CURRENT (µA) 8685S G09

Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS HV Channel RDS(ON) vs Temperature LV Channel RDS(ON) vs Temperature Top FET Current Limit vs Duty Cycle Top FET Current Limit vs Temperature Enable Pin Falling Threshold vs Temperature Enable Pin Current vs Voltage and Temperature HV Channel Minimum On-Time vs Temperature HV Channel Minimum Off-Time vs Temperature HV Channel Minimum On-Time vs Temperature, CH1 and CH2 Shared TA = 25°C. VIN1 = VIN2 = 12V, VIN3 = VIN4 = 3.3V, fSW = 2MHz unless otherwise noted. TOP FET BOTTOM FET TEMPERATURE (°C) –50 –25 100 125 150 100 150 200 250 300 350 400 R DS(ON) (mΩ) 8685S G10 TEMPERATURE (°C) –50 –25 100 125 150 100 R DS(ON) (mΩ) 8685S G11 TOP FET BOTTOM FET HV CHANNEL LV CHANNEL DUTY CYCLE (%) 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 CURRENT LIMIT (A) 8685S G12 HV CHANNEL LV CHANNEL TEMPERATURE (°C) –50 –25 100 125 150 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 CURRENT LIMIT (A) 8685S G13 EN/UVLO (CH1) EN2, EN3, EN4 TEMPERATURE (°C) –50 –25 100 125 150 780 784 788 792 796 800 804 808 812 816 820 FALLING THRESHOLD (mV) 8685S G14 150°C 125°C 25°C VOL TAGE (V) PIN INPUT CURRENT (nA) 8685S G15 I LOAD = 1.5A TEMPERATURE (°C) –50 –25 100 125 150 MINIMUM ON-TIME (ns) 8685S G16 I LOAD = 1A TEMPERATURE (°C) –50 –25 100 125 150 MINIMUM OFF-TIME (ns) 8685S G17 TEMPERATURE (°C) –50 –25 100 125 150 MINIMUM ON-TIME (ns) 8685S G18 I LOAD = 1.5A

Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS HV Channel Minimum Off-Time vs Temperature, CH1 and CH2 Shared LV Channel Minimum On-Time vs Temperature LV Channel Minimum On-Time vs Temperature, CH3 and CH4 Shared Reference Voltage Variation vs Temperature HV Channel Load Regulation LV Channel Load Regulation Switching Frequency vs Temperature HV Channel Switching Frequency vs Load, R T = 22.6kΩ LV Channel Switching Frequency vs Load, R T = 22.6kΩ TA = 25°C. VIN1 = VIN2 = 12V, VIN3 = VIN4 = 3.3V, fSW = 2MHz unless otherwise noted. TEMPERATURE (°C) –50 –25 100 125 150 MINIMUM OFF-TIME (ns) 8685S G19 I LOAD = 1.2A TEMPERATURE (°C) –50 –25 100 125 150 MINIMUM ON-TIME (ns) 8685S G20 I LOAD = 1A TEMPERATURE (°C) –50 –25 100 125 150 MINIMUM ON-TIME (ns) 8685S G21 I LOAD = 2A TEMPERATURE (°C) –50 100 150 –1.25 –1.00 –0.75 –0.50 –0.25 0.25 0.50 0.75 1.00 1.25 DEVIATION (%) 8685S G22 P VIN = 12V LOAD CURRENT (A) 0.5 1.5 2.5 –1.5 –1.0 –0.5 0.5 1.0 1.5 CHANGE IN V OUT (%) 8685S G23 LOAD CURRENT (A) –1.5 –1.0 –0.5 0.5 1.0 1.5 CHANGE IN V OUT (%) 8685S G24 P VIN = 5V 350kHz 2MHz 3MHz TEMPERATURE (°C) –50 –25 100 125 150 –10 VARIATION (%) 8685S G25 VIN = 12V V OUT = 5V L = 1.5µH Burst Mode OPERATION PULSE SKIP MODE LOAD CURRENT (A) 0.0001 0.001 0.01 0.1 0.001 0.01 0.1 SWITCHING FREQUENCY (MHz) 8685S G26 LOAD CURRENT (A) 0.0001 0.001 0.01 0.1 0.001 0.01 0.1 SWITCHING FREQUENCY (MHz) 8685S G27 VIN = 5V V OUT = 1.8V L = 0.40µH Burst Mode OPERATION PULSE SKIP MODE

Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Switching Waveform Continuous Full Frequency Operation Switching Waveform Burst Mode Operation Switching Waveform Pulse Skipping Operation HV Channel Load Step LV Channel Load Step TA = 25°C. VIN1 = VIN2 = 12V, VIN3 = VIN4 = 3.3V, fSW = 2MHz unless otherwise noted. 12V IN TO 5V OUT AT 1A SYNC_MODE = GND 2µs/DIV V SW 5V/DIV I L 1A/DIV 8685S G28 12V IN TO 5V OUT AT 20mA SYNC_MODE = GND 1µs/DIV V SW 5V/DIV I L 200mA/DIV 8685S G29 12V IN TO 5V OUT AT 20mA SYNC_MODE = FLOATING 1µs/DIV V SW 5V/DIV I L 200mA/DIV 8685S G30 1.25A TO 2.25A STEP OUT C OUT = 47µF Burst Mode, f SW = 2MHz 50µs/DIV V OUT 200mV/DIV I LOAD 1A/DIV 8685S G31 1A TO 3A STEP 1.8V OUT C OUT = 47µF ×2 Burst Mode, f SW = 2MHz 50µs/DIV V OUT 200mV/DIV I LOAD 1A/DIV 8685S G32

Rev. 0For more information www.analog.com Conducted EMI Performance TYPICAL PERFORMANCE CHARACTERISTICS Radiated EMI Performance – Vertical Polarization (CISPR25 Radiated Emission Test with Class 5 Peak Limits) Radiated EMI Performance – Horizontal Polarization (CISPR25 Radiated Emission Test with Class 5 Peak Limits) TA = 25°C. VIN1 = VIN2 = 12V, VIN3 = VIN4 = 3.3V, fSW = 2MHz unless otherwise noted. EVAL-L T8685S DEMO BOARD (WITH EMI FIL TER INSTALLED) VEMI = 14V , V OUT1 = 5V , V OUT2 = 3.3V , V OUT3 = 1.8V , V OUT4 = 1.2V I OUT1 = I VIN3 + I VIN4 + I BIAS , I OUT2 = 1A, I OUT3 = I OUT4 = 4A, f SW = 2MHz CLASS 5 PEAK LIMIT SPREAD SPECTRUM MODE FIXED FREQUENCY MODE FREQUENCY (MHz) –20 –10 AMPLITUDE (dBµV) 8685S G33 EVAL-L T8685S DEMO BOARD (WITH EMI FIL TER INSTALLED) VEMI = 14V , V OUT1 = 5V , V OUT2 = 3.3V , V OUT3 = 1.8V , V OUT4 = 1.2V I OUT1 = I VIN3 + I VIN4 + I BIAS , I OUT2 = 1A, I OUT3 = I OUT4 = 4A, f SW = 2MHz FREQUENCY (MHz) 100 200 300 400 500 600 700 800 900 1000 –10 AMPLITUDE (dBµV/m) 8685S G34 CLASS 5 PEAK LIMIT SPREAD SPECTRUM MODE FIXED FREQUENCY MODE EVAL-L T8685S DEMO BOARD (WITH EMI FIL TER INSTALLED) VEMI = 14V , V OUT1 = 5V , V OUT2 = 3.3V , V OUT3 = 1.8V , V OUT4 = 1.2V I OUT1 = I VIN3 + I VIN4 + I BIAS , I OUT2 = 1A, I OUT3 = I OUT4 = 4A, f SW = 2MHz FREQUENCY (MHz) 100 200 300 400 500 600 700 800 900 1000 –10 AMPLITUDE (dBµV/m) 8685S G35 CLASS 5 PEAK LIMIT SPREAD SPECTRUM MODE FIXED FREQUENCY MODE

Rev. 0 For more information www.analog.com PIN FUNCTIONS VIN1 (Pin 1): Channel 1 and Internal INTV CC Regulator Power Supply Input. This pin should be closely decou - pled to ground with a low ESR capacitor of value 2.2µF or greater. VIN2 (Pin 2): Channel 2 Power Supply Input. This pin should be closely decoupled to ground with a low ESR capacitor of value 2.2µF or greater . This pin must be shorted to V IN1 when channel 2 is combined with channel 1. SYNC/MODE (Pin 4): Mode Selection and External Synchronization Input Pin. This pin places all active LT8685S channels into high efficiency Burst Mode oper- ation when tied to ground. Tie this pin to ground with a 26k (5% tolerance or better) resistor to enable high efficiency Burst Mode with spread spectrum modula - tion. Float this pin to enable pulse-skipping mode. Tie this pin to INTV CC to enable pulse-skipping mode with spread-spectrum modulation. When this pin is driven by an external clock source, the LT8685S will synchronize its switching frequency to that of the external clock and operate in pulse-skipping mode. Channels 1 to 4 clock phases default to 0° , 180°, 270°, and 90° respectively when operating independently. When combining chan - nels, the master channel determines the operating phase. See the Applications Information section for more detail. RT (Pin 5): Switching Frequency Program Pin. Connect an external resistor from this pin to ground to program the LT8685S switching frequency from 350kHz to 3MHz. When using external clock synchronization, an RT resistor must be selected to match the nominal incoming clock frequency. See the Applications Information section for more detail. V IN3 (Pins 7, 8): Channel 3 Power Supply Input. When driven from another LT8685S channel, the required decoupling capacitance for this pin is largely satisfied by the output capacitance of the driving channel. In this sce- nario, a low ESR capacitor of value 1µF or greater located close to the V IN3 pin is generally sufficient. If driven from an external source, this pin should be closely decoupled with a low ESR capacitor of value 4.7µF or greater . V IN4 (Pins 9, 10): Channel 4 Power Supply Input. When driven from another LT8685S channel, the required decoupling capacitance for this pin is largely satisfied by the output capacitance of the driving channel. In this sce- nario, a low ESR capacitor of value 1µF or greater located close to the V IN4 pin is generally sufficient. If driven from an external source, this pin should be closely decoupled with a low ESR capacitor of value 4.7µF or greater . This pin must be shorted to V IN3 when channel 4 is combined with channel 3. FB3 (Pin 11): Channel 3 Output Voltage Feedback Pin. Channel 3 regulates this pin to a precision, internal, 0.7V reference voltage. Connect this pin to the appropriate resistor divider network to program the desired output voltage. FB4 (Pin 13): Channel 4 Output Voltage Feedback Pin. Channel 4 regulates this pin to a precision, internal, 0.7V reference voltage. Connect this pin to the appropriate resistor divider network to program the desired output voltage. When this pin is tied to INTVCC, channel 4 is com- bined with channel 3 to create a single output channel with increased output current capability. See the Applications Information section for more detail. INTVCC (Pin 24): Internal Regulator Output Pin. This regu- lator provides the supply current for the power FET driver circuits and internal control circuitry. This pin should be decoupled to ground with a low ESR ceramic capacitor of value 4.7µF. This capacitor should be placed close to the INTV CC pin with a low impedance connection to the exposed pad ground. This supply is not intended as a power supply output. Do not connect external circuitry to this pin. BIAS (Pin 25): External Regulator Input Pin. The inter - nal regulator , INTVCC, will draw current from this supply instead of VIN1 when BIAS is tied to a voltage higher than 4.5V and V VIN1 is greater than V BIAS + 1V. Connecting this pin to a high efficiency supply, such as an LT8685S output channel regulating to 5V, improves overall effi - ciency by reducing the on-chip power consumption that would normally result when drawing current from V IN1. When used, this pin should be decoupled to ground with

Rev. 0For more information www.analog.com PIN FUNCTIONS a low ESR ceramic capacitor of value 0.1µF or greater . When driven by another LT8685S channel, the required decoupling capacitance may be satisfied with the output capacitance of the driving channel. When not used, tie this pin to ground. SW1, SW2, SW3, SW4 (Pin 29, Pin 28, Pins 19 - 20, Pins 17 - 18): Channel Switch Pins. These pins are the outputs of each corresponding channel’s internal power switches. When channels are operating independently, connect each SW pin to the corresponding channel’s inductor and boost capacitor . When combining channels, tie the combined channel’s SW pins together with a low impedance connection. SW traces on the PCB should be kept short for best efficiency and EMI performance. BST1, BST2, BST3, BST4 (Pin 30, Pin 27, Pin 21, Pin 16): Channel Boost Pins. These pins provide a drive volt- age, higher than the supply voltage, to the gate of each channel’s top power switch. PG1 , PG2, PG3, PG4 (Pin 31, Pin 26, Pin 22, Pin 15): Open-Drain Power Good Output Pins. Each channel’s PG pin is pulled to ground when the voltage at the corre - sponding FB pin is not within ±7.5% of the internal refer- ence. PG becomes high impedance once the voltage at the corresponding FB pin returns to within ±6% of the internal reference. PG outputs for enabled channels are valid for V IN1 voltages greater than 3V. PG outputs are pulled low for channels which are not enabled. When channels are combined, the dependent (slave) channel’s PG pin should be open. TRK/SS1, TRK/SS2, TRK/SS3, TRK/SS4 (Pin 32, Pin 3, Pin 23, Pin 6): Output T racking and Soft-Start Pins. These pins allow user control of output voltage ramp rate during startup. A TRK/SSx voltage below the internal reference forces the channel to regulate the FBx pin to equal the TRK/SSx voltage. When TRK/SSx is above internal ref - erence, the tracking function is disabled and the internal reference resumes control of the error amplifier . An inter- nal 2μA pull-up current from INT VCC on this pin allows a capacitor to program output voltage slew rate. When channels are combined, the dependent (slave) channel’s TRK/SS pin should be open. EN/UVLO (Pin 33): Channel 1 Enable and Undervoltage Lockout Pin. The LT8685S is in low power shutdown when this pin is below 0.4V regardless of the state of the remaining LT8685S enable pins. A voltage above 0.9V (rising) enables LT8685S operation and channel 1. A pre- cision threshold at 0.8V (falling) allows this pin to be used as an input undervoltage lockout by connecting a resistor divider between VIN1 and ground. FB1 (Pin 34): Channel 1 Output Voltage Feedback Pin. Channel 1 regulates this pin to a precision, internal, 0.8V reference voltage. Connect this pin to the appropriate resistor divider network to program the desired output voltage. EN2, EN3, EN4 (Pin 35, Pin 12, Pin 14): Channel Enable Pins. Each LT8685S channel is active when the voltage on its corresponding enable pin is above 0.9V (rising). A precision threshold at 0.81V (falling) allows each enable pin to act as a programmable undervoltage lockout by connecting a resistor divider between the correspond - ing input supply and ground. When channels are com - bined, the dependent (slave) channel’s EN pin should be connected to the enable pin of the controlling (master) channel. FB2 (Pin 36): Channel 2 Output Voltage Feedback Pin. Channel 2 regulates this pin to a precision, internal, 0.8V reference voltage. Connect this pin to the appropriate resistor divider network to program the desired output voltage. When this pin is tied to INTVCC, channel 2 is com- bined with channel 1 to create a single output channel with increased output current capability. See the Application Section for more detail. GND (Exposed Pad Pins 37 - 40): Ground Pins. These pins must be soldered to the PCB to provide low imped- ance electrical contact to ground and good thermal con- tact to the PCB. See the Applications Information section for more detail. CORNER PINS: These pins are for mechanical support only and can be tied anywhere on the PCB, typically ground.

Rev. 0 For more information www.analog.com BLOCK DIAGRAM 8685S BD REFERENCE INTVCC REGULATOR BIASVIN1 EN/UVLO BST1 VIN1 ILIM1 ILIM1 ILIM2 LOGIC 1 LOGIC 2 CURRENT SENSE COMPARATOR REVERSE CURRENT COMPARATOR INTVCC LOOP COMPENSATION LOOP COMPENSATION LOOP COMPENSATION LOOP COMPENSATION SW1 GND TRK/SS1 FB1 PG1 SYNC/MODE EN3 BST3 VIN3 SW3 GND TRK/SS3 FB3 PG3 EN2 INTVCC BST2 VIN2 SW2 GND TRK/SS2 FB2 PG2 RT EN4 BST4 VIN4 SW4 GND TRK/SS4 FB4 PG4 0.75V 0.65V 0.7V 2/uni03BCA ILIM3INTVCC DRIVER LOGIC 3 LOGIC 4 CURRENT SENSE COMPARATOR REVERSE CURRENT COMPARATOR DRIVER CURRENT SENSE COMPARATOR REVERSE CURRENT COMPARATOR DRIVER CURRENT SENSE COMPARATOR REVERSE CURRENT COMPARATOR DRIVER ILIM3 0.81V 0.86V 0.74V CLK1 CLK2 CLK3 CLK4 OSCILLATOR 0.8V 2/uni03BCA 0.8V 0.75V 0.65V 0.7V 2/uni03BCA INTVCCILIM4 ILIM4 0.81V 0.1/uni03BCF 0.86V 0.74V 0.8V 2/uni03BCA INTVCC 0.81V 0.01/uni03BCF ILIM2 0.1/uni03BCF 0.01/uni03BCF

Rev. 0For more information www.analog.com OPERATION The LT8685S is a 42V input capable quad, monolithic, step-down regulator which incorporates Analog Device’s 2nd generation Silent Switcher technology to allow fast switching edges for high efficiency at high switching fre- quency, while simultaneously achieving good EMI/EMC performance. Channels 1 and 2 are designed to provide output currents up to 2.5A each from an input supply voltage as high as 42V. Channels 3 and 4 are designed to provide output currents up to 4A each from an input supply voltage as high as 8V. Higher output currents can be achieved by combining channels with a single inductor . For example, channels 1 and 2 can be combined using a single inductor to provide a regulated output up to 5A. Channels 3 and 4 can be combined using a single inductor to provide a regulated output up to 8A. Independent V IN pins allow for the output of one channel to supply the input of the other channels. START-UP When enabled by setting the EN/UVLO voltage above its threshold, the LT8685S INTVCC regulator charges its out- put capacitor to supply the internal chip circuitry. Setting the EN/UVLO above 0.9V (rising) will enable the channel 1 regulator . Setting the EN/UVLO voltage below the UVLO threshold will put the part in low power shutdown mode regardless of the state of the other enable pins. Channels 2, 3 and 4 are enabled by setting their respec - tive enable pins above 0.9V (rising). When combining channels, connect the enable pin of the slave channel to that of the controlling channel. See Combining Channels in the Applications Information section for further detail. BUCK REGULATOR OPERATION Each channel is a monolithic, synchronous step-down regulator that operates from an independent VIN pin. The internal top power MOSFET is turned on at the beginning of each oscillator cycle and turned off when the current flowing through the top MOSFET reaches a level deter - mined by the error amplifier . The error amplifier measures the output voltage through an external resistor divider tied to the FB pin to control the peak current in the top switch. The reference of the error amplifier is determined by the lower of the internal reference and the voltage at its soft-start (TRK/SSx) pin. While the top MOSFET is off, the bottom MOSFET is turned on for the remainder of the oscillator cycle or until the inductor current starts to reverse. In current overload conditions the bottom MOSFET will remain on and the next clock cycle will be delayed until the switch current is reduced. PRECISION ENABLE PINS When driven below 0.4V, the EN/UVLO pin will place the LT8685S into low power shutdown mode. A voltage on the EN/UVLO pin above 0.9V (rising) will enable channel 1 operation. Channels 2, 3 and 4 are also activated by driv- ing their respective EN2, EN3 and EN4 pins above 0.9V (rising). A precision threshold of 0.8V (falling) allows the EN/UVLO to be used as an input undervoltage lockout by connecting a resistor divider between V IN1 and ground. Similarly, a precision threshold of 0.81V allows EN2, EN3, and EN4 to also be used as input undervoltage lockouts. See the Applications Information section for more detail. POWER GOOD COMPARATORS Each channel has a power good comparator with an open- drain output that pulls its PG pin low when its feedback voltage is more than 7.5% above or below the reference voltage. The PG pin is released when the feedback pin is within 6% of the reference voltage. The PG outputs are not valid until INTV CC rises to 2.7V. SWITCHING FREQUENCY Each channel operates from a clock provided by an internal oscillator whose frequency is determined by an external resistor connected from the RT pin to ground. By selecting the appropriate external resistor value, the switching frequency may be configured from 350kHz to 3MHz. See the Applications Information section for fur - ther frequency selection information. The oscillator generates four clock phases. When operat- ing independently, the relative phases of the channels are

grammed frequency plus approximately 20%. width is 100ns for a high pulse and 100ns for a low pulse. ping mode while synchronized to an external clock. The INTVCC regulator supplies internal LT8685S circuitry. LT8685S to avoid unexpected interactions. between the VIN1 input supply pin and the EN/UVLO pin. less of the state of EN2, EN3, and EN4 pins. The LT8685S UVLO divider circuit is shown in Figure 1.

• 0.8V

Figure 1. LT8685S UVLO Resistor Divider Connection

Rev. 0For more information www.analog.com APPLICATIONS INFORMATION The maximum duty cycle achievable at a given operating frequency is calculated as: DMAX = 1 – (tOFF(MIN) • fSW) Combining these equations, the minimum V IN voltage while regulating at full frequency is VVINx(MIN)= VOUTx 1– tOFF(MIN) • fSW( ) Below VVINx(MIN) the buck regulator will enter dropout, and the top switch will stay on longer than a clock cycle. While operating in dropout, the buck regulator’s output voltage will be below the programmed value. The maximum V IN voltage while regulating at full fre - quency is VVINx(MAX)= VOUTx tON(MIN) • fSW If the V VINx(MAX) given above is exceeded during regu - lation, the buck regulator will skip switch-on cycles to maintain regulation. Inductor Selection For a given input and output voltage, the inductor value and operating frequency determine the inductor ripple current. More specifically, the inductor ripple current decreases with higher inductor value or higher operating frequency according to the following equation: ΔIL = VOUT fSW •L ⎟ 1– VOUT VIN where ΔIL = inductor ripple current (A), f SW = switching frequency (Hz), L = inductor value (H), and V IN is the nominal input voltage rating. A trade-off between compo- nent size, efficiency and operating frequency can be seen from this equation. Accepting larger values of ΔIL allows the use of lower value inductors but results in greater core loss in the inductor , greater ESR loss in the output capacitor , and larger output ripple. The inductor value should be chosen to give a peak-to- peak ripple current ΔI L of between 35% and 45% of the rated channel output current at the nominal input voltage. Note, the rated channel output current is 2.5A for chan - nels 1 and 2, and 4A for channels 3 and 4. Channels 1 and 2 have a rating of 5A when combined, and channels 3 and 4 have a rating of 8A when combined. Rearranging the equation above, select the inductor value according to: L = VOUT fSW •ΔIL ⎟ 1– VOUT VIN To avoid overheating and poor efficiency, an inductor must be chosen with an RMS current rating that is greater than the maximum expected output load of the applica - tion. In addition, for best efficiency the inductor series resistance should be as small as possible, and the core material should be intended for the application switching frequency. The saturation current rating of the inductor must be higher than the load plus half the ripple current. This peak inductor current can be computed per the following equation: IL(PEAK) = IOUT(MAX) + ΔIL where I OUT(MAX) is the maximum output current for a given application. The optimum inductor for a given application may differ from the one indicated by this design guide. Careful eval- uation of the application circuit should be completed with the chosen inductor to ensure adequate design margin. Input Capacitor Selection Buck, or step-down, converters draw current from the input supply in pulses with very fast rise and fall times. An input capacitor is required to reduce the resultant voltage ripple at the input and minimize EMI. For this function, a ceramic X7R or X5R bypass capacitor should be placed between each buck regulator’s V IN pin and ground. To be most effective, the input capacitor must have low imped- ance at the switching frequency and an adequate ripple current rating.

Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION The worst-case ripple current occurs when VOUT is one- half VIN. Under this condition, the ripple current is: ICIN(RMS) = IOUT Reasonable starting values for the input capacitance are 2.2µF for channels 1 and 2 and 2.2µF for channels 3 and 4. When combining channels, the shared channel V IN pins must be connected together , and the input capacitor should be chosen based on the total current supplied by the combined channels. Output Capacitor Selection The output capacitor performs two functions. First, it filters the inductor current to generate an output with low voltage ripple. Second, it stores energy to minimize droop and overshoot during transient loads. Because the LT8685S buck converters are able to operate at a high frequency, required output capacitance is minimal. The internally compensated current mode control loops are stable without requiring a minimum series resistance (ESR) in the output capacitor . Therefore, ceramic capaci- tors may be used and will result in very low output ripple. An estimate for the output ripple is as follows for a given capacitor type: VRIPPLE = ΔIL 8 • fSW • COUT for ceramic capacitors, and VRIPPLE= ΔIL • ESR for aluminum or tantalum capacitors. VRIPPLE is the peak- to-peak output ripple, f SW is the switching frequency in MHz, ΔIL is the peak-to-peak ripple current in the inductor , COUT is the output capacitor value in µF and ESR is the output capacitor effective series resistance. The low ESR and small size of ceramic capacitors make them the preferred type for LT8685S applications. However , not all ceramic capacitors are the same. Many of the higher value capacitors use dielectrics with high temperature and voltage coefficients. Y5V and Z5U types lose a large fraction of their capacitance with applied volt- age and at temperature extremes. Because loop stability, transient response ripple and EMI depend on the value of the input and output capacitors, it is best to use X5R (max 85°C), X7R (max 125°C) or X8R (max 150°C) capacitors depending on the operating temperature range. Electrolytic capacitors are also an option. The ESRs of most aluminum electrolytic capacitors are too large to deliver low output ripple. Tantalum, as well as newer , lower ESR organic electrolytic capacitors intended for power supply use are suitable. Choose a capacitor with a low enough ESR for the required output ripple. Because the volume of the capacitor determines its ESR, both the size and value will be larger than a ceramic capacitor that would give similar ripple performance. The Typical Applications section provides a reasonable starting point for output capacitor values. Careful evalua- tion of each application must be made to ensure adequate design margin. Boost Capacitor Selection Connecting a capacitor between each channel’s BST and SW pins creates an internal approximately 3.4V supply used to drive the internal power devices. For most applica- tions, choosing a 0.1μF ceramic capacitor for this function works well. Although the SW and BST pins of combined channels are connected at the board level to drive a single inductor , for robust operation, each of the combined channels must have its own boost capacitor connected between their respective BST and SW pins. Output Voltage T racking and Soft-Start The LT8685S’ s programmable channel soft-start fea - ture, which controls the output voltage ramp time during startup, combined with channel power good (PG) and enable (EN) functions, supports flexible startup sequenc- ing and control. In addition, the soft-start feature can be used to reduce input surge current and prevent out - put voltage overshoot. To program the output voltage

Rev. 0For more information www.analog.com APPLICATIONS INFORMATION soft-start time, connect a capacitor between the channel’s TRK/SS pin and ground according to: tSS = CSS • VREF 2µA where 2µA is the TRK/SS pull-up current, CSS is the value of the capacitor in Farads, and VREF is 0.8V for CH1 and CH2, 0.7V for CH3 and CH4. The channel TRK/SSx pins are pulled down through approximately 300kΩ, which will discharge the external soft-start capacitor when the part is shut down or during certain fault conditions. For output voltage tracking, the channel TRK/SS pin can be driven by an external voltage source. More specifically, when driven with a voltage between 0V and the internal reference level, the TRK/SS pin will override the internal reference input to the error amplifier thus regulating the FB voltage to that present on the TRK/SS pin. When TRK/ SS is above the reference level, tracking is disabled, and the feedback voltage will regulate to the internal reference voltage. When combining channels, slave channel TRK/SS pins should be open. Power Good Comparators Each LT8685S channel has a power good comparator with an open drain output pin, PGx. Each PG pin is pulled low when the corresponding feedback voltage is either above or below its reference voltage by more than 7.5%. See the Electrical Characteristics table for more information on each channel’s power good thresholds. All PG pins will be pulled low when the part is shut down. Individual channel PG pins will be pulled low when their corresponding EN pin is low. When combining channels, only the master channel PG pins are valid. Slave PG pins should be open. PCB LAYOUT The LT8685S is specifically designed to minimize EMI/ EMC emissions and to maximize efficiency when switch- ing at high frequencies. For proper operation and minimum EMI, care must be taken during printed circuit board layout. A recommended board layout is available with the latest LT8685S demo board. Some general guidelines are available in the remainder of this section. Place a local, unbroken ground plane under the application circuit on the layer closest to the surface layer and con - nect the exposed GND pad to this layer . The exposed pad ground connection should be made with the maximum number of vias possible to reduce thermal and electrical impedance to the board ground. For best performance, maximize unbroken board ground planes in the vicinity of the LT8685S. The SW and BST nodes should be made as small as possible to minimize noise coupling to sensitive traces. Minimize traces connecting to the RT and all FB pins and provide ground shielding as needed to minimize noise coupling to these sensitive nodes. For each buck regulator , place input bypass capacitors close to the V INx pins with a low impedance connection to the exposed pad through the ground plane mentioned above. The recommended layer use for a 4-layer board is: Layer 1 (Components): use 2oz (70µm) copper . Unbroken high frequency/high current routing, including SW and BST node routing, plus inductor , input, and output capac- itor placement. Ground fill on the remainder . Layer 2 (Internal): Unbroken ground plane. Layer 3 (Internal): Signal routing with ground plane on remainder . Layer 4 (Bottom): Use 2oz (70µm) copper . Use for remain- ing signal routing with ground fill on the remainder . THERMAL CONSIDERATIONS The exposed pad is the path for conducting heat from the silicon die to the PC board and the surrounding air . For good heat conduction, thermal vias should be placed under the device to conduct heat down to internal ground planes and the back side of the board. Multiple small vias work better than a few large ones as the copper plating of

tribute heat over a large area. with the maximum application ambient temperature. Figure 5. Maximum Loss vs Ambient Temperature production tested and is intended as a failsafe only.

Rev. 0For more information www.analog.com TYPICAL APPLICATIONS 42V Input, Quad Output 2MHz Step-Down Regulator with Spread Spectrum and Ratiometric Output Start-Up (Details of Front Page Application) Startup Sequence 4.7µF 4.7µF 4.7µF 2.2µF 0.1µF 0.1µF 47µF 191k 3.3pF 0.1µF 0.40µH 100µF 634k 3.3pF 0.1µF 0.30µH 665k 100µF 931k 10pF 26.1k 22.6k 0.1µF 1.2µH 976k 47µF 309k 3.3pF 1.5µH 10nF 10nF BST3 SW3 FB3 BST4 SW4 FB4 BIAS BST1 SW1 FB1 BST2 SW2 FB2 EN/UVLO EN2 VIN1 VIN2 EN3 EN4 VIN3 VIN4 6V TO 42V PG4 PG3 PG2 PG1 TRK/SS4 TRK/SS3 TRK/SS2 TRK/SS1 RT SYNC/MODE OUT1 5V , 2.5A* INTVCC OUT4 1.2V , 4A VIN OUT3 1.8V , 4A GND OUT2 3.3V , 2.5A L T8685S OUT1 *CURRENT AVAILABLE FROM OUT1: **INDUCTOR VALUES CHOSEN FOR VIN = 12V 2.5A – I VIN3 – I VIN4 – I BIAS 8685S TA02a STARTUP SEQUENCE: VIN HIGH ENABLES HV CHANNELS HV CHANNELS TRACK RATIOMETRICALL Y V OUT1 HIGH ENABLES LV CHANNELS LV CHANNELS TRACK RATIOMETRICALL Y 1ms/DIV VIN 10V/DIV V OUT1 2V/DIV V OUT2 2V/DIV V OUT3 1V/DIV V OUT4 1V/DIV 8685S TA02b

Rev. 0 For more information www.analog.com TYPICAL APPLICATIONS 2.2µF 2.2µF 4.7µF 0.1µF 0.1µF 31.6k 47µF 10.2k 0.1µF 0.1µH 100µF ×3 0.1µF 22.6k 0.8µH 12.7k 100µF 10.2k 1.2µH 4.7µF 499k 499k 499k 10nF 10nF 10nF BST3 SW3 FB3 BST4 SW4 FB4 BIAS BST1 SW1 FB1 BST2 SW2 FB2 EN/UVLO EN2 VIN1 VIN2 VIN3 VIN4 4V TO 42V TRK/SS4 TRK/SS3 TRK/SS2 TRK/SS1 RT SYNC/MODE OUT1 3.3V , 2.5A* VIN OUT3 0.7V , 8A GND OUT2 1.8V , 2.5A L T8685S INTVCC EN3 PG4 PG3 PG2 PG1 INTVCC EN4 *CURRENT AVAILABLE FROM OUT1: 2.5A – I VIN3 – I VIN4 OUT1 8685S TA03a INDUCTOR VALUES CHOSEN FOR VIN = 12V STARTUP SEQUENCE: VIN HIGH ENABLES OUT1 V OUT1 IN REGULATION ENABLES OUT3,4 V OUT3,4 IN REGULATION ENABLES OUT2 2ms/DIV VIN 10V/DIV V OUT1 2V/DIV V OUT3,4 1V/DIV V OUT2 1V/DIV 8685S TA03b Startup Sequencing Startup Sequencing Compact Microcontroller Power Supply with Supply Sequencing High Efficiency Quad Output Regulator Suitable for Driving Multiple LDO’s or Remote Circuitry 4.7µF 4.7µF 4.7µF 0.1µF 0.1µF 47µF 97.6k 2.2pF 0.1µF 2.2µH 787k 100µF ×2 499k 4.7pF 0.1µF 1.2µH 261k 100µF ×2 909k 10pF 133k 0.1µF 8.2µH 953k 47µF 154k 2.2pF 5.6µH** 124k 22nF 22nF 22nF 22nF 499K BST3 SW3 FB3 BST4 SW4 FB4 BIAS BST1 SW1 FB1 BST2 SW2 FB2 EN/UVLO EN2 VIN1 VIN2 EN3 EN4 VIN3 VIN4 10V TO 42V PG4 PG3 PG2 PG1 RT SYNC/MODE OUT1 9V , 2.5A INTVCC OUT4 0.9V , 4A VIN OUT3 1.8V , 4A GND OUT2 5.75V , 2.5A* L T8685S TRK/SS4 TRK/SS3 TRK/SS2 TRK/SS1 *CURRENT AVAIALBLE FROM OUT2: 2.5A – I VIN3 – I VIN4 – I BIAS OUT2 2.2µF 8685S TA04a **INDUCTOR VALUES CHOSEN FOR VIN = 12V STARTUP SEQUENCE: VIN HIGH ENABLES OUT1 AND OUT2 V AND OUT4 OUT2 IN REGULATION ENABLES OUT3 5ms/DIV VIN 10V/DIV V OUT1 5V/DIV V OUT2 5V/DIV V OUT3 1V/DIV V OUT4 1V/DIV 8685S TA04b

Rev. 0For more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION PACKAGE BOTTOM VIEW eb 18 11 0.375 e b SEE NOTES MXY Z ccc 0.40 1.60 1.60 0.40 0.20 0.20 0.40 0.40 2.10 2.10 36-Lead (5mm × 6mm × 0.95mm) (Reference L TC DWG # 05-08-7056 Rev Ø) DETAIL B A PACKAGE TOP VIEW PIN 1 CORNER Y X aaa Z2× E D DETAIL B SUBSTRATE MOLD CAP // bbb Z Z DETAIL C SUGGESTED PCB LAYOUT TOP VIEW 0.000 0.000 0.250 0.750 1.250 2.250 1.750 0.250 1.250 0.750 1.750 2.250 1.750 0.750 0.250 0.250 1.750 1.250 0.750 1.250 aaa Z 2× PACKAGE OUTLINE 0.25 REF 0.375 0.375

0.70 REF

6.50 ±0.05 5.50 ±0.05 LQFN 36 1020 REV Ø TRAY PIN 1 BEVEL PACKAGE IN TRAY LOADING ORIENTATION COMPONENT PIN 1 L TXXXXXX ddd Z 36× SYMBOL A L b D E e aaa bbb ccc ddd eee fff MIN 0.85 0.30 0.22 NOM 0.95 0.40 0.25 5.00 6.00 3.40 4.40 0.50

0.25 REF

1.05 0.04 0.50 0.28 0.10 0.10 0.10 0.10 0.15 0.08 DIMENSIONSZ DETAIL C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. PRIMARY DATUM -Z- IS SEATING PLANE METAL FEATURES UNDER THE SOLDER MASK OPENING NOT SHOWN SO AS NOT TO OBSCURE THESE TERMINALS AND HEAT FEATURES DETAILS OF PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN 1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE NOTES SUBSTRATE THK MOLD CAP HT DETAIL A SEE NOTES 29 36M X Y Z ccc PIN 1 NOTCH 0.23 × 45°1 36b e DETAIL A M X Y Z eee M Zfff L e/2

6 THE EXPOSED HEAT FEATURE IS SEGMENTED AND ARRANGED

IN A MATRIX FORMAT . IT MAY HAVE OPTIONAL CORNER RADII ON EACH SEGMENT

7 CORNER SUPPORT PAD CHAMFER IS OPTIONAL

1.60 1.60 2.10 2.10 0.35 0.35 0.35 0.35 0.20 0.20

Rev. 0 For more information www.analog.com  ANALOG DEVICES, INC. 2022 www.analog.com RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LT8601 42V, 94% Efficiency, 2.2MHz T riple Output (1.5A + 2.5A + 1.8A) Synchronous Micropower Step-Down DC/DC Converter with IQ = 30μA VIN: 3V to 42V, VOUT(MIN) = 0.8V, IQ = 30µA, ISD < 25µA, 6mm × 6mm QFN-40 Package LT8602 42V, Quad Output (2.5A + 1.5A + 1.5A + 1.5A) 95% Efficiency , 2.2MHz Synchronous Micropower Step-Down DC/DC Converter with IQ = 25µA VIN: 3V to 42V, VOUT(MIN) = 0.8V, IQ = 25µA, ISD < 25µA, 6mm × 6mm QFN-40 Package LT8603 42V, Low IQ, Quad Output T riple Monolithic Buck Converter and Boost Controller VIN: 3V to 42V, VOUT(MIN) = 0.8V, IQ = 25µA, ISD < 25µA, 6mm × 6mm QFN-40 Package Startup Sequencing T riple Output, 3MHz Step-Down Regulator with Sequenced Ratiometric Start-Up 1A LOAD PER OUTPUT STARTUP SEQUENCE: VIN HIGH ENABLES OUT1,2 V OUT1,2 IN REGULATION ENABLES OUT3 AND OUT4 V OUT3 AND V OUT4 SOFT-START RATIOMETRICALL Y 2ms/DIV VIN 10V/DIV V OUT1,2 5V/DIV V OUT3 2V/DIV V OUT4 2V/DIV 8685S TA05b 2.2µF 2.2µF 4.7µF 1µF 499k 0.1µF 0.1µF 0.68µH** 953k 47µF 105k 2.2pF 0.1µF 0.47µH 976k 47µF 261k 2.2pF 0.1µF 0.33µH 787k 100µF 499k 3.3pF 499k 499k 10nF 10nF 13.7k 0.1µF BST3 SW3 FB3 BST4 SW4 FB4 BIAS BST1 SW1 FB1 BST2 SW2 FB2 EN/UVLO EN2 VIN1 VIN2 EN3 EN4 VIN3 VIN4 9V TO 42V PG4 PG3 PG2 PG1 TRK/SS4 TRK/SS3 TRK/SS2 TRK/SS1 RT SYNC/MODE OUT1 8V , 5A* INTVCC OUT4 1.8V , 4A VIN INTVCC OUT3 3.3V , 4A GND L T8685S CLK IN 3MHz OUT1 *CURRENT AVAILABLE FROM OUT1: 5A – I VIN3 – I VIN4 – I BIAS **INDUCTOR VALUE CHOSEN FOR VIN = 12V 8685S TA05a