LT8550

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Rev. 0For more information www.analog.comDocument Feedback VIN REG VIN POWER STAGE 1 REG REG REG GND 8550 TA01a ISP ISN TG1 BST1 SW1 BG1 ISP1 ISN1 10/uni03A9 1nF 100µF 47µF 47µF 150µF 10/uni03A9 10/uni03A9 33nF 220pF 10µF 10/uni03A9 0.22µF 1nF SENSEN SENSEP HG CBOOT SW LG 100µF 47µF 47µF 150µF 0.22µF POWER STAGE 2 POWER STAGE 3 POWER STAGE 4 VOUT VOUT VOUT ENOUT CLK1 REGSNS TGSR TGSH TGSLBGSHVIN SHDN REGIS REGDRV REG PHS1 PHS2 ILIM VCC PHS3 SYNC RT/MS IAMPP IAMPN CTRL1 VREF CTRL2 VC RT SS EN/UVLO SYNC VCC_INTGND FB VIN 200k 47k 1/uni03A9 10nF 1nF 22µF 1.3µH 2.5m/uni03A9 1.3µH 2.5m/uni03A9 88.7k 12.1k100k RHOT 45.3k 10k 2.2µF 4.7nF 4.7µF137k 1µF RNTC 680k LT8550 LT3741 PINS FOR POWER STAGE2,3,4 24k 62k 4.7µF 1/uni03A9 PINS NOT SHOWN IN THIS CIRCUIT : ISP2, ISN2, BST2, TG2, SW2, BG2 ISP3, ISN3, BST3, TG3, SW3, BG3 ISP4, ISN4, BST4, TG4, SW4, BG4, CLK2, TGBUF , BGBUF , MODE VIN 14V TO 36V MP VOUT 10V/100A MAX TYPICAL APPLICATION FEATURES DESCRIPTION 4-Phase DC/DC Expander with Internal Gate Drivers for Buck Converters The LT®8550 is a multiphase expander for synchronous buck DC/DC converters. It operates in tandem with any buck DC/DC converter to increase the load current capa- bility by adding additional phases, which are clocked out- of-phase to reduce ripple current and filtering capacitance. It easily adds phases without the need to route sensitive feedback and control signals. The LT8550 integrates gate drivers and can support up to four buck phases per device. Multiple LT8550’s can be used for up to 18 phases. It accurately monitors and adjusts the current of each channel to achieve excellent DC and transient current sharing. The LT8550 operates over a fixed frequency from 100kHz to 1MHz, or can be synchronized to an external clock. All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. Patents, including 9077244. 10V/100A Step-Down Phase Expander System n Expands Up to Four Phases per Chip n Up to 80V Input or Output Voltage n Cascade with Multiple Chips for Very High Current

Applications

n Supports Up to 18 Distinct Phases from 20° to 180° n Phases Can Share Phase Angle n Excellent DC and T ransient Current Sharing n Phase-Lockable Fixed Frequency 125kHz to 1MHz n Supports Bidirectional Current Flow n RSENSE or DCR Current Sensing n Eliminates the Need to Route Sensitive Feedback and Control Signals n 52-Lead (7mm × 8mm) QFN Package n High Current Distributed Power Systems n Telecom, Datacom, and Storage Systems n Industrial and Automotive

Rev. 0 For more information www.analog.com ABSOLUTE MAXIMUM RATINGS ISP1/2/3/4, ISN1/2/3/4, ISP , ISN, VIN, REGIS, REGDRV Voltage (Note 2) ...–0.3V to 80V BG1/2/3/4, RT/MS, SYNC, PHS1/2/3, CLK1/2, REGSNS, IAMPP , ILIM, BGSH, BGBUF, TGBUF, ENOUT, MODE, VCC, REG, (BST-SW)1/2/3/4, (TG-SW)1/2/3/4, (VIN-REGDRV), (TGSR-TGSL), Operating Junction Temperature Range (Note 3) (Note 1) ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8550EUKG#PBF LT8550EUKG#TRPBF 8550 52-PIN (7mm × 8mm) Plastic QFN –40°C to 125°C LT8550IUKG#PBF LT8550IUKG#TRPBF 8550 52-PIN (7mm × 8mm) Plastic QFN –40°C to 125°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. 1615 17 18 19 TOP VIEW GND UKG PACKAGE 52-LEAD (7mm × 8mm) PLASTIC QFN TJMAX = 125°C, θJA = 31°C/W , θJC = 2°C/W EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB 20 21 22 23 24 25 26 5152 50 49 48 47 46 45 44 43 42 41 1BG4 BG3 REG SW3 TG3 BST3 BST2 TG2 SW2 BG2 BG1 BGBUF TGBUF BST1 REGSNS ISN4 ISP4 ISN2 ISP2 ISN ISP IAMPP IAMPN SHDN MODE VCC ENOUT ILIM BST4 TG4 SW4 VIN REGDRV REGIS ISN3 ISP3 ISP1 ISN1 NC PHS3 TG1 SW1 TGSR TGSH TGSL CLK2 CLK1 BGSH SYNC PHS2 PHS1 RT/MS PIN CONFIGURATION

Rev. 0For more information www.analog.com

ELECTRICAL CHARACTERISTICS

PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Operating Voltage Range For Min Spec VCC, REG = 0V l 3.6 80 V VIN Quiescent Current REG = VCC = 5V, REGDRV REGIS Floating 800 µA VIN Quiescent Current in Shutdown 2 µA VCC Quiescent Current Not Switching 5 mA VCC Undervoltage Lockout VCC Falling, REG = VCC l 3.3 3.55 3.8 V VCC Undervoltage Lockout Hysteresis REG = VCC 0.1 V SHDN Input Voltage High SHDN Falling l 1.05 1.15 1.25 V SHDN Input Voltage High Hysteresis 60 mV SHDN Input Voltage Low Device Disabled, Low Quiescent Current, VCC = 3V, REG = 3V l 0.3 V SHDN Pin Bias Current VSHDN = 3V VSHDN = 12V 8.5 µA µA MODE Low Falling Threshold Slave LT8550 l 0.5 V MODE High Rising Threshold Slave LT8550 l 4.5 V MODE Output Voltage Low Master LT8550, 200µA into MODE Pin 50 mV MODE Output Voltage High Master LT8550, 20µA Out of MODE Pin 4.8 V MODE Pin Impedance in Middle State Master LT8550 9 kΩ ENOUT Output Voltage Low Master LT8550, 1mA into ENOUT Pin, VCC, REG in UVLO 60 mV ENOUT Leakage Current ENOUT = 5V, REG, VCC = 3V 0.2 1 µA ENOUT Rising Threshold 2.1 V ENOUT Threshold Hysteresis 0.4 V Current Sensing Maximum Positive Current Sense Voltage, (ISPn-ISNn) ILIM = 0V, ISNn = 12V, ISPn Rising ILIM = REG, ISNn = 12V, ISPn Rising ILIM = Float, ISNn = 12V, ISPn Rising l l l 84.5 32.5 95.5 mV mV mV Maximum Negative Current Sense Voltage, (ISNn-ISPn) ILIM = 0V, ISNn = 12V, ISPn Falling ILIM = REG, ISNn = 12V, ISPn Falling ILIM = Float, ISNn = 12V, ISPn Falling l l l 26.5 55.5 64.5 mV mV mV ISP , ISN Common Mode Operating Voltage Range l 0 80 V ISPn, ISNn Common Mode Operating Voltage Range l 0 80 V ILIM High Rising Threshold l 4.65 V ILIM High Threshold Hysteresis 90 mV ILIM Low Falling Threshold l 0.3 V ILIM Low Threshold Hysteresis 80 mV ILIM Impedance at Floating 11 kΩ IAMPP Output Voltage (ISP-ISN) = 30mV, ILIM = 0V, Master LT8550, ISN = 12V (ISP-ISN) = 0mV, ILIM = 0V, Master LT8550, ISN = 12V (ISP-ISN) = –30mV, ILIM = 0V, Master LT8550, ISN = 12V (ISP-ISN) = 60mV, ILIM = REG, Master LT8550, ISN = 12V (ISP-ISN) = 0mV, ILIM = REG, Master LT8550, ISN = 12V (ISP-ISN) = –60mV, ILIM = REG, Master LT8550, ISN = 12V (ISP-ISN) = 90mV, ILIM = Float, Master LT8550, ISN = 12V (ISP-ISN) = 0mV, ILIM = Float, Master LT8550, ISN = 12V (ISP-ISN) = –90mV, ILIM = Float, Master LT8550, ISN = 12V l l l l l l l l l 2.33 1.33 0.33 2.33 1.35 0.34 2.33 1.35 0.34 2.40 1.40 0.40 2.40 1.40 0.40 2.40 1.40 0.40 2.47 1.47 0.47 2.47 1.45 0.46 2.47 1.45 0.46 V V V V V V V V V The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, REG = 5V, VCC = 5V, SHDN = High, unless otherwise noted.

Rev. 0 For more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS (ISPn-ISNn) Voltage In Regulation IAMPP = 2.20V, IAMPN = 0V, ILIM = 0V, ISNn = 12V IAMPP = 0.60V, IAMPN = 0V, ILIM = 0V, ISNn = 12V IAMPP = 2.20V, IAMPN = 0V, ILIM = REG, ISNn = 12V IAMPP = 0.60V, IAMPN = 0V, ILIM = REG, ISNn = 12V IAMPP = 2.20V, IAMPN = 0V, ILIM = Float, ISNn = 12V IAMPP = 0.60V, IAMPN = 0V, ILIM = Float, ISNn = 12V l l l l l l 21.25 –26.75 45.0 –51.0 67.25 –76.75 26.75 –21.25 51.0 –45.0 76.75 –67.25 mV mV mV mV mV mV (ISP-ISN) to IAMPP Voltage Gain ILIM = 0V, Master LT8550, ISN = 0V ILIM = REG, Master LT8550, ISN = 0V ILIM = FLOAT , Master LT8550, ISN = 0V 33.3 16.7 11.1 IAMPP Sourcing Current Limit (ISP-ISN) = 0mV, Master LT8550 l 250 µA IAMPP Sinking Current Limit (ISP-ISN) = 0mV, Master LT8550 l 60 µA IAMPP Load Regulation ILOAD = –200µA to 50µA, Master LT8550 1 mV IAMPP Pin Bias Current IAMPP = 1.2V, Slave LT8550 IAMPP = 2.4V, Slave LT8550 µA µA Mismatch Between (ISPn-ISNn) and Master LT8550’s (ISP-ISN) in Regulation ILIM = REG l –6 –4.75 4.75 Mismatch Between (ISPn-ISNn) and Master LT8550’s (ISP-ISN) in Regulation ILIM = FLOAT l –6 –5.5 5.5 Mismatch Between (ISPn-ISNn) and Master LT8550’s (ISP-ISN) in Regulation ILIM = 0V l –10 Oscillator CLK1 Frequency RT/MS = 24.3kΩ, Master LT8550 RT/MS = 100 kΩ, Master LT8550 RT/MS = 249kΩ, Master LT8550 l l l 900 236 1000 250 100 1100 264 110 kHz kHz kHz Switching Frequency Range Free-Running Synchronizing l l 100 125 1000 1000 kHz kHz SYNC High Level for Synchronization l 1.2 V SYNC Low Level for Synchronization l 0.8 V CLK1, CLK2 Rise Time CLOAD = 220pF, Master LT8550 (Note 4) 7 ns CLK1, CLK2 Fall Time CLOAD = 220pF, Master LT8550 (Note 4) 5 ns CLK2 Rising Threshold Slave LT8550 l 4.0 V CLK2 Falling Threshold Slave LT8550 l 1.0 V PHS1, PHS2 High Rising Threshold l 4.65 V PHS1, PHS2 High Threshold Hysteresis 80 mV PHS1, PHS2 Low Falling Threshold l 0.3 V PHS1, PHS2 Low Threshold Hysteresis 80 mV PHS1, PHS2 Impedance at Floating 11 kΩ PHS3 Rising Threshold l 4.65 V PHS3 Threshold Hysteresis 80 mV REG LDO REG Voltage REGSNS = 5V, IAMPN = 0V, ILOAD = 45mA l 4.9 5.1 5.3 V REG LDO Current Limit VIN = 12V, REGSNS = 5V, REG, VCC = 4V VIN = 24V, REGSNS = 5V, REG, VCC = 4V 250 145 mA mA REG LDO Gate Drive Clamp Voltage (VIN – REGDRV) Voltage, REG, VCC = 4.5V 5.3 V REG Load Regulation ILOAD = 0 to 100mA, REGSNS = 5V, IAMPN = 0V 90 mV REGSNS Pin Bias Current REGSNS = 5V 12 µA The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, REG = 5V, VCC = 5V, SHDN = High, unless otherwise noted.

Rev. 0For more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS Gate Drivers TG1, TG2, TG3, TG4 Rise Time CLOAD = 3.3nF, SWx = 0V, BSTx = 5V (Note 4) 30 ns TG1, TG2, TG3, TG4 Fall Time CLOAD = 3.3nF, SWx = 0V, BSTx = 5V (Note 4) 20 ns BG1, BG2, BG3, BG4 Rise Time CLOAD = 3.3nF (Note 4) 50 ns BG1, BG2, BG3, BG4 Fall Time CLOAD = 3.3nF (Note 4) 27 ns Bottom & Top Gate Non-Overlap Time TG Falling to BG Rising, CLOAD = 3.3nF (Note 4) BG Falling to TG Rising, CLOAD = 3.3nF (Note 4) ns ns Bottom & Top Gate Minimum Off-Time CLOAD = 3.3nF (Note 4) 140 ns Primary Gate Sensing BGSH Rising Threshold l 4.0 V BGSH Falling Threshold l 1.0 V BGSH Threshold Hysteresis 1.4 V BGSH to BGBUF Delay CLOAD = 220pF, Master LT8550 (Note 4) 45 ns BGBUF Rise Time CLOAD = 220pF, Master LT8550 (Note 4) 8 ns BGBUF Fall Time CLOAD = 220pF, Master LT8550 (Note 4) 6 ns TGSH Rising Threshold TGSR = 5V, TGSL = 0V l 4.0 V TGSH Falling Threshold TGSR = 5V, TGSL = 0V l 1.0 V TGSH Threshold Hysteresis 1.4 V TGSH to TGBUF Delay CLOAD = 220pF, Master LT8550 (Note 4) 45 ns TGBUF Rise Time CLOAD = 220pF, Master LT8550 (Note 4) 8 ns TGBUF Fall Time CLOAD = 220pF, Master LT8550 (Note 4) 6 ns The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, REG = 5V, VCC = 5V, SHDN = High, unless otherwise noted. Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating Condition for extended periods may affect device reliability and lifetime. Note 2: Do not apply a positive or negative voltage or current source to REGDRV , BG1, BG2, BG3, BG4, TG1, TG2, TG3 and TG4, otherwise permanent damage may occur . Note 3: The LT8550E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8550I is guaranteed to meet performance specifications from –40°C to 125°C junction temperature. Note 4: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels. Note 5: Negative voltages on SW1/2/3/4 pins are limited, in an application, by the body diodes of the external NMOS devices, or the parallel Schottky diodes when present. The SW1/2/3/4 pins are tolerant of these negative voltages in excess of one diode drop below ground, guaranteed by design.

Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. REG LDO Load Regulation REG Voltage vs REGSNS Voltage REG LDO Current Limit REG Quiescent Current vs VIN Voltage, Not Switching REG Quiescent Current vs Temperature, Not Switching REG LDO Line Regulation VCC Quiescent Current vs VIN Voltage, Not Switching VCC Quiescent Current vs Temperature, Not Switching VCC UVLO Threshold REG LDO LOAD CURRENT (mA) 135 180 225 4.8 4.9 5.0 5.1 5.2 5.3 REG VOL TAGE (V)

8550 G01

T = 25°C REGSNS = 5V IAMPN = 0V VIN = 12V REGSNS VOL TAGE (V) 3.5 4.5 5.5 4.0 4.3 4.6 4.9 5.2 5.5 REG VOL TAGE (V)

8550 G02

T = 25°C IAMPN = 0.1V IAMPN = 0V IAMPN = –0.1V T = 25°C VIN VOL TAGE (V) 120 180 240 300 REG LDO CURRENT LIMIT (mA)

8550 G03

VIN VOL TAGE (V) 5.0 7.5 10.0 12.5 15.0 17.5 20.0 REG QUIESCENT CURRENT (µA)

8550 G04

T = 130°C T = 25°C T = –50°C TEMPERATURE (°C) –50 –25 100 125 150 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 REG QUIESENCT CURRENT (µA)

8550 G05

VIN = 6V VIN = 12V VIN = 80V LOAD = 0mA T = 25°C REGSNS–IAMPN = 5V VIN VOL TAGE (V) 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 REG VOL TAGE (V)

8550 G06

TEMPERATURE (°C) –50 –25 100 125 150 3.0 3.2 3.4 3.6 3.8 4.0 VCC UVLO THRESHOLD (V)

8550 G09

T = 25°C T = 150°C T = –50°C VIN VOL TAGE (V) 4.9 5.0 5.1 5.2 5.3 V CC QUIESCENT CURRENT (mA)

8550 G07

VIN = 6V VIN = 12V VIN = 80V TEMPERATURE (°C) –50 –25 100 125 150 4.9 5.0 5.1 5.2 5.3 V CC QUIESCENT CURRENT (mA)

8550 G08

Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. SHDN Pin Threshold VIN UVLO Threshold VIN Quiescent Current vs VIN Voltage, Not Switching VIN Quiescent Current vs Temperature, Not Switching SHDN Pin Current vs Voltage IAMPP-IAMPN Voltage vs (ISP-ISN) Voltage Maximum Positive Current Limit vs Temperature Maximum Negative Current Limit vs Temperature PHS1 Pin Current RISING FALLING TEMPERATURE (°C) –50 –25 100 125 150 1.10 1.15 1.20 1.25 1.30 SHDN PIN THRESHOLD (V)

8550 G10

TEMPERATURE (°C) –50 –25 100 125 150 3.0 3.1 3.2 3.3 3.4 3.5 VIN UVLO THRESHOLD (V)

8550 G11

T = 130°C T = 25°C T = –50°C VIN VOL TAGE (V) 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 VIN QUIESCENT CURRENT (mA)

8550 G12

TEMPERATURE (°C) –50 –25 100 125 150 4.7 4.9 5.1 5.3 5.5 5.7 VIN QUIESENCT CURRENT (mA)

8550 G13

VIN = 6V VIN = 12V VIN = 80V SHDN PIN VOL TAGE (V) SHDN PIN CURRENT (µA)

8550 G14

T = 150°C T = 25°C T = –50°C T = 25°C ISP–ISN VOL TAGE (mV) –90 –60 –30 0.2 0.5 0.8 1.1 1.4 1.7 2.0 2.3 2.6 IAMPP–IAMPN VOL TAGE (V)

8550 G15

ILIM = FLOAT ILIM = REG ILIM = GND ILIM = REG ILIM = FLOAT ILIM = GND TEMPERATURE (°C) –50 –25 100 125 150 100 MAXIMUM POSITIVE CURRENT LIMIT (mV)

8550 G16

ILIM = FLOAT ILIM = REG ILIM = GND TEMPERATURE (°C) –50 –25 100 125 150 –100 –90 –80 –70 –60 –50 –40 –30 –20 MAXIMUM NEGATIVE CURRENT LIMIT (mV)

8550 G17

T = 25°C PHS1 PIN VOL TAGE (V) –180 –120 –60 120 180 PHS1 PIN CURRENT (µA)

8550 G18

Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. PHS1 High Threshold Voltage vs Temperature PHS1 Low Threshold Voltage vs Temperature PHS2 Pin Current PHS2 High Threshold Voltage vs Temperature PHS2 Low Threshold Voltage vs Temperature PHS3 Pin Current PHS3 Threshold Voltage vs Temperature ILIM Pin Current vs Voltage ILIM High Threshold Voltage vs Temperature RISING FALLING TEMPERATURE (°C) –50 –25 100 125 150 4.25 4.30 4.35 4.40 4.45 4.50 PHS1 VOL TAGE (V)

8550 G19

TEMPERATURE (°C) –50 –25 100 125 150 0.4 0.5 0.6 0.7 0.8 PHS1 VOL TAGE (V)

8550 G20

T = 25°C PHS2 PIN VOL TAGE (V) –180 –120 –60 120 180 PHS2 PIN CURRENT (µA)

8550 G21

TEMPERATURE (°C) –50 –25 100 125 150 4.25 4.30 4.35 4.40 4.45 4.50 PHS2 VOL TAGE (V)

8550 G22

TEMPERATURE (°C) –50 –25 100 125 150 0.4 0.5 0.6 0.7 0.8 PHS2 VOL TAGE (V)

8550 G23

T = 25°C PHS3 PIN VOL TAGE (V) PHS3 PIN CURRENT (µA)

8550 G24

TEMPERATURE (°C) –50 –25 100 125 150 4.25 4.30 4.35 4.40 4.45 4.50 PHS3 VOL TAGE (V)

8550 G25

ILIM VOL TAGE (V) –180 –120 –60 120 180 ILIM PIN CURRENT (µA)

8550 G26

TEMPERATURE (°C) –50 –25 100 125 150 4.20 4.25 4.30 4.35 4.40 ILIM VOL TAGE (V)

8550 G27

Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICSTA = 25°C, unless otherwise noted. ILIM Low Threshold Voltage vs Temperature ENOUT Threshold Voltage TGSR-TGSL UVLO Threshold Oscillator Frequency vs Temperature BST-SW UVLO Threshold Efficiency and Power Loss vs Load Current — LT8550 + LT3763 Load Response from 0A to 80A — LT3741 + LT8550 RISING FALLING TEMPERATURE (°C) –50 –25 100 125 150 0.3 0.4 0.5 0.6 0.7 0.8 0.9 ILIM VOL TAGE (V)

8550 G28

TEMPERATURE (°C) –50 –25 100 125 150 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 ENOUT THRESHOLD VOL TAGE (V)

8550 G29

TEMPERATURE (°C) –50 –25 100 125 150 2.20 2.25 2.30 2.35 2.40 TGSR–TGSL UVLO THRESHOLD (V)

8550 G30

RT = 249K RT = 100K RT = 49.9K TEMPERATURE (°C) –50 –25 100 125 150 100 200 300 400 500 600 OSCILLATOR FREQUENCY (kHz)

8550 G31

TEMPERATURE (°C) –50 –25 100 125 150 3.3 3.4 3.5 3.6 3.7 BST–SW UVLO THRESHOLD (V)

8550 G32

V OUT = 12V EFFICIENCY POWER LOSS fs = 250kHz 24V IN–W/O SHEDDING 24V IN–W/ SHEDDING 56V IN–W/O SHEDDING 56V IN–W/ SHEDDING LOAD CURRENT (A) 0.1 100 100 100 EFFICIENCY (%) POWER LOSS (W)

8550 G33

400µs/DIV EXPANDER IL4 10A/DIV EXPANDER IL3 10A/DIV EXPANDER IL2 10A/DIV PRIMARY IL 10A/DIV

8550 G34

fS = 350kHz VIN = 24V VOUT = 6V

Rev. 0 For more information www.analog.com PIN FUNCTIONS REG (Pin 3): Output of REG LDO. Power supply for gate drivers. Decouple this pin to ground with a minimum 4.7µF low ESR ceramic capacitor . Connect this pin to the external PMOS drain side. BG1, BG2, BG3, BG4 (Pins 11, 10, 2, 1) : Bottom Gate Driver Output. These pins drive the gates of the bottom N-channel MOSFETs. Voltage swing at these pins is from ground to REG. BGBUF (Pin 12): Logic Output Pin. This pin is pulled up to REG when BGSH is at logic high, and it is pulled down to ground when BGSH is at logic low. For a slave LT8550, leave this pin floating. See the Applications Information section for more information. TGBUF (Pin 13): Logic Output Pin. For a master LT8550, this pin is pulled up to REG voltage when (TGSH-TGSL) is at logic high, and it is pulled down to ground when (TGSH-TGSL) is at logic low. For a slave LT8550, leave this pin floating. See the Applications Information section for more information. BST1, BST2, BST3, BST4 (Pins 14, 7, 6, 52): Boosted Floating Driver Supply. The (+) terminal of the boost-strap capacitor is connected to this pin. This pin swings from a diode voltage drop below REG up to VIN + REG. TG1, TG2, TG3, TG4 (Pins 15, 8, 5, 51): Top Gate Driver Output. This is the output of a floating driver with a volt- age swing equal to REG superimposed on the switch node voltage. SW1, SW2, SW3, SW4 (Pins 16, 9, 4, 50): Switch Node. Voltage swing at these pins is from a diode voltage drop below ground to VIN. TGSR (Pin 17) : The Rail of Primary Channel Top Gate Sense Circuit. For a master LT8550, connect this pin to the primary channel top gate driver’s boost node. This pin, combined with TGSH, TGSL pins, is to sense the primary channel top MOSFET’s state. For a slave LT8550, connect this pin to REG. TGSH (Pin 18): Input of Primary Channel Top Gate Sense Circuit. For a master LT8550, connect this pin to the pri- mary channel top MOSFET ’s gate. This pin, combined with TGSR, TGSL pins, is to sense the primary channel top MOSFET’s state. For a slave LT8550, connect this pin to the master LT8550’s TGBUF pin. TGSL (Pin 19): Lower Rail of Primary Channel Top Gate Sense Circuit. For a master LT8550, connect this pin to the primary channel top MOSFET’s source. This pin, com- bined with TGSR, TGSH pins, is to sense the primary channel top MOSFET’s state. For a slave LT8550, connect this pin to ground. CLK1, CLK2 (Pins 21, 20) : Clock Pin. These two pins are used to synchronize the primary channel to all other channels. See the Applications Information section for more information. BGSH (Pin 22): Logic Input of Primary Channel Bottom Gate Sense Circuit. For a master LT8550, connect this pin to the primary channel bottom MOSFET ’s gate. This pin is to sense the primary channel bottom MOSFET ’s state. For a slave LT8550, connect this pin to the master LT8550’s BGBUF pin. SYNC (Pin 23): To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock must exceed 1.2V, and the low level must be less than 0.8V. Drive this pin to less than 0.8V to revert to the internal free-running clock. See the Typical Applications section. PHS1, PHS2 (Pins 25, 24) : Phase Selection Pin. These pins, combined with PH S3 and RT/MS, set the switch - ing frequency and the phase of each channel. PH S1 and PHS2 are three-level input pins, they can be floated, set to REG or ground. When the PHS1/PHS2 is floating, add a 1nF cap from PHS1/PHS2 to ground. See the Operation section for more information. RT/MS (Pin 26): Timing Resistor Pin and Master Slave Selection Pin. This pin, combined with PHS1, PHS2 and PHS3, sets the switching frequency and the phase of each channel. Connecting a resistor to ground sets the chip as master LT8550. Connecting this pin to the REG pin sets the chip as slave LT8550. See the Applications Information section for more information. (QFN)

Rev. 0For more information www.analog.com PIN FUNCTIONS ILIM (Pin 27) : Maximum Current Sense Voltage Programming Pin. This pin is used to set the maximum sense voltage in the primary channel current sense ampli- fier and expanded channel current sense amplifier . It is a three level input pin. Connecting this pin to ground, REG or leaving it floating sets the maximum current sense voltage to 30mV, 60mV or 90mV, respectively. When the ILIM is floating, add a 1nF cap from the ILIM to ground. ENOUT (Pin 28): For a master LT8550, this pin is an open- drain logic output pin. For a slave LT8550, it is an input pin. See more details in ENOUT Connection Section. VCC (Pin 29): Power supply for control circuits. Decouple this pin to ground with a minimum 1µF low ESR ceramic capacitor . VCC and REG need to be connected through a 1Ω resistor . MODE (Pin 30): Stage Shedding Selection Pin. Connecting this pin to GND disables stage shedding feature. See the Operation section for more information. SHDN (Pin 31): Shutdown Pin. This pin is used to enable/ disable the chip. Drive below 0.3V to disable the chip. Drive above 1.2V (typical) to activate the chip. Do not float this pin. IAMPN (Pin 32): For a master LT8550, connect this pin to local ground. For a slave LT8550, connect this pin to the master LT8550’s IAMPN. See the Applications Information section for more information. IAMPP (Pin 33) : For a master LT8550, this is an out - put pin. It is the buffered signal of the Primary Channel Current Sense Amplifier output. For a slave LT8550, this is an input pin. When multiple LT8550s are used, connect all IAMPP pins together . See the Applications Information section for more information. ISP (Pin 34) : Primary Channel Current Sense Amplifier Input. The (+) input to the current sense amplifier is nor- mally connected to DCR sensing network or current sens- ing resistor . This pin is only used for a master LT8550. Ground this pin for a slave LT8550. ISN (Pin 35) : Primary Channel Current Sense Amplifier Input. The ( –) input to the current sense amplifier is normally connected to DCR sensing networks or cur - rent sensing resistors. This pin is only used for a master LT8550. Ground this pin for a slave LT8550. REGSNS (Pin 40): REG LDO Voltage Sense Pin. Connect this pin to the primary channel gate driver power supply pin. PHS3 (Pin 41): Phase Select Pin. This pin, combined with PHS1, PHS2 and RT/MS, set the switching frequency and the phase of each channel. PH S3 connects to REG or ground. See the Operation section for more information. NC (Pin 42) : No Connection. Leave this pin floating or connect to any adjacent pin. ISN1, ISN2, ISN3, ISN4 (Pins 43, 37, 46, 39): Expanded Channel Current Sense Amplifier (–) Input. The (–) input to the current sense amplifier is normally connected to DCR sensing network or current sensing resistor . ISP1, ISP2, ISP3, ISP4 (Pins 44, 36, 45, 38): Expanded Channel Current Sense Amplifier (+) Input. The (+) input to the current sense amplifier is normally connected to DCR sensing network or current sensing resistor . REGIS (Pin 47) : REG LDO Current Sense Pin. Connect this pin to the external PMOS source side. REGDRV (Pin 48) : Gate Driver Output for REG LDO. Connect this pin to the external PMOS gate. VIN (Pin 49): Input Supply Pin. Must be locally bypassed to ground. GND (Exposed Pad Pin 53/Pin 27) : Ground. Tie directly to local ground plane. (QFN)

Rev. 0 For more information www.analog.com BLOCK DIAGRAM VIN REG ILIM VC1 VIN REG ILIM VC4 CHANNEL 2 AND 3 NOT SHOWN VBIAS 8550 BD SHDN ENOUT VIN REGIS REGDRV ISP1 ISN1 REG TIMING CONTROL CURRENT LIMIT AND FAUL T CONTROL 1 EA1 IAMP_INT1 + – REGSNS IAMPN STAGE SHEDDING CONTROL START-UP CONTROL UVLO_VIN UVLO_VCC OT ENOUT CONTROL CURRENT LIMIT CONTROL REGS_INT A5 (1×) +1.8V A7 (1×) VOUT BST4 TG4 SW4 BG4 BST1 TG1 SW1 BG1 ISP4 ISN4 REG TIMING CONTROL CURRENT LIMIT AND FAUL T CONTROL 4 EA4 IAMP_INT4 VOUT REG MODE VCC ILIM IAMPP IAMPN ISP ISN SYNC PHS1 PHS2 PHS3 CLK1 CLK2 TGSR TGSH TGSL BGSH TGBUF BGBUF REG PRIMARY GATE SENSING OSCILLATOR AND CLOCK PROCESSING RT/MS 48 44 IAMP_INT

Rev. 0For more information www.analog.com OPERATION Introduction The LT8550 is a multiphase expander for synchronous buck controllers. Each LT8550, which has 8 gate driv - ers, can expand up to four phases. Multiple LT8550s can also be used together in a system, and up to 18 different phases can be supported. In addition, the part supports more than one phase per phase angle. The ADI proprietary control architecture allows the LT8550 to cycle-by-cycle duplicate the operation of a buck controller (named as Primary Controller). The LT8550 measures the primary controller’s inductor current as well as primary controller’s gate driver operation timing, and at the same time, accurately monitors and adjusts the cur - rent of each expanded channel to achieve excellent DC and transient current sharing. The current sharing accuracy is ±6%, ±6% and ±10% over temperature when ILIM set at REG, Float and GND, respectively. In normal operation, the primary buck regulator’s switch current is compared with the expanded channel’s switch current by the EA ( EA1/2/3/4 in the Block Diagram). When the primary channel ’s current increases, the VC (VC1/2/3/4 in the Block Diagram) voltage also increases, which in turn controls the expanded channel’s switches to increase the current until the expanded channel’s current matches the primary channel’s current. System with Multiple LT8550s One LT8550 can expand up to four channels. This config- uration can provide enough power for most high current applications. However , for even higher power applications, the LT8550 can be configured for multi-chip operation. When two or more LT8550s are used together in a system, one LT8550 is the master and other LT8550s are slaves. Connecting a resistor from the RT/MS pin to ground sets the chip as the master and connecting the RT/MS pin to REG sets the chip as a slave. When only one LT8550 is used in a system, this LT8550 needs to be set as a master . Stage Shedding Mode The MODE pin is dedicated for the Stage Shedding fea - ture. The MODE pin is an output pin for a master LT8550, and it is an input pin for a slave LT8550. For a master LT8550, when the MODE pin is floating, the LT8550 operates in Stage Shedding mode at light loads. In this case, when the (ISP-ISN) peak voltage is lower than a certain value for some period of time, the part turns off channels 1 and 3 to increase overall efficiency. After channel 1 and 3 are off, if the (ISP-ISN) peak volt - age is still lower than a certain value for some period of time, the part also turns off channel 4 and only leaves channel 2 running. For bidirectional applications, stage shedding should be disabled when the current is regulated in the reverse direction. Driving the MODE pin below 0.5V disables the Stage Shedding feature. In a multiple LT8550s system, all chips’ MODE pins need to be connected together and left floating if the Stage Shedding feature is desired. The master LT8550 senses the (ISP-ISN) voltage to decide proper operation. The slave LT8550s follows the master LT8550’s Stage Shedding operation with some delay. Driving all chips’ MODE pins below 0.5V disables the Stage Shedding feature. Clock Scheme This section discusses the LT8550 clock scheme for a multiple LT8550 system. This clock scheme can easily apply to a single LT8550 system by ignoring the slave LT8550s. A master LT8550 generates two clock signals: CLK1 and CLK2. In a multiple LT8550 system, as shown in Figure 1, all LT8550s’ CLK2 pins need to be connected together . The CL K1 signal is at the fundamental switching fre - quency (Refer to Internal Oscillator and SYNC Pin and Clock Synchronization sections for more information), and it is used to synchronize the primary buck controller and the slaves (in Figure 1). Under normal operation, the CLK2 frequency is at the CLK1 frequency times the total distinct phase number (TDPN), as shown in Figure 2. The number shown above the CLK2 pulses in Figure 2 is called the phase angle number (PAN).

equals the TDPN (in Figure 2).

• • •

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Figure 1. Clock Configuration in a Multiple LT8550 System by the eight expanded channels are shown in Figure 3. Table 1. Table for Programming Total Distinct Phase Number Table 2. Design Example for a 9-Phase Application

• • •

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Figure 2. CLK1, CLK2 and Primary’s (TG-SW) Figure 3. Clock Waveforms for a T wo LT8550 System Figure 4. CLK1, CLK2 and Primary’s (TG-SW) Waveforms for Pulse Skipping

This section discusses a system with multiple LT8550s. Figure 5. The slave’s TGSR and TGSL are connected to the Applications Information section for more information. (BGSH) is needed for the primary’s BG detection. noisy BST , TG, SW and BG signals around the board.

• • •

8550 F07

Figure 5. Gate Sensing in a Multiple LT8550 System This section discusses a system with multiple LT8550s. the master and slave LT8550s. the IAMPN pins to the master LT8550’s local ground. small signals around the board is avoided. Figure 6. Primary Regulator’s Switch Current Sensing in Multiple

Figure 7. There is a 1.4V offset. For expanded channels, current fault as shown in Figure 8. current limit are indicated in Figure 7. Figure 9 illustrates the start-up sequence for the LT8550. REG LDO is enabled (switcher off state). 3.55V, the ENOUT is pulled to GND to disable switching. Figure 7. Current Sensing Amplifier Output Vs. Input

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Figure 8. IAMP_INTx Voltage for Current Limit and Current Fault

8550 F09

• SWITCHER OFF
• REG LDO ON CHIP OFF
• SWITCHER OFF
• REG LDO OFF FAUL T DETECTED
• SWITCHER DISABLED
• FAUL T COUNTER +1
• WAITING FOR FAUL T CONDITION CLEARED NORMAL MODE
• NORMAL OPERATION
• RESET FAUL T COUNTER POST FAUL T DELAY
• SWITCHER DISABLED
• WAITING FOR ABOUT 800 CLOCK CYCLES PRE-NORMAL MODE
• NORMAL OPERATION FOR ABOUT 800 CLOCK CYCLES LATCH OFF MODE
• SWITHER DISABLED IS FAUL T COUNTER LESS THAN 15?

Figure 9. Start-Up and Fault Sequence driver’s switching activity is disabled.

8550 F10

Figure 10. Recommended ENOUT Connection

or higher than 5.25V respectively, as shown in Figure 11. should be placed close to the primary controller . typical current limit is about 110mA. limit depends on the V IN voltage as shown in Figure 13. the current limit is about 220mA or 100mA respectively. maximum power dissipation in the external power PMOS.

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Figure 12. REG LDO Configuration

8550 F11

Figure 11. REG Voltage vs REGSNS Voltage ing activity when VCC is lower than 3.55V (typical). INTVCC, as shown in Figure 12.

LDO for a specific application. appropriate PMOS that will not overheat. P is the power dissipation of the PMOS. board is needed for the PMOS to alleviate thermal stress. choose a PMOS with Qg < 40nC.

8550 F13

Figure 13. REG LDO Current Limit vs VBIAS Voltage master CLK1 and each primary ’s or slave ’s SYNC pin. sections provide more details.

nize the internal oscillator to the external clock signal.

1. The PLL is guaranteed to work properly only when the
2. The external clock can be synchronized to only when

set by RT , the internal oscillator will oscillate at fOSC. detected by the master LT8550 gate sensing pins (i.e. LT8550’s TGBUF and BGBUF respectively. RF = 20Ω, C = 1nF are recommended.

8550 F14

Figure 14. Gate Sensing Configuration with Filters

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Figure 15. Gate Sensing Configuration when Primary

Table 3. Recommended Values for Gate Sensing Filters should be close to the master LT8550 in the PCB layout. due to the limited peak inductor current. and Efficiency Considerations. logic level (5V) MOSFET must be used for the LT8550.

2 IMAX

• 1 VREG – VTH(MIN) + 1 VTH(MIN) ⎥⎢ ⎥
• fOSC PSYNC = VIN – VOUT VIN IMAX 2 1+ δ( )RDS(ON) Where δ is the temperature dependency of RDS(ON), RDR is effective gate driver resistance at the MOSFET’s Miller threshold voltage, VTH(MIN) is the typical MOSFET mini - mum threshold voltage and fOSC is the switching frequency. Both MOSFETs have I 2R losses while the main switch equation includes an additional term for transition

Rev. 0For more information www.analog.com losses, which dominates the power losses at high input voltages. For VIN < 20V, the high current efficiency gen - erally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly increase to the point that the use of a higher R DS(ON) device with lower Miller capacitance provides higher efficiency. The synchronous MOSFET losses are greatest at highest input voltage when the duty cycle of the main switch is lowest. In this case, it’s helpful to use two or more MOSFETs in parallel to reduce the power dissipation on each device. Based on the power dissipation, the MOSFET junction temperature can be obtained using the formula (1) in the REG LDO Current Limit and External Power PMOS Selection section to pick an adequate MOSFET that will not overheat. An optional Schottky diode in parallel with the bottom switch conducts during the dead time between the conduc- tion of the main switch and the synchronous switch. This prevents the body diode of the synchronous switch from turning on, storing charge and requiring a reverse recovery period that could cost as much as 3% in lower efficiency at high VIN. Although improving the efficiency, the Schottky diode also exhibits much higher reverse leakage current than the silicon diode particularly at high temperature, the combination of high reverse voltage and current can lead to self-heating of the diode. Choose a package with lower ther- mal resistance (θJA) to minimize self-heating of the diode. CIN Capacitance In continuous mode, the source current of the top N-channel MOSFET is a square wave of duty cycle VOUT/ VIN. To prevent large voltage transients, a low ESR (equiv- alent series resistance) input capacitor sized for the maxi- mum RMS current must be used. The maximum RMS capacitor current is given by: CIN Required IRMS ≅ IMAX VIN VOUT( ) VIN – VOUT( )⎡⎣ ⎤⎦ This formula has a maximum at V IN = 2VOUT, where IRMS = IO(MAX)/2. This simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours of APPLICATIONS INFORMATION life, this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be used in parallel to meet requirement. Typically multiple X5R or X7R ceramic capacitors are put in parallel with either conductive-polymer or aluminum-electrolytic types of bulk capacitors. Because of its low ESR, the ceramic capacitors will take most of the RMS ripple current. Vendors do not consistently specify the ripple current rating for ceramics, but ceramics could also fail due to excessive ripple current, consult the manufac- turer if there is any question. COUT Capacitance The output capacitors need to have very low ESR to reduce output voltage ripple. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS cur- rent handling requirements. Dry tantalum, special poly - mer , aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-driven applications. Typically, once the ESR requirement for COUT has met, the RMS current rating far exceeds the require- ment. A minimum of 20μF/A of load capacitor is recom- mended in most designs. Topside MOSFET Driver Supply (CBX, DBX) An external bootstrap capacitor , CBX, supplies the gate driver voltage for the top switch. This capacitor is con - nected between BSTx and SWx and is charged through Schottky diode DBX from REG when the SWx pin is low. When the top switch turns on, the SWx rises to power VIN and the BSTx rises to VIN + REG. The boost capacitor needs to store about 100 times the gate charge required by the top switch. In most applications, a 0.1μF to 0.47μF, X5R or X7R dielectric capacitor is adequate. The bypass capacitance from REG to GND should be at least ten times the bootstrap capacitor value. In addition, the reverse breakdown of the Schottky diode must greater than the maximum power VIN voltage.

accurate DCR current sensing. underneath the sense resistor as shown in Figure 17. RSENSE is chosen based on the maximum output current.

8550 F17

Figure 17. Sense Lines Placement for DCR Sensing several points of efficiency compared to DCR sensing.

8550 F16a

8550 F16b

Figure 16. Inductor Current Sense Filter

Rev. 0For more information www.analog.com The inductor DCR is sensed by connecting an RC filter across the inductor . This filter typically consists of one or two resistors ( R1 and R2) and one capacitor (C). If the external ( R1||R2) • C time constant is chosen to be exactly equal to the L/DCR time constant, the voltage drop across C will be: VSENSE = IL • DCR R2 R1+ R2 Therefore, R2 may be used to scale the voltage across the sense terminals when the DCR is greater than the target sense resistance. With the ability to program the current limit through ILIM pin, R2 may be optional. C is usually selected in the range of 0.01μF to 0.47μF. This forces R1||R2 to be around the kΩ range. For DCR current sensing, the sense lines should also run close together to a Kelvin connection underneath the inductor as shown in Figure 17. To prevent noise from coupling into the sensitive small-signal nodes, resistor R1 should be placed close to the inductor , while R2 and C are placed close to the LT8550 as shown in Figure 16b. Thermal Shutdown If the die junction temperature reaches approximately 165°C, the LT8550 will go into thermal shutdown. All the power switches will be turned off. For a master LT8550, the ENOUT pin will be pulled down to ground so that it will shut down all the switching activity of the system. The LT8550 will be re-enabled when the die temperature has dropped by about 5°C (nominal). Efficiency Considerations The percent efficiency of LT8550 is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would lead to the most improvement. Percentage efficiency can be expressed as: %Efficiency = 100% – (L1 + L2 + L3 + …) Where L1, L2, etc. are the individual losses as a percent- age of input power . Although all dissipative elements in APPLICATIONS INFORMATION the circuit produce power losses, several sources usually account for most of the losses in LT8550 circuits: 1. I 2R losses. I 2R losses arise from the DC resistance of the MOSFETs, inductor and current sense resistor . It is the majority of power losses under high output current conditions. In continuous mode, the aver - age output current flows through the inductor and RSENSE, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the inductor’s DCR, RSENSE and the board traces to obtain I2R losses. 2. T ransition loss. This loss mostly arises from the brief amount of time the top MOSFET spends in the satura- tion (Miller) region during the switching node transi- tions. It depends on the input voltage, load current, driver strength and MOSFET capacitance. The transi- tion can be significant at high input voltages or high switching frequency. 3. REG current. This is the sum of MOSFETs driver and REG control currents. The MOSFET driver cur - rent results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high then to low again, a packet of charge dQ moves from REG to ground. The result- ing dQ/dt is a current out of REG that is typically much larger than the control circuit current. In continuous mode, IGATECHG = f • [QT + QB], where QT and QB are the gate charges of the top and bottom MOSFETs. As mentioned in the REG LDO and VCC Power Section, powering the REG LDO with a lower power supply voltage will not only improve efficiency, especially for high input voltage application, but also alleviate the thermal stress for the LDO’s P-channel MOSFET . 4. C IN loss. The input capacitor filters large square-wave input currents drawn by the LT8550 into an averaged DC current from the supply. The capacitor itself has zero average DC current, but there is an AC current flowing through it. Therefore, the input capacitor must have a very low ESR to minimize the RMS current loss due to ESR. It must also have sufficient capacitance to filter out the AC component of the input current to

Figure 18. Recommended PC Board Design for a 9-Phase System

8550 F18

ture can help reduce the ESR losses.

1. Body diode conduction loss. During the dead time,

ing cycle period and causes the efficiency to drop.

1. The VIN current is the DC supply current which flows

typically results in a small (<0.1%) loss. during the system design phase.

• A multilayer PC board with dedicated ground planes is generally preferred to reduce noise coupling and improve heat sinking. The ground plane should be immediately next to the routing layer for the compo- nents (i.e. MOSFETs, inductors, sense resistors, input and output capacitors etc.
• Keep small signal ground (SGND) and power ground (PGND) separate. Only one connection point between the SGND and PGND is required. It ’s desirable to return the SGND to a clean point on the PGND plane. Do not return the small signal components grounds to SGND through PGND. All power train components should be referenced to PGND. Use immediate vias to connect the power components to PGND. Several vias are needed for each power component.
• Place power components, such as CIN, COUT, inductor and MOSFET, in one compact area. Use wide but the shortest possible traces for high current paths (e.g. VIN, VOUT, PGND etc.) in this area to minimize copper loss.
• The BSTx/SWx nodes ’ voltage swings with a high dV/dt rate. These nodes are rich in high frequency noise components, and they are strong sources of EMI noise. To minimize the coupling between these nodes and other noise-sensitive traces, the copper area should be minimized. However , on the other hand, to conduct high inductor current and provide a heat sink to the power MOSFET , the SWx nodes APPLICATIONS INFORMATION PCB area cannot be too small. It ’s usually preferred to have a ground copper area placed underneath the SWx nodes to provide additional shielding. In addition to BSTx/SWx, the TGx and BGx are also high dV/dt signals, which must be routed away from the noise-sensitive traces. It is also highly recommended to use short and wide traces to route gate driver sig- nals in order to minimize the impedance in gate driver paths. The TGx and SWx should be routed together with minimum loop area to minimize the inductance and high dV/dt noise. Likewise, the BGx should be routed close to a PGND trace, as shown in Figure 19. T ry to route TGx, SWx, BGx traces on one layer only. LT8550 BSTX TGx SWx REG BGx REG PGND PGND PLANE MTOP MBOT VIN

8550 F19

Figure 19. Gate Driver Routing Example

• Keep the high di/dt loop, which consists of the top MOSFET , bottom MOSFET , and the ceramic capacitor CH as shown in Figure 20, as short as possible to minimize the pulsating loop inductance and absorb switching noise.
• The decoupling capacitors for REG, VCC, VIN and the current sense, etc. should be placed close to their pins, use PGND for the REG decoupling capacitor and SGND for VIN and V CC decoupling capacitors. To minimize the connection impedance, it’s desired to connect the

Figure 20. Minimize the High di/dt Loop Area in PCB Layout

8550 F20

• Of all the small signal traces, current sensing traces are most sensitive to noise. The current sensing traces should be routed differentially with minimum spacing to minimize the chance of picking-up noise, as shown in Figure 21. In addition, the filter resistors and capacitors for current sensing traces should be placed as close to the ISPx/ISNx pins as possible. If the DCR sensing is used with an R/C network, the APPLICATIONS INFORMATION DCR sensing resistor R1 should be close to the induc- tor , while R2 and C should be close to the IC. Place the vias that connect the ISPx/ISNx lines directly at the terminals of the current sensing resistors or the inductors as shown in Figure 21.
• When routing the interface signals between a mas - ter LT8550, primary controller , and/or slave LT8550, keep the small-signal lines far from the noisy lines and shield these lines with a ground plane. A recom- mended line arrangement is shown in Figure 22.

Figure 21. Current Sensing PCB Design Figure 22. Recommended Signal Lines Arrangement for PCB

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Rev. 0For more information www.analog.com TYPICAL APPLICATIONS Five Phase 6V/100A Step-Down Expander VINREG VINREG VINREG VINREG VIN REG 33nF 20/uni03A9

8550 TA02

+ CIN2 100µF CIN3 10µF CIN4 100µF CIN5 10µF CIN6 100µF CIN7 10µF CIN8 100µF CIN9 10µF COUT2 10µF COUT3 150µF COUT4 10µF COUT5 150µF COUT6 10µF COUT7 150µF COUT8 10µF COUT9 150µF 10/uni03A9 10/uni03A9 33nF 220pF 62k 10/uni03A9 0.22µF 1nF SENSEN SENSEP HG CBOOT SW LG + CIN0 100µF CIN1 10µF COUT0 10µF COUT1 150µF 0.22µF ENOUT CLK1 REGSNS TGSR TGSH TGSLBGSHVIN SHDN REGIS REGDRV CTRL1 VREF CTRL2 VC RT SS EN/UVLO SYNC VCC_INTGND FB VIN 200k 47k 10/uni03A9 10nF 1nF 22µF 1nF L1, 1.3µH 2m/uni03A9 L0, 1.3µH 2m/uni03A9 40.2k 10k100k 45.3k 10k 2.2µF 4.7nF 4.7µF137k 1µF 680k LT8550 LT3741 24k 4.7µF 1/uni03A9 L0–L4: WURTH ELEKTRONIK 7443551130 M1–M10: INFINEON BSC093N04LSG CIN0, CIN2, CIN4, CIN6, CIN8: PANASONIC EEHZAH101P CIN1, CIN3, CIN5, CIN7, CIN9: TDK C3225X7R1H106M250AC COUT0, COUT2, COUT4, COUT6, COUT8: PANASONIC 16TQC150MYF COUT1, COUT3, COUT5, COUT7, COUT9: TDK C3216X7R1V106K160AC VIN 12V TO 36V 10/uni03A9 0.22µF 1nF L2, 1.3µH 2m/uni03A9 10/uni03A9 0.22µF 1nF L3, 1.3µH 2m/uni03A9 10/uni03A9 0.22µF 1nF L4, 1.3µH 2m/uni03A9 M10 VOUT 6V/100A MAX 10µF MP TG2 BST2 SW2 BG2 ISP2 ISN2 TG3 BST3 SW3 BG3 ISP3 ISN3 TG3 BST4 SW4 BG4 ISP4 ISN4 REG ILIM PHS1 PHS2 PHS3 VCC SYNC RT/MS IAMPP IAMPN CLK2 TGBUF BGBUF MODE GND REG

Rev. 0 For more information www.analog.com VINREG VINREG VIN REG INTVCC VIN REG REG REG 100k 330kHz

8550 TA03a

0.22µF 1nF SENSE– SENSE+ TG BOOST SW BG CIN0 22µF CIN1 150µF CIN2 22µF CIN3 150µF + COUT1 330µF COUT0 22µF COUT3 330µF COUT2 47µF 0.22µF ENOUT CLK1 REGSNS TGSR TGSL TGSHVIN SHDN FREQ/PLLFIL TER ILIM VIN ITH TK/SS RUN MODE/ PLLIN INTVCC GND FB 47k 0.1µF 330pF 22µF L1 1.3µH L0 1.3µH RS0 2m/uni03A9 RS1 2m/uni03A9 154k 48.7k 15k 2.2nF 4.7µF 10µF 1µF 1/uni03A9 33k BGSH LT8550 LTC3851A-1 CH2 AND CH3 NOT SHOWN 12k VIN 4.5V TO 32V TG4 BST4 SW4 BG4 ISP4 ISN4 10/uni03A9 0.22µF 1nF CIN4 22µF CIN5 150µF COUT5 330µF COUT4 22µF L4, 1.3µH RS4 2m/uni03A9 1nF 10nF 4.7µF MP 1nF33nF 20/uni03A9 470pF L1–L4: WURTH ELEKTRONIK 7443556130 M1–M6: INFINEON BSC093N04LSG CIN0, CIN2, CIN4: TDK C4532X7R1E226M250KC CIN1, CIN3, CIN5: PANASONIC EEUFC1V151 COUT0, COUT2, COUT4: TDK C3216JB1E476M160AC COUT1, COUT3, COUT5: PANASONIC EEUFM1E331 RS0–RS4: PANASONIC ERJMP3PF2MOU VOUT 3.3V/75A MAX ILIM PHS1 PHS2 PHS3 RT/MS SYNC MODE TGBUF BGBUF CLK2 IAMPP IAMPN GND REGIS REGDRV REG VCC REG TYPICAL APPLICATIONS Five Phase 3.3V/75A Step-Down Expander System Start-Up Waveform with 10A Load T ransient Response with 20A to 70A Output Load Step 10ms/DIV VOUT 2V/DIV IL4 5A/DIV IL2 5A/DIV IL0 5A/DIV

8550 TA03b

400µs/DIV IL4 10A/DIV IL3 10A/DIV IL2 10A/DIV IL0 10A/DIV

8550 TA03c

Rev. 0For more information www.analog.com TYPICAL APPLICATIONS Five Phase 12V/70A Step-Down Expander System VINREG VINREG VIN REG VIN 14V TO 56V REG REG REG 124k 250kHz 10nF 1nF 10nF INTVCC LT8550

8550 TA04a

0.22µF 1nF SENSE– SENSE+ ISMON IVINMON TG BOOST SW BG PWM_OUT PWM FAUL T FBIN VREF CIN0, CIN1 15µF CIN10 4.7µF CIN2, CIN3 15µF CIN11 4.7µF + COUT5,6 150µF COUT0 22µF COUT7,8 150µF VOUT 12V 70A MAX COUT1 22µF 47pF 0.22µF ENOUT CLK1 REGSNS TGSR TGSL TGSH BGSH VIN SHDN SS EN/UVLO SYNC INTVCC GND FB 47k 47k IN4448HWT 10nF 22µF L1 6.8µH L0 6.8µH RS0 2.5m/uni03A9 RS1 2.5m/uni03A9 107k 909/uni03A9 12.1k 10k 4.7nF 210k 2.2µF 10µF 2.2µF 1/uni03A9 118k LT3763 CH2 AND CH3 NOT SHOWN 13k VIN 11.5V M0, M1 M4, M5 M6, M7 M18, M19 M2, M6, TG4 BST4 SW4 BG4 ISP4 ISN4 10/uni03A9 0.22µF 1nF CIN8, CIN9 15µF CIN14 4.7µF COUT13,14 150µF COUT4 22µF L4 6.8µH RS4 2.5m/uni03A9 M16, M17 M18, M19 2.2µF 1µF MP 1nF 10nF 20/uni03A9 100pF L0–L4: COILCRAFT SER2915L-682KL M0–M19: INFINEON BSC100N06LS3 MP: ZETEX ZXMP10A18G CIN0–CIN9: MURATA KRM55WR72A156MH01K CIN10–CIN14: MURATA GRJ32DC72A475KE11L COUT0–COUT4: MURATA GRM32ER71C226MEA8L COUT5–COUT14: PANASONIC 16SVP150M RS0–RS4: PANASONIC ERJMP4PF2M5U D0–D4: BAT46WJ 15k 150k IVINN IVINP VIN VC 470k NTCT 10/uni03A910/uni03A9 ILIM PHS1 PHS2 PHS3 RT/MS SYNC MODE TGBUF BGBUF CLK2 IAMPP IAMPN GND REGIS REGDRV REG VCC REG CTRL1 CTRL2 RT VIN

Rev. 0 For more information www.analog.com TYPICAL APPLICATIONS Ten Phase Bidirectional Expander System Direction Change from Buck to Boost (15A per Phase) 50ms/DIV IL4 20A/DIV IL3 20A/DIV IL1 20A/DIV BUCK

8550 TA04c

1µF COUT0 10µF COUT4 100µF COUT5 100µF ISP ISN BST1 TG1 SW1 BG1 ISP1 ISN1 10/uni03A9 1nF 2.2µF CIN1 33µF 1µF COUT2 10µF COUT6 100µF 1µF COUT1 10µF 100pF 10/uni03A9 0.22µF 1nF CIN4 100µF TG2 SW2 BG2 1nF 47k ENOUT CLK1REGSNS TGSL TGSR TGSH BGSH VIN SHDN REGIS REGDRV REG VCC ILIM PHS1 PHS2 PHS3 SYNC RT/MS IAMPP IAMPN CLK2 RUN SYNC SGND PGND VFBHIGH 47k 4.7k 4.7k 47k 4.7k 10nF 22/uni03A9 10/uni03A9 1nF 47k 4.7k L3, 10µH 1m/uni03A9 1m/uni03A9 4.7µF 10µF 169k LT8550 LTC3871-1 PINS FOR POWER STAGE2,3,4 10k 1/uni03A9 4.7µF 205k VHIGH 26V TO 58V 37.5A AT 48V 10nF 47k 0.33µF 499/uni03A90.22µF BST2 DRVCC M4 ×2 M3 ×2 L2, 10µH 7.15k 2.2µF CIN0 33µF CIN3 100µF 1µF TG1 SW1 BG1 VFBLOW 1m/uni03A9 10k 0.33µF 499/uni03A90.22µF BST1 DRVCC ×2 L1 10µH 7.15k SNS2 SNSD2 EXTVCC SNS1 SNSD1 TGBUF BGBUF MODE GND PGATE PGATE VHIGH VHIGH1 5/uni03A9 M9 ×2 215k 10k 603k 10k OVHIGH UVHIGH ITHHIGH ITHLOW 102k 10k OVLOW 4.7µF 4.7µF 0.1µF 0.1µF 47pF 4.53k 10nF 3.01k 100pF DRVSET 10pF 35.7k IMON FREQ VLOW SNSA2 SNSA1 392k 10k M10 ×2 M5 ×2 M6 ×2 M12 ×2 M7 ×2 M8 ×2 DRVCC SS SETCUR BUCK SETCUR BUCK

8550 TA05a

2.2µF CIN2 33µF 1µF COUT3 10µF COUT7 100µF 100pF 10/uni03A9 0.22µF 1nF CIN5 100µF POWER STAGE 2 POWER STAGE 3 POWER STAGE 4 ENOUT CLK1REGSNS TGSL TGSR TGSH BGSH VIN SHDN REGIS REGDRV REG VCC ILIM PHS1 PHS2 PHS3 SYNC RT/MS IAMPP IAMPN CLK2 L4, 10µH 1m/uni03A9 4.7µF 10µF 169k LT8550 PINS FOR POWER STAGE2,3,4 10k 1/uni03A9 4.7µF 1nF 10/uni03A9 VHIGH TGBUF BGBUF REG2REG REG2 REG2 VHIGH VLOW 12V 150A 90.9k VHIGH5 PGATE VHIGH M13 ×2 VHIGH4 VHIGH5 POWER STAGE 2 POWER STAGE 3 POWER STAGE 4 VHIGH3 PGATE VHIGH M11 ×2 VHIGH3 VHIGH2 MODE GND L1–L4: WURTH ELEKTRONIK 7443641000 M1–M8: VISHAY SQJA84EP M9–M13: VISHAY SUD50P08 MP: ON FDMS86263P CIN0–CIN2: PANASONIC EEE-FK1K330P CIN3–CIN5: SUN 100CE100KXT COUT0–COUT3: MURATA GRM31CR71E106KA12L COUT4–COUT7: PANASONIC EEHZA1E101XP RS0–RS4: VISHAY WSL20101L000FEA18

Rev. 0For more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION 7.00 ±0.10 (2 SIDES) NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT , SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONL Y A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (SEE NOTE 6) PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45°C CHAMFER 0.40 ±0.10 5251 BOTTOM VIEW—EXPOSED PAD TOP VIEW SIDE VIEW

6.50 REF

(2 SIDES) 8.00 ±0.10 (2 SIDES)

5.50 REF

(2 SIDES)0.75 ±0.05 0.75 ±0.05 R = 0.115 TYP R = 0.10 TYP 0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05 6.45 ±0.10 5.41 ±0.10 0.00 – 0.05 (UKG52) QFN REV Ø 0306 (2 SIDES) 5.41 ±0.05 6.45 ±0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.70 ±0.05 6.10 ±0.05 7.50 ±0.05 0.25 ±0.05 52-Lead Plastic QFN (7mm × 8mm) (Reference LTC DWG # 05-08-1729 Rev Ø)

Rev. 0 For more information www.analog.com  ANALOG DEVICES, INC. 2019 www.analog.com RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LT3741 High Power , Constant Current, Constant Voltage, Step-Down Controller Fixed 200kHz to 1MHz Operating Frequency, ±6% Current Regulation, 6V ≤ VIN ≤ 36V, VOUT Up to (VIN – 2V) LTC3851A-1 No RSENSE™ Wide VIN Range Synchronous Step-Down DC/DC Controller Phase-Lockable Fixed Operating Frequency, 250kHz to 750kHz, 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 5.25V, MSOP-16E, 3mm × 3mm QFN-16, SSOP-16 LT3763 60V High Current Step-Down LED Driver Controller Fixed 200kHz to 1MHz Operating Frequency, ±6% current Regulation, ±1.5% Voltage Regulation Accuracy, 6V ≤ VIN ≤ 60V, VOUT Up to 55V LTC3871 Bidirectional PolyPhase Synchronous Buck or Boost Controller Phase=Lockable Fixed Operating Frequency, 60kHz to 460kHz, Up to 97% Efficiency, VHIGH Up to 100V, VLOW Up to 30V, ±1.5% Voltage Regulation Accuracy Over Temperature LTC7801/ LTC3895 150V Low IQ, Synchronous Step-Down DC/DC Controller Wide VIN Range: 4V to 140V, Wide output Voltage Range: 0.8V to 60V, 24-Lead 4mm × 5mm QFN, TSSOP-24, TSSOP-38(31) Five Phase 5V/100A Buck Phase Expander System VIN REG 10nF 1nF VIN POWER STAGE 1 MP REG 10/uni03A9 10/uni03A9 33nF SENSE– SENSE+ HG CBOOT SW LG 100µF 10µF + 150µF 10µF VOUT 5V/100A 220nF ENOUT CLK1 REGSNS TGSR TGSHBGSHTGSL SS EN/UVLO SYNC VCC_INT GND FB 47k 22µF L0 1.3µH 2.5m/uni03A9 38.3k 12.1k 10k 4.7nF 200k LT3741 M1 2.2µF 100k VC RHOT 45.3k RNTC 470k 1/uni03A9 CTRL1 VREF CTRL2 VIN RT ISP ISN 10/uni03A9 1nF 470pF 10/uni03A9 220nF 1nF POWER STAGE 2 POWER STAGE 3 POWER STAGE 4 VIN 1.3µH 2.5m/uni03A9 1µF 4.7µF LT8550 PINS FOR POWER STAGE2,3,4 24.3k 62k 109k 1/uni03A9 4.7µF VIN 10V TO 36V

8550 TA06

100µF 10µF 150µF 10µF REG 1µF L0, L1: WURTH ELEKTRONIK 7443551300 M1–M4: INFINEON BSC093N04LSG ISP1 ISN1 BST1 SW1 BG1 TG1 VCC SYNC PHS3 RT/MS IAMPP IAMPN BGBUF TGBUF CLK2 GND SHDN REGIS REGDRV REG PHS1 PHS2 ILIM