LT8491

LT8491 (Rev.0)

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 82

Technical content

Rev. 0For more information www.analog.comDocument Feedback TYPICAL APPLICATION FEATURES DESCRIPTION High Voltage Buck-Boost Battery Charge Controller with Maximum Power Point Tracking (MPPT) and I2C The LT®8491 is a buck-boost switching regulator battery charger that implements a constant-current constant- voltage (CCCV) charging profile used for most battery types, including sealed lead-acid (SLA), flooded, gel and lithium-ion. The device operates from input voltages above, below or equal to the output voltage and can be powered by a solar panel or a DC power supply. On-chip logic provides auto- matic maximum power point tracking (MPPT) for solar powered applications. The LT8491 can perform automatic temperature compensation by sensing an external therm- istor thermally coupled to the battery. The STATUS pin can be used to drive an LED indicator lamp. The device is available in a low profile (0.75mm) 7mm × 11mm 64-lead QFN package. Simplified Solar Powered Battery Charger Schematic Maximum Power Point T racking

APPLICATIONS

n VIN Range: 6V to 80V n VBAT Range: 1.3V to 80V n Single Inductor Allows VIN Above, Below, or Equal to VBAT n Automatic MPPT for Solar Powered Charging n Automatic Temperature Compensation n I2C Telemetry and Configuration n Internal EEPROM for Configuration Storage n Operation from Solar Panel or DC Supply n Four Integrated Feedback Loops n Synchronizable Fixed Frequency: 100kHz to 400kHz n 64-Lead (7mm × 11mm × 0.75mm) QFN Package n Solar Powered Battery Chargers n Multiple Types of Lead-Acid Battery Charging n Li-Ion Battery Charger n Battery Equipped Industrial or Portable Military Equipment All registered trademarks and trademarks are the property of their respective owners. L T8491 SOLAR PANEL TG1 BOOST1 CSNIN CSPIN V IN CSPOUT CSNOUT EXTVCC AVDD TEMPSENSEGATEVCC INTVCC SDA SCL SW1 BG1 CSP CSN STATUS CA AVDD BG2 SW2 BOOST2 TG2 GND RECHARGABLE BATTERY LOAD THERMISTOR + –

8491 TA01a

GATEVCC´ I2C INTERFACE TELEMETRY STATUS CONTROL CONFIGURATION GATEVCC´ GATEVCC´ VBAT

8491 TA01b

0.5s/DIV VPANEL 6V/DIV IMON_IN 0.2V/DIV PERTURB AND OBSERVE PERTURB AND OBSERVE FULL PANEL SCAN

Rev. 0 For more information www.analog.com TABLE OF CONTENTS

Electrical Characteristics

Typical Performance Characteristics Pin Functions Block Diagram Overview Data: Memory Regions Data: Bytes, Words and Long Words Data: Min/Max Register Values Da Startup Sequence Battery Charging Algorithm S tage 1: Full Constant Current Stage 2: Constant Voltage Stage 3: (Optional) Reduced Constant Voltage Done Charging M aximum Power Point Tracking Telemetry Operation Telemetry: Configuration Settings T elemetry: Acquisition CRC Operation EEPROM Operation E EPROM: Reading EEPROM: Writing T elemetry Registers TELE_TBAT TELE_POUT TELE_PIN TELE_EFF T ELE_IIN TELE_VBAT TELE_VIN TELE_VINR Status Registers STAT_CHARGER STAT_SYSTEM STAT_SUPPLY STAT_TSx_REMAIN STAT_CHRG_FAULTS STAT_VERSION STAT_BOOT_CRC Control The EEPROM CTRL_WRT_TO_BOOT CTRL_EE_WRT_EN Control Other Functions CTRL_HALT_STARTUP CTRL_CHRG_EN CTRL_RESTART_CHIP CTRL_RESET_FLAG CTRL_UPDATE_TELEM Configure The Telemetry C C FG_RIMON_OUT CFG_RSENSE2 C FG_RFBOUT1 CFG_RFBOUT2 CFG_RDACI CFG_RFBIN2 CFG_RFBIN1 Configure Initial Charger Enable CFG_INIT_CHRG_EN

Rev. 0For more information www.analog.com C FG_VS3_25C CF G_S0_UV CFG_S0_S1 CFG_S1_S0 Configure Temperature Fault Limits CFG_TBAT_MIN CFG_TBAT_MAX Configure Stage Timeout Limits CFG_TMR_S0 CFG_TMR_S1 C FG_TMR_S3 Configure Automatic Restart CFG_RSTRT_IN_FLT CFG_RSTRT_IN_DONEA CFG_RSTRT_IN_DONEB CFG_RSTRT_IN_S3 Configure Charge Termination CFG_TERMINATE Configure Misc. CFG_SCAN_RATE_LP CFG_SCAN_RATE CFG_CHRG_MISC Configure Temperature Compensation CFG_TC3, CFG_TC2, CFG_TC1 Configure User Code C FG_USER_CODE Manufacturer Data MFR_DATA1 MFR_DATA2 MFR_DATA3 Hardware Configuration HW Config: Input Voltage Sensing and Modulation .. 61 HW Config: VINR Pin Connections HW Config: Solar Panel Powered Charging HW Config: DC Supply Powered Charging HW Config: Input Current Sense and Limit HW Config: Output Current Sense and Limit HW Config: Current Sense Filtering H W Config: Battery Temperature and Disconnect Sensing HW Config: SHDN Pin Connections HW Config: MODE Pin – Current Conduction Mode . 67 HW Config: Driving an LED with the STATUS Pin I n-Situ Battery Charging Hot-Plugging Considerations S Lithium-Ion Battery Charging Lead-Acid Battery Charging O ptional: Low Power Mode Optional: Output Feedback Resistor Disconnect O Optional: Remote Battery Voltage Sensing Optional: DC Supply Detection Circuit Board Layout Considerations Design Example Typical Applications Package Description Typical Application Related Parts

Rev. 0 For more information www.analog.com PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS VCSP – VCSN, VCSPIN – VCSNIN, SS, CLKOUT, CSP , CSN Voltage RT, FBOUT Voltage 3V to 5V SYNC Voltage SWEN, MODE Voltage 3V to 30V SRVO_IIN, SRVO_IOUT Voltage FBIN, SHDN Voltage CSNIN, CSPIN, CSPOUT, CSNOUT Voltage SW1, SW2 Voltage BOOST1, BOOST2 Voltage 3V to 87V BG1, BG2, TG1, TG2 IOW, ECON, CLKDET Voltage SWENO, STATUS Voltage 3V to VDD + 0.5V FBOW, FBIW, Voltage VINR, FBOR, IIR, IOR Voltage SDA, SCL, CA Voltage Operating Junction Temperature Range Storage Temperature Range (Note 1) TOP VIEW UKJ PACKAGE 64-LEAD (7mm × 11mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB GND FBIR 1 CA 2 TEMPSENSE 3 VDD 4 FBOW 5 FBIW 6 INTVCC 7 SWEN 8 MODE 9 IMON_IN 10 SHDN 11 CSN 12 CSP 13 LDO33 14 FBIN 15 FBOUT 16 IMON_OUT 17 VC 18 SS 19 CLKOUT 20 52 NC

51 STATUS

50 IOW

49 SWENO

48 ECON

45 CSPIN

44 CSNIN

42 CSPOUT

41 CSNOUT

40 EXTV

38 SRVO_FBOUT

37 SRVO_IOUT

36 SRVO_IIN

35 SRVO_FBIN

33 BOOST1

64 IOR

63 SCL

62 GND

61 SDA

59 GND

57 FBOR

56 CLKDET

55 GND

54 VINR

53 IIR

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8491EUKJ#PBF LT8491EUKJ#TRPBF LT8491UKJ 64-Lead (7mm × 11mm) Plastic QFN –40°C to 125°C LT8491IUKJ#PBF LT8491IUKJ#TRPBF LT8491UKJ 64-Lead (7mm × 11mm) Plastic QFN –40°C to 125°C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

Rev. 0For more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS Voltage Supply and Regulators VIN Operating Voltage Range (Note 7) l 6 80 V VIN Quiescent Current Not Switching, VEXTVCC = 0, VDD = AVDD = Float 2.65 4.2 mA VIN Quiescent Current in Shutdown VSHDN = 0V 0 1 µA VDD Quiescent Current IAVDD + IVDD, VDD = AVDD = 3.3V l 2.5 4 6.5 mA EXTVCC Switchover Voltage IINTVCC = 20mA, VEXTVCC Rising l 6.15 6.4 6.6 V EXTVCC Switchover Hysteresis 0.18 V LDO33 Pin Voltage 5mA from LDO33 Pin l 3.23 3.295 3.35 V LDO33 Pin Load Regulation ILDO33 = 0.1mA to 5mA –0.25 –1 % LDO33 Pin Current Limit l 12 17.25 22 mA LDO33 Pin Undervoltage Lockout LDO33 Falling 2.96 3.04 3.12 V LDO33 Pin Undervoltage Lockout Hysteresis 35 mV Switching Regulator Control SHDN Input Voltage High SHDN Rising to Enable the Device l 1.184 1.234 1.284 V SHDN Input Voltage High Hysteresis 50 mV SHDN Input Voltage Low Device Disabled, Low Quiescent Current l 0.35 V SHDN Pin Bias Current VSHDN = 3V VSHDN = 12V µA µA SWEN Rising Threshold V oltage l 1.156 1.206 1.256 V SWEN Threshold Voltage Hysteresis 22 mV MODE Pin Thresholds Discontinuous Mode Automatic DCM/CCM Mode l l 0.4 2.3 V V IMON_OUT Rising threshold for CCM Operation MODE = 0V 168 195 224 mV IMON_OUT Falling threshold for DCM MODE = 0V 95 122 150 mV Voltage Regulation Regulation Voltage for FBOUT VC = 1.2V, EXTVCC = 0 l 1.193 1.207 1.222 V Regulation Voltage for FBIN VC = 1.2V, EXTVCC = 0 l 1.184 1.205 1.226 V FBOUT Pin Bias Current Current Out of Pin 15 nA FBIN Pin Bias Current Current Out of Pin 10 nA Current Regulation Regulation Voltage for IMON_IN and IMON_OUT VC = 1.2V, EXTV CC = 0 l 1.187 1.208 1.229 V IMON_IN Output Current VCSPIN – VCSNIN = 50mV, VCSPIN = 5.025V VCSPIN – VCSNIN = 50mV, VCSPIN = 5.025V VCSPIN – VCSNIN = 0mV, VCSPIN = 5V l l 2.5 11.5 µA µA µA IMON_IN Overvoltage Threshold l 1.55 1.61 1.67 V IMON_OUT Output Current VCSPOUT – VCSNOUT = 50mV, VCSPOUT = 5.025V VCSPOUT – VCSNOUT = 50mV, VCSPOUT = 5.025V VCSPOUT – VCSNOUT = 5mV, VCSPOUT = 5.0025V VCSPOUT – VCSNOUT = 5mV, VCSPOUT = 5.0025V l l 47.5 3.25 2.75 52.5 54.25 6.75 µA µA µA µA IMON_OUT Overvoltage Threshold l 1.55 1.61 1.67 V The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VDD = AVDD = 3.3V, SHDN = 3V unless otherwise noted. (Note 3)

Rev. 0 For more information www.analog.com PARAMETER CONDITIONS MIN TYP MAX UNITS Switching Regulator Oscillator (OSC1) Switch Frequency Range Syncing or Free Running 100 400 kHz Switching Frequency, fOSC RT = 365kΩ RT = 215kΩ RT = 124kΩ l l l 102 170 310 120 202 350 142 235 400 kHz kHz kHz SYNC High Level for Synchronization l 1.3 V SYNC Low Level for Synchronization l 0.5 V SYNC Clock Pulse Duty Cycle VSYNC = 0V to 2V 20 80 % Recommended Min SYNC Ratio, fSYNC/fOSC ¾ f/f CLKOUT Output Voltage HIGH 1mA Out of CLKOUT Pin 2.3 2.45 2.55 V CLKOUT Output Voltage LOW 1mA into CKLKOUT Pin 25 100 mV CLKOUT Duty Cycle TJ = –40°C TJ = 25°C TJ = 125°C 22.7 44.1 Charging Control ST ATUS, FBOW , FBIW , SWENO, IOW , ECON Output Low Voltage IOL = 5mA l 0.22 0.5 V STATUS, FBOW , FBIW , SWENO, IOW , ECON Output High Voltage IOH = –5mA l 2.7 3 V Power Supply Mode Detection Threshold (Note 6) VINR Pin Falling l 155 174 mV Power Supply Mode Detection Threshold Hysteresis (Note 6) 29 mV Minimum VINR Voltage for Startup (Note 6) Not in Power Supply Mode Low Power Mode Enabled Low Power Mode Disabled l l 380 213 395 225 410 237 mV mV High Charging Current Threshold on IOR (Note 6) IOR Rising → ECON Rising l 168 195 224 mV Low Charging Current Threshold on IOR (Note 6) IOR Falling → ECON Falling l 95 122 150 mV Minimum TEMPSENSE % of AVDD to Detect Battery Disconnected (Note 6) l 94.5 96 97.5 % VCSPOUT – VCSNOUT Threshold for C/5 Detection (Note 6) VCSxOUT Common Mode = 5.0V, RTOTAL from IMON_OUT to Ground = 24.3kΩ 9 10 11 mV VCSPOUT – VCSNOUT Threshold for C/10 Detection (Note 6) VCSxOUT Common Mode = 5.0V, IOR Falling, RTOTAL from IMON_OUT to Ground = 24.3kΩ 4.25 5 5.75 mV FBIW , FBOW PWM Frequency (OSC2) 31.25 kHz FBIW , FBOW PWM Resolution 8 bits Internal A/D Resolution 10 bits The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VDD = AVDD = 3.3V, SHDN = 3V unless otherwise noted. (Note 3)

Rev. 0For more information www.analog.com Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Do not force voltage on the V C pin. Note 3: The LT8491E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8491I is guaranteed over the full –40°C to 125°C junction temperature range. Note 4: Do not apply a voltage or current source to these pins. They must be connected to capacitive loads only; otherwise permanent damage may occur . Note 5: Negative voltages on the SW1 and SW2 pins are limited in the applications by the body diodes of the external NMOS devices M2 and M3 or parallel Schottky diodes when present. The SW1 and SW2 pins are tolerant of these negative voltages more than one diode drop below ground, guaranteed by design. Note 6: These thresholds are measured by the internal A/D converter . The A/D reference voltage is AV DD. AVDD, VDD and an additional 2.8mA load are regulated by LDO33 to create the AVDD reference for these measurements. The absolute threshold voltages will shift with corresponding changes in the AV DD voltage. Note 7: 10V minimum VIN required for solar powered start-up if low power mode is enabled. Note 8: The EEPROM has an endurance of at least 100,000 write/erase cycles. Data retention of 20 years at 85°C, 100 years at 25°C. These statements are based on published information from vendor . Note 9: A master device must provide a hold time of at least 300ns for the SDA signal (referred to the minimum V IH of the SCL signal) to bridge the undefined region of the SCL falling edge. PARAMETER CONDITIONS MIN TYP MAX UNITS EEPROM Characteristics Endurance (Note 8) 0°C < TJ < 85°C During EEPROM Write Operations 100,000 Cycles Digital Input/Output SCL, SDA SDA Input Voltage High (V SDA_VIH) l 2.25 V SDA Input Voltage Low (VSDA_VIL) l 0.65 V SCL Input Voltage High (VSCL_VIH) l 2.25 V SCL Input Voltage Low (VSCL_VIL) l 0.65 V SDA Input Leakage Current (ILEAK_SDA) SDA = 0V and 3.3V l <0.05 ±1 µA SCL Input Leakage Current (ILEAK_SCL) SCL = 0V and 3.3V l <0.05 ±1 µA SDA Output Low Voltage (VSDA_OL) 3mA into SDA Pin l 0.4 V I2C Timing Characteristics Serial Clock Frequency (fSCL) l 100 kHz Serial Clock Low Period (tLOW) l 4.7 µs Serial Clock High Period (tHIGH) l 4 µs Bus Free Time Between Stop and Start (tBUF) l 4.7 µs Start Condition Hold Time (tHD,STA) l 4 µs Start Condition Setup Time (tSU,STA) l 4.7 µs Stop Condition Setup Time (tSU,STO) l 4 µs Data Hold Time (tHD,DAT) (Note 9) l 0 ns Data Setup Time (tSU,DAT) l 250 ns The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VDD = AVDD = 3.3V, SHDN = 3V unless otherwise noted. (Note 3)

Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Solar Powered Charging Lead-Acid Battery Solar Powered Charging Lithium-Ion Battery Solar Powered Charging Lithium- Ion Battery – C/10 Termination Power Supply Mode Charging Lead-Acid Battery STATUS, SDA, SCL V OH and VOL (VDD = AVDD = 3.3V) LDO33 Load Regulation (Not Connected to AV DD and VDD) IMON Output Currents FBOUT , FBIN, IMONIN, IMONOUT Voltage Rise vs Power PARTL Y CLOUDY SUNSET VBAT IBAT TIME OF DAY 9AM 8PM 2.5 5.0 7.5 10.0 12.5 15.0 17.5 VBAT (V) AND IBAT CHARGING STAGE

8491 G01

|IPIN| (mA) VSTATUS (V)

8491 G05

–40°C 125°C 25°C –40°C 125°C VOH VOL 25°C STATUS ONL Y LOAD CURRENT (mA) LDO33 (V) 3.1 3.3 3.4 3.2

8491 G06

25°C –40°C 125°C CSxIN-CSxOUT (mV) –100 PIN CURRENT (µA) 175 200 125 150 100 –25 0 50

8491 G07

200–50 100 150 IMON_OUT IMON_IN INTVCC REGULATOR POWER (W) VOL TAGE RISE (%) 0.2 1.0 0.6 0.8 0.4 0.5

8491 G08

21 1.5 INTVCC REGULATED FROM VIN INTVCC REGULATED FROM EXTVCC PARTL Y CLOUDY STAGE 1 STAGE 2 VBAT IBAT TIME OF DAY 10AM 12PM VBAT (V) IBAT (A)

8491 G02

< C/10 PARTL Y CLOUDY STAGE 1 STAGE 2 VBAT IBAT TIME OF DAY 9AM 12PM VBAT (V) IBAT (A)

8491 G03

< C/10 VBAT IBAT VIN = 36V CHARGING TIME (HOURS) 2.5 5.0 7.5 10.0 12.5 15.0 VBAT (V) AND IBAT CHARGING STAGE

8491 G04

Rev. 0For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS Max Power Point T racking Perturb and Observe Perturb and Observe Perturb and Observe Max Power Point T racking Full Panel Scan Single Power Peak Full Panel Scan – Partially Shaded with Dual Power Peaks Panel Voltage in Low Power Mode Panel Voltage in Low Power Mode

8491 G09

IMON_OUT 500mV/DIV PERTURB AND OBSERVE FIGURE 37 APPLICATION

8491 G10

0.5s/DIV VPANEL 5V/DIV IMON_OUT 200mV/DIV FIGURE 37 APPLICATION

8491 G11

0.5s/DIV VPANEL 5V/DIV IMON_OUT 100mV/DIV FIGURE 37 APPLICATION

8491 G12

IMON_OUT 500mV/DIV ROTATE PANEL TOWARDS THE SUN PANEL VOL TAGE AND CURRENT ARE AUTOMATICALL Y ADJUSTED TO NEW MAX POWER POINT FIGURE 37 APPLICATION

8491 G13

0.5s/DIV VPANEL 10V/DIV IMON_OUT 500mV/DIV IMON_IN 500mV/DIV FIGURE 37 APPLICATION POWER PEAK

8491 G15

IMON_OUT 50mV/DIV SWEN 5V/DIV 29.4V 17.75V3.3V FIGURE 37 APPLICATION

8491 G14

0.5s/DIV VPANEL 10V/DIV IMON_OUT 500mV/DIV IMON_IN 500mV/DIV LOWER POWER PEAK MAX POWER PEAK FIGURE 37 APPLICATION

8491 G16

IMON_OUT 50mV/DIV SWEN 5V/DIV 16.0V 3.3V FIGURE 37 APPLICATION

Rev. 0 For more information www.analog.com PIN FUNCTIONS FBIR (Pin 1): A/D Input Pin. Connects to FBIN pin to mea- sure input voltage. CA (Pin 2): A/D Input Pin. Connects to a resistor divider to program the I2C address. This pin is measured during the power up sequence. TEMPSENSE (Pin 3): A/D Input Pin. Connects to a therm- istor divider network for sensing battery temperature or a resistor divider if unused. This pin is frequently monitored for temperature compensation and enforcing temperature limits. VDD (Pin 4): I2C and Control Logic Power Supply Pin. Connect this pin to LDO33 and AVDD. FBOW (Pin 5): PWM Digital Output Pin. Connects to FBOUT through an RCR network to temperature com - pensate the battery voltage. FBIW (Pin 6): PWM Digital Output Pin. Connects to FBIN through an RCR network to adjust the solar panel voltage for MPPT . INTVCC (Pin 7): Internal 6.35V Regulator Output Pin. Connects to the GATEV CC pin. INTV CC is powered from EXTVCC when the EXTV CC voltage is higher than 6.4V, otherwise INTVCC is powered from V IN. Bypass this pin to ground with a minimum 4.7µF ceramic capacitor . See HW Config: MODE Pin - Current Conduction Mode for additional details. SWEN (Pin 8): Switch Enable Pin. Tie to the SWENO pin. MODE (Pin 9): Mode Pin. The voltage applied to this pin sets the operating mode of the switching regulator . Tie this pin to INTVCC to make discontinuous current mode active. Tie this pin to ground to operate in discontinuous current mode for low battery charging currents and con- tinuous current mode for high battery charging currents. Do not float this pin. See HW Config : MODE Pin - Current Conduction Mode for additional details. IMON_IN (Pin 10): Input Current Monitor and Limit Pin. The current out of this pin is proportional to the input cur- rent. See the Applications Information section for more information. SHDN (Pin 11): Shutdown Pin. In conjunction with the UVLO (undervoltage lockout) circuit, this pin is used to enable/disable the chip. Do not float this pin. CSN (Pin 12): The (–) Input to the Inductor Current Sense and Reverse Current Detect Amplifier . CSP (Pin 13): The (+) Input to the Inductor Current Sense and Reverse Current Detect Amplifier . The VC pin voltage and built-in offsets between the CSP and CSN pins set the inductor current trip threshold. LDO33 (Pin 14): 3.3V Regulator Output. This pin pro - vides power to the VDD and AVDD pins. Bypass this pin to ground with a minimum 4.7µF ceramic capacitor . FBIN (Pin 15): Input Feedback Pin. This pin is connected to the input error amplifier input. FBOUT (Pin 16): Output Feedback Pin. This pin connects the error amplifier input to an external resistor divider from the output. IMON_OUT (Pin 17): Output Current Monitor and Limit Pin. The current out of this pin is proportional to the aver- age output current. See the Applications Information sec- tion for more information. V C (Pin 18): Error Amplifier Output Pin. Tie the external compensation network to this pin. SS (Pin 19): Soft-Start Pin. Place 100nF of capacitance from this pin to ground. Upon start-up, this pin will be charged by an internal resistor to 2.5V. CLKOUT (Pin 20): Switching Regulator Clock Output Pin. CLKOUT will toggle at the same frequency as the switch- ing regulator oscillator (OSC1 on the Block Diagram) or as the SYNC pin but is approximately 180° out-of-phase. CLKOUT can also be used as a temperature monitor of the switching regulator since the CLKOUT duty cycle varies linearly with the junction temperature of the switching regulator . It is connected to the CLKDET pin through an RC filter . The CLKOUT pin can drive capacitive loads up to 200pF.

Rev. 0For more information www.analog.com PIN FUNCTIONS SYNC (Pin 21): To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock needs to exceed 1.3V, and the low level should be less than 0.5V. Drive this pin to less than 0.5V to revert to the internal free-running clock (OSC1 in the Block Diagram). RT (Pin 22): Timing Resistor Pin. Adjusts the switching regulator frequency (OSC1) when SYNC is not driven by a clock. Place a resistor from this pin to ground to set the free-running frequency of OSC1. Do not float this pin. BG1, BG2 (Pin 23/Pin 25): Bottom Gate Drive. Drives the gates of the bottom N-channel MOSFETs between ground and GATEVCC. GATEVCC (Pin 24): Power Supply for Gate Drivers. Must be connected to the INTVCC pin. Do not power from any other supply. Locally bypass to ground. BOOST1, BOOST2 (Pin 33/Pin 27): Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitor connects here. The BOOST1 pin swings from a diode volt- age below GATEVCC up to V IN + GATEVCC. The BOOST2 pin swings from a diode voltage below GATEV CC up to VBAT + GATEVCC. SW1, SW2 (Pin 31/Pin 29): Switch Nodes. The (–) termi- nal of the bootstrap capacitors connect here. TG1, TG2 (Pin 32/Pin 28): Top Gate Drive. Drives the top N-channel MOSFETs with voltage swings equal to GATEVCC superimposed on the switch node voltages. SRVO_FBIN (Pin 35): Open-Drain Logic Output. This pin is pulled to ground when the input voltage feedback loop is active. This pin is unused for most LT8491 applications and can be floated. SRVO_IIN (Pin 36): Open-Drain Logic Output. This pin is pulled to ground when the input current feedback loop is active. This pin is unused for most LT8491 applications and can be floated. SRVO_IOUT (Pin 37): Open-Drain Logic Output. This pin is pulled to ground when the output current feedback loop is active. This pin is unused for most LT8491 applications and can be floated. SRVO_FBOUT (Pin 38): Open-Drain Logic Output. This pin is pulled to ground when the output voltage feedback loop is active. This pin is unused for most LT8491 applica- tions and can be floated. EXTVCC (Pin 40): External V CC Input. When EXTV CC exceeds 6.4V (typical), INTVCC will be powered from this pin. When EXTVCC is lower than 6.22V (typical), INTV CC will be powered from V IN. See HW Config: MODE Pin - Current Conduction Mode for additional details. CSNOUT (Pin 41): The (– ) Input to the Output Current Sense Amplifier . CSPOUT (Pin 42): The (+) Input to the Output Current Sense Amplifier . This pin and the CSNOUT pin measure the voltage across the sense resistor to provide the output current signals. CSNIN (Pin 44): The (–) Input to the Input Current Sense Amplifier . This pin and the CSPIN pin measure the voltage across the sense resistor to provide the instantaneous input current signals. CSPIN (Pin 45): The (+) Input to the Input Current Sense Amplifier . V IN (Pin 46): Main Input Supply Pin. Must be bypassed to local ground plane. ECON (Pin 48): Digital Output Pin. Optional control output signal used to disconnect EXTVCC from the battery when the average charge current drops below a predetermined threshold. SWENO (Pin 49): Digital Output Pin. Connect to SWEN. Enables the switching regulator . A 200k pull-down resistor is required from this pin to ground. IOW (Pin 50): Digital Output Pin. Connects to IMON_OUT through a resistor . By switching the pin between logic low and high impedance, the total RIMON_OUT changes, which changes the output current limit. STATUS (Pin 51): Digital Output Pin. When used with an LED, this signal provides a visual indication of the prog- ress of the charging algorithm.

Rev. 0 For more information www.analog.com PIN FUNCTIONS NC (Pins 52, 60): Not connected. IIR (Pin 53): A/D Input Pin. Connects to IMON_IN to read input current. Used to manage MPPT and for telemetry. VINR (Pin 54): A/D Input Pin. Connects to resistive divider on VIN to measure input voltage. Used for telemetry and to manage MPPT and startup. CLKDET (Pin 56) : A/D Input Pin. Connects to CLKOUT through an RC filter to detect the duty cycle of CLKOUT . Used to manage startup. FBOR (Pin 57): A/D Input Pin. Connects to FBOUT pin to read charger output voltage. Used to manage the charg- ing algorithm. AV DD (Pin 58): A/D Positive Reference Pin. Tie this pin to VDD and LDO33. SDA (Pin 61): I2C Bidirectional Data Pin. SCL (Pin 63): I2C Clock Input Pin (100kHz Maximum). IOR (Pin 64): A/D Input Pin. Connects to IMON_OUT pin to read the charger output current. Used for telemetry and to manage the charging algorithm. GND (Pins 55, 59, 62, Exposed Pad 65): Ground. Tie directly to local ground plane.

9 MODE

13 CSP

12 CSN

16 VIN

20 CLKOUT

21 SYNC

11 SHDN

8 SWEN

36 SRVO_IINNC

10 IMON_IN

15 FBIN

1 FBIR

6 FBIW

3 TEMPSENSE

35 SRVO_FBINNC

Figure 1. Block Diagram

Rev. 0 For more information www.analog.com OPERATION OVERVIEW The LT8491 is a powerful and easy to use battery charging controller with automatic maximum power point track - ing (MPPT), temperature compensation and an I2C inter- face for telemetry, status, control and configuration. The LT8491 is based on the LT8705 buck-boost controller with additional battery charging and MPPT control func- tions. Refer to the LT8705 data sheet for more detailed information about the switching regulator portions of the LT8491 Several reference applications are included in this data sheet to simplify system design. Many battery-charging applications can be implemented using one of the refer - ence applications with little or no modification required. Various charging parameters can be configured via the digital I2C interface and can be made permanent in the on-chip EEPROM. Since the battery charging and MPPT are controlled by the LT8491, no firmware development is required. Interfacing to the I 2C pins is only required to configure and/or monitor the charger . For reference, factory default I2C configuration settings are listed in the I2C Register Map section. The LT8491 includes four different forms of regulation: output current, input current, input voltage and output voltage (EA1 - EA4 respectively as shown in Figure 1). The commanded inductor current is limited by whichever form of regulation requires the lowest voltage on the V C pin. When powered by a solar panel, the MPPT function uses input voltage regulation to locate and track the maximum power point of the solar panel. Input current regulation is used to limit the maximum current drawn from the input supply to safe levels. The output current regulation sets the maximum battery charging current, and the output voltage regulation is used to set the maximum battery charging voltage. The LT8491 offers user configurable charge timers. If a timer has been set and subsequently expires, the LT8491 will halt charging and communicate this through the I interface and the STATUS pin. Options for automatic restart of the charging cycle are discussed later in the Configure Automatic Restart section. The LT8491 also includes a TEMPSENSE pin, which can be connected to an NTC resistor divider network ther - mally coupled to the battery pack. The TEMPSENSE pin can facilitate several functions including temperature compensated charging, battery temperature telemetry, and charging disable when the battery is outside of safe temperature limits. Detection of the NTC resistor can also give an indication to the charger if the battery is connected or not. The LT8491 also provides charging telemetry and status through the I 2C interface and the STATUS pin. Refer to the Telemetry Registers and Status Registers sections for the I2C indicators. The behavior of the STATUS pin is described in the STATUS Indicator Pin section. I2C SERIAL INTERFACE The LT8491 includes a slave I 2C compatible interface facilitating digital control of the charger settings and digi- tal readouts of telemetry and status. The following sub - sections explain how to read and write data to the LT8491. The I2C Register Map and I2C Register Descriptions sec- tions provide detailed descriptions of all the I2C registers and their functions. I2C: START and STOP Conditions When the bus is idle, both SCL and SDA are high. A bus master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high, as shown in Figure 2. When the master has finished communicating with the slave, it issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. I2C: ACKnowledge The acknowledge signal (ACK) is used in handshaking between the transmitter and receiver to indicate that the most recent byte of data was received. When the slave is the receiver , it pulls down the SDA line so that it remains LOW during this pulse to acknowledge receipt of the data. If the slave fails to acknowledge, by leaving SDA high, then the master may abort the transmission by generat- ing a STOP condition. When the master is receiving data

required chip address (A6:A0) depends on the CA pin. action requires four I2C bytes to read one byte of chip data. valid 16-bit telemetry data. repeated for each subsequent word of data that is read. and SCL pins, thus effecting communication on the bus. Figure 2. Data T ransfer Over I2C Bus

8491 F02

Figure 3. I2C Byte-Write T ransaction Figure 4. I2C Byte-Read T ransaction Figure 5. I2C Word-Read T ransaction

8491 F03

8491 F04

8491 F05

Table 1. LT8491 I2C Addressable Memory Regions Telemetry Registers 0x00-0x11 Charging telemetry. Status Registers 0x12-0x1F Charging and system status. Configuration Registers 0x28-0x5B Charger configuration settings. Manufacturer Registers 0x5C-0x61 Manufacturer Data. mismatched bytes (see I2C: Data T ransfer T ransactions). tions for further telemetry information. vided in the Status Registers section. Register Descriptions section. manufacturer data that is determined at the factory.

the EEPROM by writing to appropriate control registers. 2C register address locations. (LSB) is stored at the lower I2C register address location. higher I2C register address and so on. Table 2. Example of TELE_IOUT Word Storage and then DATA1 (0x14) indicating 5.274 Amps. figuration region, are the only data stored as long words. stored as the 32-bit floating point value 0xB AC9D9D3. Table 3. Example of CFG_TC1 Long Word Storage addresses 0x56 through 0x59. data is ignored and not written to the addressed location. sion is denied, the returned data is all zeros.

Table 4. Register Access Permissions (Except Control Region) See EEPROM: Writing section. Except when chip is powered down or the I2C interface has not been activated yet during the startup sequence. read-only bits in the STAT_SYSTEM register . Table 5. Control Region Access Permissions Reserved 0x27 Writes to this reserved register always ignored. Figure 6 illustrates the startup sequence for the LT8491.

CRC checking is discussed in the CRC Operation section. the STAT_SYSTEM→ BOOT_SUCCESS bit is set to 1. Figure 6. Startup Sequence

8491 F06

• ENABLE I2C READ COMMANDS
• ENABLE I2C WRITE TO CTRL_HAL T_STARTUP REGISTER CTRL_HAL T_STARTUP=0X5A CRC_ERR_FACTORY=0 NO NOYES
• I2C INTERFACE IS DISABLED
• SET ALL TELEMETRY AND CONTROL REGISTERS TO DEFAUL T VALUES
• SET ALL STATUS REGISTERS TO THEIR APPROPRIATE VALUES
• SET BOOT_SUCCESS TO 1
• COPY BOOT_INIT_CHRG_EN TO CTRL_CHRG_EN SET CONFIGURATION REGION TO FACTORY DEFAUL T VALUES
• COPY EEPROM BOOT REGION TO CONFIGURATION REGION AND CALCULATE CRC OF CONFIGURATATION REGION
• COMPARE CRC OF CONFIGURATION REGION TO BOOT_CRC
• UPDATE STAT_BOOT_CRC VALUE
• UPDATE CRC_ERR_BOOT BIT
• COMPARE CRC OF FACTORY SETTINGS TO MFR_DATA3
• UPDATE CRC_ERR_FACTORY BIT YES SET SYSTEM_BUSY TO 00b START BATTERY CHARGING SEE FIGURE 8 YES NO CRC_ERR = 0 CHRG_EN = 1

The LT8491 implements a CCCV charging algorithm. assumes constant temperature and adequate input power . battery will vary accordingly. Figure 8 illustrates a flow chart for the charging algorithm. aspects of the algorithm and the related thresholds. Figure 7. Typical Battery Charging Cycle

8491 F07

Rev. 0For more information www.analog.com OPERATION Configure VBAT for Stages 0, 1 and 3 section. Stage 1 is often referred to as bulk charging in the battery charging community. However , this stage will continue to be called Stage 1 for the remainder of this document. Stage 1 charg- ing is indicated in the STAT_CHARGER register when the CHRG_STAGE bits are 001b and the CHRG_LOGIC_ON bit is 1. Stage 2: Constant Voltage In Stage 2, the LT8491 charges the battery to a constant voltage (VS2). This constant voltage stage is indicated for battery voltages above 98% (typical) of the Stage 2 voltage. Stage 2 is often referred to as float charging for lithium-ion batteries and absorption charging for lead- acid batteries. To avoid confusion, this stage is referred to as Stage 2 for the remainder of this document. Stage 2 charging is indicated in the STAT_CHARGER register when the CHRG_STAGE bits are 010b and the CHRG_ LOGIC_ON bit is 1. Charging in Stage 2 typically continues until the output current (IOUT) falls below C/10. Options are available to configure how the charger proceeds from Stage 2. These options include: T erminate charging when IOUT < C/10 T erminate when the Stage 2 timer expires Proceed to Stage 3 when IOUT < C/10 Continue charging in Stage 2 indefinitely Footnotes in Figure 8 indicate the respective I2C configu- ration registers for these options. Stage 3 : (Optional) Reduced Constant Voltage Stage 3 is optionally enabled in the CFG_CHRG_MISC register . In Stage 3 the LT8491 charges the battery with a reduced constant voltage. Stage 3 is often referred to as float charging for lead-acid batteries. It will continue to be called Stage 3 for the remainder of this document. Stage 3 charging is indicated in the STAT_CHARGER register when the CHRG_STAGE bits are 011b and the CHRG_LOGIC_ON bit is 1. Done Charging When done charging, the power stage is disabled, and charging is complete. This is indicated in the STAT_ CHARGER register when the CHRG_STAGE bits are 100b and the CHRG_LOGIC_ON bit is 1. Telemetry acquisition generally continues although some telemetry, related to the battery side of the charger , may be limited as dis - cussed in the Telemetry: Acquisition section. In addition, although some telemetry continues to be acquired, no charging faults will be reported. Restarting the charging, when done charging, can be done in four ways: The charging can be restarted by toggling the control charger enable bit low to high. See the CTRL_CHRG_ EN register description. The charger can be configured to restart automatically under various conditions. See the Configure Automatic Restart section. The charger can be reset by cycling the power

• Issuing a restart chip command while CTRL_CHRG_EN is cleared, will also restart the charger if CFG_INIT_ CHRG_EN is set. See the CTRL_RESTART_CHIP reg - ister description. Charging Faults The LT8491 periodically monitors for the following fault conditions, on a priority basis, while the charging logic is on (STAT_CHARGER→ CHRG_LOGIC_ON=1) and the charger isn’ t in an input UVLO condition (STAT_SUPPLY→VIN_UVLO=0): VBAT too low for charging Batter y temperature too low for charging Batter y temperature too high for charging Batter y disconnected Stage timer expired and configured to be a fault, indi- cating that charging took too much time These faults are reported in the STAT_CHRG_FAULTS register . Detailed information about each fault bit and its’ source is provided in the register’s data sheet section.

Figure 8. LT8491 Charging Algorithm

8491 F08

NOTE: IF VBAT FALLS BELOW THE VS1_S0 THRESHOLD WHILE IN STAGE 2 OR STAGE 3, THE CHARGING ALGORITHM WILL RESET .

Rev. 0For more information www.analog.com OPERATION Any active fault causes the charging to stop, the stage timers to pause their countdown, and the status to be reported as follows:

• STAT_CHARGER →CHRG_FAULT= 1, indicating the presence of a fault. STAT_CHARGER →CHRG_STAGE holds its last value.
• STAT_CHRG_FAULTS indicates the source of the fault.
• STAT_SUPPLY →SOLAR_STATE=000b. ST ATUS pin indication. See Table 25. After a fault is detected, the LT8491 typically continues to monitor for the presence of faults and, when no faults are present, the charging resumes or restarts. However , this behavior depends on the CFG_RSTRT_IN_FLT register settings discussed in the Configure Automatic Restart section and below. Telemetry acquisition generally contin- ues during a fault although some telemetry, related to the battery side of the charger , may be limited as discussed in the Telemetry: Acquisition section. Faults are monitored on a priority basis as follows:
• Batter y Disconnect Fault: (BAT_DISCON_FLT=1) The presence of a battery disconnect fault, as measured at the TEMPSENSE pin, inhibits checking for all faults except this one. As such, the low V BAT and VBAT tem- perature faults are cleared. If CFG_RSTRT_IN_FLT→ NO_RSTRT_ON_DISCON_FLT =1 then the detection of this fault stops the LT8491 from checking the status of all faults and the charging won’t restart until it’s reset or cycled off-then-on via the CHRG_EN control bit.
• TBA T Battery Temperature Fault: ( LOW_TBAT_FLT or HIGH_TBAT_FLT=1) During a T BAT fault the LOW_ VBAT_FLT bit is not updated. If CFG_RSTRT_IN_ FLT→NO_RESUME_ON_TBAT_FLT=1 then the charg- ing won’t resume until the charger is reset or cycled off-then-on via the CHRG_EN control bit.
• S tage Timer Expired Fault : ( TSx_EXPIRED_FLT =1) During a stage timer fault, if CFG_RSTRT_IN_FLT→ NO_RSTRT_ON_VOLTS= 0 and there is no battery disconnect or T BAT fault, the LT8491 measures V BAT every 5 seconds to check if an automatic restart can be initiated. The TELE_VBAT register and the LOW_VBAT_ FLT bit are updated with each new VBAT measurement. During a stage timer fault, if CFG_RSTRT_IN_ FLT→NO_RSTRT_ON_VOLTS=1, then the charging will not restart until the charger (1) is reset or (2) is cycled off-then-on via the CHRG_EN control bit, or (3) automatically restarts due to the CFG_RSTRT_IN_ FLT→RSTRT_ON_TMR_FLT_HRS settings. In addi - tion, the LOW_VBAT_FLT bit is not updated until the charging restarts.
• VBAT Low Fault: ( LOW_VBAT_FLT=1) When LOW_ VBAT_FLT is the only fault present, VBAT is measured once per second to check for higher voltage to restart the charger . However , if CFG_RSTRT_IN_FLT→ NO_ RSTRT_ON_BATLOW_FLT=1 then the charging and VBAT measurements stop until the charger is reset or cycled off-then-on via the CHRG_EN control bit. MAXIMUM POWER POINT TRACKING When powered by a solar panel, the LT8491 employs a proprietary Perturb and Observe algorithm for identify - ing the maximum power point. This algorithm provides accurate MPPT for slow to moderate changes in panel illumination. The panel is also fully scanned periodically to avoid settling on a false maximum power point for long periods of time, in the case of non-uniform panel illumi- nation. The frequency of performing full panel scans can be configured in the CFG_SCAN_RATE and CFG_SCAN_ RATE_LP registers. TELEMETRY OPERATION The LT8491 generates digital telemetry including battery temperature, input and output current, input and output voltage, power and efficiency. The latest measurement results are stored in the read-only telemetry registers summarized in the I2C Register Map and in Table 9. These word-sized values must be read using the I2C word-read transaction to avoid retrieving mismatched bytes (see I2C: Data T ransfer T ransactions)

Table 6. Telemetry Acquisition These six registers hold their last values. Reads return last measured value. ters as discussed in the Configure the Telemetry section. These registers are not configured at the factory. depending on the operating conditions of the LT8491. force some measurement updates to occur . stages is limited as shown in Table 6. must match before the startup sequence can continue. See the Startup Sequence section for more information. EEPROM: Writing section for further details. or the corresponding 52 bytes located in the EEPROM.

that are related to EEPROM operation. Sequence section for more information. during an EEPROM write operation will return zeros.

• STAT_CHARGER →CHRG_LOGIC_ON= 0 indicating that the charging logic is turned off. STAT_SYSTEM →SYSTEM_BUSY=00b indicating that the system is not busy with other operations.
• CTRL_EE_WRT_EN =0xCC to enable EEPROM write capability. When the conditions are met, an EEPROM write operation is initiated by writing an appropriate byte to the CTRL_ WRT_TO_BOOT register . After the register is written, the EEPROM write operation will commence.

Table 7. Summary of CRC-Related Registers Table 8. Summary of EEPROM-Related Registers CRC error was detected in the EEPROM boot region. CTRL_EE_WRT_EN 0x21 Must be written 0xCC to allow writes to the EEPROM. Configuration All registers in this region. 0x28-0x5B Data in EEPROM is copied into these configuration region registers during startup. Contents of these registers can be copied back to the EEPROM boot region.

Rev. 0 For more information www.analog.com OPERATION Copy the Configuration Registers to the EEPROM: The configuration register contents are copied to the boot region of the EEPROM by writing 0x30 to the CTRL_ WRT_TO_BOOT register . This copy command performs the following operations:

• The status of this operation is indicated within the CTRL_WRT_TO_BOOT register where BUSY_ RDY=1, WRITE_FAIL= 0 and WRITE_SUCCESS=0. Also, STAT_SYSTEM→ SYSTEM_BUSY= 10b and STAT_SYSTEM→CRC_ERROR_BOOT=0.
• The configuration register data, located in I2C addresses 0x28 through 0x5B, is copied to the boot region. A CRC of the configuration register data is calculated and written to STAT_CFG_CRC and BOOT_CRC. The boot region is read and verified against the con - figuration region. Any mismatch results in the CTRL_ WRT_TO_BOOT →WRITE_FAIL bit being set. The CRC of the boot region is calculated and written to the STAT_BOOT_CRC register . If STAT_CFG_CRC or the new STAT_BOOT_CRC value don’t match BOOT_CRC then a CRC error is indi - cated by STAT_SYSTEM→ C RC_ERR_BOOT=1 and CTRL_WRT_TO_BOOT→WRITE_FAIL=1.
• Other wise, a successful write operation is indicated by CTRL_WRT_TO_BOOT→ WRITE_SUCCESS=1.
• Finally, CTRL_WRT_TO_BOOT→BUSY_RDY is cleared and STAT_SYSTEM→ SYSTEM_BUSY is cleared to 00b. Approximately 200ms is required to proceed through all of these steps. Restore Factory Defaults: The boot data can be restored to the factory defaults by writing 0x57 to the CTRL_WRT_ TO_BOOT register . The default values are listed in the I2C Register Map section. This restore command perform the following operations:
• The status of this operation is indicated within the CTRL_WRT_TO_BOOT register by setting BUSY_ RDY=1, WRITE_FAIL= 0 and WRITE_SUCCESS=0. Also, STAT_SYSTEM→ SYSTEM_BUSY= 10b and STAT_SYSTEM→CRC_ERROR_BOOT=0. The factor y default values, including BOOT_CRC, are written to the boot region.
• Th e CRC of the boot region is calculated and the STAT_BOOT_CRC status register is updated with the calculated value.
• If the new STAT_BOOT_CRC value does not match BOOT_CRC then a CRC error is indicated by STAT_SYSTEM→ CRC_ERR_BOOT= 1 and CTRL_WRT_TO_BOOT→WRITE_FAIL=1.
• Other wise, a successful write operation is indicated by CTRL_WRT_TO_BOOT→ WRITE_SUCCESS=1.
• Finally, CTRL_WRT_TO_BOOT→BUSY_RDY is cleared and STAT_SYSTEM→ SYSTEM_BUSY is cleared to 00b. Approximately 200ms is required to proceed through all these steps. Note that this operation doesn’t modify any data in the configuration registers. Refer to the CTRL_RESTART_ CHIP register to restart the chip and automatically copy the factory setting into the configuration registers.

Rev. 0For more information www.analog.com I2C REGISTER MAP MEMORY REGION REGISTER NAME I2C REG ADDR SIZE REF PG. BRIEF REG. DESCRIPTION DEFAUL T VALUE DESCRIPTION OF DEFAUL T VALUE Telemetry TELE_TBAT 0x00 Word 30 Battery temperature 0x7FFF Indicates that the value has not been measured yet. TELE_POUT 0x02 Word Output power 0x0000 Charger not on yet. TELE_PIN 0x04 Word Input power 0x0000 Charger not on yet. TELE_EFF 0x06 Word Charger efficiency 0x0000 Charger not on yet. TELE_IOUT 0x08 Word Output current 0x0000 Charger not on yet. TELE_IIN 0x0A Word Input current 0x0000 Charger not on yet. TELE_VBAT 0x0C Word Battery voltage 0x0000 Indicates that the value has not been calculated yet. TELE_VIN 0x0E Word Input voltage measured from the FBIN pin. 0x0000 Indicates that the value has not been calculated yet. TELE_VINR 0x10 Word Input voltage measured from the VINR pin. 0xFFFF Indicates that the value has not been calculated yet. Status STAT_CHARGER 0x12 Byte 34 Charger status 0x00 Charging off. STAT_SYSTEM 0x13 Byte System status - Indicates present system status. STAT_SUPPLY 0x14 Byte Input supply status - Indicates present supply status. STAT_TS0_REMAIN 0x15 Byte Stage 0 limit timer 0xFF No Stage 0 time limit. STAT_TS1_REMAIN 0x16 Byte Stage 1 limit timer 0xFF No Stage 1 time limit. STAT_TS2_REMAIN 0x17 Byte Stage 2 limit timer 0xFF No Stage 2 time limit. STAT_TS3_REMAIN 0x18 Byte Stage 3 limit timer 0xFF No Stage 3 time limit. STAT_CHRG_FAULTS 0x19 Byte Charging fault sources 0x00 No faults. STAT_VERSION 0x1A Byte LT8491 version code 0x00 - Reserved 0x1B Byte Reserved - Reserved STAT_BOOT_CRC 0x1C Word Calculated boot region CRC - Depends on boot region contents. STAT_CFG_CRC 0x1E Word Calculated configuration CRC - Depends on boot region contents. Control CTRL_WRT_TO_BOOT 0x20 Byte 39 Write to EEPROM 0x00 EEPROM writing not initiated. CTRL_EE_WRT_EN 0x21 Byte Enable EEPROM writes 0x00 EEPROM writes not enabled. CTRL_HALT_STARTUP 0x22 Byte 40 Halt startup CRC checks 0x00 Always returns 0x00 on reads. CTRL_CHRG_EN 0x23 Byte Enable/disable charger - See Startup Sequence section. CTRL_RESTART_CHIP 0x24 Byte Restart the LT8491 0x00 Always returns 0x00 on reads. CTRL_RESET_FLAG 0x25 Byte Reset flag 0x01 Indicates that LT8491 has been reset. CTRL_UPDATE_TELEM 0x26 Byte Measure and update telemetry when charging logic is off 0x00 Telemetry update not initiated. Reserved 0x27 Byte Reserved - Reserved Summary Table

Rev. 0 For more information www.analog.com I2C REGISTER MAP MEMORY REGION REGISTER NAME I2C REG ADDR SIZE REF PG. BRIEF REG. DESCRIPTION DEFAUL T VALUE DESCRIPTION OF DEFAUL T VALUE Configuration CFG_RSENSE1 0x28 Word 42 PCB resistor value Copied from EEPROM during startup. See Boot registers in this table for the factory settings.CFG_RIMON_OUT 0x2A Word PCB resistor value CFG_RSENSE2 0x2C Word PCB resistor value CFG_RDACO 0x2E Word PCB resistor value CFG_RFBOUT1 0x30 Word PCB resistor value CFG_RFBOUT2 0x32 Word PCB resistor value CFG_RDACI 0x34 Word PCB resistor value CFG_RFBIN2 0x36 Word PCB resistor value CFG_RFBIN1 0x38 Word PCB resistor value CFG_INIT_CHRG_EN 0x3A Byte 45 Auto start charging after IC startup CFG_VS3_25C 0x3B Byte 46 Stage 3 VBAT at 25°C CFG_UV_S0 0x3C Byte Min. Stage 0 V BAT voltage CFG_S0_UV 0x3D Byte Low VBAT voltage CFG_S0_S1 0x3E Byte Max. Stage 0 V BAT voltage CFG_S1_S0 0x3F Byte Min. Stage 1 V BAT voltage CFG_TBAT_MIN 0x40 Byte 50 Min. battery temperature CFG_TBAT_MAX 0x41 Byte Max. battery temperature CFG_TMR_S0 0x42 Byte 51 Stage 0 time limit CFG_TMR_S1 0x43 Byte Stage 1 time limit CFG_TMR_S2 0x44 Byte Stage 2 time limit CFG_TMR_S3 0x45 Byte Stage 3 time limit CFG_RSTRT_IN_FLT 0x46 Byte 52 Auto-restart when fault CFG_RSTRT_IN_ DONEA 0x47 Byte Auto-restart threshold voltage when done charging CFG_RSTRT_IN_ DONEB 0x48 Byte Auto-restart delay time when done charging CFG_RSTRT_IN_S3 0x49 Byte Auto-restart when in Stage 3 CFG_TERMINATE 0x4A Byte 55 Charging termination options CFG_SCAN_RATE_LP 0x4B Byte 56 Full panel scan rate in LP CFG_SCAN_RATE 0x4C Byte Full panel scan rate CFG_CHRG_MISC 0x4D Byte Miscellaneous charger settings CFG_TC3 0x4E Long Word

58 Temperature coefficient

CFG_TC2 0x52 Temperature coefficient CFG_TC1 0x56 Temperature coefficient CFG_USER_CODE 0x5A Word 59 Write user input data Manufacturer MFR_DATA1 0x5C Word 60 Manufacturer Data - Calculated at production. MFR_DATA2 0x5E Word Manufacturer Data - Calculated at production. MFR_DATA3 0x60 Word Manufacturer Data - Calculated at production.

Rev. 0For more information www.analog.com I2C REGISTER MAP MEMORY REGION REGISTER NAME I2C REG ADDR SIZE REF PG. BRIEF REG. DESCRIPTION DEFAUL T VALUE DESCRIPTION OF DEFAUL T VALUE Boot (EEPROM) BOOT_RSEN SE1 0x88 Word 42 PCB resistor value 0x0000 Must be configured by user . BOOT_RIMON_OUT 0x8A Word PCB resistor value 0x0000 Must be configured by user . BOOT_RSENSE2 0x8C Word PCB resistor value 0x0000 Must be configured by user . BOOT_RDACO 0x8E Word PCB resistor value 0x0000 Must be configured by user . BOOT_RFBOUT1 0x90 Word PCB resistor value 0x0000 Must be configured by user . BOOT_RFBOUT2 0x92 Word PCB resistor value 0x0000 Must be configured by user . BOOT_RDACI 0x94 Word PCB resistor value 0x0000 Must be configured by user . BOOT_RFBIN2 0x96 Word PCB resistor value 0x0000 Must be configured by user . BOOT_RFBIN1 0x98 Word PCB resistor value 0x0000 Must be configured by user . BOOT_INIT_CHRG_EN 0x9A Byte 45 Auto start charging after IC startup 0x00 Don’t start charging automatically after startup. BOOT_VS3_25C 0x9B Byte 46 Stage 3 VBAT at 25°C 0x6B V S3 = 95.7% of VS2. BOOT_UV_S0 0x9C Byte Min. Stage 0 V BAT voltage 0x46 V (UV_S0) = 35% of VS2. BOOT_S0_UV 0x9D Byte Low V BAT voltage 0x3E V (S0_UV) = 31% of VS2. BOOT_S0_S1 0x9E Byte Max. Stage 0 V BAT voltage 0x8C V (S0_S1) = 70% of VS2. BOOT_S1_S0 0x9F Byte Min. Stage 1 V BAT voltage 0x84 V (S1_S0) = 66% of VS2. BOOT_TBAT_MIN 0xA0 Byte 50 Min. battery temperature 0x00 Under temperature fault limit = 0°C. BOOT_TBAT_MAX 0xA1 Byte Max. battery temperature 0x32 Over temperature fault limit = 50°C. BOOT_TMR_S0 0xA2 Byte 51 Stage 0 time limit 0x00 Infinite time limit. BOOT_TMR_S1 0xA3 Byte Stage 1 time limit 0x00 Infinite time limit. BOOT_TMR_S2 0xA4 Byte Stage 2 time limit 0x00 Infinite time limit. BOOT_TMR_S3 0xA5 Byte Stage 3 time limit 0x00 Infinite time limit. BOOT_RSTRT_IN_FLT 0xA6 Byte 52 Auto-restart when fault 0x20 RSTRT_ON_TMR_FLT_HRS = 1hour . NO_RSTRT_ON_VOLTS = 0. NO_RSTRT_ON_DISCON_FLT = 0. NO_RSTRT_ON_BATLOW_FLT = 0. NO_RSTRT_ON_TBAT_FLT = 0. BOOT_RSTRT_IN_ DONEA A7 Byte Auto-restart threshold voltage when done charging 0x00 Don’t restart charging automatically in Charge State Done. BOOT_RSTRT_IN_ DONEB 0xA8 Byte Auto-restart delay time when done charging 0x04 RSTRT_IN_DONE_HRS = 2 hours. BOOT_RSTRT_IN_S3 0xA9 Byte Auto-restart when in Stage 3 0x01 RSTRT_S3_C5_VS3 = 1. BOOT_TERMINATE 0xAA Byte 55 Charging termination options 0x08 S3_TMR_TERM_EN = 1. BOOT_SCAN_RATE_LP 0xAB Byte 56 Full panel scan rate in LP 0x1F Full panel scan every 8.5 minutes. BOOT_SCAN_RATE 0xAC Byte Full panel scan rate 0x0B Full panel scan ever y 3 minutes. BOOT_CHRG_MISC 0xAD Byte Miscellaneous charger settings 0x08 Use V S3 in Stage 2 disabled. LP Mode enabled. Stage 3 disabled. Temperature Compensation disabled. BOOT_T C3 0xAE Long Word

58 Temperature coefficient 0xB41F-

Coefficient = –1.49e-7. BOOT_TC2 0xB2 Temperature coefficient 0x3760- D090 Coefficient = 1.34e-5. BOOT_TC1 0xB6 Temperature coefficient 0xBAC9- D9D3 Coefficient = –1.54e-3. BOOT_USER_CODE 0xBA Word 59 User input data 0x0000 - BOOT_CRC 0xBC Word 60 Expected CRC result for boot region - Expected CRC result for boot region. Default value is factory CRC. This value will change if the user writes EEPROM with new values.

manufacturer reserved values. If the user writes these locations with new values they will not be stored. the data sheet, for additional information. Table 9. Summary of Telemetry Registers the batter y disconnect has been detected.

Rev. 0For more information www.analog.com I2C REGISTER DESCRIPTIONS TELE_POUT I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES DESCRIPTION 0x02 [15:0] Watts • 100 Unsigned Integer 210.6W = 0x5244 5.3W = 0x0212 Calculated power delivered out of the charger This register contains the most recently measured power delivered out of the charger . The value is in Watts multiplied by 100 in an unsigned integer format. TELE_POUT can be converted to Watts by casting it to a floating-point value and dividing the result by 100. TELE_POUT is the product of the most recently calculated TELE_IOUT and TELE_VBAT values. Calculation of TELE_POUT requires that non-zero values are in the following telemetry configuration registers: CFG_ RSENSE2, CFG_RIMON_OUT, CFG_RDACO, CFG_RFBOUT1, CFG_RFBOUT2. The contents of these registers must match the hardware values on the PCB to achieve the correct TELE_POUT values. Reading 0xFFFF from TELE_POUT indicates that one or more of the required configuration registers was set to 0x0000. Related Data Sheet Section: Telemetry Operation TELE_PIN I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES DESCRIPTION 0x04 [15:0] Watts • 100 Unsigned Integer 210.6W = 0x5244 5.3W = 0x0212 Calculated power drawn from the charger ’s supply. This register contains the most recently measured power drawn from the charger’s supply. The value is in Watts multi- plied by 100 in an unsigned integer format. TELE_PIN can be converted to Watts by casting it to a floating-point value and dividing the result by 100. TELE_PIN is the product of the most recently calculated TELE_IIN and either TELE_VINR or TELE_VIN. TELE_VINR is used when powered by a solar panel. TELE_VIN is used when the VINR pin is pulled low to activate the DC supply charging mode. Calculation of TELE_PIN requires that non-zero values are in the following telemetry configuration registers: CFG_ RSENSE1 and, when powered by a DC supply, CFG_RDACI, CFG_RFBIN1, CFG_RFBIN2. The contents of these registers must match the hardware values on the PCB to achieve the correct TELE_PIN values. Reading 0xFFFF from TELE_PIN indicates that one or more of the required configuration registers was set to 0x0000. Related Data Sheet Sections: Telemetry Operation, HW Config: DC Supply Powered Charging TELE_EFF I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES DESCRIPTION 0x06 [15:0] %Efficiency • 100 Unsigned Integer 96.21% = 0x2595 84.75% = 0x211B Calculated charger power efficiency This register contains the most recently measured power conversion efficiency. The value is in % multiplied by 100 in an unsigned integer format. TELE_EFF can be converted to % by casting it to a floating-point value and dividing the result by 100. TELE_EFF is the ratio of the most recently measured TELE_POUT and TELE_PIN. Calculation of TELE_EFF requires that TELE_POUT and TELE_PIN are properly configured. See the data sheet description for those registers for further information. Reading 0xFFFF from TELE_EFF indicates that one or more of the required configuration registers was set to 0x0000. Note: The maximum calculated efficiency value is 99.99%. Related Data Sheet Sections: Telemetry Operation, HW Config: DC Supply Powered Charging

Rev. 0 For more information www.analog.com I2C REGISTER DESCRIPTIONS TELE_IOUT I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES DESCRIPTION 0x08 [15:0] Milliamps Unsigned Integer 5.274A = 0x149A 0.039A = 0x0027 Output current to VBAT. This register contains the most recently measured current flowing out of the charger through the RSENSE2 resistor . The value is in milliamps in an unsigned integer format. TELE_IOUT can be converted to Amps by casting it to a floating- point value and dividing the result by 1000. To determine TELE_IOUT, the LT8491 measures the voltage at the IOR pin which is proportional to the output current as discussed in the HW Config: Output Current Sense and Limit section. Calculation of TELE_IOUT requires that non-zero values are in the CFG_RIMON_OUT and CFG_RSENSE2 registers. The contents of these registers must match the hardware values on the PCB to achieve the correct TELE_IOUT values. Reading 0xFFFF from TELE_IOUT indicates that one or more of the required configuration registers was set to 0x0000. Related Data Sheet Sections: Telemetry Operation, HW Config: Output Current Sense and Limit TELE_IIN I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES DESCRIPTION 0x0A [15:0] Milliamps Unsigned Integer 5.274A = 0x149A 0.039A = 0x0027 Input current from VIN. This register contains the most recently measured current flowing into the charger through the RSENSE1 resistor . The value is in milliamps in an unsigned integer format. TELE_IIN can be converted to Amps by casting it to a floating-point value and dividing the result by 1000. To determine TELE_IIN, the LT8491 measures the voltage at the IIR pin which is proportional to the input current as discussed in the HW Config: Input Current Sense and Limit section. Calculation of TELE_IIN requires that a non-zero value is in the CFG_RSENSE1 register . The contents of this register must match the hardware value on the PCB to achieve the correct TELE_IIN value. Reading 0xFFFF from TELE_IIN indicates that CFG_RSENSE1 was set to 0x0000. Related Data Sheet Sections: Telemetry Operation, HW Config: Input Current Sense and Limit TELE_VBAT I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES DESCRIPTION 0x0C [15:0] Volts • 100 Unsigned Integer 27.42V = 0x0AB6 Charger V BAT output voltage. This register contains the most recently measured V BAT voltage as measured at the FBOR pin. The value is in Volts multiplied by 100 in an unsigned integer format. TELE_VBAT can be converted to volts by casting it to a floating-point value and dividing the result by 100. Proper reporting of TELE_VBAT requires that non-zero values are in the following telemetry configuration registers: CFG_RDACO, CFG_RFBOUT1, CFG_RFBOUT2. The contents of these registers must match the hardware values on the PCB to achieve the correct TELE_VBAT values. The reset default value of TELE_VBAT is 0x0000 indicating that the voltage has not yet been measured. Reading 0xFFFF from TELE_VBAT indicates one or more of the required configura- tion registers was set to 0x0000. Related Data Sheet Sections : Telemetry Operation, HW Config: VBAT in Stage 2 (VS2)

Rev. 0For more information www.analog.com I2C REGISTER DESCRIPTIONS TELE_VIN I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES DESCRIPTION 0x0E [15:0] Volts • 100 Unsigned Integer 27.42V = 0x0AB6 V IN voltage measured from the FBIR pin. This register contains the most recently measured V IN voltage as measured at the FBIR pin. The value is in Volts multiplied by 100 in an unsigned integer format. TELE_VIN can be converted to volts by casting it to a floating-point value and dividing the result by 100. Proper reporting of TELE_VIN requires that non-zero values are in the following telemetry configuration registers: CFG_RDACI, CFG_RFBIN1, CFG_RFBIN2. The contents of these registers must match the hardware values on the PCB to achieve the correct TELE_VIN values. When solar supply operation is detected, TELE_VIN will indicate 0x0000. In this case, read V IN voltage from TELE_VINR instead. The reset default value of TELE_VIN is 0x0000 indicating that the voltage has not yet been measured. Reading 0xFFFF from TELE_VIN indicates one or more of the required configura- tion registers was set to 0x0000. Related Data Sheet Sections : Telemetry Operation, HW Config: Input Voltage Sensing and Modulation TELE_VINR I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES DESCRIPTION 0x10 [15:0] Volts • 100 Unsigned Integer 27.42V = 0x0AB6 V IN voltage measured from the VINR pin. This register contains the most recently measured V IN voltage as measured at the VINR pin. The value is in Volts multi-plied by 100 in an unsigned integer format. TELE_VINR can be converted to volts by casting it to a floating- point value and dividing the result by 100. During low power and V IN pulsing, TELE_VINR reports the valley voltage. TELE_VINR will not accurately represent the VIN voltage when the VINR pin is being pulled low for DC power supply operation (see HW Config: DC Supply Powered Charging). When DC power supply operation is detected TELE_VINR will indicate 0x0000. In this case, read V IN voltage from TELE_VIN instead. The reset default value of TELE_VINR is 0xFFFF indicating that the voltage has not yet been measured. Related Data Sheet Sections: Telemetry Operation, HW Config: Solar Panel Powered Charging, HW Config: DC Supply Powered Charging

tion about each register and its respective data follows this table. Table 10. Summary of Status Registers STAT_TS1_REMAIN BYTE 0x16 Time remaining on Stage 1 limit timer . STAT_TS2_REMAIN BYTE 0x17 Time remaining on Stage 2 limit timer . STAT_TS3_REMAIN BYTE 0x18 Time remaining on Stage 3 limit timer . 0x12 CHRG_FAULT [7] 1 indicates that one or more of the bits in the STAT_CHRG_FAULTS register is 1. 0 indicates that all the STAT_CHRG_FAULTS bits are presently 0. possible telemetry measurements have been made at least once since CHRG_EN has toggled from 0 to 1. 0 indicates that none of the telemetry registers are being periodically updated. Telemetry Registers section for further information. automatically restarts at Stage 0.

Rev. 0For more information www.analog.com I2C REGISTER DESCRIPTIONS I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x12 CHARGING [2] 1 indicates that battery charging is ongoing in one of the 4 charging stages (Stage 0 to 3). 0 indicates that the charging is not active, and the power stage has been turned off. 0 (not charging) is indicated due to any of the following conditions The charging logic is disabled as indicated by CHRG_LOGIC_ON=0 The charging has been stopped due to a fault condition as indicated by CHRG_FAULT=1 The charging has reached the done charging stage CHRG_STAGE=100b The charging logic was recently enabled by setting CHRG_EN=1, but the logic hasn’t started Stage 0 charging yet GT_C10 [1] 0 indicates that the charging current telemetry (TELE_IOUT) is less than C/10. 1 indicates that the charging current telemetry (TELE_IOUT) is greater than C/10. CHRG_LOGIC_ON [ 0] 1 indicates that the charging logic is enabled and some I 2C byte-write transactions will be ignored. Refer to Data: Access Permissions for further information about I2C write permissions. This bit is set to 1 immediately after the CHRG_EN bit, in the CTRL_CHRG_EN register , is set to 1. This bit clears to 0 typically 6ms to 90ms after the CHRG_EN bit is cleared to 0. STAT_SYSTEM I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x13 Reserved [7:6] Reserved BOOT_SUCCESS [5] Indicates that startup was successful and configuration data was copied from the EEPROM boot region with a passing CRC check. More details are available in the Startup Sequence section. CRC_ERR_FACTORY [4] 1 indicates that a CRC check of the factory settings failed. 0 indicates a successful CRC check of the settings. More details are available in the Startup Sequence section. CRC_ERR_BOOT [3] 1 indicates that a CRC check of the boot EEPROM region failed. 0 indicates a successful CRC check of the boot EEPROM. More details are available in the Startup Sequence and EEPROM: Writing sections. SWENO [2] Indicates the present state of the SWENO pin. This pin state may toggle on/off while the charger is enabled as part of its normal operation. SYSTEM_BUSY [1:0] Indicates the status of the internal logic control system. Non-zero values indicate that the system is busy and may have limited ability to handle I2C byte-write commands, as discussed in the Data: Access Permissions section. 00b = Not busy with other tasks 01b = Busy with startup and related CRC checking 10b = Busy with a long operation (EEPROM write or CTRL_UPDATE_TELEM command)

Rev. 0 For more information www.analog.com I2C REGISTER DESCRIPTIONS STAT_SUPPLY I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x14 Reserved [7:5] Reserved VIN_UVLO [4] When powered by a panel: 1 indicates that the input voltage is below 10 Volts if Low Power Mode is enabled, otherwise input voltage is below 5.7 Volts. 0 indicates that the Input Panel Voltage is above 10 Volts if Low Power Mode is enabled, otherwise input panel voltage is above 5.7 Volts. Related Data Sheet Sections: Configure Misc. section PS_OR_SOLAR [3] 1 Indicates that the LT8491 is being supplied by a DC power supply as detected by a low voltage on the VINR pin. MPPT and related functions are disabled. 0 Indicates that the LT8491 is being supplied by a solar panel. Related Data Sheet Sections: HW Config: DC Supply Powered Charging, Optional: DC Supply Detection Circuit, TELE_VINR SOLAR_STATE [2:0] Indicates the operating state of the solar panel: 101b = Battery Limited: The battery may not presently be capable of drawing the maximum power available from the solar panel, therefore the panel may not be operating at the maximum power point. 100b = Full Panel Scan: In this state, a full scan of the solar panel is being performed to make sure that the global maximum power point is being tracked. 011b = Perturb and Observe: The solar panel is tracking a maximum power point. 010b = LP Mode and VIN Pulsing: The available panel current is too low for constant charging. Instead the low power operating mode is active, resulting in pulsing of the panel voltage as discussed in the Optional: Low Power Mode section. 001b = LP Mode and VIN too low: The available panel current is too low for constant charging and the panel voltage is too low to extract charging energy from. See Optional: Low Power Mode section. 000b = None of the Above This is indicated if none of the above conditions exist. Examples may include: the input is not a solar panel; the panel voltage and/or current is not adequate for any of the above operations; a fault has occurred, and no charging is occurring; charger is in done charging state; other conditions may be possible. STAT_TSx_REMAIN I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x15 STAT_TS0_REMAIN [7:0] Time remaining before respective stage timer expires. More details below. 0x16 STAT_TS1_REMAIN [7:0] 0x17 STAT_TS2_REMAIN [7:0] 0x18 STAT_TS3_REMAIN [7:0] These four registers indicate the time remaining in the respective stage timers (Stages 0 to 3). Configuration of the starting values is discussed in the Configure Stage Timeout Limits section. If configured for a finite time limit and powered by a DC power supply, the respective timer will count down while charging in the respective stage. When a timer counts down to 0x00 the charging stops. The CFG_TERMINATE→Sx_TMR_TERM_EN bits determine if an expired timer indicates a fault or not.

Rev. 0For more information www.analog.com I2C REGISTER DESCRIPTIONS The time remaining is approximately 4.47 minutes multiplied by the register value. For example, 0x0D represents 58 minutes remaining. The countdown for each timer pauses when not charging (STAT_CHARGER→CHARGING=0) or a temperature fault occurs. The countdown for a timer also pauses when charging proceeds to the next stage. If either a battery disconnect fault or a low V BAT fault is detected, all countdown timer values are reset. These registers indicate the values of the corresponding CFG_TMR_Sx registers when powered up in solar panel mode (STAT_SUPPLY→PS_OR_SOLAR=0). Related Data Sheet Sections: Configure Stage Timeout Limits, Battery Charging Algorithm, Configure Charge Termination STAT_CHRG_FAULTS I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x19 TS3_EXPIRED_FLT [7] 1 indicates that a charging stage timeout fault has occurred. These fault bits are cleared to 0: When the charging restarts automatically When the charging is disabled by setting CHRG_EN=0. The bits may remain set until STAT_ CHARGER→CHRG_LOGIC_ON indicates 0 During the startup sequence Other wise, one of these fault bits is set when: The charging logic is on ( STAT_CHARGER→CHRG_LOGIC_ON=1) and The respective STAT_TSx_REMAIN register has counted down to 0x00 and The timer ’s expiration is configured to be a fault (the respective Sx_TMR_TERM_EN bit, in the CFG_TERMINATE register , is set to 0) Related Data Sheet Sections: Charging Faults, Configure Stage Timeout Limits, Configure Automatic Restart, Status Registers, Startup Sequence TS2_EXPIRED_FLT [6] TS1_EXPIRED_FLT [5] TS0_EXPIRED_FLT [4] BAT_DISCON_FLT [3] 1 indicates that the battery has been disconnected, as measured at the TEMPSENSE pin. This fault bit is cleared to 0: When the charging is disabled by setting CHRG_EN=0. The bit may remain set until STAT_ CHARGER→CHRG_LOGIC_ON indicates 0 During the startup sequence Other wise, the LT8491 periodically measures the TEMPSENSE pin to check for battery temperature and connection faults as discussed in the Charging Faults section. Related Data Sheet Sections: Charging Faults, HW Config: Battery Temperature and Disconnect Sensing, Configure Temperature Fault Limits, TELE_TBAT, Startup Sequence HIGH_TBAT_FLT [2] 1 in either bit indicates that the battery temperature, as measured from the TEMPSENSE pin, is outside of the allowed battery temperature range. These fault bits are cleared to 0: When the charging is disabled by setting CHRG_EN=0. The bit may remain set until STAT_ CHARGER→CHRG_LOGIC_ON indicates 0 During the startup sequence During a batter y disconnect fault (BAT_DISCON_FLT=1) Otherwise, the LT8491 periodically measures the TEMPSENSE pin to check for battery temperature and connection faults as discussed in the Charging Faults section. Related Data Sheet Sections: Charging Faults, HW Config: Battery Temperature and Disconnect Sensing, Configure Temperature Fault Limits, TELE_TBAT, Startup Sequence LOW_TBAT_FLT [1]

Rev. 0 For more information www.analog.com I2C REGISTER DESCRIPTIONS I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x19 LOW_VBAT_FLT [0] 1 indicates that the low battery voltage fault has been detected. The V BAT thresholds for this fault (VS0_UV and VUV_S0) are configured in the CFG_UV_S0 and CFG_S0_UV registers. This fault bit is cleared to 0: When the charging is disabled by setting CHRG_EN=0. The bit may remain set until STAT_ CHARGER→CHRG_LOGIC_ON indicates 0 During the startup sequence During a batter y disconnect fault (BAT_DISCON_FLT=1) During a low or high batter y temperature fault If the VBAT > VUV_S0 threshold is reached for a pre-determined amount of time Related Data Sheet Sections: Charging Faults, TELE_VBAT, Startup Sequence STAT_VERSION I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x1A - [7:0] LT8491 version information. See I 2C Register Map for factory default value. STAT_BOOT_CRC I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x1C - [15:0] Contains the most recent CRC of the boot region calculated by the LT8491. See CRC Operation for more information. STAT_CFG_CRC I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x1E - [15:0] Contains the most recent CRC of the configuration region calculated by the LT8491. See CRC Operation for more information.

Rev. 0For more information www.analog.com I2C REGISTER DESCRIPTIONS CONTROL THE EEPROM The following registers are used to initiate and monitor EEPROM write operations. Write access permissions are detailed in the Data: Access Permissions section. CTRL_WRT_TO_BOOT I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x20 Reserved [7:3] Reserved WRITE_FAIL [2] Read of this bit returns a 1 if the most recent attempt to write the EEPROM boot region failed. WRITE_SUCCESS [1] Read of this bit returns a 1 if the most recent attempt to write the EEPROM boot region succeeded. BUSY_RDY [0] Read of this bit returns a 1 if a write to the EEPROM boot region is in progress. I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x20 - [7:0] Write to 0x30 to copy the configuration registers to the boot region of the EEPROM. Write to 0x57 to restore the boot region to the factory default settings. This register is used to initiate a write to the EEPROM boot region. It can also be read to monitor status of the write operation. Writing one of two unique byte patterns initiates the desired write operation as listed above. Reading of this register indicates the status of the write operation, also shown above. Writes to this register are only accepted if CTRL_EE_WRT_EN=0xCC and STAT_SYSTEM→SYSTEM_BUSY=00b. Reads are permitted any time that the I interface is operational. Related Data Sheet Sections: EEPROM: Writing, Data: Access Permissions CTRL_EE_WRT_EN I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x21 CTRL_EE_WRT_EN [7:0] This register must be set to 0xCC to allow the on-chip EEPROM to be written. Any other value prohibits the EEPROM from being modified. Setting this register to 0xCC also prohibits writes to the configuration registers. This register must be written to 0xCC before any on-chip EEPROM data can be modified. Any other value prohibits writes to the EEPROM. Note that this register can only be written when STAT_SYSTEM→SYSTEM_BUSY=00b and STAT_CHARGER→CHRG_LOGIC_ON=0. Setting this register to 0xCC also prohibits writes to the configuration registers within addresses 0x28-0x5B until this register is written to a value other than 0xCC. Related Data Sheet Sections: EEPROM: Writing, Data: Access Permissions

respective function follow this table. Table 11. Summary of Other Control Registers information. Returns 0’s on reads. CHRG_EN [0] Discussed below. is set high and is stopped when CHRG_EN is set low. More details are as follows. STAT_CHARGER→CHRG_LOGIC_ON=1. I2C write access is immediately restricted as discussed in the Data: Access Permissions section. y charging, stage timers, and fault checking starts as shown at the top of Figure 8. elemetry acquisition commences as discussed in the Telemetry: Acquisition section. y charger is immediately turned off as indicated by STAT_SYSTEM→SWENO=0. elemetry measurements stop as discussed in the Telemetry: Acquisition section.

• The charger status register STAT_CHARGER normally clears to 0x00. If a fault was present and not cleared before CHRG_EN=0 then its value will be 0x80.

Rev. 0For more information www.analog.com I2C REGISTER DESCRIPTIONS

• The supply status register STAT_SUPPLY→SOLAR_STATE bits [2:0] clear to 000b. The fault register STAT_CHRG_FAULTS holds its last value reported before CHRG_EN=0. The ECON pin is driven low (see Optional : EXTVCC Disconnect section). Some registers cannot be written until the CHRG_LOGIC_ON bit clears in the STAT_CHARGER register . Be sure to poll the CHRG_LOGIC_ON bit before attempting subsequent register writes. After changing the CHRG_EN setting, some operations listed above may not happen immediately unless otherwise indicated. As discussed in the Startup Sequence section, the BOOT_INIT_CHRG_EN value is automatically copied from the EEPROM into this CTRL_CHRG_EN register near the end of the startup sequence. This provides a way to start the charging automatically after startup by storing 0x01 in the BOOT_INIT_CHRG_EN. Related Data Sheet Sections: Data: Access Permissions CTRL_RESTART_CHIP I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x24 - [7:0] Write 0x99 to restart the LT8491. See Startup Sequence section for more information. Returns 0’s on reads. To issue a restart chip command, the CTRL_CHRG_EN register must be cleared. The part will restart after 0x99 is written to the CTRL_RESTART_CHIP register . Upon restarting, the CTRL_CHRG_EN→CHRG_EN bit is set to the value read from the BOOT_INIT_CHRG_EN EEPROM location. Related Data Sheet Sections: Startup Sequence, Data: Access Permissions CTRL_RESET_FLAG I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x25 Reserved [7:1] Reserved RESET_FLAG [0] This bit is set to 1 during startup. It can be cleared by the user after startup completes. Subsequent reading of this bit will indicate if the IC has reset (power cycle) or restarted (write 0x99 to CTRL_ RESTART_CHIP to restart the chip) since the last time the bit was cleared. Related Data Sheet Sections: Startup Sequence, Data: Access Permissions CTRL_UPDATE_TELEM I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x26 Reserved [7:1] Reserved BUSY_RDY [0] Read of this bit returns a 1 while the telemetry update is in progress. I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x26 - [7:0] Write to 0xAA to update telemetry.

are permitted any time that the I2C interface is operational. the feedback divider to measure the battery voltage. Table 12. Summary of Telemetry Configuration Registers TELE_PIN, TELE_EFF, TELE_IIN.

Rev. 0For more information www.analog.com I2C REGISTER DESCRIPTIONS multiplied by 100 in an unsigned integer format. See the examples above. The default value is 0x0000 indicating that this value has not been configured. Related Data Sheet Section: See HW Config: Input Current Sense and Limit for information about RSENSE1 CFG_RIMON_OUT I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES DESCRIPTION 0x2A [15:0] kΩ • 100 Unsigned Integer 95.3kΩ = 0x253A 24.3kΩ = 0x097E RIMON_OUT resistor value. Required for calculate telemetry for TELE_IOUT, TELE_POUT, TELE_EFF. The LT8491 uses this register value to calculate telemetry for the TELE_IOUT, TELE_POUT, and TELE_EFF registers. CFG_RIMON_OUT is not used for any other purpose and does not affect charging in any way. Write this register to indicate the value of the R IMON_OUT output current monitoring resistor . The value written to this register should be RIMON_OUT, in kΩ multiplied by 100 in an unsigned integer format. See the examples above. The default value is 0x0000 indicating that this value has not been configured. Related Data Sheet Section: See HW Config: Output Current Sense and Limit for information about RIMON_OUT CFG_RSENSE2 I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES DESCRIPTION 0x2C [15:0] mΩ • 100 Unsigned Integer 4.7mΩ = 0x01D6 10mΩ = 0x03E8 RSENSE2 resistor value. Required to calculate telemetry for TELE_POUT, TELE_EFF, TELE_IOUT. The LT8491 uses this register value to calculate telemetry for the TELE_POUT, TELE_EFF and TELE_IOUT registers. CFG_RSENSE2 is not used for any other purpose and does not affect charging in any way. Write this register to indicate the value of the RSENSE2 output current sense resistor . The value written to this register should be RSENSE2, in milliohms, multiplied by 100 in an unsigned integer format. See the examples above. The default value is 0x0000 indicating that this value has not been configured. Related Data Sheet Section: See HW Config: Output Current Sense and Limit for information about R SENSE2 CFG_RDACO I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES DESCRIPTION 0x2E [15:0] kΩ • 100 Unsigned Integer 95.3kΩ = 0x253A 24.3kΩ = 0x097E V alue of RDACO1 + RDACO2. Required to calculate telemetry for TELE_VBAT, TELE_POUT, TELE_EFF. The LT8491 uses this register value to calculate telemetry for the TELE_VBAT, TELE_POUT, and TELE_EFF registers. CFG_RDACO is not used for any other purpose and does not affect charging in any way. Write this register to indicate the total value of R DACO1 + RDACO2 in the output feedback divider network. The value written to this register should be the total value of RDACO1 + RDACO2, in kΩ multiplied by 100 in an unsigned integer format. See the examples above. The default value is 0x0000 indicating that this value has not been configured. Related Data Sheet Section: See HW Config: VBAT in Stage 2 (VS2) for information about the RDACO resistors

Rev. 0 For more information www.analog.com I2C REGISTER DESCRIPTIONS CFG_RFBOUT1 I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES DESCRIPTION 0x30 [15:0] kΩ • 10 Unsigned Integer 442kΩ = 0x1144 274kΩ = 0x0AB4 V alue of RFBOUT1. Required to calculate telemetry for TELE_VBAT, TELE_POUT, TELE_EFF. The LT8491 uses this register value to calculate telemetry for the TELE_VBAT, TELE_POUT, and TELE_EFF registers. CFG_RFBOUT1 is not used for any other purpose and does not affect charging in any way. Write this register to indicate the value of RFBOUT1 in the output feedback divider network. The value written to this register should be R FBOUT1, in kΩ multiplied by 10 in an unsigned integer format. See the examples above. The default value is all 0’s indicating that this value has not been configured. Related Data Sheet Section: See HW Config: VBAT in Stage 2 (VS2) for information about RFBOUT1 CFG_RFBOUT2 I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES DESCRIPTION 0x32 [15:0] kΩ • 100 Unsigned Integer 10kΩ = 0x03E8 20kΩ = 0x07D0 V alue of RFBOUT2. Required to calculate telemetry for TELE_VBAT, TELE_POUT, TELE_EFF. The LT8491 uses this register value to calculate telemetry for the TELE_VBAT, TELE_POUT, and TELE_EFF registers. CFG_RFBOUT2 is not used for any other purpose and does not affect charging in any way. Write this register to indi- cate the value of RFBOUT2 in the output feedback divider network. The value written to this register should be RFBOUT2, in kΩ multiplied by 100 in an unsigned integer format. See the examples above. The default value is all 0’s indicating that this value has not been configured. Related Data Sheet Section: See HW Config: V BAT in Stage 2 (VS2) for information about RFBOUT2 CFG_RDACI I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES DESCRIPTION 0x34 [15:0] kΩ • 100 Unsigned Integer 95.3kΩ = 0x253A 24.3kΩ = 0x097E V alue of RDACI1 + RDACI2. Required to calculate telemetry for TELE_VIN. Also required for TELE_PIN and TELE_EFF telemetry when powered by a DC power supply. The LT8491 uses this register value to calculate telemetry for the TELE_VIN register . It is also used to calculate telem- etry for TELE_PIN and TELE_EFF when powered by a DC power supply. CFG_RDACI is not used for any other purpose and does not affect charging in any way . Write this register to indicate the total value of R DACI1 + RDACI2 in the input feedback divider network. The value written to this register should be the total value of RDACI1 + RDACI2, in kΩ multi- plied by 100 in an unsigned integer format. See the examples above. The default value is 0x 0000 indicating that this value has not been configured. Related Data Sheet Sections : HW Config : Input Voltage Sensing and Modulation, HW Config: DC Supply Powered Charging

alue of RFBIN2. Required to calculate telemetry for TELE_VIN. powered by a DC power supply. network. The value written to this register should be R FBIN2, in kΩ multiplied by 100 in an unsigned integer format. See the examples above. The default value is 0x0000 indicating that this value has not been configured. divider network. The value written to this register should be RFBIN1, in k multiplied by 10 in an unsigned integer format. See the examples above. The default value is 0x0000 indicating that this value has not been configured. Table 13. Summary of Register to Configure Initial Charger Enable INIT_CHRG_EN [0] Value of this bit is copied to CTRL_CHRG_EN during the startup sequence if CRC error checking passes.

value, the default register value will be used instead. Table 14. Summary of Stage 0, 1 and 3 VBAT Configuration Registers voltage (VS2) at 25°C. It has a resolution of 0.1% per bit. Configure Temperature Compensation section. VS2 (25°C) is set by external resistors as discussed in the HW Config: VBAT in Stage 2 (VS2) section. Example: Presume that VS2 (25°C) is set to 14.2V, via external resistors, and we wish to configure VS3 (25°C) = 13.59V.

Rev. 0For more information www.analog.com I2C REGISTER DESCRIPTIONS Related Data Sheet Sections: Battery Charging Algorithm, HW Config: V BAT in Stage 2 (V S2), Configure Temp. Compensation, CFG_CHRG_MISC CFG_UV_S0 I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES MIN VALUE MAX VALUE DESCRIPTION 0x3C [7:0] 200 • (% of V S2) Unsigned Integer 30% = 0x3C 55.5% = 0x6F = 0x00 90% = 0xB4 Configure V UV_S0 voltage as percentage of VS2. Resolution of 0.5% per bit. This register sets VUV_S0, the minimum VBAT voltage required to exit the low V BAT fault condition and enter Stage 0 charging. This effectively sets the minimum battery voltage required to start charging. V UV_S0 is a percentage of the Stage 2 voltage VS2. Therefore, if Stage 2 temperature compensation is enabled, via the CFG_CHRG_MISC→TC_ENABLE bit, VUV_S0 will vary with temperature in proportion to VS2. Setting CFG_UV_S0 = 0x00 effectively disables the minimum VBAT voltage checking to enter Stage 0. Consider setting CFG_UV_S0 = 0x00, for example when charging a lithium-ion battery that uses battery undervoltage protection circuitry. CFG_UV_S0 is an 8-bit unsigned integer , representing a percentage of VS2 between 0% to 90% and is calculated as follows: CFG_UV_S0= 200 • VUV _S0 VS2

• 100%⎡ Example: Presume that VS2 is set to 14.2V and we wish to set VUV_S0 = 7.81V. Set CFG_UV_S0 as follows: CFG_UV_S0= 200 • 7.81V 14.2V •100%⎡ = 200 •[55%] = 110 (decimal) = 0x6E (hexadecimal) Therefore, writing CFG_UV_S0 to 0x6E configures V UV_S0 to be 55% of V S2. Be sure to set CFG_UV_S0 to a higher VS2 percentage than CFG_S0_UV to achieve threshold hysteresis and avoid oscillating between stages. A 4%, or more, difference is recommended. Also, be sure to set CFG_UV_S0 lower than CFG_S1_S0 to avoid stage selection oscilla- tions. A 4%, or more, difference is also recommended. Related Data Sheet Sections: Charging Faults, Battery Charging Algorithm, HW Config: VBAT in Stage 2 (VS2), Configure Temp. Compensation CFG_S0_UV I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES MIN VALUE MAX VALUE DESCRIPTION 0x3D [7:0] 200 • (% of V S2) Unsigned Integer 30% = 0x3C 55.5% = 0x6F = 0x00 90% = 0xB4 Configure V S0_UV voltage as percentage of VS2. Resolution of 0.5% per bit.

Rev. 0 For more information www.analog.com I2C REGISTER DESCRIPTIONS This register is used to set VS0_UV, the falling VBAT threshold to exit Stage 0 charging and enter the low VBAT fault con- dition. VS0_UV is a percentage of the Stage 2 voltage VS2. Therefore, if Stage 2 temperature compensation is enabled, via the CFG_CHRG_MISC→TC_ENABLE bit, VS0_UV will vary with temperature in proportion to VS2. CFG_S0_UV is an 8-bit unsigned integer , representing a percentage of VS2 between 0% to 90% and is calculated as follows: CFG_S0_UV= 200 • VS0_UV VS2

• 100%⎡ Example: Presume that VS2 is set to 14.2V and we wish to configure VS0_UV = 7.1V. Set CFG_S0_UV as follows: CFG_S0_UV= 200 • 7.1V 14.2V •100%⎡ = 200 •[50%] = 100 (decimal) = 0x64 (hexadecimal) Therefore, writing CFG_S0_UV to 0x64 configures VS0_UV to be 50% of VS2. Be sure to set CFG_S0_UV to a lower VS2 percentage than CFG_UV_S0 to achieve threshold hysteresis and avoid oscillating between stages. A 4%, or more, difference is recommended Note: CFG_UV_S0 and CFG_S0_UV allow the charger to start even if there is a battery protection circuit in between the VBAT terminal and the battery. Setting both registers to 0x00 ensures that the charger can start and will not enter fault, even if the initial VBAT voltage is 0. Related Data Sheet Sections: Charging Faults, Battery Charging Algorithm, HW Config: VBAT in Stage 2 (VS2), Configure Temp. Compensation CFG_S0_S1 I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES MIN VALUE MAX VALUE DESCRIPTION 0x3E [7:0] 200 • (% of V S2) Unsigned Integer 70% = 0x8C 55.5% = 0x6F = 0x00 90% = 0xB4 Configure V S0_S1 voltage as percentage of VS2. Precision of 0.5% per bit. This register is used to set VS0_S1, the rising VBAT threshold to exit Stage 0 trickle charging and enter Stage 1 constant- current charging. VS0_S1 is a percentage of the Stage 2 voltage VS2. Therefore, if Stage 2 temperature compensation is enabled, via the CFG_CHRG_MISC→TC_ENABLE bit, VS0_S1 will vary with temperature in proportion to VS2. CFG_S0_S1 is an 8-bit unsigned integer , representing a percentage of V S2 between 0% - 90% and is calculated as follows: CFG_S0_S1=200 • VS0_S1 VS2
• 100%⎡

Rev. 0For more information www.analog.com I2C REGISTER DESCRIPTIONS Example: Presume that VS2 is set to 14.2V and we wish to configure VS0_S1 = 9.94V. Set CFG_S0_S1 as follows: CFG_S0_S1= 200 • 9.94V 14.2V •100%⎡ = 200 •[70%] = 140 (decimal) = 0x8C (hexadecimal) Therefore, writing CFG_S0_S1 to 0x8C configures VS0_S1 to be 70% of VS2. Be sure to set CFG_S0_S1 to a higher VS2 percentage than CFG_S1_S0 to achieve threshold hysteresis and avoid stage selection oscillations. A 4%, or more, difference is recommended. Related Data Sheet Sections: Battery Charging Algorithm, HW Config: VBAT in Stage 2 (VS2), Configure Temp. Compensation CFG_S1_S0 I2C REG ADDRESS BIT(S) UNITS FORMAT EXAMPLES MIN VALUE MAX VALUE DESCRIPTION VS2) Unsigned Integer 66% = 0x84 55.5% = 0x6F = 0x00 90% = 0xB4 Configure V S1_S0 threshold as percentage of VS2. Resolution of 0.5% per bit. This register is used to set V S1_S0, the falling V BAT threshold to exit Stage 1 charging and return to Stage 0 trickle charging. VS1_S0 is a percentage of the Stage 2 voltage VS2. Therefore, if Stage 2 temperature compensation is enabled, via the CFG_CHRG_MISC→TC_ENABLE bit, VS1_S0 will vary with temperature in proportion to VS2. CFG_S1_S0 is an 8-bit unsigned integer , representing a percentage of VS2 between 0% to 90% and is calculated as follows: CFG_S1_S0= 200 • VS1_S0 VS2

• 100%⎡ Example: Presume that VS2 is set to 14.2V and we wish to configure VS1_S0 = 9.39V. Set CFG_S1_S0 as follows: CFG_S1_S0= 200 • 9.39V 14.2V •100%⎡ = 200 •[66%] = 132 (decimal) = 0x84 (hexadecimal) Therefore, writing CFG_S1_S0 to 0x84 configures VS1_S0 to be 66% of VS2. Make sure to set CFG_S1_S0 to a lower VS2 percentage than CFG_S0_S1 to achieve threshold hysteresis and avoid stage selection oscillations. A 4%, or more, difference is recommended. Also, be sure to set CFG_S1_S0 to higher VS2 percentage than CFG_UV_S0 threshold to avoid stage selection oscillations. A 4%, or more, difference is also recommended. Note: If VBAT falls below the VS1_S0 threshold while in Stage 2 or Stage 3, the charging algorithm will reset. Related Data Sheet Sections: Battery Charging Algorithm, HW Config: VBAT in Stage 2 (VS2), Configure Temp. Compensation

fault limits. The register values are stored in °C as two’s complement, signed integers. Table 15. Summary of Battery Temperature Configuration Registers y low temperature fault limit. normal operation, CFG_TBAT_MIN must be lower than CFG_TBAT_MAX. y high temperature fault limit. (5°C of hysteresis). If the fault properly clears, it will be indicated by STAT_CHRG_FAULTS→HIGH_TBAT_FAULT=0. For normal operation, CFG_TBAT_MAX must be higher than CFG_TBAT_MIN.

0x00 to the appropriate registers disables them, allowing the charging to run indefinitely in lieu of any fault conditions. interpreted as an infinite time limit. Table 16. Summary of Stage 0 to 3 Timer Configuration Registers

63 Min = 0x0E

Configures Stage 0 charging time limit. 4.47 minutes per bit. V alue of 0x00 disables timer . Configures Stage 1 charging time limit. 4.47 minutes per bit. alue of 0x00 disables timer . Configures Stage 2 charging time limit. 4.47 minutes per bit. alue of 0x00 disables timer . Configures Stage 3 charging time limit. 4.47 minutes per bit. alue of 0x00 disables timer . Related Data Sheet Section: STAT_TSx_REMAIN, Battery Charging Algorithm, Configure Automatic Restart.

from a battery temperature fault. Table 17. Summary of Automatic Restart Configuration Registers Example: 0100b = 2-hour restart delay.

• Stage 1 timer fault occurred (T S1_EXPIRED_FLT=1) and (VBAT rises 5% or VBAT rises to 98% of VS2) Stage 0 timer fault occurred (T S0_EXPIRED_FLT=1) and VBAT ≥ VS0_S1 If 1 then don’t automatically restart due to any of these conditions. NO_RSTRT_ON_DISCON_FLT [2] If 1 and a battery disconnect fault is detected, then stop charging and don’t allow charging to automatically restart. Restarting the charger , after a battery disconnect fault will require that the charging logic is cycled off-then-on via the CTRL_CHRG_EN register . NO_RSTRT_ON_BATLOW_FLT [1] If 1 and a low V BAT fault is detected, then stop charging and don’t allow charging to automatically restart. Restarting the charger , after a low VBAT fault will require that the charging logic is cycled off-then-on via the CTRL_CHRG_EN register . NO_RESUME_ON_TBAT_FLT [0] If 1 and a battery temperature fault is detected, then stop charging and don’t allow charging to automatically resume. Charging can only restart after a battery temperature fault, by cycling the charging control logic off-then-on via the CTRL_CHRG_EN register .

but the restart condition behaves unconditionally from the prioritized fault indication. Figure 9. No Restart Condition Example

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Rev. 0 For more information www.analog.com I2C REGISTER DESCRIPTIONS CFG_RSTRT_IN_DONEA I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x47 RSTRT_IN_DONE_ON_VOLTS [7] Setting this bit causes the battery charging to automatically restart, if in the done charging stage, when the VBAT voltage is detected to be below the voltage configured in the RSTRT_IN_ DONE_SET_VOLTS bits. See Figure 8. RSTRT_IN_DONE_SET_VOLTS [6:0] Configure V DONE_RSTRT voltage as percentage of VS2. Maximum value is 99% or 0x8C, with a resolution of 1% per bit. The RSTRT_IN_DONE_SET_VOLTS bits set VDONE_RSTRT, the falling VBAT voltage that causes an automatic charging restart when in the done charging stage. The done charging stage is indicated in the STAT_CHARGER register when the CHRG_STAGE bits are 100b and the CHRG_LOGIC_ON bit is 1. VDONE_RSTRT is a percentage of the Stage 2 voltage VS2. Therefore, if Stage 2 temperature compensation is enabled, via the CFG_CHRG_MISC→TC_ENABLE bit, VDONE_RSTRT will vary with temperature in proportion to VS2. RSTRT_IN_DONE_SET_VOLTS is a 7-bit unsigned integer , representing a percentage of VS2 between 0% to 99% and is calculated as follows: RSTRT_IN_DONE_SET_VOLTS= 100 • VDONE_RSTRT VS2

• 100%⎡ Example: Presume that VS2 is set to 14.2V and we wish to configure V DONE_RSTRT = 12.07V. Set RSTRT_IN_DONE_ SET_VOLTS as follows: RSTRT_IN_DONE_SET_VOLTS= 100 • 12.07V 14.2V •100%⎡ = 100 •[85%] = 85 (decimal) = 0x55 (hexadecimal) Therefore, writing RSTRT_IN_DONE_SET_VOLTS to 0x55 configures VDONE_RSTRT to be 85% of VS2. Be sure to always set RSTRT_IN_DONE_SET_VOLTS lower than VS3 over all TBAT conditions if Stage 3 charging is configured. Also, to avoid STAT_CHRG_FAULTS→LOW_VBAT_FLT from being triggered, it’s recommended to set RSTRT_IN_DONE_SET_ VOLTS higher than the CFG_S0_UV threshold over all TBAT conditions. A 4%, or more, difference is recommended. Related Data Sheet Sections: Battery Charging Algorithm, Done Charging

Rev. 0For more information www.analog.com I2C REGISTER DESCRIPTIONS CFG_RSTRT_IN_DONEB I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x48 Reserved [7:6] Reserved RSTRT_IN_DONE_HRS [5:0] By setting these bits to a non-zero value, the charger will wait for a delay time after reaching the done charging stage (see Figure 8), then automatically restart the charging in Stage 0. These bits set the delay in ½ hour steps between 0.5 to 31.5 hours. Setting these bits to all-zeros disables this automatic restart function. Example: 000100b = 2-hour automatic restart delay. CFG_RSTRT_IN_S3 I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x49 Reserved [7:1] Reserved RSTRT_S3_C5_VS3 [0] Setting this bit causes the charging to restart when in Stage 3 and (1) I OUT exceeds C/5 or (2) VBAT falls below 96% of the VS3 voltage threshold set in register CFG_VS3_25C. Related Data Sheet Section: Battery Charging Algorithm, Configure Automatic Restart, Configure V BAT for Stages 0, 1 and 3 CONFIGURE CHARGE TERMINATION CFG_TERMINATE I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x4A Reserved [7:6] Reserved PS_S2_C10_TERM_EN [5] DC Power Supply Powered, Stage 2, C/10 Termination Enable: Setting this bit to 1 causes the charging to terminate when the IOUT current falls below C/10 in Stage 2 while powered by a DC power supply. Upon termination, the charging will stop, and the charger will proceed to the Done Charging state as described in the Battery Charging Algorithm section. If the CFG_CHRG_ MISC→PS_S3_ENABLE bit is also set, then the charging will instead proceed to Stage 3 rather than terminating. SOLAR_S2_C10_TERM_EN [4] Solar Powered, Stage 2, C/10 Termination Enable: Setting this bit to 1 causes the charger to terminate charging when the I OUT current falls below C/10 in Stage 2 while powered by a solar panel. Upon termination, the charging will stop, and the charger will proceed to the Done Charging state as described in the Battery Charging Algorithm Section. Refer to the HW Config: Solar Panel Powered Charging section for additional information about C/10 termination when powered by a solar panel. If the CFG_CHRG_MISC→SOLAR_S3_ENABLE bit is set, then the charging will instead proceed to Stage 3 rather than terminating. 0x4A S3_TMR_TERM_EN [3] Stage Timer Termination Enable: Setting the respective bit to 1 causes the charging to terminate, without activating a fault flag, when the respective stage timer expires while charging in that stage. Upon termination, the charging will stop, and the charger will proceed to the Done Charging state as described in the Battery Charging Algorithm Section. A 0 setting causes the expiration of the timer to be treated as a fault condition. Note that timers and timer termination are automatically deactivated when powered by a solar panel. S2_TMR_TERM_EN [2] S1_TMR_TERM_EN [1] S0_TMR_TERM_EN [0] Related Data Sheet Sections: Battery Charging Algorithm, HW Config: Solar Panel Powered Charging, HW Config: DC Supply Powered Charging, Configure Stage Timeout Limits

Table 18. Summary of Miscellaneous Configuration Registers Configures timed full panel scan period in solar low power mode. Configures timed full panel scan period when solar powered. that performing full panel scans at short intervals can disrupt the charger output power and efficiency. certain stage transitions as part of the proprietary algorithm for identifying the maximum power point.

Rev. 0For more information www.analog.com I2C REGISTER DESCRIPTIONS CFG_CHRG_MISC I2C REGISTER ADDRESS BIT NAME BIT(S) DESCRIPTION 0x4D Reserved [7:5] Reserved USE_VS3_IN_STAGE2 [4] Reduces the Stage 2 battery charging voltage to the value set in CFG_VS3_25C. See below for details. LPMODE_EN [3] Setting this bit enables low power mode as discussed in the Optional: Low Power Mode section. PS_S3_ENABLE [2] When powered by a DC power supply, 1 permits the use of Stage 3 charging and 0 disables the use of Stage 3. See HW Config: Solar Panel Powered Charging and Battery Charging Algorithm for more information. SOLAR_S3_ENABLE [1] When powered by a solar panel, 1 permits the use of Stage 3 charging and 0 disables the use of Stage 3. See HW Config: DC Supply Powered Charging and Battery Charging Algorithm for more information. TC_ENABLE [0] Set to 1 to enable temperature compensation of V S2 and VS3. See Configure Temperature Compensation section. BIT[4] – USE_VS3_IN_STAGE2: Setting this bit allows for reduced voltage battery charging in Stage 2. It can be used, for example, for in-situ lead-acid battery charging when the battery load current exceeds C/10 (see the In-Situ Battery Charging section). In this case the charger is unable to proceed to Stage 3 because the charger output current does not drop below C/10 and maintaining V S2 voltage on the battery may be undesirable. Setting USE_VS3_IN_STAGE2 effects the charger as follows: In Stage 2 the battery will charge to a maximum voltage of VS3 instead of VS2. VS3 is configured in the following registers: CFG_VS3_25C, CFG_TC3, CFG_TC2, CFG_TC1 and the TC_ENABLE bit (listed above).

• T he V BAT stage voltage thresholds V UV_S0, VS0_UV, VS0_S1, VS1_S0 remain unaffected by this bit setting (see Battery Charging Algorithm and Configure VBAT for Stages 0, 1 and 3). The transition from Stage 1 to Stage 2 will occur when VBAT rises to 98% of VS3 instead of 98% of VS2. The transition from Stage 2 to Stage 1 will occur when VBAT falls to 95% of VS3 instead of 95% of VS2. See Figure 7 and Figure 8 for additional detail. When setting this bit, it is also recommended to:
• Disable Stage 3 charging by setting PS_S3_ENABLE and SOLAR_S3 _ENABLE to 0 in the CFG_CHRG_MISC register . Stage 3 charging can be re-enabled when USE_VS3_IN_STAGE2 is cleared. Consider disabling the C/10 charger termination in Stage 2 by clearing the PS_S2_C10_TERM_EN and SOLAR_ S2_C10_TERM_EN bits in the CFG_TERMINATE register .

Table 19. Summary of Temperature Compensation Configuration Registers CFG_TC2 LONG-WORD 0x52 0xB2 2nd order coefficient for Stage 2 and 3 temperature compensation. CFG_TC1 LONG-WORD 0x56 0xB6 1st order coefficient for Stage 2 and 3 temperature compensation. Disconnect Sensing section for more information about the thermistor connection. VBAT stage voltages listed in the Configure VBAT for Stages 0, 1 and 3 section, since they are all percentages of VS2. Figure 10. Default Battery Voltage Temperature Compensation in Stage 2

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VS2(TBAT) and VS3(TBAT) to the range of approximately 82% to 123.5% of VS2(25°C). For proper charger operation, VS3 must always be set lower than VS2. 0x4E CFG_TC3 [31:0] Single Precision Float –1.49e-7 = 0xB41FFCCF The TC3 temperature coefficient. 0x52 CFG_TC2 [31:0] 1.34e-5 = 0x3760D090 The TC2 temperature coefficient. 0x56 CFG_TC1 [31:0] –1.54e-3 = 0xBAC9D9D3 The TC1 temperature coefficient. values are described in the prior section. Table 20. User Code Register 0x5A USER_INPUT_DATA [15:0] 2 bytes for user information. tion. This data is not used for any function by the LT8491.

Table 21. Manufacturer CRC 0x5C - [15:0] Manufacturer data. 0x5E - [15:0] Manufacturer data. 0x60 - [15:0] Manufacturer data.

ply is a solar panel or a DC voltage source. multiple resistors in series to match the calculated results. final component selections with the following equations. equal to the desired VMAX for the application. be required to determine the best standard resistor values. values that achieve the best overall results. Table 22. Input Feedback Network vs VMAX required voltage range for each application. Figure 11. Input Feedback Resistor Network

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Figure 12. These resistors should have a 1% tolerance Figure 12. VINR Resistor Divider Circuit LT8491 to operate properly from a DC voltage source. STAT_SUPPLY and TELE_VINR registers. shown in Figure 12 when being powered by a solar panel. Timeout Limits and Configure Charge Termination.

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information about available C/10 state transitions. voltages are required in various other cases.

1. LOW POWER MODE ENABLED : Low power mode allows

Optional: Low Power Mode section for more details.

1. LOW POWER MODE DISABLED : If low power mode

detected, the LT8491 will temporarily stop charging. significant fall in battery voltage.

cally when a DC supply is present. FBIR and (2) connecting the FBIN pin directly to LDO33. gets closer to its regulation voltage of 1.205V (typical). Figure 13 the more the current can reduce. olds in Figure 13 and current limiting is rarely an issue. Figure 13. Minimum Full Charging Current VIN Voltage Figure 14. Output Feedback Resistor Network Config: Input Current Sense and Limit section.

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multiple resistors in series to match the calculated results. N1 should be as close as possible to 1.22. be required to determine best standard resistor values. select these values that achieve the best overall results. Table 23. Standard Value Output Feedback Network vs Output ing and limiting circuit and how to properly configure it.

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stability and minimizes inductor current overshoot. of 4.7nF to 22nF is suitable for most applications. the maximum power point calculations. output power to input power , less some efficiency loss. charger components can tolerate. current is sensed through RSENSE1 as shown in Figure 15. Figure 15. Input Current Regulation Loop

tion as illustrated in Figure 8. Figure 16. Output Current Regulation Loop Figure 17. Recommended Current Sense Filter

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OK to exclude RIOW from the PCB and float the IOW pin. IOUT(MAXS0) must be at least 20% of IOUT(MAX). can introduce more noise into the ADC measurements. range of 4.7nF to 22nF is suitable for most applications. values for RS1, RS2 and CS1, CS2 are 22Ω and 470nF. the LT8491 for best performance.

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and RS2 will show up in the telemetry as a small error . to the LT8491 that the battery is always at 25°C. (1% resistor tolerance or better required). Figure 18. Battery Temperature and Disconnect Sensing Circuit Figure 19. SHDN Pin Resistor Divider 60°C which can be read from the TELE_TBAT register . cussed in the Configure Temperature Fault Limits section.

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1. Automatic CCM/DCM Mode Switching: Very large

8491 F19

Figure 21. 2.5mA STATUS LED Indicator Figure 20. Simplified Diagram of Power Switches through the body diode of this device. ing by activating the hybrid conduction mode (HCM). tion (MODE tied high) if this behavior is not desired.

1. Automatic EXTVCC Regulator Disconnect: As discussed

when charging current becomes low or charging stops. describes the STATUS pin operation. to 2.5mA or less when STATUS is driven close to 3.3V. ~2.5mA when the STATUS is driven low.

8491 F20

8491 F21

is suitable for most applications.

Table 24. I2C Address Resistor Values connected to the battery terminals as shown in Figure 24. Configure Stage Timeout Limits section). where ID is the desired bias current through the LED. Figure 22. Higher Current Drive for STATUS LED Figure 23. Chip Address Select Circuit Figure 24. Load Connection to Battery in LT8491 Application

8491 F22

8491 F23

8491 F24

Use the recommended resistor values stated in Table 24. function and yield low current consumption.

Figure 25. Example Waveform for STATUS Pin in STAGE 3 directly to a load without the presence of a battery. initial voltage of the capacitors, and (4) cable impedance. that can cause electrical overstress on LT8491 pins. make a current limited connection. pin in relationship to the charger status. and drive to ground to turn the LED off. Table 25. Status LED Indicator LT8491 into a typical setup for lithium-ion battery charging.

8491 F25

Table 26. Lithium-Ion Battery Register Settings high as described in Table 25. The LT8491 can be used to charge lead-acid batteries. LT8491 into a typical setup for lead-acid battery charging. Table 27. Lead-Acid Battery Register Settings tion enabled, a standard setting for lead-acid batteries. register definition for an in-depth explanation. typical lead-acid charging cycle. Figure 26. Lithium-Ion Battery Charging Cycle Figure 27. Lead-Acid Battery Charging Cycle

8491 F26

8491 F27

cuitry is used, consider setting V UV_S0 and VS0_UV to 0. See Configure VBAT for Stages 0, 1, and 3 section.

Figure 29. Battery Discharge when Not Charging will automatically begin operating in low power mode. that would otherwise cause the LT8491 to stop charging. Performance Characteristics section. when operating with low input capacitance. before transferring the input charge to the battery.

8491 F28

8491 F29

Figure 28. Minimum Input Capacitance

cation can tolerate this error . ing it suitable for the RLIM3 value shown in Figure 30. Figure 31. Employing the optional feedback resistor dis-

8491 F30

8491 F31

Figure 31. Optional Feedback Resistor Disconnect Circuit #2 Figure 30. Optional Feedback Resistor Disconnect Circuit #1

Figure 32. Optional EXTVCC Disconnect Circuit Figure 33. IR Drop Present in Battery Connection from the battery when charging current becomes low. CC is disconnected from the LT8491. optional EXTVCC disconnect circuit. the actual battery voltage by 2 • VIR.

8491 F32

Figure 34 can correct for these effects.

8491 F33

to pull up the R" FBOUT1 battery voltage sensing resistor . The R3 resistance should be less than 1% of R FBOUT1. Figure 34. Remove (+) and (–) Cable VIR Measurement Errors

8491 F34

Selecting R3 as a 100Ω resistor is often a good choice. appropriate power rating, often at least 1 Watt. making the remote sense connection. this case. 4.99k is a good value for R4. the Hot-Plugging Considerations section for more detail).

Figure 35. How to Combine Figure 30 and Figure 34 Figure 36. Optional DC Supply Detection Circuit

8491 F35

avoid overvoltage of the NMOS gate. Checklist and drawing is provided. rent (C) is 10A with a trickle charge current of 2.5A (C/4). multiple resistors in series may be required.

• With RFBOUT2 set at 20k and a desired Stage 2 volt - age limit of 14.2V, the top output feedback resistor , RFBOUT1, is calculated according to the following equation: RFBOUT1=RFBOUT2 • V S2 • 1.241 1.211– 0.128⎛ ⎝⎜ ⎞ ⎠⎟–1⎡ ⎦⎥Ω 1.211– 0.128⎛ ⎝⎜ ⎞ ⎠⎟–1⎡ ⎦⎥Ω = 234,684Ω Choose R FBOUT1 = 237k which is the closest standard value resistor .

8491 F36

Rev. 0For more information www.analog.com APPLICATIONS INFORMATION

• Following the calculation of RFBOUT1, solve for RDACO1, RDACO2 and CDACO according to the following formulas: RDACO2 = 0.833•RFBOUT1•RFBOUT2 RFBOUT2 • VS2 •1.241 1.211 ⎝⎜ ⎞ ⎠⎟– RFBOUT2 –RFBOUT1 Ω 20k •14.2•1.241 1.211 ⎝⎜ ⎞ ⎠⎟– 20k – 234,684 Ω = 107,556Ω Choose RDACO2 = 107k which is the closest standard value resistor . RDACO1= 0.2•RDACO2Ω = 0.2•107,556Ω = 21 ,511Ω Choose RDACO1 = 21.5k which is the closest standard value resistor . CDACO = 1 500 •RDACO1 F = 1 500 •21 ,511F = 93nF
• Using the standard value resistors calculated above, the VX3, N1 and N2 checking equations yield the following: VX3 = 14.31V = 1.22 = 0.804
• T o find a resistor combination that yields V X3 closer to the desired 14.2V, RFBOUT2 is increased to the next higher standard value and the above calculations are repeated.
• Iterations of the previous step are per formed that include adjustments to R FBOUT1, RDAC01 and R DAC02 until the following standard value feedback resistors were chosen: RFBOUT1 = 274k RFBOUT2 = 23.2k RDACO1 = 26.1k RDACO2 = 124k CDACO = 0.082µF where: VX3 = 14.27V = 1.22 = 0.805
• With the output feedback network determined, use VMAX and solve for the input resistor feedback network according to the following formulas: RFBIN1= 100k • 1+ 4.47V VMAX – 6V 1+ 5.593V VMAX – 6V Ω = 100k • 1+ 4.47V 53V – 6V ⎝⎜ ⎞ 1+ 5.593V 53V – 6V ⎝⎜ ⎞ Ω = 97,865Ω The closest standard value for RFBIN1 is 97.6k. RDACI2= 2.75• RFBIN1 VMAX – 6V ⎠⎟Ω = 2.75• 97,865 53V – 6V ⎝⎜ ⎞ ⎠⎟Ω = 5726Ω

Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION Choose RDACI2 = 5.76k which is the closest standard value. RFBIN2= 1 100k –RFBIN1 ⎠⎟– 1 RDACI2 Ω = 1 100k – 97,865 ⎠⎟– 1 5726 ⎝⎜ ⎞ Ω = 3404Ω Choose RFBIN2 = 3.4k which is the closest standard value. RDACI1 = 0.2 • R DACI2 Ω 0.2 • 5726Ω 1145Ω Choose RDAC1 = 1.1k which is the closest standard value. CDACI = 1 1000 •RDACI1 F = 1 1000 •1 ,145F = 873nF

• Like the output feedback resistors, the final input feed- back resistors were chosen to be standard values using an iterative process. The VX1 and VX2 equations in the HW Config: Input Voltage Sensing and Modulation net- work section were used to validate the selections: RFBIN1 = 93.1kΩ RFBIN2 = 3.24kΩ RDACI1 = 1.05kΩ RDACI2 = 5.49kΩ CDACI = 1µF where: VX1 = 6V VX2 = 53V
• The 10A maximum charge current limit and 2.5A trickle charge current limit are set by choosing R SENSE2, RIMON_OUT and RIOW using the following formulas: RSENSE2 = 0.0497 IOUT MAX( ) Ω= 0.0497 10 ≅5mΩ RIMON_OUT = 1208 IOUT MAXS0( ) •RSENSE2 Ω = 1208 2.5•5mΩ = 96.64kΩ where the nearest standard value is 97.6kΩ RIOW = 24.3k •RIMON_OUT RIMON_OUT – 24.3kΩ = 24.3k • 47.6k 97.6k – 24.3kΩ = 32,356Ω where the nearest standard value is 32.4kΩ
• The input current limit is set by properly choosing RSENSE1. In this example, the panel can deliver up to RSENSE1= 0.0505 IIN MAX( ) = 0.0505 1.3•5.4 = 7.2MΩ
• F or greater charging voltage accuracy, it is recom - mended that 0.1% tolerance resistors be used for the output feedback resistor network.
• Please reference the LT8705 data sheet for completing the remaining power portions of the LT8491.

8491 F37

Figure 37. 24.6V Lithium-Ion Polymer Battery Charger

Rev. 0 For more information www.analog.com TYPICAL APPLICATIONS CIN2 2.2µF

8491 TA02

CSPBG1 SW1BOOST1TG1 CSN GND BG2 SW2 BOOST2 TG2 CSPOUT CSNOUT EXTVCC FBOR FBOUT FBOW 10/uni03A9 6m/uni03A9 15µH ½W 10m/uni03A9 COUT2 4.7µF C OUT3 4.7µF C IN3 2.2µF COUT1 220µF 100/uni03A9 220nF220nF DB1 22.6k GATEVCC´ VDD AVDD CIN4 2.2µF DB2 GATEVCC´ 56.8V FLOODED LEAD ACID LOAD 5m/uni03A9 470nF VOC < 80V SOLAR PANEL M1 M4 20k TEMPSENSE SRVO_FBIN SRVO_IIN SRVO_FBOUT SRVO_IOUT ECON SWEN SWENO RT SS IIR IMON_IN IOW IMON_OUT IOR SYNC V C CLKDET CLKOUT LT8491 115k LDO33 CSNIN CSPIN V IN GATEVCCGATEVCC´ MODE INTVCC FBIN FBIR FBIW VINR SHDN 4.7µF 0.1µF 1µF 100nF 10/uni03A9 10/uni03A9 200k 4.7µF 196k 8.06k 133k 3.09k 110k 35.7k 4/uni03A9 4.87k 301k 53.6k 1.05k1µF 100nF 8.2nF I2C ADDRESS: 0x10 56.8V STAGE 2 (ABSORPTION) CHARGE VOLTAGE (VS2) AT 25°C 55.2V STAGE 3 (FLOAT) CHARGE VOLTAGE (VS3) AT 25°C 5A CHARGING CURRENT LIMIT 1.25A TRICKLE CURRENT LIMIT 11.4A INPUT CURRENT LIMIT 80V MAXIMUM PANEL VOLTAGE (V MAX) NO TIMER LIMITS TEMPERATURE COMPENSATION ENABLED –20°C TO 50°C BATTERY TEMPERATURE RANGE 145kHz SWITCHING FREQUENCY EXAMPLE SOLAR PANEL: SHARP NT-175UC1 175W, SHARP NU-U235F3 235W M1: INFINEON BSC046N10NS M2: INFINEON BSC109N10NS M3, M4: INFINEON BSC057N08NS L1: 15µH COILCRAFT SER2915H-153KL, 15µH WURTH 744 364 115 00 D B1, DB2: CENTRAL SEMI CMMR1U-02 CIN1, COUT1: 220µF, 100V, UNITED CHEMI-CON EKZE101ELL221MK255 CIN2, CIN3, CIN4: 2.2µF, 100V, AVX 12101C225KAT2A COUT2, COUT3: 4.7µF, 100V, TDK C4532X7S2A475M230KB COUT4: 1µF, 100V AVX 12101C105KAT2A CCSPOUT: 100nF, 50V, AVX 08055C10 68nF 11.3k 3.01k 32.4k 220pF 10nF 21k 97.6k10nF 470nF 18.2k 10k AT 25°C ß = 3380 NTC CIN1 220µF COUT4 1µF CCSPOUT 100nF 549/uni03A9 STATUS CA DS 1.3k 19.1k AVDD SDA TO MASTER SCL 10k 10k AVDD I 2C REG REGISTER NAME ADDR VALUE CFG_RSENSE1 0x28 0x01FA → (5m/uni03A9) CFG_RIMON_OUT 0x2A 0x2620 → (97.6k/uni03A9) CFG_RSENSE2 0x2C 0x03E8 → (10m/uni03A9) CFG_RDACO 0x2E 0x35C0 → (137.6k/uni03A9) CFG_RFBOUT1 0x30 0x2710 → (1M/uni03A9) CFG_RFBOUT2 0x32 0x07D0 → (20k/uni03A9) CFG_RDACI 0x34 0x0250 → (5.92k/uni03A9) CFG_RFBIN2 0x36 0x0144 → (3.09k/uni03A9) CFG_RFBIN1 0x38 0x03AE → (133k/uni03A9) CFG_VS3_25C 0x3B 0x7A → (97.2%) CFG_TBAT_MIN 0x40 0xEC → (–20°C) CFG_TBAT_MAX 0x41 0x32 → (50°C) CFG_TMR_S0 0x42 0x00 CFG_TMR_S1 0x43 0x00 CFG_TMR_S2 0x44 0x00 CFG_TMR_S3 0x45 0x00 CFG_RSTRT_IN_S3 [0] 0x49 1b CFG_CHRG_MISC [2:0] 0x4D 111b 56.8V Lead-Acid Battery Charger (Four 12V Batteries in Series)

Rev. 0For more information www.analog.com Information furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PACKAGE DESCRIPTION 11.00 ±0.10 7.00 ±0.10 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS PIN 1 TOP MARK (SEE NOTE 6) BOTTOM VIEW—EXPOSED PAD 11.00 ±0.10 9.50 REF 0.75 ±0.05 0.25 ±0.05 (UKJ64(58)) QFN 0412 REV Ø

0.50 BSC

0.50 REF

0.200 REF

0.00 – 0.05 APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

5.50 REF

0.325 REF 0.40 ±0.10 0.45

9.50 REF

11.50 ±0.05 10.10 ±0.05 7.50 ±0.05 0.70 ±0.05 1.50 ±0.05 9.38 ±0.05 3.60 ±0.05 3.83 0.25 ±0.05 PACKAGE OUTLINE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 6453 31 27 25 21 Variation: UKJ64(58) 64(58)-Lead Plastic QFN (7mm × 11mm) (Reference LTC DWG # 05-08-1922 Rev Ø) 3.60 ±0.10 3.83 ±0.10 0.45 ±0.10 9.38 ±0.10 1.50 ±0.10 1 .20 ±0. 10 1.80 ±0.05

Rev. 0  ANALOG DEVICES, INC. 2020 www.analog.com RELATED PARTS TYPICAL APPLICATION PART NUMBER DESCRIPTION COMMENTS LT8490 High Voltage, High Current Buck-Boost Battery Charger with MPPT V IN Range = 6V to 80V, VBAT Range = 1.3V to 80V LT3652/LT3652HV Power T racking 2A Battery Charger for Solar Power VIN Range = 4.95V to 32V (LT3652), 4.95V to 34V (HV), MPPC LTC4000-1 High Voltage, High Current Controller for Battery Charger with MPPC V IN and VOUT Range = 3V to 60V, MPPC LTC4200 55V VIN/VOUT Buck-Boost Multi-Chemistry Battery Charging Controller Li-Ion and Lead-Acid Algorithms, MPPC 14.2V Flooded Lead-Acid Battery Charger CIN2 2.2µF

8491 TA03

3.3nF 3.3nF 10/uni03A9 CSPBG1 SW1BOOST1TG1 CSN GND BG2 SW2 BOOST2 TG2 CSPOUT CSNOUT EXTVCC FBOR FBOUT FBOW 10/uni03A9 5m/uni03A9 15µH ½W 5m/uni03A9 COUT2 10µF C OUT3 10µF C IN3 2.2µF COUT1 150µF 220nF220nF DB1 26.1k GATEVCC´ 274k VDD AVDD CIN4 2.2µF DB2 GATEVCC´ 14.2V FLOODED LEAD ACID LOAD 7m/uni03A9 470nF VOC < 53V SOLAR PANEL M1 M4 23.2k TEMPSENSE SRVO_FBIN SRVO_IIN SRVO_FBOUT SRVO_IOUT ECON SWEN SWENO RT SS IIR IMON_IN IOW IMON_OUT IOR SYNC V C CLKDET CLKOUT LT8491 124k LDO33 CSNIN CSPIN V IN GATEVCCGATEVCC´ MODE INTVCC FBIN FBIR FBIW VINR SHDN 4.7µF 0.082µF 1µF 100nF 10/uni03A9 2/uni03A9 10/uni03A9 200k 4.7µF 196k 8.06k 93.1k 3.24k 110k 35.7k 4/uni03A9 5.49k 249k 53.6k 1.05k1µF 100nF 4.7nF I2C ADDRESS: 0x10 14.27V STAGE 2 (ABSORPTION) CHARGE VOLTAGE (VS2) AT 25°C 13.87V STAGE 3 (FLOAT) CHARGE VOLTAGE (VS3) AT 25°C 10A CHARGING CURRENT LIMIT 2.5A TRICKLE CURRENT LIMIT 7.2A INPUT CURRENT LIMIT 53V MAXIMUM PANEL VOLTAGE (V MAX) NO TIMER LIMITS TEMPERATURE COMPENSATION ENABLED –20°C TO 50°C BATTERY TEMPERATURE RANGE 175kHz SWITCHING FREQUENCY EXAMPLE SOLAR PANEL: SHARP NT-175UC1 175W M1, M2: INFINEON BSC028N06NS M3, M4: INFINEON BSC042N03LSG L1: 15µH COILCRAFT SER2915H-153KL, 15µH WURTH 744 364 1500 D B1, DB2: CENTRAL SEMI CMMR1U-02 CIN1: 33µF, 63V, SUNCON 63HVH33M CIN2, CIN3, CIN4: 2.2µF, 100V, AVX 12101C225KAT2A COUT1: 150µF, 25V SUNCON 25HVH 150M COUT2, COUT3: 10µF, 35V, MURATA GRM32ER7YA106KA2L COUT4: 1µF, 25V AVX 12063C105KAT2A 68nF 8.45k 3.01k 32.4k 220pF 10nF 21k 97.6k8.2nF 470nF 18.2k 10k AT 25°C ß = 3380 NTC CIN1 33µF COUT4 1µF 549/uni03A9 STATUS CA DS 1.3k 100k AVDD SDA TO MASTER SCL 10k 10k AVDD VBAT 2/uni03A9 REGISTER NAME I 2C REG ADDR VALUE CFG_RSENSE1 0x28 0x02BC → (7m/uni03A9) CFG_RIMON_OUT 0x2A 0x2620 → (97.6k/uni03A9) CFG_RSENSE2 0x2C 0x01FA → (5m/uni03A9) CFG_RDACO 0x2E 0x3AA2 → (150.1k/uni03A9) CFG_RFBOUT1 0x30 0x0AB4 → (274k/uni03A9) CFG_RFBOUT2 0x32 0x0910 → (23.2k/uni03A9) CFG_RDACI 0x34 0x028E → (6.54k/uni03A9) CFG_RFBIN2 0x36 0x0144 → (3.24k/uni03A9) CFG_RFBIN1 0x38 0x03AE → (93.1k/uni03A9) CFG_VS3_25C 0x3B 0x7A → (97.2%) CFG_TBAT_MIN 0x40 0xEC → (–20°C) CFG_TBAT_MAX 0x41 0x32 → (50°C) CFG_TMR_S0 0x42 0x00 CFG_TMR_S1 0x43 0x00 CFG_TMR_S2 0x44 0x00 CFG_TMR_S3 0x45 0x00 CFG_RSTRT_IN_S3 [0] 0x49 1b CFG_CHRG_MISC [2:0] 0x4D 111b