LT8490 - High Voltage, High Current Buck-Boost Battery Charge Controller with Maximum Power Point Tracking (MPPT)
Document overview
- Manufacturer or author: Linear Technology Corporation
- PDF pages: 42
Technical content
8490faFor more information www.linear .com/L T8490 Typical applicaTion FeaTures DescripTion High Voltage, High Current Buck-Boost Battery Charge Controller with Maximum Power Point Tracking (MPPT) The LT®8490 is a buck-boost switching regulator battery charger that implements a constant-current constant- voltage (CCCV) charging profile used for most battery types, including sealed lead-acid (SLA), flooded, gel and lithium-ion. The device operates from input voltages above, below or equal to the output voltage and can be powered by a solar panel or a DC power supply. On-chip logic provides automatic maximum power point tracking (MPPT) for solar powered applications. The LT8490 can perform automatic temperature compensation by sensing an external thermistor thermally coupled to the battery. STATUS and FAUL T pins containing charger information can be used to drive LED indicator lamps. The device is available in a low profile (0.75mm) 7mm × 11mm 64-lead QFN package. Simplified Solar Powered Battery Charger Schematic
applicaTions
n VIN Range: 6V to 80V n VBAT Range: 1.3V to 80V n Single Inductor Allows VIN Above, Below, or Equal to VBAT n Automatic MPPT for Solar Powered Charging n Automatic Temperature Compensation n No Software or Firmware Development Required n Operation from Solar Panel or DC Supply n Input and Output Current Monitor Pins n Four Integrated Feedback Loops n Synchronizable Fixed Frequency: 100kHz to 400kHz n 64-Lead (7mm × 11mm × 0.75mm) QFN Package n Solar Powered Battery Chargers n Multiple Types of Lead-Acid Battery Charging n Li-Ion Battery Charger n Battery Equipped Industrial or Portable Military Equipment L, L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. L T8490 SOLAR PANEL TG1 BOOST1 CSNIN CSPIN V IN CSPOUT CSNOUT EXTVCC AVDD TEMPSENSE GATEVCC INTVCC SW1 BG1 CSP CSN STATUS FAUL T AVDD BG2 SW2 BOOST2 TG2 GND RECHARGABLE BATTERY LOAD THERMISTOR + –
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GATEVCC´ GATEVCC´ GATEVCC´ VBAT
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0.5s/DIV VPANEL 6V/DIV IPANEL 1.36A/DIV BACK PAGE APPLICATION PERTURB & OBSERVE PERTURB & OBSERVE FULL PANEL SCAN Maximum Power Point T racking
8490fa For more information www.linear .com/L T8490 pin conFiguraTionabsoluTe MaxiMuM raTings VCSP – VCSN, VCSPIN – VCSNIN, 3V to 3V 3V to 5V V to 5V 3V to 5.5V 3V to 7V V to 30V 3V to 30V 3V to 30V CSNIN, CSPIN, CSPOUT, CSNOUT Voltage .. –0. 3V to 80V 1V (Note 5) 3V to 87V Note 4) 3V to VDD + 0.5V V to VDD + 0.5V 3V to VDD + 0.5V 3V to VDD + 0.5V CHARGECFG2, 3V to VDD + 0.5V Operating Junction Temperature Range LT8 C to 125°C LT8 C to 125°C C to 150°C (Note 1) TOP VIEW UKJ PACKAGE 64-LEAD (7mm × 11mm) PLASTIC QFN GND FBIR 1 FAULT 2 TEMPSENSE 3 VDD 4 FBOW 5 FBIW 6 INTVCC 7 SWEN 8 MODE 9 IMON_IN 10 SHDN 11 CSN 12 CSP 13 LDO33 14 FBIN 15 FBOUT 16 IMON_OUT 17 VC 18 SS 19 CLKOUT 20 52 NC
51 STATUS
50 IOW
49 SWENO
48 ECON
45 CSPIN
44 CSNIN
42 CSPOUT
41 CSNOUT
40 EXTV
38 SRVO_FBOUT
37 SRVO_IOUT
36 SRVO_IIN
35 SRVO_FBIN
33 BOOST1
64 IOR
63 CHARGECFG2
62 GND
61 CHARGECFG1
59 GND
57 FBOR
56 CLKDET
55 GND
54 VINR
53 IIR
TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB orDer inForMaTion LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT8490EUKJ#PBF LT8490EUKJ#TRPBF LT8490UKJ 64-Lead (7mm × 11mm) Plastic QFN –40°C to 125°C LT8490IUKJ#PBF LT8490IUKJ#TRPBF LT8490UKJ 64-Lead (7mm × 11mm) Plastic QFN –40°C to 125°C Consult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container . For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
8490faFor more information www.linear .com/L T8490 elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VDD = AVDD = 3.3V, SHDN = 3V unless otherwise noted. (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS Voltage Supply and Regulators VIN Operating Voltage Range (Note 7) l 6 80 V VIN Quiescent Current Not Switching, VEXTVCC = 0, VDD = AVDD = Float 2.65 4.2 mA VIN Quiescent Current in Shutdown VSHDN = 0V 0 1 µA VDD Quiescent Current IAVDD + IVDD, VDD = AVDD = 3.3V l 2.5 4 6.5 mA EXTVCC Switchover Voltage IINTVCC = 20mA, VEXTVCC Rising l 6.15 6.4 6.6 V EXTVCC Switchover Hysteresis 0.18 V LDO33 Pin Voltage 5mA from LDO33 Pin l 3.23 3.295 3.35 V LDO33 Pin Load Regulation ILDO33 = 0.1mA to 5mA –0.25 –1 % LDO33 Pin Current Limit l 12 17.25 22 mA LDO33 Pin Undervoltage Lockout LDO33 Falling 2.96 3.04 3.12 V LDO33 Pin Undervoltage Lockout Hysteresis 35 mV Switching Regulator Control SHDN Input Voltage High SHDN Rising to Enable the Device l 1.184 1.234 1.284 V SHDN Input Voltage High Hysteresis 50 mV SHDN Input Voltage Low Device Disabled, Low Quiescent Current l 0.35 V SHDN Pin Bias Current VSHDN = 3V VSHDN = 12V µA µA SWEN Rising Threshold Voltage l 1.156 1.206 1.256 V SWEN Threshold Voltage Hysteresis 22 mV MODE Pin Thresholds Discontinuous Mode Forced Continuous Mode l l 0.4 2.3 V V IMON_OUT Rising threshold for CCM Operation MODE = 0V l 168 195 224 mV IMON_OUT Falling threshold for DCM MODE = 0V l 95 122 150 mV Voltage Regulation Regulation Voltage for FBOUT VC = 1.2V, EXTVCC = 0V l 1.193 1.207 1.222 V Regulation Voltage for FBIN VC = 1.2V, EXTVCC = 0V l 1.184 1.205 1.226 V FBOUT Pin Bias Current Current Out of Pin 15 nA FBIN Pin Bias Current Current Out of Pin 10 nA Current Regulation Regulation Voltage for IMON_IN and IMON_OUT V C = 1.2V, EXTVCC = 0V l 1.187 1.208 1.229 V IMON_IN Output Current VCSPIN – VCSNIN = 50mV, VCSPIN = 5.025V VCSPIN – VCSNIN = 50mV, VCSPIN = 5.025V VCSPIN – VCSNIN = 0mV, VCSPIN = 5V l l 2.5 11.5 µA µA µA IMON_IN Over voltage Threshold l 1.55 1.61 1.67 V IMON_OUT Output Current VCSPOUT – VCSNOUT = 50mV, VCSPOUT = 5.025V VCSPOUT – VCSNOUT = 50mV, VCSPOUT = 5.025V VCSPOUT – VCSNOUT = 5mV, VCSPOUT = 5.0025V VCSPOUT – VCSNOUT = 5mV, VCSPOUT = 5.0025V l l 47.5 3.25 2.75 52.5 54.25 6.75 µA µA µA µA IMON_OUT Over voltage Threshold l 1.55 1.61 1.67 V
8490fa For more information www.linear .com/L T8490 PARAMETER CONDITIONS MIN TYP MAX UNITS Switching Regulator Oscillator (OSC1) Switch Frequency Range Syncing or Free Running 100 400 kHz Switching Frequency, fOSC RT = 365k RT = 215k RT = 124k l l l 102 170 310 120 202 350 142 235 400 kHz kHz kHz SYNC High Level for Synchronization l 1.3 V SYNC Low Level for Synchronization l 0.5 V SYNC Clock Pulse Duty Cycle VSYNC = 0V to 2V 20 80 % Recommended Min SYNC Ratio, fSYNC /f OSC 3/4 CLKOUT Output Voltage HIGH 1mA Out of CLKOUT Pin 2.3 2.45 2.55 V CLKOUT Output Voltage LOW 1mA into CLKOUT Pin 25 100 mV CLKOUT Duty Cycle TJ = –40°C TJ = 25°C TJ = 125°C 22.7 44.1 Charging Control STA TUS, FBOW , FBIW , SWENO, IOW , ECON Output Low Voltage IOL = 5mA l 0.22 0.5 V STATUS, FBOW , FBIW , SWENO, IOW , ECON Output High Voltage IOH = –5mA l 2.7 3.0 V FAUL T Output Voltage Low IOL = 0.5mA l 0.1 0.25 V FAUL T Output Voltage High IOH = –0.1mA l 1.7 2.2 V Power Supply Mode Detection Threshold (Note 6) VINR Pin Falling l 155 174 mV Power Supply Mode Detection Threshold Hysteresis (Note 6) VINR Pin 29 mV Minimum VINR Voltage for Start-Up (Note 6) Not in Power Supply Mode Low Power Mode Enabled Low Power Mode Disabled l l 380 213 395 225 410 237 mV mV High Charging Current Threshold on IOR (Note 6) IOR Rising g ECON Rising l 168 195 224 mV Low Charging Current Threshold on IOR (Note 6) IOR Falling g ECON Falling l 95 122 150 mV Minimum CHARGECFG1 % of AVDD to Disable Stage 3 (Note 6) Temperature Compensation Enabled l 94 95 96 % Maximum CHARGECFG1 % of AVDD to Disable Stage 3 (Note 6) Temperature Compensation Disabled l 4 5 6 % Minimum CHARGECFG2 % of AVDD to Disable Time Limits (Note 6) Wide Valid T emperature Range l 94 95 96 % Maximum CHARGECFG2 % of AVDD to Disable Time Limits (Note 6) Narrow Valid T emperature Range l 4 5 6 % Minimum TEMPSENSE % of AVDD to Detect Battery Disconnected (Note 6) l 94.5 96 97.5 % VCSPOUT – VCSNOUT Threshold for C/5 Detection (Note 6) V CSxOUT Common Mode = 5.0V, RTOTAL from IMON_OUT to Ground = 24.3kΩ 9 10 11 mV VCSPOUT – VCSNOUT Threshold for C/10 Detection (Note 6) V CSxOUT Common Mode = 5.0V, IOR Falling, RTOTAL from IMON_OUT to Ground = 24.3kΩ 4.25 5 5.75 mV FBIW , FBOW PWM Frequency (OSC2) 31.25 kHz FBIW , FBOW PWM Resolution 8 Bits STATUS UART Bit Rate l 2160 2400 2640 Baud Internal A/D Resolution 10 Bits elecTrical characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VDD = AVDD = 3.3V, SHDN = 3V unless otherwise noted. (Note 3)
8490faFor more information www.linear .com/L T8490
elecTrical characTerisTics
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Do not force voltage on the V C pin. Note 3: The LT8490E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT8490I is guaranteed over the full –40°C to 125°C junction temperature range. Note 4: Do not apply a voltage or current source to these pins. They must be connected to capacitive loads only, otherwise permanent damage may occur . Note 5: Negative voltages on the SW1 and SW2 pins are limited in the applications by the body diodes of the external NMOS devices M2 and M3 or parallel Schottky diodes when present. The SW1 and SW2 pins are tolerant of these negative voltages in excess of one diode drop below ground, guaranteed by design. Note 6: These thresholds are measured by the internal A-D converter . The A-D reference voltage is AV DD. AVDD, VDD and an additional 2.8mA load are regulated by LDO33 to create the AVDD reference for these measurements. The absolute threshold voltages will shift with corresponding changes in the AV DD voltage. Note 7: 10V minimum VIN required for solar powered start-up if low power mode is enabled.
8490fa For more information www.linear .com/L T8490 Typical perForMance characTerisTics STATUS VOH and VOL (VDD = AVDD = 3.3V) FAUL T VOH and VOL (VDD = AVDD = 3.3V) LDO33 Load Regulation (Not Connected to AVDD and VDD) IMON Output Currents Power Supply Mode Charging Lead Acid Battery "B” T A = 25°C, unless otherwise noted. |IFAUL T| (mA) VFAUL T (V)
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–40°C 125°C –40°C 25°C VOH VOL 125°C 25°C LOAD CURRENT (mA) LDO33 (V) 3.1 3.3 3.4 3.2
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25°C –40°C 125°C CSxIN-CSxOUT (mV) –100 PIN CURRENT (µA) 175 200 125 150 100 –25 0 50
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200–50 100 150 IMON_OUT IMON_IN |ISTATUS| (mA) VSTATUS (V)
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–40°C 125°C 25°C –40°C 125°C VOH VOL 25°C STAGE 2STAGE 1 STAGE 3 CHARGING TIME (HOURS) VBAT (V) AND IBAT (A) 2.50 15.0 12.5 7.50 10.0 5.00
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VIN = 36V FBOUT , FBIN, IMONIN, IMONOUT Voltage Rise vs Power INTVCC REGULATOR POWER (W) VOL TAGE RISE (%) 0.2 1.0 0.6 0.8 0.4 0.5
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21 1.5 INTVCC REGULATED FROM VIN INTVCC REGULATED FROM EXTVCC Solar Powered Charging Lead Acid Battery "A” Solar Powered Charging Lead Acid Battery "B” Solar Powered Charging Lithium Ion Battery TIME OF DAY 9AM VBAT (V) AND IBAT (A) 2.50 17.5 15.0 12.5 10.0 7.50 5.00
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FOR CLARITY. VBAT IBAT SUNSET CHARGING STAGE BACK PAGE APPLICATION TIME OF DAY 10AM VBAT (V) AND IBAT (A) CHARGING STAGE 2.50 17.5 15.0 12.5 10.0 7.50 5.00
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FOR CLARITY. SUNSET BACK PAGE APPLICATION TIME OF DAY 1PM VBAT (V) IBAT (A)
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FOR CLARITY. UART AND STATUS INDICATE < C/10 FIGURE 34 APPLICATION
8490faFor more information www.linear .com/L T8490 Typical perForMance characTerisTics Perturb and Observe Maximum Power Point T racking Full Panel Scan Single Power Peak Full Panel Scan—Partially Shaded with Dual Power Peaks Panel Voltage in Low Power Mode Panel Voltage in Low Power Mode Maximum Power Point T racking Perturb and Observe Perturb and Observe T A = 25°C, unless otherwise noted.
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IMON_OUT 500mV/DIV PERTURB & OBSERVE FIGURE 34 APPLICATION FULL PANEL SCANS
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0.5s/DIV VPANEL 5V/DIV IMON_OUT 200mV/DIV FIGURE 34 APPLICATION
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0.5s/DIV VPANEL 5V/DIV IMON_OUT 100mV/DIV FIGURE 34 APPLICATION
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IMON_OUT 100mV/DIV FIGURE 34 APPLICATION ROTATE PANEL TOWARDS THE SUN. PANEL VOL TAGE AND CURRENT ARE AUTOMATICALL Y ADJUSTED TO NEW MAX.
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0.5s/DIV VPANEL 10V/DIV IMON_IN 500mV/DIV IMON_OUT 500mV/DIV FIGURE 34 APPLICATION POWER PEAK
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0.5s/DIV VPANEL 10V/DIV IMON_IN 200mV/DIV IMON_OUT 200mV/DIV FIGURE 34 APPLICATION LOWER POWER PEAK MAX POWER PEAK
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IMON_OUT 50mV/DIV FIGURE 34 APPLICATION 10.6mV 10.4V 17.6V 3.3V
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IMON_OUT 50mV/DIV FIGURE 34 APPLICATION 10.6mV 10.1V 3.3V
8490fa For more information www.linear .com/L T8490 pin FuncTions FBIR (Pin 1): A/D Input Pin. Connects to FBIN pin to measure input feedback voltage. FAUL T (Pin 2): FAUL T Pin. This pin generates an active high digital output that, when used with an LED, provides a visual indication of a fault event. TEMPSENSE (Pin 3): A/D Input Pin. Connects to a thermis- tor divider network for sensing battery temperature or a resistor divider if unused. This pin is frequently monitored for temperature compensation and enfor cing temperature limits. VDD (Pin 4): Control Logic Power Supply Pin. Connect this pin to LDO33 and AVDD. FBOW (Pin 5): PWM Digital Output Pin. Connects to FBOUT through an RCR network to temperature compensate the battery voltage. FBIW (Pin 6): PWM Digital Output Pin. Connects to FBIN through an RCR network to adjust the solar panel volt- age for MPPT . INTVCC (Pin 7): Internal 6.35V Regulator Output Pin. Con- nects to the GATEVCC pin. INTVCC is powered from EXTVCC when the EXTVCC voltage is higher than 6.4V, otherwise INTVCC is powered from V IN. Bypass this pin to ground with a minimum 4.7µF ceramic capacitor . See Switching Configuration - MODE Pin for additional details. SWEN (Pin 8): Switch Enable Pin. Tie to the SWENO pin. MODE (Pin 9): Mode Pin. The voltage applied to this pin sets the operating mode of the switching regulator . Tie this pin to INTV CC to make discontinuous current mode active. Tie this pin to ground to operate in discontinuous current mode for low battery charging currents and continuous current mode for high battery charging currents. Do not float this pin. See Switching Configuration - MODE Pin for additional details. IMON_IN (Pin 10): Input Current Monitor Pin. The current out of this pin is proportional to the input current. See the Applications Information section for more information. SHDN (Pin 11): Shutdown Pin. In conjunction with the UVLO (undervoltage lockout) circuit, this pin is used to enable/disable the chip. Do not float this pin. CSN (Pin 12): The (–) Input to the Inductor Current Sense and Reverse Current Detect Amplifier . CSP (Pin 13): The (+) Input to the Inductor Current Sense and Reverse Current Detect Amplifier . The V C pin voltage and built-in offsets between the CSP and CSN pins set the current trip threshold. LDO33 (Pin 14): 3.3V Regulator Output. This supply provides power to the V DD and AV DD pins. Bypass this pin to ground with a minimum 4.7µF ceramic capacitor . FBIN (Pin 15): Input Feedback Pin. This pin is connected to the input error amplifier input. FBOUT (Pin 16): Output Feedback Pin. This pin connects the error amplifier input to an external resistor divider from the output. IMON_OUT (Pin 17): Output Current Monitor Pin. The current out of this pin is proportional to the average out- put current. See the Applications Information section for more information. V C (Pin 18): Error Amplifier Output Pin. Tie the external compensation network to this pin. SS (Pin 19): Soft-Start Pin. Place 100nF of capacitance from this pin to ground. Upon start-up, this pin will be charged by an internal resistor to 2.5V. CLKOUT (Pin 20): Switching Regulator Clock Output Pin. CLKOUT will toggle at the same frequency as the switch- ing regulator oscillator (OSC1 on the Block Diagram) or as the SYNC pin, but is approximately 180° out-of-phase. CLKOUT can also be used as a temperature monitor of the switching regulator since the CLKOUT duty cycle varies linearly with the junction temperature of the switching regulator . It is connected to CLKDET through an RC filter . The CLKOUT pin can drive capacitive loads up to 200pF. SYNC (Pin 21): To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock needs to exceed 1.3V, and the low level should be less than 0.5V. Drive this pin to less than 0.5V to revert to the internal free-running clock (OSC1 in the Block Diagram).
8490faFor more information www.linear .com/L T8490 pin FuncTions RT (Pin 22): Timing Resistor Pin. Adjusts the switching regulator frequency (OSC1) when SYNC is not driven by a clock. Place a resistor from this pin to ground to set the free-running frequency of OSC1. Do not float this pin. BG1, BG2 (Pin 23/Pin 25): Bottom Gate Drive. Drives the gates of the bottom N-channel MOSFETs between ground and GATEV CC. GATEVCC (Pin 24): Power Supply for Gate Drivers. Must be connected to the INTVCC pin. Do not power from any other supply. Locally bypass to ground. BOOST1, BOOST2 (Pin 33/Pin 27): Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitor con - nects here. The BOOST1 pin swings from a diode voltage below GATEVcc up to V IN + GATEVCC. The BOOST2 pin swings from a diode voltage below GATEV CC up to VBAT + GATEVCC. TG1, TG2 (Pin 32/Pin 28): Top Gate Drive. Drives the top N-channel MOSFETs with voltage swings equal to GATEVCC superimposed on the switch node voltages. SW1, SW2 (Pin 31/Pin 29): Switch Nodes. The (–) terminal of the bootstrap capacitors connect here. SRVO_FBIN (Pin 35): Open-Drain Logic Output. This pin is pulled to ground when the input voltage feedback loop is active. This pin is unused for most LT8490 applications and can be floated. SRVO_IIN (Pin 36): Open-Drain Logic Output. This pin is pulled to ground when the input current feedback loop is active. This pin is unused for most LT8490 applications and can be floated. SRVO_IOUT (Pin 37): Open-Drain Logic Output. This pin is pulled to ground when the output current feedback loop is active. This pin is unused for most LT8490 applications and can be floated. SRVO_FBOUT (Pin 38): Open-Drain Logic Output. This pin is pulled to ground when the output voltage feedback loop is active. This pin is unused for most LT8490 applications and can be floated. EXTV CC (Pin 40): External V CC Input. When EXTV CC ex- ceeds 6.4V (typical), INT VCC will be powered from this pin. When EXTVCC is lower than 6.22V (typical), INTVCC will be powered from VIN. See Switching Configuration - MODE Pin for additional details. CSNOUT (Pin 41): The (–) Input to the Output Current Sense Amplifier . CSPOUT (Pin 42): The (+) Input to the Output Current Sense Amplifier . This pin and the CSNOUT pin measure the voltage across the sense resistor to provide the output current signals. CSNIN (Pin 44): The (–) Input to the Input Current Sense Amplifier . This pin and the CSPIN pin measure the voltage across the sense resistor to provide the instantaneous input current signals. CSPIN (Pin 45): The (+) Input to the Input Current Sense Amplifier . V IN (Pin 46): Main Input Supply Pin. Must be bypassed to local ground plane. ECON (Pin 48): Digital Output Pin. Optional control output signal used to disconnect EXTV CC from the battery when the average charge current drops below a predetermined threshold. SWENO (Pin 49): Digital Output Pin. Connect to SWEN. Enables the switching regulator . A 200kΩ pull-down resis- tor is required from this pin to ground. IOW (Pin 50): Digital Output Pin. Connects to IMON_OUT through a resistor . By switching the pin between logic low and high impedance, the total RIMON_OUT changes, which changes the output current limit. STATUS (Pin 51): Digital Output Pin. When used with an LED, this signal provides a visual indication of the progress of the charging algorithm. In addition, STATUS transmits two UART bytes (8 bits, no parity, one stop bit, 2400 baud) every 3.5 seconds (typical), which indicates status and fault information. IIR (Pin 53): A/D Input Pin. Connects to IMON_IN to read input current. Used to manage MPPT .
8490fa For more information www.linear .com/L T8490 VINR (Pin 54): A/D Input Pin. Connects to resistive divider on VIN to measure input voltage. Used to manage MPPT and start-up. CLKDET (Pin 56): A/D Input Pin. Connects to CLKOUT through an RC filter to detect the duty cycle of CLKOUT . Used to manage start-up. FBOR (Pin 57): A/D Input Pin. Connects to FBOUT pin to read charger output voltage. Used to manage the charg- ing algorithm. AV DD (Pin 58): A/D Positive Reference Pin. Tie this pin to VDD and LDO33. pin FuncTions CHARGECFG1 (Pin 61): A/D Input Pin. Used to configure the float voltage, temperature compensation and enable stage 3 charging. CHARGECFG2 (Pin 63): A/D Input Pin. Used to configure time limits and the valid battery temperature range. IOR (Pin 64): A/D Input Pin. Connects to IMON_OUT pin to read the charger output current. Used to manage the charging algorithm. GND (Exposed Pad 65 and Pins 55, 59, 62): Ground. Tie directly to local ground plane. NC (Pins 52, 60): Not connected.
Figure 1. Block Diagram
ware. No software or firmware development is required. voltage (EA1-EA4 respectively as shown in Figure 1). C pin limits the commanded inductor current. to limit the maximum current drawn from the input supply. the maximum battery charging voltage. Charger Restart and Fault Recovery section. The LT8490 implements a CCCV charging algorithm. assumes constant temperature and adequate input power . battery will vary accordingly. Figure 2. Typical Battery Charging Cycle
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the battery with a hardware configurable constant voltage. called Stage 2 for the remainder of this document. will be called Stage 3 for the remainder of this document. for more details about Stage 3 termination. Table 1. Description of LT8490 Charging Stages
0 T rickle
1 Constant
2 Constant
Stage 1 + Stage 2 Time Limit. MPPT for slow to moderate changes in panel illumination. the case of non-uniform panel illumination. Restart and Fault Recovery section for more information.
solar panel or a DC voltage source. desired VMAX for the application. be required to determine the best standard resistor values. for maximum input voltages of 20V, 40V, 60V and 80V. that achieve the best overall results. Table 2. Input Feedback Network vs Panel Voltage to the required voltage range for each application. Figure 3. Input Feedback Resistor Network
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tion potentially unreliable in solar powered applications. panel voltage of 6V is required to operate the charger . Figure 4. VINR Resistor Divider Circuit
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- LOW POWER MODE ENABLED: Low power mode al -
in panel voltage or a significant fall in battery voltage.
- LOW INPUT VOL TAGE EFFECTS: Figure 5 shows the
more the current can reduce. Figure 5. Minimum Full Charging Current VIN Voltage
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Figure 5. Operating V IN below this line can reduce FBIR (see Figure 3) and reconnected to the LDO33 pin. with no charging current or voltage reduction. cally below the Normal Configuration line in Figure 5. a solar panel, then connect VINR as shown in Figure 4. Figure 6. Load Connection to Battery in LT8490 Application discussed later in the Input Current Limiting section.
- The variable nature of some loads can make charg -
the battery depletes below an unacceptably low voltage. directly to a load without the presence of a battery.
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Table 3. Typical Charging Stage Voltage Thresholds RFBOUT2 is often chosen between 4.99kΩ and 49.9kΩ. multiple resistors in series to match the calculated results. results with the following equations. N1 should be as close as possible to 1.22. be required to determine best standard resistor values. Figure 7. Output Feedback Resistor Network
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Stage 2 voltage limit than the nominal batter y voltage.
these values that achieve the best overall results. Table 4. Standard Value Output Feedback Network vs Output in the Charger Configuration – CHARGECFG1 Pin section. the fault will be indicated on the FAUL T and STATUS pins. flowing out of the IMON_OUT pin (see Figure 8). Figure 8. Output Current Regulation Loop
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can introduce more noise into the ADC measurements. range of 4.7nF to 22nF is adequate for most applications. achieve the maximum charging capability of the system. used to locate the maximum power point of the solar panel. Figure 9. Input Current Regulation Loop charger components can tolerate. where IIN(MAX) is the maximum input current limit in Amps. RSENSE1 values greater than 25mΩ are not recommended.
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bility and minimizes possible inductor current overshoot. that can introduce more noise into the ADC measurements. to 22nF is adequate for most applications. Figure 11. Set this pin using a resistor divider totaling no provides more detailed information. 2 voltage limit (VS2) according to the following formulas. Figure 10. Recommended Current Sense Filter Figure 11. CHARGECFG1 Pin Configuration
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Figure 12. Battery Temperature Sensing Circuit Figure 13. Stage 2 Voltage Limit vs Temperature
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- 100% When temperature compensated charging is disabled and Stage 3 is enabled, use: CHARGECFG1%= 2.72− 2.67 • VS3 VS2
- 100% where VS3/VS2 should be between 0.86 to 0.99. For example, to enable temperature compensated charg- ing with VS3 set to 93% of VS2, choose a divider that puts CHARGECFG1 at 76% of AV DD. For best accuracy use resistors that have a 1% tolerance or better . Temperature Measurement, Compensation and Fault The LT8490 can measure the battery temperature using an NTC (negative temperature coefficient) thermistor thermally coupled to the battery pack. The temperature monitoring function is enabled by connecting a 10kΩ, ß = 3380 NTC thermistor from the TEMPSENSE pin to ground and an 11.5kΩ (1% tolerance or better) resistor from AVDD to TEMPSENSE (as shown in Figure 12). If battery temperature monitoring is not required, then use a 10kΩ resistor in place of the thermistor . This will indicate to the LT8490 that the battery is always at 25°C. The LT8490 monitors the voltage on the TEMPSENSE pin to determine the battery temperature and also to detect if the thermistor is connected or not. A TEMPSENSE volt - age greater than 96% of AV DD (typical) indicates that the thermistor has been disconnected. Three charger functions rely on the TEMPSENSE information. INVALID BA TTERY TEMPERATURE FAUL T: A tempera- ture fault occurs when the battery temperature is outside of the valid range as configured on the CHARGECFG2 pin (–20°C to 50°C or 0°C to 50°C). The temperature fault condition remains until the temperature returns within –15°C to 45°C or 5°C to 45°C (5°C of hysteresis). During a temperature fault, charging is halted and the STATUS and FAUL T pins follow the pattern described in Table 6. If timer termination is enabled with the CHARGECFG2 pin, the timer count is paused during the temperature fault and resumes when the fault state is exited. BAT TERY VOL TAGE TEMPERATURE COMPENSATION: Some battery chemistries charge best when the voltage limit is adjusted with battery temperature. Lead-acid batteries, in particular , experience a significant change in the ideal charging voltage as temperature changes. If enabled with the CHARGECFG1 pin, the battery charging voltage and all related voltage thresholds are automati- cally adjusted with battery temperature. As the voltage on the TEMPSENSE pin changes, the PWM duty cycle from the FBOW pin changes such that the voltage limits of the LT8490 follow the cur ve shown in Figure 13. BATTERY TEMPERATURE (°C) –25 100 102 104% OF VS2 AT 25°C (%) 106 108 112 110 –5 15 35–15 5 25 40 55
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- BATTERY DISCONNECT SENSING: The LT8490 detects
Figure 14. Set this pin using a resistor divider totaling no between, use one of the following formulas. information about the invalid battery temperature fault. Figure 14. CHARGECFG2 Pin Voltage Settings
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the Charger Configuration – CHARGECFG2 Pin section). amount of time that may be required to achieve full charge. the timer that expired and the configuration of the charger . TUS and FAUL T Indicators section. Table 5. Charger Conditions and Timer Expiration Results
3 Yes Stage 3 Done Charging
or above C/5 (as shown in Tables 6 and 7). STATUS pin (as shown in Tables 6 and 7). The LT8490 is well suited to charge lithium-ion batteries. charging cycle in this configuration. not exceed 95% of the lithium-ion maximum cell voltage. Figure 15. Lithium-Ion Battery Charging Cycle
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Figure 17. Example Waveform for STATUS Pin in STAGE 3 Figure 16. Lead-Acid Battery Charging Cycle
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The LT8490 can be used to charge lead-acid batteries. limits). Figure 16 shows a typical lead-acid charging cycle. the charging current rises above C/5.
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Table 6. STATUS and FAUL T LED INDICATORS these pins in relationship to the charger status. LEDs on and drive to ground to turn the LEDs off.
configuration for driving LEDs from these two pins. Figure 18, conducts ~2.5mA when STATUS is driven high. DSB conducts ~2.5mA when the STATUS is driven low. typically 3.32kΩ and increases the FAUL T LED current. rent should be limited to less than 1.5mA. collector-emitter breakdown voltage greater than INTVCC. well suited for this application. suitable for most applications. Figure 19. Higher Current Drive for STATUS/FAUL T LEDsFigure 18. Default STATUS/FAUL T LED Indicators
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Figure 20. UART T ransmission Waveform from Figure 21. Status Byte Decode zoomed in region labeled (A) from Figure 17. Table 7. Stage Description Table 8. Fault Description Table 8 is reported through the STATUS and FAUL T pins.
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0 LP S2 S1 S0 F2 F1 F0
invalid battery temperature fault. Table 9. Automatic Restart Conditions
- Not operating in power supply mode.
IN to the SHDN pin is used to set this threshold. tolerance or better required). Figure 22. SHDN Pin Resistor Divider
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Figure 23. Simplified Diagram of Switches DCM operation if this behavior is not desired. current is low to avoid discharging the battery. the input supply when charging current becomes low. Charging current is monitored on the IMON_OUT pin. from EXTVCC if EXTV CC is also above 6.4V (typical). when charging current becomes low or charging stops.
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may automatically begin operating in low power mode. with a method discussed later in this section. Performance Characteristics section. when operating with low input capacitance. input charge to the battery.
- When low power mode is disabled, the LT8490 will
normal charging operation will automatically resume.
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Figure 24. Minimum Input Capacitor
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Figure 26. Battery Discharge When Not Charging Figure 27. Optional Feedback Resistor Disconnect Circuit uses a resistor feedback network connected to the battery. able when using small capacity batteries. draw from the battery becomes negligible.
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8490 F27
age drop across the drain-source terminal of this device. LIM3 value shown in Figure 27. be limited by the required gate to source voltage of M5.
Figure 30. IR Drop Present in Battery Connection
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optional circuit shown in Figure 29. CC is reconnected to the battery. higher than the actual battery voltage by 2 • VIR. Figure 29. Optional EXTVCC Disconnect Circuit Figure 28. Optional Low Battery Voltage Feedback
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Figure 31. Remove (+) and (–) Cable VIR Measurement Errors
8490 F31
- When approaching full charge in Stage 2, the V IR er-
- Terminating at C/10 in Stage 2 will occur at a reduced
is 10% of the voltage drop at full charging current. Figure 31 can correct for these effects. in the Stage Voltage Limits section.
power rating, often at least 1W. this case. 4.99kΩ is a good value for R4. has been reconnected to the (+) battery sensing terminal. Figure 32. How to Combine Figure 27 and Figure 30
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Figure 33. Optional DC Supply Detection Circuit
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in Figure 33 shows a way to incorporate those features. avoid overvoltage of the NMOS gate. checklist and drawing is provided. electrical overstress on LT8490 pins. Hot Swap™ controller such as the LT1641, LT4256, etc. to make a current limited connection. then multiple resistors in series may be required.
8490faFor more information www.linear .com/L T8490
- With RFBOUT2 set at 20kΩ and a desired Stage 2 voltage limit of 14.2V, the top output feedback resistor , RFBOUT1, is calculated according to the following equation: RFBOUT1 = RFBOUT2 • VS2 • 1.241 1.211− 0.128⎛ ⎝⎜ ⎞ ⎠⎟−1⎡ ⎦⎥Ω = 20k • 14.2 • 1.241 1.211− 0.128⎛ ⎝⎜ ⎞ ⎠⎟−1⎡ ⎦⎥Ω = 234,684Ω Choose RFBOUT1 = 237kΩ which is the closest standard value resistor .
- Following the calculation of RFBOUT1, solve for RDACO1, RDACO2 and CDACO according to the following formulas: RDACO2 = RFBOUT1 •RFBOUT2 •0.833 RFBOUT2 •VS2 •1.241 1.211 ⎝⎜ ⎞ ⎠⎟−RFBOUT2 −RFBOUT1 Ω = 234,684•20k •0.833 20k •14.2 •1.241 1.211 ⎝⎜ ⎞ ⎠⎟− 20k − 234,684 Ω = 107,556Ω Choose RDACO2 = 107kΩ which is the closest standard value resistor . RDACO1 = (0.2 • RDACO2) Ω = 0.2
- 107,556Ω = 21,511Ω Choose RDACO1 = 21.5kΩ which is the closest standard value resistor . CDACO = 1 500 •RDACO1 F = 1 500 •21 ,511F = 93nF applicaTions inForMaTion
- Using the standard value resistors calculated above, the VX3, N1 and N2 checking equations yield the following: VX3 = 14.31V N1 = 1.22 N2 = 0.804
- In order to find a resistor combination that yields VX3 closer to the desired 14.2V, RFBOUT2 is increased to the next higher standard value and the above calculations are repeated. Iterations of the previous step are performed that include adjustments to R FBOUT1, RDACO1 and R DACO2 until the following standard value feedback resistors were chosen: RFBOUT1 = 274kΩ RFBOUT2 = 23.2kΩ RDACO1 = 26.1kΩ RDACO2 = 124kΩ CDACO = 0.082µF where VX3 = 14.27V N1 = 1.22 N2 = 0.805
- With the output feedback network determined, use VMAX and solve for the input resistor feedback network according to the following formulas: RFBIN1 = 100k • 1+ 4.47V VMAX − 6V 1+ 5.593V VMAX − 6V Ω = 100k • 1+ 4.47V 53V − 6V ⎝⎜ ⎞ 1+ 5.593V 53V − 6V ⎝⎜ ⎞ Ω = 97,865Ω
8490fa For more information www.linear .com/L T8490 applicaTions inForMaTion The closest standard value for RFBIN1 is 97.6kΩ. RDACI2 = 2.75 • RFBIN1 VMAX − 6V ⎟ Ω = 2.75 • 97,865 53V − 6V ⎝⎜ ⎞ ⎠⎟ Ω = 5,726Ω Choose RDACI2 = 5.76kΩ which is the closest standard value. RFBIN2 = 1 100k −RFBIN1 ⎠⎟− 1 RDACI2 Ω = 1 100k − 97,865 ⎠⎟− 1 5,726 Ω = 3,404Ω Choose RFBIN2 = 3.4kΩ which is the closest standard value. RDACI1 = 0.2 •RDACI2 Ω = 0.2 •5,726Ω = 1 ,145Ω Choose RDAC1 = 1.1kΩ which is the closest standard value. CDACI = 1 1000 •RDACI1 F = 1 1000 •1 ,145F = 873nF
- Similar to the output feedback resistors, the final input feedback resistors were chosen to be standard values using an iterative process. The V X1 and VX2 equations in the Input Voltage Sensing and Modulation Network section were used to validate the selections: RFBIN1 = 93.1kΩ RFBIN2 = 3.24kΩ RDACI1 = 1.05kΩ RDACI2 = 5.49kΩ CDACI = 1µF where VX1 = 6V VX2 = 53V
- The 10A maximum charge current limit and 2.5A trickle charge current limit are set by choosing RSENSE2, RIMON_OUT and RIOW using the following formulas: RSENSE2 = 0.0497 IOUT(MAX) Ω =0.0497 10 ≅ 5mΩ RIMON _ OUT = 1208 IOUT(MAXS0) •RSENSE2 Ω = 1208 2.5 •5mΩ = 96.64kΩ where the nearest standard value is 97.6kΩ. RIOW = 24.3k •RIMON _ OUT RIMON _ OUT − 24.3k Ω = 24.3k •47.6k 97.6k − 24.3k Ω = 32,356Ω where the nearest standard value is also 32.4kΩ.
8490faFor more information www.linear .com/L T8490 applicaTions inForMaTion
- The input current limit is set by properly choosing RSENSE1. In this example, the panel can deliver up to 5.4A. Choosing a margin of 30% yields: RSENSE1 = 0.0505 IIN(MAX) = 0.0505 1.3 •5.4 = 7.2mΩ
- To enable temperature compensated charging limits and allow a Stage 3 regulation voltage of 97.2% of Stage 2, use V S3 /V S2 = 0.972 in the following equation: CHARGECFG1%= 2.67 • VS3 VS2 − 0.85 ⎟+ 0.55 ⎥ •100% CHARGECFG1%= 87.6% Standard resistor values of 90.9kΩ (from CHARGECFG1 to ground) and 13kΩ (from AVDD to CHARGECFG1) can be used to set CHARGECFG1.
- To set no time limits with a –20°C to 50°C valid battery temperature range requires CHARGECFG2 to be tied to AV DD.
- For greater charging voltage accuracy , it is recom - mended that 0.1% tolerance resistors be used for the output feedback resistor network. Please reference the LT8705 data sheet for completing the remaining power portions of the LT8490.
Figure 34. 27.4V Lithium-Ion Polymer Battery Charger
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8490faFor more information www.linear .com/L T8490 applicaTions inForMaTion 56.8V Lead-Acid Battery Charger (Four 12V Batteries in Series) CIN2 2.2µF
8490 TA02
CSPBG1 SW1BOOST1TG1 CSN GND BG2 SW2 BOOST2 TG2 CSPOUT CSNOUT EXTVCC FBOR FBOUT FBOW 10/uni03A9 6m/uni03A9 15µH ½W 10m/uni03A9 COUT2 4.7µF COUT3 4.7µF C IN3 2.2µF COUT1 220µF 100/uni03A9 220nF220nF DB1 22.6k GATEVCC´ VDD AVDD CIN4 2.2µF DB2 GATEVCC´ FLOODED LEAD ACID LOAD 5m/uni03A9 470nF 549/uni03A9 VOC < 80V SOLAR PANEL M1 M4 20k TEMPSENSE SRVO_FBIN SRVO_IIN SRVO_FBOUT SRVO_IOUT ECON SWEN SWENO CHARGECFG1CHARGECFG2 RT SS IIR IMON_IN IOW IMON_OUT IOR STATUS FAULTSYNC V C CLKDET CLKOUT LT8490 549/uni03A9 DFDS 115k LDO33 CSNIN CSPIN V IN GATEVCCGATEVCC´ MODE INTVCC FBIN FBIR FBIW VINR SHDN 4.7µF 0.1µF 1µF 100nF 10/uni03A9 10/uni03A9 90.9k 200k 4.7µF 196k 8.06k 133k 3.09k 110k 35.7k 4/uni03A9 4.87k 301k 53.6k 1.3k 13k 3.32k 1.05k1µF 100nF 8.2nF 56.8V STAGE 2 (ABSORPTION) CHARGE VOLTAGE (VS2) AT 25°C 55.2V STAGE 3 (FLOAT) CHARGE VOLTAGE (VS3) AT 25°C 5A CHARGING CURRENT LIMIT 1.25A TRICKLE CURRENT LIMIT 11.4A INPUT CURRENT LIMIT 80V MAXIMUM PANEL VOLTAGE (V MAX) NO TIMER LIMITS TEMPERATURE COMPENSATION ENABLED –20°C TO 50°C BATTERY TEMPERATURE RANGE 145kHz SWITCHING FREQUENCY EXAMPLE SOLAR PANEL: SHARP NT-175UC1 175W, SHARP NU-U235F3 235W M1: INFINEON BSC046N10NS M2: INFINEON BSC109N10NS M3, M4: INFINEON BSC057N08NS L1: 15µH COILCRAFT SER2915H-153KL D B1, DB2: CENTRAL SEMI CMMR1U-02 CIN1, COUT1: 220µF, 100V, UNITED CHEMI-CON EKZE101ELL221MK255 CIN2, CIN3, CIN4: 2.2µF, 100V, AVX 12101C225KAT2A COUT2, COUT3: 4.7µF, 100V, TDK C4532X7S2A475M230KB COUT4: 1µF, 100V AVX 12101C105KAT2A CCSPOUT: 100nF, 50V, AVX 08055C10 68nF 11.3k 3.01k 32.4k 220pF 10nF 21k 97.6k10nF 470nF 11.5k 10k AT 25°C ß = 3380 NTC AV DD AVDD CIN1 220µF COUT4 1µF CCSPOUT 100nF
8490fa For more information www.linear .com/L T8490 package DescripTion Variation: UKJ64(58) 64(58)-Lead Plastic QFN (7mm × 11mm) (Reference L TC DWG # 05-08-1922 Rev Ø) 11.00 ±0.10 7.00 ±0.10 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS PIN 1 TOP MARK (SEE NOTE 6) BOTTOM VIEW—EXPOSED PAD 11.00 ±0.10 9.50 REF 0.75 ±0.05 0.25 ±0.05 (UKJ64(58)) QFN 0412 REV Ø
0.50 BSC
0.50 REF
0.200 REF
0.00 – 0.05 APPL Y SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.50 REF
0.325 REF 0.40 ±0.10 0.45
9.50 REF
11.50 ±0.05 10.10 ±0.05 7.50 ±0.05 0.70 ±0.05 1.50 ±0.05 9.38 ±0.05 3.60 ±0.05 3.83 0.25 ±0.05 PACKAGE OUTLINE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 6453 31 27 25 21 Variation: UKJ64(58) 64(58)-Lead Plastic QFN (7mm × 11mm) (Reference LTC DWG # 05-08-1922 Rev Ø) 3.60 ±0.10 3.83 ±0.10 0.45 ±0.10 9.38 ±0.10 1.50 ±0.10 1 .20 ±0. 10 1.80 ±0.05 Please refer to http://www.linear .com/product/LT8490#packaging for the most recent package drawings.
8490faFor more information www.linear .com/L T8490 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER A 11/15 Changed diode type symbol. Modified the Block Diagram. 1, 38, 39, 42
8490fa For more information www.linear .com/L T8490 LINEAR TECHNOLOGY CORPORATION 2014 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear .com/L T8490 LT 1115 REV A • PRINTED IN USA relaTeD parTs Typical applicaTion PART NUMBER DESCRIPTION COMMENTS LT3652/LT3652HV Power T racking 2A Battery Charger for Solar Power VIN Range = 4.95V to 32V (LT3652), 4.95V to 34V (HV), MPPC LTC4000-1 High Voltage, High Current Controller for Battery Charger with MPPC V IN and VOUT Range = 3V to 60V, MPPC LTC4020 55V VIN/VOUT Buck-Boost Multi-Chemistry Battery Charging Controller Li-Ion and Lead-Acid Algorithms, MPPC 14.2V Flooded Lead-Acid Battery Charger CIN2 2.2µF
8490 TA03
3.3nF 3.3nF 10/uni03A9 CSPBG1 SW1BOOST1TG1 CSN GND BG2 SW2 BOOST2 TG2 CSPOUT CSNOUT EXTVCC FBOR FBOUT FBOW 10/uni03A9 5m/uni03A9 15µH 2/uni03A9 COUT2 10µF C OUT3 10µF C IN3 2.2µF COUT1 150µF 220nF220nF DB1 26.1k GATEVCC´ 274k VBAT VDD AVDD CIN4 2.2µF DB2 GATEVCC´ FLOODED LEAD ACID LOAD 7m/uni03A9 5m/uni03A9 470nF 549/uni03A9 VOC < 53V SOLAR PANEL 2/uni03A9 M1 M4 23.2k TEMPSENSE SRVO_FBIN SRVO_IIN SRVO_FBOUT SRVO_IOUT ECON SWEN SWENO CHARGECFG1CHARGECFG2 RT SS IIR IMON_IN IOW IMON_OUT IOR STATUS FAULTSYNC V C CLKDET CLKOUT LT8490 549/uni03A9 DFDS 124k LDO33 CSNIN CSPIN V IN GATEVCCGATEVCC´ MODE INTVCC FBIN FBIR FBIW VINR SHDN 4.7µF 10k AT 25°C ß = 3380 NTC 0.082µF 1µF 100nF 10/uni03A9 10/uni03A9 200k 90.9k 4.7µF 196k 8.06k 93.1k 3.24k 110k 35.7k 4/uni03A9 5.49k 249k 53.6k 1.3k AVDD 3.32k 1.05k1µF 100nF 4.7nF 14.27V STAGE 2 (ABSORPTION) CHARGE VOLTAGE (VS2) AT 25°C 13.87V STAGE 3 (FLOAT) CHARGE VOLTAGE (VS3) AT 25°C 10A CHARGING CURRENT LIMIT 2.5A TRICKLE CURRENT LIMIT 7.2A INPUT CURRENT LIMIT 53V MAXIMUM PANEL VOLTAGE (V MAX) NO TIMER LIMITS TEMPERATURE COMPENSATION ENABLED –20°C TO 50°C BATTERY TEMPERATURE RANGE 175kHz SWITCHING FREQUENCY EXAMPLE SOLAR PANEL: SHARP NT-175UC1 175W M1, M2: INFINEON BSC028N06NS M3, M4: INFINEON BSC042N03LSG L1: 15µH COILCRAFT SER2915H-153KL D B1, DB2: CENTRAL SEMI CMMR1U-02 CIN1: 33µF, 63V, SUNCON 63HVH33M CIN2, CIN3, CIN4: 2.2µF, 100V, AVX 12101C225KAT2A COUT1: 150µF, 35V NICHICON UPJ151MPD6TD COUT2, COUT3: 10µF, 35V, MURATA GRM32ER7YA106KA12 COUT4: 1µF, 25V AVX 12063C105KAT2A 68nF 8.45k 3.01k 32.4k 470pF 10nF 21k 97.6k8.2nF 470nF 11.5k 13k AVDD CIN1 33µF COUT4 1µF