LT8418

Data Sheet

Document overview

• PDF pages: 19

Technical content

100V Half-Bridge GaN Driver with Smart Integrated Bootstrap Switch Pre-release Rev 0 DOCUMENT FEEDBACK TECHNICAL SUPPORT

FEATURES

 Half-Bridge Gate Driver for GaN FETs  0.6Ω Pull-Up Resistance at Top Gate Driver  0.2Ω Pull-Down Resistance at Bottom Gate Driver  4A Peak Source, 8A Peak Sink Current Capability  Smart Integrated Bootstrap Switch  Split-Gate-Driver to Adjust Turn-On/Turn-Off Strength  Default Low-State for All Driver Inputs and Outputs  Maximum 15V Voltage Rating at INT and INB Inputs  Independent INT, INB Inputs with TTL Logic Compatible  Fast Propagation Delay: 10ns (Typical)  Propagation Delay Matching: 1.5ns (Typical)  Balanced Driver Supply Voltage: VBST ≈ VCC = 3.85V – 5.5V  Undervoltage and Overvoltage Lockout Protections  Small 12-Ball WLCSP Package

APPLICATIONS

 High Frequency DC-DC Switching Power Converters  Half-Bridge, Full-Bridge, Push-Pull Converters  Data Center Power Supplies  Motor Drivers, Class-D Audio Amplifiers  Consumer, Industrial, and Automotive GENERAL DESCRIPTION The LT8418 is a 100V half -bridge GaN driver that integrates top and bottom driver stages, driver logic control, and protections. It can be configured into synchronous half -bridge, full -bridge topolog ies, or buck, boost, and buck -boost topologies. The LT8418 provides strong current sourcing/sinking capability with 0.6Ω pull -up and 0.2Ω pull -down resistance. It also integrates smart integrated bootstrap switch to generate a balanced bootstrap voltage fr om VCC with a minimum dropout voltage. The LT8418 provides split gate drivers to adjust the turn- on and turn -off slew rates of GaN FETs to suppress ringing and optimize EMI performance. All driver inputs and outputs have default low-state to prevent GaN FETs from false turn -on. The inputs of the LT8418, INT, and INB are independent and TTL logic compatible. Meanwhile, the LT8418 performs with a fast propagation delay of 10ns and maintains an excellent delay matching of 1.5ns between the top and bottom chan nels, making it suitable for high -frequency DC-DC converters, motor drivers, and class -D audio amplifiers. In addition, the LT8418 employs the WLCSP package to minimize parasitic inductance, enabling its wide use in high - performance and high-power density applications. TYPICAL APPLICATION Figure 1. Highly Efficient GaN-Based Switching DC-DC Converter

analog.com Rev 0 2 of 19 TABLE OF CONTENTS

REVISION HISTORY

10/2023 – Rev. 0

Table 1. Electrical Characteristics

analog.com Rev 0 4 of 19 (TA = 25°C1, VCC = VBST = 5V, VGND = VSW = 0V; TGP and TGN are connected; BGP and BGN are connected) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS TG Rise Time tTGR CL = 1nF, 10% to 90% 2.5 ns TG Fall Time tTGF CL = 1nF, 90% to 10% 2.5 ns BG Rise Time tBGR CL = 1nF, 10% to 90% 2.5 ns BG Fall Time tBGF CL = 1nF, 90% to 10% 2.5 ns Propagation Delay, Delay Matching, and Minimum Input Pulse2 TG Turn-On Propagation Delay tRPD_TG INT Rising to TG Rising (TGP = TGN = TG) 10 16 ns TG Turn-Off Propagation Delay tFPD_TG INT Falling to TG Falling 10 15 ns BG Turn-On Propagation Delay tRPD_BG INB Rising to BG Rising (BGP = BGN = BG) 10 16 ns BG Turn-Off Propagation Delay tFPD_BG INB Falling to BG Falling 10 15 ns TG Turn-Off and BG Turn-On Delay Mismatch tDMF 0.5 5 ns BG Turn-Off and TG Turn-On Delay Mismatch tDMR 0.5 6.5 ns TG, BG Minimum Input Pulse Width tTGW, tBGW 11 ns The LT8418 is tested under pulsed load conditions such that TJ ≈ TA. The LT8418A is guaranteed to meet specifications from –40°C to 125°C junction temperature. High junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125°C. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance, and other environmental factors. The junction temperature (TJ, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD × JA), where θJA (in °C/W) is the package thermal impedance. The definition of propagation delay for the top or bottom side gate driver and delay matching is illustrated in the following timing diagram.

Figure 2. Timing Definitions of Propagation Delay and Delay Matching TA = 25°C1, unless otherwise specified. Table 2. Absolute Maximum Ratings Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. (PD, in Watts) according to the formula: TJ = TA + (PD • JA), where θJA (in °C/W) is the package thermal impedance. or permanently damage the device.

Table 3. 12-Ball WLCSP Package Thermal Resistance

Figure 3. Pin Diagram Table 4. Pin Descriptions FET’s gate can program the turn-off strength of the bottom side GaN FET. ground with a minimum 4.7µF ceramic capacitor. 200 kΩ pull-down resistance internally. Leave it open or tie it to ground when it is not used. gate can program the turn-on strength of the bottom side GaN FET. minimum input pulse width for INT is 11ns. terminal of the bootstrap capacitor with low inductance and resistance. FET’s gate can program the turn-off strength of the top side GaN FET. gate can program the turn-on strength of the top side GaN FET. minimum 100nF ceramic capacitor. 1 A3 and C4 are internally connected. C1 and D4 are internally connected.

Figure 4. Block Diagram

analog.com Rev 0 12 of 19 THEORY OF OPERATION The LT8418 is a 100V half-bridge GaN driver that integrates top, bottom gate drivers, VCC, BST, UV, and OV protection control logic. It can be used in half bridges and full bridges. It is very flexible to support multiple topologies including buck, boost, buck -boost, and a variety of applications, including data center power, class -D audio amp lifier, and motor drivers. In addition, the LT8418 employs a small -footprint WLCSP package, which can be used in different applications requiring high-power density, high-frequency operation, small form factor, and low cost. 1.1. Chip Start-up, VCC UVLO/OVLO Protections The LT8418 has an undervoltage lockout (UVLO) in the V CC drive power rail. When the VCC voltage is falling below the threshold voltage of 3.35 V, both the TG and BG pins are turned off to prevent the GaN FETs from being falsely turned on. When the V CC voltage rises above its UVLO threshold of 3.55V (with 200mV hysteresis voltage), the LT8418 is activated after a 100µs wakeup time. After that, the LT8418 senses INT and INB signals, and controls TG and BG outputs. Due to the charging time of the BST rail, TG is prohibited from turning on until the BST UV threshold of 3.35V is reached. On the other hand, to protect the GaN FETs from overdrive voltage and gate damage, V CC OVLO (overvoltage lockout) feature is integrated into the LT8418. When the VCC voltage rises above 6.0V, VCC OV is triggered, which turns off both TG and BG; until the V CC voltage falls below 5.8V, VCC OV is recovered and TG/BG starts to switch again following INT and INB control signals. 1.2. Input Interface INT, INB The input pins of the LT8418 are independently controlled with TTL input thresholds and can withstand voltages up to 15V. This allows the inputs to be directly connected to the outputs of an analog PWM controller with up to 15V power supply, eliminating the need for a buffer stage. The LT8418 input pins, INT and INB, are independent and TTL logic compatible. The LT8418 provides a fast propagation delay of 10ns and maintains an excellent delay matching of 2.5ns between the top and bottom channels, making it su itable for high -frequency switching operations. Both driver input pins, INT and INB, have a default pull -down resistor of 200kΩ to prevent GaN FETs from false turn -on. LT8418 does not implement an overlap protection. If both INT and INB are asserted, both the high-side and low-side GaN FETs are turned on. Careful consideration must be applied to the input interface to avoid a possible shoot - through condition. 1.3. Smart Bootstrap (BST) Switch and BST UVLO During the dead time interval between TG turn-off to BG turn -on, or between BG turn -off to TG turn -on, the GaN power switch demonstrates a high reverse conduction voltage of 2V ~ 3V from source to drain (even higher at high conduction current), which can bring SW node down to –2V ~ –3V and leads to the overcharge of BST rail and permanent gate damage of GaN power switch. In the LT8418, the smart BST switch consists of power switches that can be fully controllable for BST charging or blocking. When the bottom switch is turned on and the switching n ode voltage is close to ground level, the BST switch is turned on to start charging the BST capacitor. In this way, the LT8418 is able to generate a well -balanced bootstrap voltage from V CC with a minimum dropout voltage, which prevents GaN FETs from overcharge and gate damage, as well as achieves matched propagation delay between the top and bottom drivers and maintains balanced gate drive strength. The LT8418 provides a bootstrap UVLO protection to prevent GaN FETs from turn -on at an insufficient gate dri ve voltage. When the BST-SW rail falls below 3.1V, TG stops to turn on until the BST capacitor is replenished and the BST rail rises above 3.35V (250mV hysteresis), and TG starts to switch again. 1.4. Split Gate Driver The LT8418 also provides split gate drivers for both top and bottom power switches. Thus, turn-on and turn-off slew rates of the top and bottom gate drivers are adjustable independently by connecting different values of gate resistors at TGP, TGN, BGP, and BGN pins. Besides, the LT8418 integrates strong gate drivers with 0.6Ω pull-up resistance, 0.2Ω

analog.com Rev 0 13 of 19 pull-down resistance, a strong 4A current sourcing, and 8A current sinking capability, which is suited to use to drive a variety of GaN FETs with different Q G or RDS(ON) values. All driver outputs, TGP and TGN, have default 500kΩ pull - down resistance to SW node; BGP and BGN have default 500kΩ pull -down resistance to ground to prevent top and bottom GaN FETs from false turn-on. APPLICATIONS INFORMATION The front page shows a typical LT8418 application circuit. This section serves as a guideline for selecting external components for typical applications. 1.1. Selecting the VCC and BST Capacitor The LT8418 can support a wide range of switching frequencies. T hus, the VCC and BST capacitors must be selected properly based on the system switching frequency, QG, of GaN FETs. The bypass capacitor CVCC provides the gate charge for the top-side and bottom-side GaN FETs. The charge to turn on the external GaN FET is referred as gate charge, QG, and is typically specified in the external GaN FET data sheet. Gate charge depends on the gate drive level and external GaN FET, ranging from 1nC to tens of nC. The required bypass capacitance can be approximated as: CVCC > QGT + QGB (1) where: QGT and QGB are the gate charge of the top-side and bottom-side GaN FETs, respectively. ∆V is the maximum allowable voltage drop across CVCC. An external boost capacitor, CBST, connected between BST and SW, supplies the gate driver voltage for its respective GaN FET driver. To turn on the external GaN FET, the driver places the CBST voltage across the gate and source of the GaN FET. The C BST capacitance must have at least ten times the gate capacitance to fully turn on the external G aN FET. For most applications, a capacitor value of 0.1uF for C BST is sufficient. However, if multiple GaN FETs are paralleled and driven by the LT8418, the C BST capacitance must be increased correspondingly and should be maintained in the following relationship: CBST > 10QGT,TOTAL (2) A BST switch is integrated into the LT8418 to keep charging the CBST, eliminating the requirement of the external VCC- to-BST Schottky diode. An additional diode from V CC to BST may cause the overcharge of the BST rail and gate damage of high side GaN FET. When the BG/TG is low, the total current from V CC is typically 250μA; when the BG/TG is switching at 400kHz with a 1nF capacitance load at driver outputs, the total current from VCC is typically 2.4mA. 1.2. Selecting the Gate Resistance The LT8418 provides split gate drivers for top and bottom GaN power switches. A typical gate resistor up to 5.6Ω can be added to TGP/TGN and BGP/BGN pins to adjust the turn -on/turn-off rate of two GaN FETs for electromagnetic interference (EMI) and efficiency optimization. 1.3. Power Dissipation The major power dissipation on the LT8418 is the sum of the power loss on the gate driver and the BST switch. The gate driver loss is caused by charging and discharging the gate capacitan ce of the GaN FETs. Because the gate loss

analog.com Rev 0 14 of 19 occurs once per cycle, it is proportional to the switching frequency. Unlike a pure capacitive load, a power GaN FET’s gate capacitance seen by the driver output varies with its V GS voltage level (V CC in this case) during switching. For simplicity, the gate power dissipation can be calculated using its gate charge Q G. For identical GaN FETs on BG and TG, the gate loss is: Pgate = 2QG ·VCC ·fsw (3) The reverse recovery loss and forward bias power loss on the traditional bootstrap diode are avoided by using the integrated BST switch. The BST switch loss is dominated by the conduction loss on its R DS(ON) while charging the capacitor. Larger GaN FET gate capacitance requires more current to charge the BST capacit or, resulting in more loss: PBST = D ·IBST 2 ·RDS(ON),BST (4) where: IBST is the BST operating current charging the top-side gate capacitance. RDS(ON),BST is the on-resistance of the BST switch. 1.4. PCB Bypass and Grounding Guideline The LT8418 requires proper bypassing on the V CC, BST-SW supplies due to its high -speed switching (nanoseconds) and large AC currents. Careless component placement and PCB routing may cause excessive ringing and undershoots/overshoots. To obtain the optimum performance from the LT8418:  Mount the capacitors as close as possible between the VCC and GND pins, and the BST and SW pins. The traces should be shortened as much as possible to reduce lead inductance.  Use a low -inductance, low -impedance ground plane to reduce any ground drop and stray capacitance. Remember that the LT8418 can sink up to 8A peak currents and any significant ground drop degrades signal integrity.  Plan the power/ground routing carefully. Know where the large load switching current is coming from and going. Maintain separate ground return paths for the input pin and output power stage.  Kelvin connect the TG pin to the top GaN FET gate and SW pin to the top GaN FET source. Kelvin connect the BG pin to the bottom GaN FET gate and the driver gro und to the bottom GaN FET source. Keep the copper trace between the driver output pin and load short and wide. 1.5. Soldering Guideline Precondition the solder pad with flux for better solder flow. Because of the small solder balls, type 4 solder paste (20 microns to 38 microns grain size) or finer solder paste is recommended to apply on the pad. After placing the IC manually, a telescope should be used to ensure a good alignment. For better accuracy, it is recommended to use automated fine-pitch placement machines with vision alignment. Melt the solder paste using a hot plate instead of a heat gun to prevent the IC from being blown away. To verify good connections, vision inspection, and X -ray inspection are recommended. Failure to make good electri cal or thermal contact between the balls and the copper board causes driver or system malfunction or higher thermal resistance.

Figure 23. Package Drawing

1.20 REF

Figure 27. Efficiency vs. Load Current (with Heat Sink)

Table 5. Ordering Guide dead time control, tristate PWM input with enable pin. pull-up, 4.5A peak pull-down. peak pull-up, 1.2Ω/0.55Ω peak pull-down. peak pull-up, 1.2Ω/0.55Ω peak pull-down.

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