LT83402

LT83401/LT83402 Rev. 1

Document overview

• Manufacturer or author: Analog Devices, Inc.
• PDF pages: 45

Technical content

42V, 1A/2.5A Step-Down Silent Switcher 3 with Ultra-Low Noise Reference Rev. 1 DOCUMENT FEEDBACK TECHNICAL SUPPORT ©2026 A n a l o g D e v i c e s , I n c . A l l r i g h t s r e s e r v e d .

FEATURES

 Silent Switcher® 3 Architecture  Ultra-Low RMS Noise (10Hz–100kHz): 2.8μVRMS  Ultra-Low Spot Noise: 4nV/√Hz at 10kHz  Ultra-Low EMI Emissions  Ultra-Fast Transient Response  Minimizes the Output Capacitance  High Efficiency at High Frequency  Up to 92.4% Efficiency at 2MHz, 12VIN to 5VOUT  Input Voltage Range: 2.8V to 42V  Output Voltage Range: 0V to (VIN - 1V)  Unity Gain Configuration Up to 15VOUT  Fast Minimum Switch On-Time: 22ns  Precision Reference: ±0.8% Over Temperature with Remote Sense  Forced Continuous Mode Capability  Adjustable and Synchronizable: 300kHz to 6MHz  Programmable Power Good  Tiny, 15-Lead 3mm x 2mm LFCSP Package  Pin-to-Pin Compatible Family: LT83201 (18V, 1A), LT83203 (18V, 3A), and LT83205 (18V, 5A)  AEC-Q100 Qualified for Automotive Applications GENERAL DESCRIPTION The LT®83401/LT®83402 synchronous step -down regulator is uniquely designed to combine an ultra - low-noise reference with Silent Switcher architecture to achieve both high efficiency and excellent wideband noise performance. The innovative, ultra-low noise architecture provides exceptional low -frequency (0.1Hz to 100kHz) output noise performance in a switching regulator. The output voltage can be programmed with a single resistor, resulting in virtually constant output noise independent of output voltage. Silent Switcher architecture minimizes Electro - magnetic interference (EMI) emissions while delive - ring high efficiency at high switching frequencies. The LT83401/LT83402 is ideal for high -current, noise- sensitive applications that benefit from the high efficiency of a synchronous switching regulator.

APPLICATIONS

 Automotive and Industrial Power Supplies  Medical Applications: Imaging and Diagnostics  High-Speed and High-Precision Data Converters  Bipolar, Very Low-Noise Power Supplies  Low-Noise Instrumentation and Displays TYPICAL APPLICATION Figure 1. Simplified Application Diagram Figure 2. 12V to 3.3V Efficiency

Data Sheet LT83401/LT83402 analog.com Rev. 1 2 of 45 TABLE OF CONTENTS

Data Sheet LT83401/LT83402 analog.com Rev. 1 3 of 45

REVISION HISTORY

0 10/25 Initial release ─ 1 4/26 Updated Features section Updated EC table Updated Figure 20 Updated Forced Continuous Mode (FCM) and Synchronization sections Updated Fast Start-Up section, Equation 13 Included Figures 60 and 61 Updated Figure 64 Included Figures 65, 66, and 67 Updated Ordering Guide table 5, 6 40, 41

Table 1. Electrical Characteristics

Data Sheet LT83401/LT83402 analog.com Rev. 1 5 of 45 (TJ = -40°C to +150°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to GND, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS PGFB Lower Threshold Hysteresis VPGL_HYS 10 mV PGFB Lower Threshold (Start-Up Only) VPGL_STARTUP VPGFB rising 479 487 495 mV PGFB Pin Current IPGFB VIN = 12V, VEN/UVLO = 2V, VPGFB = 0.5V 13 nA Power Good (PG) Leakage IPG_LKG VPG = 3.3V, TA = +25°C -40 +40 nA PG Pull-Down Resistance RPG VPG = 0.5V 380 1200 Ω SYNC/MODE Threshold VIL SYNC/MODE DC and clock low- level voltage 0.7 V VIH SYNC/MODE DC and clock high- level voltage 1.5 OUTS Pin Output Current IOUTS VOUTS = 1V, TA = +25°C 110 170 230 nA Output Voltage Line Regulation5 ΔVOUT(LINE) VIN = 4V to 42V, TA = +25°C 0.001 0.01 %/V Error Amp Offset5, 6 VEA, OFFSET VC = 1.2V, VSET = 3V, VIN = 12V, positive-negative-positive (PNP)– based input pair -2 +2 mV VC = 1.2V, VSET = 5V, VIN = 5.7V, negative-positive-negative (NPN)– based input pair -2 +2 Error Amp Transconductance6 gm(EA) VC = 1.2V, VSET = 3V, VIN = 12V, PNP–based input pair, TA = +25°C 9.5 12 14.5 mS gm(EA) VC = 1.2V, VSET = 5V, VIN = 5.7V, NPN-based input pair, TA = +25°C 8.3 10.5 12.7 Error Amp Gain AV VC = 1.2V, VSET = 1V, VIN = 6V, LT83401 2400 V/V VC = 1.2V, VSET = 1V, VIN = 6V, LT83402 2000 VC Source Current6 IVC-SRC VC = 1.2V, VSET = 3V, VIN = 12V, PNP– based input pair 340 μA VC = 1.2V, VSET = 3V, VIN = 12V, NPN– based input pair 340 VC Sink Current6 IVC-SNK VC = 1.2V, VSET = 3V, VIN = 12V, PNP- based input pair 340 μA VC = 1.2V, VSET = 3V, VIN = 12V, NPN- based input pair 340 VC Pin-to-Switch Current Gain GM LT83401 2.3 A/V LT83402 3.6 VC Clamp Voltage VC_CLAMP 2 V Minimum On-Time tON(MIN) ILOAD = 1A 22 27 ns

Data Sheet LT83401/LT83402 analog.com Rev. 1 6 of 45 (TJ = -40°C to +150°C, unless otherwise noted. Typical values are at TA = +25°C. All voltages are referenced to GND, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS/COMMENTS MIN TYP MAX UNITS Minimum Off-Time tOFF(MIN) ILOAD = 0.5A, LT83401 ILOAD = 1A, LT83402 80 105 ns Top Power N-Channel Bottom Power N-Channel MOSFET Current Limit IVALLEY-LIMIT LT83401 1.28 1.5 1.72 A LT83402 1.95 2.4 2.85 SW Leakage Current ISW_LKG VIN = 42V, VSW = 0V, 42V, TA = +25°C -1 +1 μA Power MOSFET On-Resistance Main Switch (Top) RDS-ONH 280 mΩ Power MOSFET On-Resistance Synchronous Switch (Bottom) RDS-ONL 135 mΩ SET Pull-Down Resistance RSET-PULLDOWN VSET = 0.5V 540 865 Ω EN/UVLO Threshold VENR EN/UVLO rising 0.7 0.75 0.8 V EN/UVLO Hysteresis VEN_HYS 55 mV EN/UVLO Input Current IEN VEN/UVLO = 2V, TA = +25°C -40 +40 nA 1 Not subject to production test. 2 The start-up time is defined as the time it takes from the EN/UVLO pin rising above the EN/UVLO threshold to when VOUT has reached 95% of its final value. 3 OUTS ties directly to VOUT. 4 Adding a capacitor across the SET pin resistor decreases output voltage noise. Adding this capacitor bypasses the SET pin resistor’s thermal noise as well as the reference current’s noise. Use of a SET pin bypass capacitor also increases start-up time. 5 The LT83401/LT83402 is tested in a feedback loop that servos VC to a specified voltage and measures the resultant VOUTS. 6 The PNP-based input pair is active for the error amplifier as long as VIN is at least 1.4V above VSET. As VIN drops to less than 1.4V above VSET, the part gradually transitions to operating with the NPN-based input pair active. 7 Thermal Resistance (θ) values determined per JEDEC 51-7, 51-12. For information on improving the thermal resistance and for actual temperature measurements of a demo board in typical operating conditions, see the Applications Information section. 8 This IC includes overtemperature protection that is intended to protect the device during overload conditions. Junction temperature exceeds 150°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature reduces lifetime.

TA = 25°C, unless otherwise specified. Table 2. Absolute Maximum Ratings extended periods may affect product reliability.

Figure 3. Pin Configurations Table 3. Pin Descriptions 1 RT A resistor is connected between the RT and ground to set the switching frequency. or during thermal shutdown. PG is valid when VIN is above 2.8V.

3 SYNC/MODE

9 BST

10 INTVCC

11 EN/UVLO

13 SET

14 OUTS

15 PGFB

16 GND

Data Sheet LT83401/LT83402 analog.com Rev. 1 9 of 45 4, 8 VIN The VIN pins supply current to the LT83401/LT83402 internal circuitry and to the internal topside power switch. Two 0402 capacitors of 0.1µF or more should be placed to bypass both VIN pins, with the positive terminal of the input capacitor as close as possible to the VIN pins, and the negative capacitor terminal as close as possible to the GND pins. VIN pins must also be connected with an additional local bypass capacitor of 4.7µF or more. To provide sufficient headroom for the current reference, VIN must be at least 900mV higher than the required regulation setpoint that is programmed via the SET pin. For example, for the required regulation setpoint of 3.3V, VIN must be at least 3.3V + 900mV = 4.2V, or higher. 5, 7, 16 (Exposed Pad) GND Ground. Place the negative terminal of the input capacitor as close to the GND pins as possible. The exposed pads should be soldered to the PCB for good thermal performance. If necessary due to manufacturing limitations, the exposed pad may be left disconnected; however, the performance degrades. 6 SW The SW pin is the output of the internal power switches. Connect this pin to the inductor. This node must be kept small on the PCB for good performance and low EMI.

9 BST This pin is used to provide a drive voltage higher than the input voltage to the topside

power switch. Place a 0.1µF boost capacitor as close as possible to the IC. Internal 3.4V Regulator Bypass Pin. The internal power drivers and control circuits are powered by this voltage. Do not load the INTVCC pin with external circuitry. INTVCC current is supplied by VIN. Decouple this pin to ground with at least 1µF low equivalent series resistance (ESR) ceramic capacitor placed close to the IC. A voltage at this pin greater than 0.75V enables switching, and a voltage less than 200mV is guaranteed to shut down the internal current bias and sub-regulators. The hysteretic threshold voltage is 0.75V going up and 0.7V going down. Connect to VIN if the shutdown feature is not used. An external resistor divider from VIN is used to program a VIN threshold below which the LT83401/LT83402 shuts down. 12 VC The VC pin is the output of the internal error amplifier. The voltage on this pin controls the peak switch current. Connect an RC network from this pin to ground to compensate the control loop. This pin is the non-inverting input of the error amplifier and the regulation setpoint for the LT83401/LT83402. SET sources a precision 100μA current that flows through an external resistor connected between the SET and GND. The LT83401/LT83402’s output voltage is determined by VSET = ISET × RSET when used in the default unity gain configuration. SET pin voltage range is from 0 to 15V. For applications with output voltages above 15V, see the Output Voltages Above 15V section. A capacitor should be added from SET to GND for the best noise performance. Increasing this capacitance further improves noise at the expense of increased start-up time. See the SET Pin Capacitor: Noise and Soft-Start section for important information on how to select this capacitor. For optimum load regulation, Kelvin connect the ground side of the SET pin resistor directly to the load. This pin is pulled to ground with a 520Ω MOSFET (RSET– PULLDOWN) during shutdown and fault conditions.

Data Sheet LT83401/LT83402 analog.com Rev. 1 10 of 45 Output Sense. This pin is the inverting input to the error amplifier. For optimal transient performance and load regulation, Kelvin connect OUTS directly to the output capacitor and the load. Power Good Feedback. The PG pin pulls low if PGFB increases above 537.5mV or decreases below 462.5mV. Connecting an external resistor divider between VOUT, PGFB, and GND sets the programmable power good threshold with the following transfer function: 0.5V (±7.5%) × (1 + RPGFB(TOP)/RPGFB(BOT)). As discussed in the Applications Information section, PGFB also activates the fast start-up circuitry. The PGFB pin must be connected to INTVCC or 0.5V if power good and fast start-up functionalities are not needed.

Figure 46. Block Diagram

Data Sheet LT83401/LT83402 analog.com Rev. 1 19 of 45 THEORY OF OPERATION The LT83401/LT83402 is a constant-frequency, current-mode, monolithic step-down regulator that operates using a current reference-based architecture, allowing the employment of unity gain to minimize output noise across all output voltages. An oscillator, with the frequency set using a resistor on the RT pin, turns on the internal top power switch at the beginning of each clock cycle. The current in the inductor increases until the top switch current comparator trips and turns off the top power switch. The peak inductor current at which the top switch turns off is controlled by the voltage on the VC pin. The error amplifier servos the VC node by comparing the voltage on the OUTS pin to the reference voltage on the SET pin, which is set by the user with a resistor from the SET pin to the ground. When the load current increases, it causes a reduction in the OUTS voltage relative to the reference, leading the error amplifier to raise the VC voltage until the average inductor current matches the new load current. When the top power switch turns off, the synchronous power switch turns on until the next clock cycle begins or the inductor current falls to zero (only in pulse -skipping mode). If overload conditions result in more than 1.5A (LT83401)/2.4A (LT83402) flowing through the bottom switch, the next clock cycle is delayed until the switch current returns to a safe level. The LT83401/LT83402 features third -generation Silent Switcher technology, which combines an ultra -low-noise current reference with previous-generation Silent Switcher technology. The output voltage can be programmed with a single resistor, providing unity -gain operation over the output range, and resulting in virtually constant ultra -low output noise independent of the output voltage. If the EN/UVLO pin is below 0.2V, the LT83401/LT83402 shuts down and draws 45 μA from the input. When the EN/UVLO pin rises above 0.75V, the switching regulator becomes active. To improve efficiency at light loads, the LT83401/LT83402 can operate in pulse -skipping mode in light load situations. The SYNC/MODE pin is connected to ground to use pulse -skipping operation and connected to INTVCC or to a voltage higher than 1.5V or floated to use FCM. If a clock is applied to the SYNC pin, the part synchronizes to an external clock frequency and operates in FCM. The LT83401/LT83402 can operate in FCM for fast transient response and full frequency operation over a wide load range. When in FCM, the oscillator operates continuously, and positive SW transitions are aligned to the clock. Negative inductor current is allowed. In this mode, the LT83401/LT83402 can sink current from the output and return this charge to the input, improving load-step transient response. The V C pin allows the loop compensation of the switching regulator to be optimized based on the programmed switching frequency, allowing for a fast transient response.

for setting output voltage, and the noise gain created by this resistor divider. LT83401/LT83402 allows unity -gain operation to avoid gaining up the noise from the reference to the output. therefore, the choice of the compensation network determines the drive stage noise contribution. frequency spikes and significantly reduce switching ripple. output. In practice, this is limited to 1A for the LT83401 and 2.5A for the LT83402. Figure 47. Additional Output Ripple Filtering Using Feedthrough Capacitors

a larger second L and additional output capacitance for the second C, as shown in Figure 48. Figure 48. Additional Output Ripple Filtering Using a Second LC Filter the switching frequency of interest. the output of the LT83401/LT83402 while utilizing only passive filtering. use multiple VIN bypass capacitors.

Figure 49. LT83401/LT83402 Suggested Layout perturbations onto the OUTS pin. A small capacitor may also be placed locally to decouple the OUTS pin if needed. pass underneath the main inductor and should also be kept away from the inductor vias. thermal vias to additional ground planes within the circuit board and on the bottom side.

range. When in FCM, the oscillator operates continuously, and positive SW transitions are aligned to the clock. INTVCC or > 1.5V, or float the pin. Figure 50. Load Step Transient Response with and without FCM. See Typical Application Circuit (Figure 59) negative inductor current is not allowed, and the LT83401/LT83402 operate in pulse-skipping mode. on-time and off-time of 50ns.

the slope compensation is sufficient for all synchronization frequencies. to switch from 300kHz to 6MHz by using a resistor connected from the RT pin to GND. The RT resistor required for the desired switching frequency is calculated by Equation 1. desired switching frequency. Table 4. SW Frequency vs. RT Value given application can be calculated by Equation 2.

Data Sheet LT83401/LT83402 analog.com Rev. 1 25 of 45 where VIN is the typical input voltage, V OUT is the output voltage, V SW(TOP) and VSW(BOT) are the internal switch drops (~0.28V and ~0.14V respectively at maximum load), and tON(MIN) is the minimum top switch on-time (see the Electrical Characteristics table). This equation shows that a slower switching frequency is necessary to accommodate a high VIN/VOUT ratio. For transient operation, V IN may reach as high as the absolute maximum rating of 42V regardless of the R T value. However, the LT83401/LT83402 reduces the switching frequency as necessary to maintain control of the inductor current ensuring safe operation. In pulse-skipping mode, the LT83401/LT83402 is capable of a maximum duty cycle of approximately 98%, and the VIN-to-VOUT dropout is limited by the R DS(ON) of the top switch, provided there is sufficient headroom (~0.9V) between VIN and SET for the current reference circuit to function correctly. In this mode, the LT83401/LT83402 skips switch - off-time cycles, resulting in a lower switching frequency than programmed by R T. The LT83401/LT83402 switch as frequently as necessary to keep the boost capacitor refre shed, with a minimum switching frequency of approximately 80kHz. Note that higher switching frequencies increase the minimum input voltage below which cycles are dropped to achieve a higher duty cycle. To achieve better dropout performance independent of t he current reference's ~0.9V headroom requirement, connect OUTS to V OUT via an external resistor divider (see Figure 53). For instance, in a 12V OUT application, a 2:1 divider yields 6V at OUTS, ensuring V IN-to-VSET > 0.9V across the operating range. See Figure 23 for more details. In FCM, the LT83401/LT83402 does not skip cycles, and so the maximum duty cycle is limited by the minimum off time and chosen switching frequency. For applications that cannot allow deviation from the programmed switching frequency at low VIN/VOUT ratios and must therefore operate in FCM, use Equation 3 to set the switching frequency. VIN(MIN) = VOUT + VSW(BOT) 1 − fSW × tOFF(MIN) − VSW(BOT) + VSW(TOP) (3) where VIN(MIN) is the minimum input voltage without skipped cycles, VOUT is the output voltage, VSW(TOP) and VSW(BOT) are the internal switch drops (~0.28V/0.7V and ~0.14V/0.34V, respectively, at maximum load), fSW is the switching frequency (set by RT), and tOFF(MIN) is the minimum switch off-time. Inductor Selection and Maximum Output Current The LT83401/LT83402 is designed to minimize solution size by allowing the inductor to be chosen based on the output load requirements of the application. During overload or short-circuit conditions, the LT83401/LT83402 safely tolerate operation with a saturated inductor through the use of a high-speed peak-current mode architecture. A good starting point for the inductor value is given by Equation 4. L = ( VOUT + VSW(BOT) fSW ) × 1.2 (4) where f SW is the switching frequency in MHz, V OUT is the output voltage, V SW(BOT) is the bottom switch drop (~0.14V/0.34V, and L is the inductor value in μH). To avoid overheating and poor efficiency, choose an inductor with an RMS current rating that is greater than the maximum expected output load of the application. In addition, the saturation current rating (typically labeled ISAT) of the inductor must be higher than the load current plus ½ of the inductor ripple current. See Equation 5. IL(PEAK) = ILOAD(MAX) + 2 ∆IL (5)

Data Sheet LT83401/LT83402 analog.com Rev. 1 26 of 45 where ΔIL is the inductor ripple current as calculated in Equation 7, and I LOAD(MAX) is the maximum output load for a given application. As a quick example, an application requiring 1A output should use an inductor with an RMS rating of greater than 1A and an ISAT of greater than 2A. During long -duration overload or short -circuit conditions, the inductor’s RMS rating requirement is greater to avoid overheating the inductor. To keep the efficiency high, the series resistance (DCR) should be less than 135mΩ, and the core material should be intended for high-frequency applications. The LT83401/LT83402 limits the peak switch current to protect the switches and the system from overload faults. The top switch current limit (I PEAK-LIMIT) is 2.2A (LT83401)/4A (LT83402) at low duty cycles and decreases linearly to 1.8A (LT83401)/3.2A (LT83402) at a duty cycle = 80%. The inductor value must be sufficient to supply the desired maximum output current (IOUT(MAX)), which is a function of the top switch current limit (IPEAK-LIMIT) and the ripple current (see Equation 6). IOUT(MAX) = IPEAK−LIMIT − ∆IL 2 (6) The peak-to-peak ripple current in the inductor can be calculated using Equation 7. ∆IL = VOUT L × fSW × (1 − VOUT VIN(MAX) ) (7) where f SW is the switching frequency of the LT83401/LT83402, and L is the value of the inductor. Therefore, the maximum output current that the LT83401/LT83402 delivers depends on the switch current limit, the inductor value, and the input and output voltages. The inductor value may have to be increased if the inductor ripple current does not allow sufficient maximum output current (I OUT(MAX)) given the switching frequency and maximum input voltage used in the desired application. The optimum inductor for a given application may differ from the one indicated by this design guide. A larger -value inductor provides a higher maximum load current and reduces the output voltage ripple. For applications requiring smaller load currents, the value of the inductor may be lower, and the LT83401/LT83402 may operate with a higher ripple current. This allows the use of a physically smaller inductor or one with a lower DCR, resulting in higher efficiency. Be aware that low inductance may result in discontinuous operation in pulse -skip mode, which further reduces the maximum load current. For more information about maximum output current and discontinuous operation, refer to the Application Note 44: LT1074/LT1076 Design Manual. For duty cycles greater than 50% (V OUT/VIN > 0.5), a minimum inductance is required to avoid sub -harmonic oscillation. For more information, refer to the Application Note 19: LT1070 Design Manual. Equation 8 calculates the minimum inductance, where I SC represents the slope compensation coefficient. I SC is 0.4 for LT83401 and 0.8 for LT83402. LMIN = VIN(2 × DC−1) ISC × fSW (8) where DC is the duty cycle ratio (VOUT/VIN), and fSW is the switching frequency.

Data Sheet LT83401/LT83402 analog.com Rev. 1 27 of 45 Overcurrent Protection (OCP) The LT83401/LT83402 protects against overload and output short -circuit conditions by cycle -by-cycle current limiting, both the current through the top and bottom switches. Current is sensed in the top switch when it is on. The top switch is immediately turned off when the top switch current limit (IPEAK-LIMIT) is detected, and the bottom switch is turned on. Current is also sensed in the bottom switch when it is on, and the top switch is not allowed to turn back on unless the current through the bottom switch has dropped below the bottom switch current limit ( IVALLEY-LIMIT). This effectively stretches the switching period and lowers the frequency for as long as the protection is required, as the top switch will not be allowed to turn on at the oscillator clock edge until the bottom switch current drops below I VALLEY-LIMIT. This limits the average current during an output short-circuit condition to the RMS average of IPEAK-LIMIT and IVALLEY-LIMIT. Input Capacitors The VIN of the LT83401/LT83402 should be bypassed with at least three ceramic capacitors for best performance. Two small ceramic capacitors can be placed close to the part (CIN1, CIN2). These capacitors should be 0402 in size. Note that a larger input capacitance is required when a lower switching frequency is used. If the input power source has a high impedance or there is significant inductance due to long wires or cables, additional bulk capacitance may be necessary. This can be provided with a low-performance electrolytic capacitor. A ceramic input capacitor combined with trace or cable inductance forms a high-quality (underdamped) tank circuit. If the LT83401/LT83402 are plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the LT83401/LT83402’s voltage rating. This situation is easily avoided. For more information, refer to the Application Note 88: Ceramic Input Capacitors Can Cause Overvoltage Transients. Output Capacitor and Output Ripple The output capacitor has two essential functions. Along with the inductor, it filters the square wave generated by the LT83401/LT83402 to produce the DC output. In this role, it determines the output ripple; thus, a low impedance at the switching frequency is important. The second function is to store energy to satisfy transient loads and stabilize LT83401/LT83402’s control loop. Ceramic capacitors have very low ESR and provide the best ripple performance. For good starting values, see the Typical Applications section. Use X5R or X7R types. This choice provides low output ripple and good transient response. Transient performance can be improved with a higher-value output capacitor. Increasing the output capacitance also decreases the output voltage ripple. A lower value of the output capacitor is used to save space and cost, but transient performance suffers, resulting in loop instability. For the suggested capacitor values, see the Typical Applications section. When choosing a capacitor, special attention should be given to the data sheet to calculate the effective capacitance under the relevant operating conditions of voltage bias and temperature. A physically larger capacitor or one with a higher voltage rating may be required. The LT83401/LT83402 typically operates at a switching frequency of 2MHz. Table 5 shows some examples of output capacitors with ideal frequency characteristics when operating at switching frequencies around 2MHz. Figure 51 shows the frequency characteristics of these capacitors. It can be seen that a combination of these capacitors minimizes the impedance at the switching frequency on the output and keeps the impedance low enough to suppress any higher-frequency harmonics near the switching frequency, thus achieving the lowest output ripple.

Electrical Characteristics table. Table 6 lists many common output voltages and their corresponding 1% RSET resistors. (almost) exactly 8kΩ. 0.1% resistors may be used to achieve higher accuracy. Table 6. 1% Resistor for Common Output Voltages that the regulator always operates in a unity gain configuration, independent of the programmed output voltage. voltage, output load regulation is more tightly specified. require a surface coating at the SET pin to provide a moisture barrier. behavior. This is most noticeable when operating with a minimum output capacitor at heavy load currents. Pin Capacitor: Noise and Soft-Start section. any errors present in the output voltage due to the reference current SET pin resistor tolerances.

low compared to the noise contribution of the part itself. Figure 53. Configuring the LT83401/LT83402 for Output Voltages above 15V provides a Kelvin sense connection to the load’s GND side. onto the OUTS pin, as a c ombination of excessive parasitics and noise injection can cause instability in the system.

Data Sheet LT83401/LT83402 analog.com Rev. 1 32 of 45 EN/UVLO Pin The LT83401/LT83402 are in shutdown when the EN/UVLO pin is low and active when the pin is high. The rising threshold of the EN/UVLO comparator is 0.75V, with 50mV of hysteresis. The EN/UVLO pin can be connected to V IN if the shutdown feature is not used or tied to a logic level if shutdown control is required. If connecting the EN/UVLO pin to VIN instead of driving it with a digital signal, it is recommended to connect EN/UVLO to V IN through a resistor divider to set an appropriate UVLO threshold. This ens ures correct startup and shutdown behavior in the event of rapid power cycling. When the enable pin drops below 0.7V, the part stops switching, but internal circuitry continues drawing current as the INTVCC regulator is still awake. A full shutdown is guaranteed when the enable pin drops below 200mV. In a full shutdown, the INTVCC regulator is disabled, and the part draws less than 70µA. Adding a resistor divider from VIN to EN/UVLO programs the LT83401/LT83402 to regulate the output only when VIN is above the required voltage (see the Block Diagram). This threshold, VIN(EN), is typically used when the input supply is either current-limited or has a relatively high source resistance. A switching regulator draws constant power from the source, so the source current increases as the source voltage drops. This looks like a negative resistance load to the source and causes the source to current limit or latch low under low source voltage conditions. The V IN(EN) threshold prevents the regulator from operating at source voltages where the problems might occur. This threshold can be adjusted by setting the values of REN1 and REN2 such that they satisfy Equation 10. VIN(EN) = ( REN1 REN2 + 1) × 0.75V (10) where the LT83401/LT83402 remain off until V IN is above VIN(EN). Due to the comparator’s hysteresis, switching does not stop until the input falls slightly below VIN(EN). INTVCC Regulator An internal low dropout (LDO) regulator produces the 3.4V supply from V IN that powers the drivers and the internal bias circuitry. The INTVCC supplies enough current for the LT83401/LT83402’s circuitry. The voltage on INTV CC varies SET Pin Capacitor: Noise and Soft-Start In addition to reducing output noise, using a SET pin bypass capacitor reduces the sensitivity to any parasitic coupling of voltage spikes onto the SET pin. Note that any bypass capacitor leakage deteriorates the LT83401/LT83402’s DC regulation. Capacitor leakage of even 100nA is a 0.1% DC error. Therefore, it is recommended to use a good quality, low-leakage ceramic capacitor. Using a SET pin bypass capacitor also soft -starts the output and limits inrush current. Soft -starting the output prevents a current surge on the input supply. The SET pin capacitor and resistor values set the ramp -up time of the reference voltage, and the output voltage tracks this voltage. The SET pin resistor size is determined by the application’s required output voltage; however, the capacitor size may be selected to achieve the desired ramp -up time. It is important to consider that the size of the SET pin capacitor also plays a role in noise performance, which is typically the more important factor in determining the size of this capacitor. Ceramics are manufactured with a variety of dielectrics, each with a different behavior across temperature and applied voltage. Care should be taken when selecting a ceramic capacitor for bypassing the SET pin, as this is a critical component. An X7R (or b etter) ceramic capacitor is strongly recommended for its superior stability across temperature and DC voltage bias. Additionally, larger case sizes are recommended for better DC bias and AC voltage characteristics.

As shown in Figure 55, capacitor DC bias characteristics tend to improve as the component case size increases. Figure 55. Capacitor Voltage Coefficient for Different Case Sizes As shown in Figure 56, larger case sizes tend to experience a smaller capacitance drop when operating near 0V RMS. Therefore, an 0805 or larger ceramic capacitor should be used for the SET pin bypass capacitor for best performance. Table 7 shows some recommended SET pin capacitors. Table 7. Suggested SET Capacitor Part Numbers

Figure 56. AC Voltage Characteristics for Different Capacitor Case Sizes

Data Sheet LT83401/LT83402 analog.com Rev. 1 35 of 45 Without fast start-up enabled, the RC time constant, formed by the SET pin resistor and capacitor, controls soft-start time. Connect the PGFB pin to INTVCC or to 0.5V to disable fast start-up. The ramp-up rate from 0% to 90% of nominal VOUT is given by Equation 11. 𝑡START_NO_FAST_START−UP = 2.3 × 𝑅SET × 𝐶SET (11) With fast-start-up enabled, the start-up time can be significantly reduced, with the ramp-up time from 0% to 90% of the nominal VOUT given by Equation 12. For how the 2.5mA fast start-up current varies with temperature and VIN-VSET differential voltage, see the Typical Performance Characteristics section. tSTART_FAST_START−UP = 100μA × RSET × CSET 2.5mA (12) In most applications, fast start -up is enabled, in which case a minimum SET capacitor size of 1 μF is recommended for preventing reference voltage overcharge as well as ensuring good noise performance. The SET pin is pulled to ground with a 520Ω MOSFET (R SET-PULLDOWN) during shutdown, thermal shutdown, V CC UVLO, or VIN UVLO. To ensure a soft start when the part exits any of the above conditions, there must have been sufficient time to allow the SET pin to be pulled to close to ground prior to start -up. This time will be a function of the chosen SET pin capacitance and RSET-PULLDOWN. Fast Start-Up For ultra-low noise applications that require low 1/f noise (that is, at frequencies below 100Hz), a larger value SET pin capacitor is required, up to 22 μF. A larger value capacitor can be used, but care should be taken regarding leakage. While normally larger capacitors significantly increase the regulator’s start -up time, the LT83401/LT83402 incorporate fast start-up circuitry that increases the SET pin current to about 2.5mA during start-up. Upon start-up, the 2.5mA current source remains engaged while PGFB is below the power good start -up threshold (VPGL_STARTUP) of 487mV, unless the regulator is in thermal shutdown, VIN is too low, or INTVCC has fallen too low. The fast start-up circuit is permanently disabled once PGFB rises above V PGL_STARTUP until either the part is powered down, or the part is placed into shutdown by pulling the EN/UVLO pin below 0.75V. There is one more condition under which the 2.5mA current source is disabled during start -up. The purpose of this is to prevent overcharging VSET. Since the part assumes that the PGFB pin is an accurate indication of the voltage on the SET pin, it assumes that V OUTS follows VSET closely. However, this may not always be the case, for example, if the output capacitance is very large or if, for some reason, the output is temporarily shorted to the GND. Therefore, fast charge is disabled whenever V OUTS is lagging VSET by more than 30mV. This prevents incorrect behavior where the 2.5mA current source stays on even when VSET has risen above its intended final value. If programmable power good and fast start -up capabilities are not required, the PGFB pin must be connected to either INTVCC or to 0.5V. Programmable Power Good As shown in the Block Diagram , the power good threshold is user programmable using the ratio of two external resistors, RPGFB(BOT) and RPGFB(TOP) (see Equation 13). VOUT(PG_THRESHOLD) = 0.5V × (1 + RPGFB(TOP) RPGFB(BOT) ) + IPGFB × RPGFB(TOP) (13) If the PGFB pin increases above 537.5mV or decreases below 462.5mV, the open -drain PG pin asserts and becomes low impedance, indicating power is bad. The power good comparator has a hysteresis of 10mV. The PGFB pin current

dissipation by the thermal resistance from junction to ambient. until the temperature drops about 5°C cooler. temperature rise can be managed by reducing load. The LT83401/LT83402’s top switch current limit decreases with higher duty cycle operation for slope compensation. Performance Characteristics. Figure 58. LT83401/LT83402 Case Temperature Rise

Figure 67. Ultra-Low Noise Current Source for RF Biasing Applications

Figure 68. Tiny 15-Lead 3mm x 2mm LFCSP

Table 9. Ordering Guide 1 Parts ending with PBF are RoHS and WEEE compliant. 3 Pad or ball finish code is per IPC/JEDEC J-STD-609. 4 The temperature grade is identified by a label on the shipping container. (in °C/W) is the package thermal impedance. Reliability reports for these models. 7 For parts specified with wider operating temperature ranges, contact the factory.

Table 10. Related Parts

Data Sheet LT83401/LT83402 ALL INFORMATION CONTAINED HEREIN IS PROVIDED “AS IS” WITHOUT REPRESENTATION OR WARRANTY. NO RESPONSIBILITY IS ASSUMED BY ANALOG DEVICES FOR ITS USE, NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THIRD PARTIES THAT MAY RESULT FROM ITS USE. SPECIFI CATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. NO LICENCE, EITHER EXPRESSED OR IMPLIED, IS GRANTED UNDER ANY ADI PATENT RIGHT, COPYRIGHT, MASK WORK RIGHT, OR ANY OTHER ADI INTELLECTUAL PROPERTY RIGHT RELATING TO ANY COMBINATION, MACHINE, OR PROCESS, IN WHICH ADI PRODUCTS OR SERVICES ARE USED. TRADEMARKS AND REGISTERED TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS. ALL ANALOG DEVICES PRODUCTS CONTAINED HEREIN ARE SUBJECT TO RELEASE AND AVAILABILITY. analog.com Rev. 1 45 of 45